ceph/src/crypto/isa-l/isa-l_crypto/sha512_mb/sha512_mb_x4_avx2.asm

   1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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  29
  30 %include "sha512_mb_mgr_datastruct.asm"
  31 %include "reg_sizes.asm"
  32 default rel
  33
  34 ;; code to compute quad SHA512 using AVX2
  35 ;; use YMMs to tackle the larger digest size
  36 ;; outer calling routine takes care of save and restore of XMM registers
  37 ;; Logic designed/laid out by JDG
  38
  39 ;; Function clobbers: rax, rcx, rdx,   rbx, rsi, rdi, r9-r15; ymm0-15
  40 ;; Stack must be aligned to 32 bytes before call
  41 ;; Windows clobbers:  rax rbx     rdx             r8 r9 r10 r11 r12
  42 ;; Windows preserves:         rcx     rsi rdi rbp                   r13 r14 r15
  43 ;;
  44 ;; Linux clobbers:    rax rbx rcx     rsi         r8 r9 r10 r11 r12
  45 ;; Linux preserves:           rcx rdx     rdi rbp                   r13 r14 r15
  46 ;;
  47 ;; clobbers ymm0-15
  48
  49 %define SHA512_DIGEST_WORD_SIZE 8
  50 %define NUM_SHA512_DIGEST_WORDS 8
  51 %define SHA512_DIGEST_ROW_SIZE 8*4
  52 %define PTR_SZ 8
  53 %define _data_ptr_sha512 _data_ptr
  54
  55 %ifidn __OUTPUT_FORMAT__, elf64
  56 ; LINUX register definitions
  57 %define arg1        rdi
  58 %define arg2        rsi
  59 %else
  60 ; Windows register definitions
  61 %define arg1        rcx
  62 %define arg2        rdx
  63 %endif
  64
  65 ; Common definitions
  66 %define STATE    arg1
  67 %define INP_SIZE arg2
  68
  69 %define IDX     rax
  70 %define ROUND   rbx
  71 %define TBL      r8
  72
  73 %define inp0 r9
  74 %define inp1 r10
  75 %define inp2 r11
  76 %define inp3 r12
  77
  78 %define a ymm0
  79 %define b ymm1
  80 %define c ymm2
  81 %define d ymm3
  82 %define e ymm4
  83 %define f ymm5
  84 %define g ymm6
  85 %define h ymm7
  86
  87 %define a0 ymm8
  88 %define a1 ymm9
  89 %define a2 ymm10
  90
  91 %define TT0 ymm14
  92 %define TT1 ymm13
  93 %define TT2 ymm12
  94 %define TT3 ymm11
  95 %define TT4 ymm10
  96 %define TT5 ymm9
  97
  98 %define T1  ymm14
  99 %define TMP ymm15
 100
 101 %define SZ4     4*SHA512_DIGEST_WORD_SIZE       ; Size of one vector register
 102 %define ROUNDS 80*SZ4
 103
 104 ; Define stack usage
 105
 106 ;; Assume stack aligned to 32 bytes before call
 107 ;; Therefore FRAMESZ mod 32 must be 32-8 = 24
 108 struc stack_frame
 109   .data         resb    16*SZ4
 110   .digest       resb    NUM_SHA512_DIGEST_WORDS*SZ4
 111   .align        resb    24
 112 endstruc
 113
 114 %define _DIGEST stack_frame.digest
 115
 116 %define VMOVPD  vmovupd
 117
 118 ; operates on YMMs
 119 ; transpose r0, r1, r2, r3, t0, t1
 120 ; "transpose" data in {r0..r3} using temps {t0..t3}
 121 ; Input looks like: {r0 r1 r2 r3}
 122 ; r0 = {a7 a6 a5 a4 a3 a2 a1 a0}
 123 ; r1 = {b7 b6 b5 b4 b3 b2 b1 b0}
 124 ; r2 = {c7 c6 c5 c4 c3 c2 c1 c0}
 125 ; r3 = {d7 d6 d5 d4 d3 d2 d1 d0}
 126 ;
 127 ; output looks like: {t0 r1 r0 r3}
 128 ; t0 = {d1 d0 c1 c0 b1 b0 a1 a0}
 129 ; r1 = {d3 d2 c3 c2 b3 b2 a3 a2}
 130 ; r0 = {d5 d4 c5 c4 b5 b4 a5 a4}
 131 ; r3 = {d7 d6 c7 c6 b7 b6 a7 a6}
 132 ;
 133 %macro TRANSPOSE 6
 134 %define %%r0 %1
 135 %define %%r1 %2
 136 %define %%r2 %3
 137 %define %%r3 %4
 138 %define %%t0 %5
 139 %define %%t1 %6
 140         ; vshufps does not cross the mid-way boundary and hence is cheaper
 141         vshufps %%t0, %%r0, %%r1, 0x44  ; t0 = {b5 b4 a5 a4 b1 b0 a1 a0}
 142         vshufps %%r0, %%r0, %%r1, 0xEE  ; r0 = {b7 b6 a7 a6 b3 b2 a3 a2}
 143
 144         vshufps %%t1, %%r2, %%r3, 0x44  ; t1 = {d5 d4 c5 c4 d1 d0 c1 c0}
 145         vshufps %%r2, %%r2, %%r3, 0xEE  ; r2 = {d7 d6 c7 c6 d3 d2 c3 c2}
 146
 147         vperm2f128 %%r1, %%r0, %%r2, 0x20; r1 = {d3 d2 c3 c2 b3 b2 a3 a2}
 148
 149         vperm2f128 %%r3, %%r0, %%r2, 0x31; r3 = {d7 d6 c7 c6 b7 b6 a7 a6}
 150
 151         vperm2f128 %%r0, %%t0, %%t1, 0x31; r0 = {d5 d4 c5 c4 b5 b4 a5 a4}
 152
 153         ; now ok to clobber t0
 154         vperm2f128 %%t0, %%t0, %%t1, 0x20; t0 = {d1 d0 c1 c0 b1 b0 a1 a0}
 155
 156 %endmacro
 157
 158
 159 %macro ROTATE_ARGS 0
 160 %xdefine TMP_ h
 161 %xdefine h g
 162 %xdefine g f
 163 %xdefine f e
 164 %xdefine e d
 165 %xdefine d c
 166 %xdefine c b
 167 %xdefine b a
 168 %xdefine a TMP_
 169 %endm
 170
 171 ; PRORQ reg, imm, tmp
 172 ; packed-rotate-right-double
 173 ; does a rotate by doing two shifts and an or
 174 %macro PRORQ 3
 175 %define %%reg %1
 176 %define %%imm %2
 177 %define %%tmp %3
 178         vpsllq  %%tmp, %%reg, (64-(%%imm))
 179         vpsrlq  %%reg, %%reg, %%imm
 180         vpor    %%reg, %%reg, %%tmp
 181 %endmacro
 182
 183 ; non-destructive
 184 ; PRORQ_nd reg, imm, tmp, src
 185 %macro PRORQ_nd 4
 186 %define %%reg %1
 187 %define %%imm %2
 188 %define %%tmp %3
 189 %define %%src %4
 190         vpsllq  %%tmp, %%src, (64-(%%imm))
 191         vpsrlq  %%reg, %%src, %%imm
 192         vpor    %%reg, %%reg, %%tmp
 193 %endmacro
 194
 195 ; PRORQ dst/src, amt
 196 %macro PRORQ 2
 197         PRORQ   %1, %2, TMP
 198 %endmacro
 199
 200 ; PRORQ_nd dst, src, amt
 201 %macro PRORQ_nd 3
 202         PRORQ_nd        %1, %3, TMP, %2
 203 %endmacro
 204
 205
 206
 207 ;; arguments passed implicitly in preprocessor symbols i, a...h
 208 %macro ROUND_00_15 2
 209 %define %%T1 %1
 210 %define %%i  %2
 211         PRORQ_nd a0, e, (18-14) ; sig1: a0 = (e >> 4)
 212
 213         vpxor   a2, f, g        ; ch: a2 = f^g
 214         vpand   a2, a2, e       ; ch: a2 = (f^g)&e
 215         vpxor   a2, a2, g       ; a2 = ch
 216
 217         PRORQ_nd a1, e, 41      ; sig1: a1 = (e >> 41)
 218         vmovdqa [SZ4*(%%i&0xf) + rsp],%%T1
 219         vpaddq  %%T1,%%T1,[TBL + ROUND] ; T1 = W + K
 220         vpxor   a0, a0, e       ; sig1: a0 = e ^ (e >> 5)
 221         PRORQ   a0, 14          ; sig1: a0 = (e >> 14) ^ (e >> 18)
 222         vpaddq  h, h, a2        ; h = h + ch
 223         PRORQ_nd a2, a, (34-28) ; sig0: a2 = (a >> 6)
 224         vpaddq  h, h, %%T1      ; h = h + ch + W + K
 225         vpxor   a0, a0, a1      ; a0 = sigma1
 226         vmovdqa %%T1, a         ; maj: T1 = a
 227         PRORQ_nd a1, a, 39      ; sig0: a1 = (a >> 39)
 228         vpxor   %%T1, %%T1, c   ; maj: T1 = a^c
 229         add     ROUND, SZ4 ; ROUND++
 230         vpand   %%T1, %%T1, b   ; maj: T1 = (a^c)&b
 231         vpaddq  h, h, a0
 232
 233         vpaddq  d, d, h
 234
 235         vpxor   a2, a2, a       ; sig0: a2 = a ^ (a >> 11)
 236         PRORQ   a2, 28          ; sig0: a2 = (a >> 28) ^ (a >> 34)
 237         vpxor   a2, a2, a1      ; a2 = sig0
 238         vpand   a1, a, c        ; maj: a1 = a&c
 239         vpor    a1, a1, %%T1    ; a1 = maj
 240         vpaddq  h, h, a1        ; h = h + ch + W + K + maj
 241         vpaddq  h, h, a2        ; h = h + ch + W + K + maj + sigma0
 242         ROTATE_ARGS
 243
 244 %endm
 245
 246
 247 ;; arguments passed implicitly in preprocessor symbols i, a...h
 248 %macro ROUND_16_XX 2
 249 %define %%T1 %1
 250 %define %%i  %2
 251         vmovdqa %%T1, [SZ4*((%%i-15)&0xf) + rsp]
 252         vmovdqa a1, [SZ4*((%%i-2)&0xf) + rsp]
 253         vmovdqa a0, %%T1
 254         PRORQ   %%T1, 8-1
 255         vmovdqa a2, a1
 256         PRORQ   a1, 61-19
 257         vpxor   %%T1, %%T1, a0
 258         PRORQ   %%T1, 1
 259         vpxor   a1, a1, a2
 260         PRORQ   a1, 19
 261         vpsrlq  a0, a0, 7
 262         vpxor   %%T1, %%T1, a0
 263         vpsrlq  a2, a2, 6
 264         vpxor   a1, a1, a2
 265         vpaddq  %%T1, %%T1, [SZ4*((%%i-16)&0xf) + rsp]
 266         vpaddq  a1, a1, [SZ4*((%%i-7)&0xf) + rsp]
 267         vpaddq  %%T1, %%T1, a1
 268
 269         ROUND_00_15 %%T1, %%i
 270
 271 %endm
 272
 273
 274 ;; void sha512_mb_x4_avx2(SHA512_MB_ARGS_X4 *STATE, const int INP_SIZE)
 275 ;; arg 1 : STATE    : pointer to input data
 276 ;; arg 2 : INP_SIZE : size of data in blocks (assumed >= 1)
 277 global sha512_mb_x4_avx2:function internal
 278 align 32
 279 sha512_mb_x4_avx2:
 280         ; general registers preserved in outer calling routine
 281         ; outer calling routine saves all the XMM registers
 282
 283         sub     rsp, stack_frame_size
 284
 285      ;; Load the pre-transposed incoming digest.
 286         vmovdqu a, [STATE+ 0*SHA512_DIGEST_ROW_SIZE]
 287         vmovdqu b, [STATE+ 1*SHA512_DIGEST_ROW_SIZE]
 288         vmovdqu c, [STATE+ 2*SHA512_DIGEST_ROW_SIZE]
 289         vmovdqu d, [STATE+ 3*SHA512_DIGEST_ROW_SIZE]
 290         vmovdqu e, [STATE+ 4*SHA512_DIGEST_ROW_SIZE]
 291         vmovdqu f, [STATE+ 5*SHA512_DIGEST_ROW_SIZE]
 292         vmovdqu g, [STATE+ 6*SHA512_DIGEST_ROW_SIZE]
 293         vmovdqu h, [STATE+ 7*SHA512_DIGEST_ROW_SIZE]
 294
 295
 296         lea     TBL,[K512_4_MB]
 297
 298         ;; load the address of each of the MAX_LANES (4)  message lanes
 299         ;; getting ready to transpose input onto stack
 300         mov     inp0,[STATE + _data_ptr_sha512 + 0*PTR_SZ]
 301         mov     inp1,[STATE + _data_ptr_sha512 + 1*PTR_SZ]
 302         mov     inp2,[STATE + _data_ptr_sha512 + 2*PTR_SZ]
 303         mov     inp3,[STATE + _data_ptr_sha512 + 3*PTR_SZ]
 304
 305         xor     IDX, IDX
 306 lloop:
 307         xor     ROUND, ROUND
 308
 309         ;; save old digest
 310         vmovdqa [rsp + _DIGEST + 0*SZ4], a
 311         vmovdqa [rsp + _DIGEST + 1*SZ4], b
 312         vmovdqa [rsp + _DIGEST + 2*SZ4], c
 313         vmovdqa [rsp + _DIGEST + 3*SZ4], d
 314         vmovdqa [rsp + _DIGEST + 4*SZ4], e
 315         vmovdqa [rsp + _DIGEST + 5*SZ4], f
 316         vmovdqa [rsp + _DIGEST + 6*SZ4], g
 317         vmovdqa [rsp + _DIGEST + 7*SZ4], h
 318
 319 %assign i 0
 320 %rep 4
 321         ;; load up the shuffler for little-endian to big-endian format
 322         vmovdqa TMP, [PSHUFFLE_BYTE_FLIP_MASK]
 323         VMOVPD  TT2,[inp0+IDX+i*32]
 324         VMOVPD  TT1,[inp1+IDX+i*32]
 325         VMOVPD  TT4,[inp2+IDX+i*32]
 326         VMOVPD  TT3,[inp3+IDX+i*32]
 327         TRANSPOSE       TT2, TT1, TT4, TT3, TT0, TT5
 328         vpshufb TT0, TT0, TMP
 329         vpshufb TT1, TT1, TMP
 330         vpshufb TT2, TT2, TMP
 331         vpshufb TT3, TT3, TMP
 332         ROUND_00_15     TT0,(i*4+0)
 333         ROUND_00_15     TT1,(i*4+1)
 334         ROUND_00_15     TT2,(i*4+2)
 335         ROUND_00_15     TT3,(i*4+3)
 336 %assign i (i+1)
 337 %endrep
 338 ;; Increment IDX by message block size == 8 (loop) * 16 (XMM width in bytes)
 339         add     IDX, 4 * 32
 340
 341 %assign i (i*4)
 342
 343         jmp     Lrounds_16_xx
 344 align 16
 345 Lrounds_16_xx:
 346 %rep 16
 347         ROUND_16_XX     T1, i
 348 %assign i (i+1)
 349 %endrep
 350
 351         cmp     ROUND,ROUNDS
 352         jb      Lrounds_16_xx
 353
 354         ;; add old digest
 355         vpaddq  a, a, [rsp + _DIGEST + 0*SZ4]
 356         vpaddq  b, b, [rsp + _DIGEST + 1*SZ4]
 357         vpaddq  c, c, [rsp + _DIGEST + 2*SZ4]
 358         vpaddq  d, d, [rsp + _DIGEST + 3*SZ4]
 359         vpaddq  e, e, [rsp + _DIGEST + 4*SZ4]
 360         vpaddq  f, f, [rsp + _DIGEST + 5*SZ4]
 361         vpaddq  g, g, [rsp + _DIGEST + 6*SZ4]
 362         vpaddq  h, h, [rsp + _DIGEST + 7*SZ4]
 363
 364         sub     INP_SIZE, 1 ;; consumed one message block
 365         jne     lloop
 366
 367         ; write back to memory (state object) the transposed digest
 368         vmovdqu [STATE+ 0*SHA512_DIGEST_ROW_SIZE ],a
 369         vmovdqu [STATE+ 1*SHA512_DIGEST_ROW_SIZE ],b
 370         vmovdqu [STATE+ 2*SHA512_DIGEST_ROW_SIZE ],c
 371         vmovdqu [STATE+ 3*SHA512_DIGEST_ROW_SIZE ],d
 372         vmovdqu [STATE+ 4*SHA512_DIGEST_ROW_SIZE ],e
 373         vmovdqu [STATE+ 5*SHA512_DIGEST_ROW_SIZE ],f
 374         vmovdqu [STATE+ 6*SHA512_DIGEST_ROW_SIZE ],g
 375         vmovdqu [STATE+ 7*SHA512_DIGEST_ROW_SIZE ],h
 376
 377         ;; update input data pointers
 378         add inp0, IDX
 379         mov     [STATE + _data_ptr_sha512 + 0*PTR_SZ], inp0
 380         add inp1, IDX
 381         mov     [STATE + _data_ptr_sha512 + 1*PTR_SZ], inp1
 382         add inp2, IDX
 383         mov     [STATE + _data_ptr_sha512 + 2*PTR_SZ], inp2
 384         add inp3, IDX
 385         mov     [STATE + _data_ptr_sha512 + 3*PTR_SZ], inp3
 386
 387         ;;;;;;;;;;;;;;;;
 388         ;; Postamble
 389
 390         add rsp, stack_frame_size
 391
 392         ; outer calling routine restores XMM and other GP registers
 393         ret
 394
 395 section .data
 396 align 64
 397 K512_4_MB:
 398         dq 0x428a2f98d728ae22, 0x428a2f98d728ae22, 0x428a2f98d728ae22, 0x428a2f98d728ae22
 399         dq 0x7137449123ef65cd, 0x7137449123ef65cd, 0x7137449123ef65cd, 0x7137449123ef65cd
 400         dq 0xb5c0fbcfec4d3b2f, 0xb5c0fbcfec4d3b2f, 0xb5c0fbcfec4d3b2f, 0xb5c0fbcfec4d3b2f
 401         dq 0xe9b5dba58189dbbc, 0xe9b5dba58189dbbc, 0xe9b5dba58189dbbc, 0xe9b5dba58189dbbc
 402         dq 0x3956c25bf348b538, 0x3956c25bf348b538, 0x3956c25bf348b538, 0x3956c25bf348b538
 403         dq 0x59f111f1b605d019, 0x59f111f1b605d019, 0x59f111f1b605d019, 0x59f111f1b605d019
 404         dq 0x923f82a4af194f9b, 0x923f82a4af194f9b, 0x923f82a4af194f9b, 0x923f82a4af194f9b
 405         dq 0xab1c5ed5da6d8118, 0xab1c5ed5da6d8118, 0xab1c5ed5da6d8118, 0xab1c5ed5da6d8118
 406         dq 0xd807aa98a3030242, 0xd807aa98a3030242, 0xd807aa98a3030242, 0xd807aa98a3030242
 407         dq 0x12835b0145706fbe, 0x12835b0145706fbe, 0x12835b0145706fbe, 0x12835b0145706fbe
 408         dq 0x243185be4ee4b28c, 0x243185be4ee4b28c, 0x243185be4ee4b28c, 0x243185be4ee4b28c
 409         dq 0x550c7dc3d5ffb4e2, 0x550c7dc3d5ffb4e2, 0x550c7dc3d5ffb4e2, 0x550c7dc3d5ffb4e2
 410         dq 0x72be5d74f27b896f, 0x72be5d74f27b896f, 0x72be5d74f27b896f, 0x72be5d74f27b896f
 411         dq 0x80deb1fe3b1696b1, 0x80deb1fe3b1696b1, 0x80deb1fe3b1696b1, 0x80deb1fe3b1696b1
 412         dq 0x9bdc06a725c71235, 0x9bdc06a725c71235, 0x9bdc06a725c71235, 0x9bdc06a725c71235
 413         dq 0xc19bf174cf692694, 0xc19bf174cf692694, 0xc19bf174cf692694, 0xc19bf174cf692694
 414         dq 0xe49b69c19ef14ad2, 0xe49b69c19ef14ad2, 0xe49b69c19ef14ad2, 0xe49b69c19ef14ad2
 415         dq 0xefbe4786384f25e3, 0xefbe4786384f25e3, 0xefbe4786384f25e3, 0xefbe4786384f25e3
 416         dq 0x0fc19dc68b8cd5b5, 0x0fc19dc68b8cd5b5, 0x0fc19dc68b8cd5b5, 0x0fc19dc68b8cd5b5
 417         dq 0x240ca1cc77ac9c65, 0x240ca1cc77ac9c65, 0x240ca1cc77ac9c65, 0x240ca1cc77ac9c65
 418         dq 0x2de92c6f592b0275, 0x2de92c6f592b0275, 0x2de92c6f592b0275, 0x2de92c6f592b0275
 419         dq 0x4a7484aa6ea6e483, 0x4a7484aa6ea6e483, 0x4a7484aa6ea6e483, 0x4a7484aa6ea6e483
 420         dq 0x5cb0a9dcbd41fbd4, 0x5cb0a9dcbd41fbd4, 0x5cb0a9dcbd41fbd4, 0x5cb0a9dcbd41fbd4
 421         dq 0x76f988da831153b5, 0x76f988da831153b5, 0x76f988da831153b5, 0x76f988da831153b5
 422         dq 0x983e5152ee66dfab, 0x983e5152ee66dfab, 0x983e5152ee66dfab, 0x983e5152ee66dfab
 423         dq 0xa831c66d2db43210, 0xa831c66d2db43210, 0xa831c66d2db43210, 0xa831c66d2db43210
 424         dq 0xb00327c898fb213f, 0xb00327c898fb213f, 0xb00327c898fb213f, 0xb00327c898fb213f
 425         dq 0xbf597fc7beef0ee4, 0xbf597fc7beef0ee4, 0xbf597fc7beef0ee4, 0xbf597fc7beef0ee4
 426         dq 0xc6e00bf33da88fc2, 0xc6e00bf33da88fc2, 0xc6e00bf33da88fc2, 0xc6e00bf33da88fc2
 427         dq 0xd5a79147930aa725, 0xd5a79147930aa725, 0xd5a79147930aa725, 0xd5a79147930aa725
 428         dq 0x06ca6351e003826f, 0x06ca6351e003826f, 0x06ca6351e003826f, 0x06ca6351e003826f
 429         dq 0x142929670a0e6e70, 0x142929670a0e6e70, 0x142929670a0e6e70, 0x142929670a0e6e70
 430         dq 0x27b70a8546d22ffc, 0x27b70a8546d22ffc, 0x27b70a8546d22ffc, 0x27b70a8546d22ffc
 431         dq 0x2e1b21385c26c926, 0x2e1b21385c26c926, 0x2e1b21385c26c926, 0x2e1b21385c26c926
 432         dq 0x4d2c6dfc5ac42aed, 0x4d2c6dfc5ac42aed, 0x4d2c6dfc5ac42aed, 0x4d2c6dfc5ac42aed
 433         dq 0x53380d139d95b3df, 0x53380d139d95b3df, 0x53380d139d95b3df, 0x53380d139d95b3df
 434         dq 0x650a73548baf63de, 0x650a73548baf63de, 0x650a73548baf63de, 0x650a73548baf63de
 435         dq 0x766a0abb3c77b2a8, 0x766a0abb3c77b2a8, 0x766a0abb3c77b2a8, 0x766a0abb3c77b2a8
 436         dq 0x81c2c92e47edaee6, 0x81c2c92e47edaee6, 0x81c2c92e47edaee6, 0x81c2c92e47edaee6
 437         dq 0x92722c851482353b, 0x92722c851482353b, 0x92722c851482353b, 0x92722c851482353b
 438         dq 0xa2bfe8a14cf10364, 0xa2bfe8a14cf10364, 0xa2bfe8a14cf10364, 0xa2bfe8a14cf10364
 439         dq 0xa81a664bbc423001, 0xa81a664bbc423001, 0xa81a664bbc423001, 0xa81a664bbc423001
 440         dq 0xc24b8b70d0f89791, 0xc24b8b70d0f89791, 0xc24b8b70d0f89791, 0xc24b8b70d0f89791
 441         dq 0xc76c51a30654be30, 0xc76c51a30654be30, 0xc76c51a30654be30, 0xc76c51a30654be30
 442         dq 0xd192e819d6ef5218, 0xd192e819d6ef5218, 0xd192e819d6ef5218, 0xd192e819d6ef5218
 443         dq 0xd69906245565a910, 0xd69906245565a910, 0xd69906245565a910, 0xd69906245565a910
 444         dq 0xf40e35855771202a, 0xf40e35855771202a, 0xf40e35855771202a, 0xf40e35855771202a
 445         dq 0x106aa07032bbd1b8, 0x106aa07032bbd1b8, 0x106aa07032bbd1b8, 0x106aa07032bbd1b8
 446         dq 0x19a4c116b8d2d0c8, 0x19a4c116b8d2d0c8, 0x19a4c116b8d2d0c8, 0x19a4c116b8d2d0c8
 447         dq 0x1e376c085141ab53, 0x1e376c085141ab53, 0x1e376c085141ab53, 0x1e376c085141ab53
 448         dq 0x2748774cdf8eeb99, 0x2748774cdf8eeb99, 0x2748774cdf8eeb99, 0x2748774cdf8eeb99
 449         dq 0x34b0bcb5e19b48a8, 0x34b0bcb5e19b48a8, 0x34b0bcb5e19b48a8, 0x34b0bcb5e19b48a8
 450         dq 0x391c0cb3c5c95a63, 0x391c0cb3c5c95a63, 0x391c0cb3c5c95a63, 0x391c0cb3c5c95a63
 451         dq 0x4ed8aa4ae3418acb, 0x4ed8aa4ae3418acb, 0x4ed8aa4ae3418acb, 0x4ed8aa4ae3418acb
 452         dq 0x5b9cca4f7763e373, 0x5b9cca4f7763e373, 0x5b9cca4f7763e373, 0x5b9cca4f7763e373
 453         dq 0x682e6ff3d6b2b8a3, 0x682e6ff3d6b2b8a3, 0x682e6ff3d6b2b8a3, 0x682e6ff3d6b2b8a3
 454         dq 0x748f82ee5defb2fc, 0x748f82ee5defb2fc, 0x748f82ee5defb2fc, 0x748f82ee5defb2fc
 455         dq 0x78a5636f43172f60, 0x78a5636f43172f60, 0x78a5636f43172f60, 0x78a5636f43172f60
 456         dq 0x84c87814a1f0ab72, 0x84c87814a1f0ab72, 0x84c87814a1f0ab72, 0x84c87814a1f0ab72
 457         dq 0x8cc702081a6439ec, 0x8cc702081a6439ec, 0x8cc702081a6439ec, 0x8cc702081a6439ec
 458         dq 0x90befffa23631e28, 0x90befffa23631e28, 0x90befffa23631e28, 0x90befffa23631e28
 459         dq 0xa4506cebde82bde9, 0xa4506cebde82bde9, 0xa4506cebde82bde9, 0xa4506cebde82bde9
 460         dq 0xbef9a3f7b2c67915, 0xbef9a3f7b2c67915, 0xbef9a3f7b2c67915, 0xbef9a3f7b2c67915
 461         dq 0xc67178f2e372532b, 0xc67178f2e372532b, 0xc67178f2e372532b, 0xc67178f2e372532b
 462         dq 0xca273eceea26619c, 0xca273eceea26619c, 0xca273eceea26619c, 0xca273eceea26619c
 463         dq 0xd186b8c721c0c207, 0xd186b8c721c0c207, 0xd186b8c721c0c207, 0xd186b8c721c0c207
 464         dq 0xeada7dd6cde0eb1e, 0xeada7dd6cde0eb1e, 0xeada7dd6cde0eb1e, 0xeada7dd6cde0eb1e
 465         dq 0xf57d4f7fee6ed178, 0xf57d4f7fee6ed178, 0xf57d4f7fee6ed178, 0xf57d4f7fee6ed178
 466         dq 0x06f067aa72176fba, 0x06f067aa72176fba, 0x06f067aa72176fba, 0x06f067aa72176fba
 467         dq 0x0a637dc5a2c898a6, 0x0a637dc5a2c898a6, 0x0a637dc5a2c898a6, 0x0a637dc5a2c898a6
 468         dq 0x113f9804bef90dae, 0x113f9804bef90dae, 0x113f9804bef90dae, 0x113f9804bef90dae
 469         dq 0x1b710b35131c471b, 0x1b710b35131c471b, 0x1b710b35131c471b, 0x1b710b35131c471b
 470         dq 0x28db77f523047d84, 0x28db77f523047d84, 0x28db77f523047d84, 0x28db77f523047d84
 471         dq 0x32caab7b40c72493, 0x32caab7b40c72493, 0x32caab7b40c72493, 0x32caab7b40c72493
 472         dq 0x3c9ebe0a15c9bebc, 0x3c9ebe0a15c9bebc, 0x3c9ebe0a15c9bebc, 0x3c9ebe0a15c9bebc
 473         dq 0x431d67c49c100d4c, 0x431d67c49c100d4c, 0x431d67c49c100d4c, 0x431d67c49c100d4c
 474         dq 0x4cc5d4becb3e42b6, 0x4cc5d4becb3e42b6, 0x4cc5d4becb3e42b6, 0x4cc5d4becb3e42b6
 475         dq 0x597f299cfc657e2a, 0x597f299cfc657e2a, 0x597f299cfc657e2a, 0x597f299cfc657e2a
 476         dq 0x5fcb6fab3ad6faec, 0x5fcb6fab3ad6faec, 0x5fcb6fab3ad6faec, 0x5fcb6fab3ad6faec
 477         dq 0x6c44198c4a475817, 0x6c44198c4a475817, 0x6c44198c4a475817, 0x6c44198c4a475817
 478
 479 align 32
 480 PSHUFFLE_BYTE_FLIP_MASK: dq 0x0001020304050607, 0x08090a0b0c0d0e0f
 481                          dq 0x1011121314151617, 0x18191a1b1c1d1e1f
 482
 483