1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
4 ; Redistribution and use in source and binary forms, with or without
5 ; modification, are permitted provided that the following conditions
7 ; * Redistributions of source code must retain the above copyright
8 ; notice, this list of conditions and the following disclaimer.
9 ; * Redistributions in binary form must reproduce the above copyright
10 ; notice, this list of conditions and the following disclaimer in
11 ; the documentation and/or other materials provided with the
13 ; * Neither the name of Intel Corporation nor the names of its
14 ; contributors may be used to endorse or promote products derived
15 ; from this software without specific prior written permission.
17 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
31 ;;; gf_4vect_mad_avx512(len, vec, vec_i, mul_array, src, dest);
34 %include "reg_sizes.asm"
36 %ifdef HAVE_AS_KNOWS_AVX512
38 %ifidn __OUTPUT_FORMAT__, elf64
52 %ifidn __OUTPUT_FORMAT__, win64
61 %define stack_size 16*10 + 3*8
62 %define arg(x) [rsp + stack_size + PS + PS*x]
63 %define func(x) proc_frame x
67 movdqa [rsp+16*0],xmm6
68 movdqa [rsp+16*1],xmm7
69 movdqa [rsp+16*2],xmm8
70 movdqa [rsp+16*3],xmm9
71 movdqa [rsp+16*4],xmm10
72 movdqa [rsp+16*5],xmm11
73 movdqa [rsp+16*6],xmm12
74 movdqa [rsp+16*7],xmm13
75 movdqa [rsp+16*8],xmm14
76 movdqa [rsp+16*9],xmm15
77 save_reg r12, 10*16 + 0*8
78 save_reg r15, 10*16 + 1*8
85 movdqa xmm6, [rsp+16*0]
86 movdqa xmm7, [rsp+16*1]
87 movdqa xmm8, [rsp+16*2]
88 movdqa xmm9, [rsp+16*3]
89 movdqa xmm10, [rsp+16*4]
90 movdqa xmm11, [rsp+16*5]
91 movdqa xmm12, [rsp+16*6]
92 movdqa xmm13, [rsp+16*7]
93 movdqa xmm14, [rsp+16*8]
94 movdqa xmm15, [rsp+16*9]
95 mov r12, [rsp + 10*16 + 0*8]
96 mov r15, [rsp + 10*16 + 1*8]
105 %define mul_array arg3
109 %define dest2 mul_array
113 %ifndef EC_ALIGNED_ADDR
114 ;;; Use Un-aligned load/store
115 %define XLDR vmovdqu8
116 %define XSTR vmovdqu8
118 ;;; Use Non-temporal load/stor
123 %define XLDR vmovntdqa
124 %define XSTR vmovntdq
139 %define xgft1_hi zmm7
140 %define xgft1_lo zmm8
141 %define xgft1_loy ymm8
142 %define xgft2_hi zmm9
143 %define xgft2_lo zmm10
144 %define xgft2_loy ymm10
145 %define xgft3_hi zmm11
146 %define xgft3_lo zmm12
147 %define xgft3_loy ymm12
148 %define xgft4_hi zmm13
149 %define xgft4_lo zmm14
150 %define xgft4_loy ymm14
155 %define xmask0f zmm19
162 global gf_4vect_mad_avx512:function
163 func(gf_4vect_mad_avx512)
169 vpbroadcastb xmask0f, tmp ;Construct mask 0x0f0f0f...
170 sal vec_i, 5 ;Multiply by 32
171 sal vec, 5 ;Multiply by 32
172 lea tmp, [mul_array + vec_i]
173 vmovdqu xgft1_loy, [tmp] ;Load array Ax{00}..{0f}, Ax{00}..{f0}
174 vmovdqu xgft2_loy, [tmp+vec] ;Load array Bx{00}..{0f}, Bx{00}..{f0}
175 vmovdqu xgft3_loy, [tmp+2*vec] ;Load array Cx{00}..{0f}, Cx{00}..{f0}
177 vmovdqu xgft4_loy, [tmp+2*vec] ;Load array Dx{00}..{0f}, Dx{00}..{f0}
178 vshufi64x2 xgft1_hi, xgft1_lo, xgft1_lo, 0x55
179 vshufi64x2 xgft1_lo, xgft1_lo, xgft1_lo, 0x00
180 vshufi64x2 xgft2_hi, xgft2_lo, xgft2_lo, 0x55
181 vshufi64x2 xgft2_lo, xgft2_lo, xgft2_lo, 0x00
182 vshufi64x2 xgft3_hi, xgft3_lo, xgft3_lo, 0x55
183 vshufi64x2 xgft3_lo, xgft3_lo, xgft3_lo, 0x00
184 vshufi64x2 xgft4_hi, xgft4_lo, xgft4_lo, 0x55
185 vshufi64x2 xgft4_lo, xgft4_lo, xgft4_lo, 0x00
186 mov dest2, [dest1+PS] ; reuse mul_array
187 mov dest3, [dest1+2*PS] ; reuse vec
188 mov dest4, [dest1+3*PS] ; reuse vec_i
194 XLDR x0, [src+pos] ;Get next source vector
195 XLDR xd1, [dest1+pos] ;Get next dest vector
196 XLDR xd2, [dest2+pos] ;Get next dest vector
197 XLDR xd3, [dest3+pos] ;Get next dest vector
198 XLDR xd4, [dest4+pos] ;reuse xtmpl1. Get next dest vector
200 vpandq xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
201 vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
202 vpandq x0, x0, xmask0f ;Mask high src nibble in bits 4-0
205 vpshufb xtmph1 {k1}{z}, xgft1_hi, x0 ;Lookup mul table of high nibble
206 vpshufb xtmpl1 {k1}{z}, xgft1_lo, xtmpa ;Lookup mul table of low nibble
207 vpxorq xtmph1, xtmph1, xtmpl1 ;GF add high and low partials
208 vpxorq xd1, xd1, xtmph1 ;xd1 += partial
211 vpshufb xtmph2 {k1}{z}, xgft2_hi, x0 ;Lookup mul table of high nibble
212 vpshufb xtmpl2 {k1}{z}, xgft2_lo, xtmpa ;Lookup mul table of low nibble
213 vpxorq xtmph2, xtmph2, xtmpl2 ;GF add high and low partials
214 vpxorq xd2, xd2, xtmph2 ;xd2 += partial
217 vpshufb xtmph3 {k1}{z}, xgft3_hi, x0 ;Lookup mul table of high nibble
218 vpshufb xtmpl3 {k1}{z}, xgft3_lo, xtmpa ;Lookup mul table of low nibble
219 vpxorq xtmph3, xtmph3, xtmpl3 ;GF add high and low partials
220 vpxorq xd3, xd3, xtmph3 ;xd2 += partial
223 vpshufb xtmph4 {k1}{z}, xgft4_hi, x0 ;Lookup mul table of high nibble
224 vpshufb xtmpl4 {k1}{z}, xgft4_lo, xtmpa ;Lookup mul table of low nibble
225 vpxorq xtmph4, xtmph4, xtmpl4 ;GF add high and low partials
226 vpxorq xd4, xd4, xtmph4 ;xd2 += partial
228 XSTR [dest1+pos], xd1
229 XSTR [dest2+pos], xd2
230 XSTR [dest3+pos], xd3
231 XSTR [dest4+pos], xd4
233 add pos, 64 ;Loop on 64 bytes at a time
243 lea tmp, [len + 64 - 1]
247 mov pos, len ;Overlapped offset length-64
248 jmp .loop64 ;Do one more overlap pass
263 %ifidn __OUTPUT_FORMAT__, win64
264 global no_gf_4vect_mad_avx512
265 no_gf_4vect_mad_avx512:
267 %endif ; ifdef HAVE_AS_KNOWS_AVX512