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1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
3 ;
4 ; Redistribution and use in source and binary forms, with or without
5 ; modification, are permitted provided that the following conditions
6 ; are met:
7 ; * Redistributions of source code must retain the above copyright
8 ; notice, this list of conditions and the following disclaimer.
9 ; * Redistributions in binary form must reproduce the above copyright
10 ; notice, this list of conditions and the following disclaimer in
11 ; the documentation and/or other materials provided with the
12 ; distribution.
13 ; * Neither the name of Intel Corporation nor the names of its
14 ; contributors may be used to endorse or promote products derived
15 ; from this software without specific prior written permission.
16 ;
17 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
29
30 %ifndef _REG_SIZES_ASM_
31 %define _REG_SIZES_ASM_
32
33 %ifdef __NASM_VER__
34 %ifidn __OUTPUT_FORMAT__, win64
35 %error nasm not supported in windows
36 %else
37 %define endproc_frame
38 %endif
39 %endif
40
41 %define EFLAGS_HAS_CPUID (1<<21)
42 %define FLAG_CPUID1_ECX_CLMUL (1<<1)
43 %define FLAG_CPUID1_EDX_SSE2 (1<<26)
44 %define FLAG_CPUID1_ECX_SSE3 (1)
45 %define FLAG_CPUID1_ECX_SSE4_1 (1<<19)
46 %define FLAG_CPUID1_ECX_SSE4_2 (1<<20)
47 %define FLAG_CPUID1_ECX_POPCNT (1<<23)
48 %define FLAG_CPUID1_ECX_AESNI (1<<25)
49 %define FLAG_CPUID1_ECX_OSXSAVE (1<<27)
50 %define FLAG_CPUID1_ECX_AVX (1<<28)
51 %define FLAG_CPUID1_EBX_AVX2 (1<<5)
52
53 %define FLAG_CPUID7_EBX_AVX2 (1<<5)
54 %define FLAG_CPUID7_EBX_AVX512F (1<<16)
55 %define FLAG_CPUID7_EBX_AVX512DQ (1<<17)
56 %define FLAG_CPUID7_EBX_AVX512IFMA (1<<21)
57 %define FLAG_CPUID7_EBX_AVX512PF (1<<26)
58 %define FLAG_CPUID7_EBX_AVX512ER (1<<27)
59 %define FLAG_CPUID7_EBX_AVX512CD (1<<28)
60 %define FLAG_CPUID7_EBX_AVX512BW (1<<30)
61 %define FLAG_CPUID7_EBX_AVX512VL (1<<31)
62 %define FLAG_CPUID7_ECX_AVX512VBMI (1<<1)
63
64 %define FLAGS_CPUID7_ECX_AVX512_G1 (FLAG_CPUID7_EBX_AVX512F | FLAG_CPUID7_EBX_AVX512VL | FLAG_CPUID7_EBX_AVX512BW | FLAG_CPUID7_EBX_AVX512CD | FLAG_CPUID7_EBX_AVX512DQ)
65
66 %define FLAG_XGETBV_EAX_XMM (1<<1)
67 %define FLAG_XGETBV_EAX_YMM (1<<2)
68 %define FLAG_XGETBV_EAX_XMM_YMM 0x6
69 %define FLAG_XGETBV_EAX_ZMM_OPM 0xe0
70
71 %define FLAG_CPUID1_EAX_AVOTON 0x000406d0
72 %define FLAG_CPUID1_EAX_STEP_MASK 0xfffffff0
73
74 ; define d and w variants for registers
75
76 %define raxd eax
77 %define raxw ax
78 %define raxb al
79
80 %define rbxd ebx
81 %define rbxw bx
82 %define rbxb bl
83
84 %define rcxd ecx
85 %define rcxw cx
86 %define rcxb cl
87
88 %define rdxd edx
89 %define rdxw dx
90 %define rdxb dl
91
92 %define rsid esi
93 %define rsiw si
94 %define rsib sil
95
96 %define rdid edi
97 %define rdiw di
98 %define rdib dil
99
100 %define rbpd ebp
101 %define rbpw bp
102 %define rbpb bpl
103
104 %define ymm0x xmm0
105 %define ymm1x xmm1
106 %define ymm2x xmm2
107 %define ymm3x xmm3
108 %define ymm4x xmm4
109 %define ymm5x xmm5
110 %define ymm6x xmm6
111 %define ymm7x xmm7
112 %define ymm8x xmm8
113 %define ymm9x xmm9
114 %define ymm10x xmm10
115 %define ymm11x xmm11
116 %define ymm12x xmm12
117 %define ymm13x xmm13
118 %define ymm14x xmm14
119 %define ymm15x xmm15
120
121 %define DWORD(reg) reg %+ d
122 %define WORD(reg) reg %+ w
123 %define BYTE(reg) reg %+ b
124
125 %define XWORD(reg) reg %+ x
126
127 %ifidn __OUTPUT_FORMAT__,elf32
128 section .note.GNU-stack noalloc noexec nowrite progbits
129 section .text
130 %endif
131 %ifidn __OUTPUT_FORMAT__,elf64
132 section .note.GNU-stack noalloc noexec nowrite progbits
133 section .text
134 %endif
135 %ifidn __OUTPUT_FORMAT__, macho64
136 %define elf64 macho64
137 %endif
138
139 %macro slversion 4
140 section .text
141 global %1_slver_%2%3%4
142 global %1_slver
143 %1_slver:
144 %1_slver_%2%3%4:
145 dw 0x%4
146 db 0x%3, 0x%2
147 %endmacro
148
149 %endif ; ifndef _REG_SIZES_ASM_