ceph/src/spdk/dpdk/drivers/net/ixgbe/base/ixgbe_dcb_82598.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #ifndef _IXGBE_DCB_82598_H_
   6 #define _IXGBE_DCB_82598_H_
   7
   8 /* DCB register definitions */
   9
  10 #define IXGBE_DPMCS_MTSOS_SHIFT 16
  11 #define IXGBE_DPMCS_TDPAC       0x00000001 /* 0 Round Robin,
  12                                             * 1 DFP - Deficit Fixed Priority */
  13 #define IXGBE_DPMCS_TRM         0x00000010 /* Transmit Recycle Mode */
  14 #define IXGBE_DPMCS_ARBDIS      0x00000040 /* DCB arbiter disable */
  15 #define IXGBE_DPMCS_TSOEF       0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
  16
  17 #define IXGBE_RUPPBMR_MQA       0x80000000 /* Enable UP to queue mapping */
  18
  19 #define IXGBE_RT2CR_MCL_SHIFT   12 /* Offset to Max Credit Limit setting */
  20 #define IXGBE_RT2CR_LSP         0x80000000 /* LSP enable bit */
  21
  22 #define IXGBE_RDRXCTL_MPBEN     0x00000010 /* DMA config for multiple packet
  23                                             * buffers enable */
  24 #define IXGBE_RDRXCTL_MCEN      0x00000040 /* DMA config for multiple cores
  25                                             * (RSS) enable */
  26
  27 #define IXGBE_TDTQ2TCCR_MCL_SHIFT       12
  28 #define IXGBE_TDTQ2TCCR_BWG_SHIFT       9
  29 #define IXGBE_TDTQ2TCCR_GSP     0x40000000
  30 #define IXGBE_TDTQ2TCCR_LSP     0x80000000
  31
  32 #define IXGBE_TDPT2TCCR_MCL_SHIFT       12
  33 #define IXGBE_TDPT2TCCR_BWG_SHIFT       9
  34 #define IXGBE_TDPT2TCCR_GSP     0x40000000
  35 #define IXGBE_TDPT2TCCR_LSP     0x80000000
  36
  37 #define IXGBE_PDPMCS_TPPAC      0x00000020 /* 0 Round Robin,
  38                                             * 1 DFP - Deficit Fixed Priority */
  39 #define IXGBE_PDPMCS_ARBDIS     0x00000040 /* Arbiter disable */
  40 #define IXGBE_PDPMCS_TRM        0x00000100 /* Transmit Recycle Mode enable */
  41
  42 #define IXGBE_DTXCTL_ENDBUBD    0x00000004 /* Enable DBU buffer division */
  43
  44 #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
  45 #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
  46 #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
  47 #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
  48
  49 /* DCB driver APIs */
  50
  51 /* DCB PFC */
  52 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8);
  53
  54 /* DCB stats */
  55 s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *);
  56 s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *,
  57                                  struct ixgbe_hw_stats *, u8);
  58 s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *,
  59                                   struct ixgbe_hw_stats *, u8);
  60
  61 /* DCB config arbiters */
  62 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *,
  63                                            u8 *, u8 *);
  64 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *,
  65                                            u8 *, u8 *);
  66 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, u8 *);
  67
  68 /* DCB initialization */
  69 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, u8 *);
  70 #endif /* _IXGBE_DCB_82958_H_ */