1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
10 #include "ecore_status.h"
11 #include "ecore_chain.h"
12 #include "ecore_spq.h"
13 #include "ecore_init_fw_funcs.h"
14 #include "ecore_cxt.h"
15 #include "ecore_sp_commands.h"
16 #include "ecore_gtt_reg_addr.h"
17 #include "ecore_iro.h"
19 #include "ecore_int.h"
21 #include "ecore_dcbx.h"
22 #include "ecore_sriov.h"
25 enum _ecore_status_t
ecore_sp_init_request(struct ecore_hwfn
*p_hwfn
,
26 struct ecore_spq_entry
**pp_ent
,
29 struct ecore_sp_init_data
*p_data
)
31 u32 opaque_cid
= p_data
->opaque_fid
<< 16 | p_data
->cid
;
32 struct ecore_spq_entry
*p_ent
= OSAL_NULL
;
33 enum _ecore_status_t rc
;
38 /* Get an SPQ entry */
39 rc
= ecore_spq_get_entry(p_hwfn
, pp_ent
);
40 if (rc
!= ECORE_SUCCESS
)
43 /* Fill the SPQ entry */
45 p_ent
->elem
.hdr
.cid
= OSAL_CPU_TO_LE32(opaque_cid
);
46 p_ent
->elem
.hdr
.cmd_id
= cmd
;
47 p_ent
->elem
.hdr
.protocol_id
= protocol
;
48 p_ent
->priority
= ECORE_SPQ_PRIORITY_NORMAL
;
49 p_ent
->comp_mode
= p_data
->comp_mode
;
50 p_ent
->comp_done
.done
= 0;
52 switch (p_ent
->comp_mode
) {
53 case ECORE_SPQ_MODE_EBLOCK
:
54 p_ent
->comp_cb
.cookie
= &p_ent
->comp_done
;
57 case ECORE_SPQ_MODE_BLOCK
:
58 if (!p_data
->p_comp_data
)
61 p_ent
->comp_cb
.cookie
= p_data
->p_comp_data
->cookie
;
64 case ECORE_SPQ_MODE_CB
:
65 if (!p_data
->p_comp_data
)
66 p_ent
->comp_cb
.function
= OSAL_NULL
;
68 p_ent
->comp_cb
= *p_data
->p_comp_data
;
72 DP_NOTICE(p_hwfn
, true, "Unknown SPQE completion mode %d\n",
77 DP_VERBOSE(p_hwfn
, ECORE_MSG_SPQ
,
78 "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
79 opaque_cid
, cmd
, protocol
,
80 (unsigned long)&p_ent
->ramrod
,
81 D_TRINE(p_ent
->comp_mode
, ECORE_SPQ_MODE_EBLOCK
,
82 ECORE_SPQ_MODE_BLOCK
, "MODE_EBLOCK", "MODE_BLOCK",
85 OSAL_MEMSET(&p_ent
->ramrod
, 0, sizeof(p_ent
->ramrod
));
90 static enum tunnel_clss
ecore_tunn_clss_to_fw_clss(u8 type
)
93 case ECORE_TUNN_CLSS_MAC_VLAN
:
94 return TUNNEL_CLSS_MAC_VLAN
;
95 case ECORE_TUNN_CLSS_MAC_VNI
:
96 return TUNNEL_CLSS_MAC_VNI
;
97 case ECORE_TUNN_CLSS_INNER_MAC_VLAN
:
98 return TUNNEL_CLSS_INNER_MAC_VLAN
;
99 case ECORE_TUNN_CLSS_INNER_MAC_VNI
:
100 return TUNNEL_CLSS_INNER_MAC_VNI
;
101 case ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE
:
102 return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE
;
104 return TUNNEL_CLSS_MAC_VLAN
;
109 ecore_set_pf_update_tunn_mode(struct ecore_tunnel_info
*p_tun
,
110 struct ecore_tunnel_info
*p_src
,
113 if (p_src
->vxlan
.b_update_mode
|| b_pf_start
)
114 p_tun
->vxlan
.b_mode_enabled
= p_src
->vxlan
.b_mode_enabled
;
116 if (p_src
->l2_gre
.b_update_mode
|| b_pf_start
)
117 p_tun
->l2_gre
.b_mode_enabled
= p_src
->l2_gre
.b_mode_enabled
;
119 if (p_src
->ip_gre
.b_update_mode
|| b_pf_start
)
120 p_tun
->ip_gre
.b_mode_enabled
= p_src
->ip_gre
.b_mode_enabled
;
122 if (p_src
->l2_geneve
.b_update_mode
|| b_pf_start
)
123 p_tun
->l2_geneve
.b_mode_enabled
=
124 p_src
->l2_geneve
.b_mode_enabled
;
126 if (p_src
->ip_geneve
.b_update_mode
|| b_pf_start
)
127 p_tun
->ip_geneve
.b_mode_enabled
=
128 p_src
->ip_geneve
.b_mode_enabled
;
131 static void ecore_set_tunn_cls_info(struct ecore_tunnel_info
*p_tun
,
132 struct ecore_tunnel_info
*p_src
)
134 enum tunnel_clss type
;
136 p_tun
->b_update_rx_cls
= p_src
->b_update_rx_cls
;
137 p_tun
->b_update_tx_cls
= p_src
->b_update_tx_cls
;
139 /* @DPDK - typecast tunnul class */
140 type
= ecore_tunn_clss_to_fw_clss(p_src
->vxlan
.tun_cls
);
141 p_tun
->vxlan
.tun_cls
= (enum ecore_tunn_clss
)type
;
142 type
= ecore_tunn_clss_to_fw_clss(p_src
->l2_gre
.tun_cls
);
143 p_tun
->l2_gre
.tun_cls
= (enum ecore_tunn_clss
)type
;
144 type
= ecore_tunn_clss_to_fw_clss(p_src
->ip_gre
.tun_cls
);
145 p_tun
->ip_gre
.tun_cls
= (enum ecore_tunn_clss
)type
;
146 type
= ecore_tunn_clss_to_fw_clss(p_src
->l2_geneve
.tun_cls
);
147 p_tun
->l2_geneve
.tun_cls
= (enum ecore_tunn_clss
)type
;
148 type
= ecore_tunn_clss_to_fw_clss(p_src
->ip_geneve
.tun_cls
);
149 p_tun
->ip_geneve
.tun_cls
= (enum ecore_tunn_clss
)type
;
152 static void ecore_set_tunn_ports(struct ecore_tunnel_info
*p_tun
,
153 struct ecore_tunnel_info
*p_src
)
155 p_tun
->geneve_port
.b_update_port
= p_src
->geneve_port
.b_update_port
;
156 p_tun
->vxlan_port
.b_update_port
= p_src
->vxlan_port
.b_update_port
;
158 if (p_src
->geneve_port
.b_update_port
)
159 p_tun
->geneve_port
.port
= p_src
->geneve_port
.port
;
161 if (p_src
->vxlan_port
.b_update_port
)
162 p_tun
->vxlan_port
.port
= p_src
->vxlan_port
.port
;
166 __ecore_set_ramrod_tunnel_param(u8
*p_tunn_cls
,
167 struct ecore_tunn_update_type
*tun_type
)
169 *p_tunn_cls
= tun_type
->tun_cls
;
173 ecore_set_ramrod_tunnel_param(u8
*p_tunn_cls
,
174 struct ecore_tunn_update_type
*tun_type
,
175 u8
*p_update_port
, __le16
*p_port
,
176 struct ecore_tunn_update_udp_port
*p_udp_port
)
178 __ecore_set_ramrod_tunnel_param(p_tunn_cls
, tun_type
);
179 if (p_udp_port
->b_update_port
) {
181 *p_port
= OSAL_CPU_TO_LE16(p_udp_port
->port
);
186 ecore_tunn_set_pf_update_params(struct ecore_hwfn
*p_hwfn
,
187 struct ecore_tunnel_info
*p_src
,
188 struct pf_update_tunnel_config
*p_tunn_cfg
)
190 struct ecore_tunnel_info
*p_tun
= &p_hwfn
->p_dev
->tunnel
;
192 ecore_set_pf_update_tunn_mode(p_tun
, p_src
, false);
193 ecore_set_tunn_cls_info(p_tun
, p_src
);
194 ecore_set_tunn_ports(p_tun
, p_src
);
196 ecore_set_ramrod_tunnel_param(&p_tunn_cfg
->tunnel_clss_vxlan
,
198 &p_tunn_cfg
->set_vxlan_udp_port_flg
,
199 &p_tunn_cfg
->vxlan_udp_port
,
202 ecore_set_ramrod_tunnel_param(&p_tunn_cfg
->tunnel_clss_l2geneve
,
204 &p_tunn_cfg
->set_geneve_udp_port_flg
,
205 &p_tunn_cfg
->geneve_udp_port
,
206 &p_tun
->geneve_port
);
208 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg
->tunnel_clss_ipgeneve
,
211 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg
->tunnel_clss_l2gre
,
214 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg
->tunnel_clss_ipgre
,
217 p_tunn_cfg
->update_rx_pf_clss
= p_tun
->b_update_rx_cls
;
220 static void ecore_set_hw_tunn_mode(struct ecore_hwfn
*p_hwfn
,
221 struct ecore_ptt
*p_ptt
,
222 struct ecore_tunnel_info
*p_tun
)
224 ecore_set_gre_enable(p_hwfn
, p_ptt
, p_tun
->l2_gre
.b_mode_enabled
,
225 p_tun
->ip_gre
.b_mode_enabled
);
226 ecore_set_vxlan_enable(p_hwfn
, p_ptt
, p_tun
->vxlan
.b_mode_enabled
);
228 ecore_set_geneve_enable(p_hwfn
, p_ptt
, p_tun
->l2_geneve
.b_mode_enabled
,
229 p_tun
->ip_geneve
.b_mode_enabled
);
232 static void ecore_set_hw_tunn_mode_port(struct ecore_hwfn
*p_hwfn
,
233 struct ecore_ptt
*p_ptt
,
234 struct ecore_tunnel_info
*p_tunn
)
236 if (ECORE_IS_BB_A0(p_hwfn
->p_dev
)) {
237 DP_NOTICE(p_hwfn
, true,
238 "A0 chip: tunnel hw config is not supported\n");
242 if (p_tunn
->vxlan_port
.b_update_port
)
243 ecore_set_vxlan_dest_port(p_hwfn
, p_ptt
,
244 p_tunn
->vxlan_port
.port
);
246 if (p_tunn
->geneve_port
.b_update_port
)
247 ecore_set_geneve_dest_port(p_hwfn
, p_ptt
,
248 p_tunn
->geneve_port
.port
);
250 ecore_set_hw_tunn_mode(p_hwfn
, p_ptt
, p_tunn
);
254 ecore_tunn_set_pf_start_params(struct ecore_hwfn
*p_hwfn
,
255 struct ecore_tunnel_info
*p_src
,
256 struct pf_start_tunnel_config
*p_tunn_cfg
)
258 struct ecore_tunnel_info
*p_tun
= &p_hwfn
->p_dev
->tunnel
;
260 if (ECORE_IS_BB_A0(p_hwfn
->p_dev
)) {
261 DP_NOTICE(p_hwfn
, true,
262 "A0 chip: tunnel pf start config is not supported\n");
269 ecore_set_pf_update_tunn_mode(p_tun
, p_src
, true);
270 ecore_set_tunn_cls_info(p_tun
, p_src
);
271 ecore_set_tunn_ports(p_tun
, p_src
);
273 ecore_set_ramrod_tunnel_param(&p_tunn_cfg
->tunnel_clss_vxlan
,
275 &p_tunn_cfg
->set_vxlan_udp_port_flg
,
276 &p_tunn_cfg
->vxlan_udp_port
,
279 ecore_set_ramrod_tunnel_param(&p_tunn_cfg
->tunnel_clss_l2geneve
,
281 &p_tunn_cfg
->set_geneve_udp_port_flg
,
282 &p_tunn_cfg
->geneve_udp_port
,
283 &p_tun
->geneve_port
);
285 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg
->tunnel_clss_ipgeneve
,
288 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg
->tunnel_clss_l2gre
,
291 __ecore_set_ramrod_tunnel_param(&p_tunn_cfg
->tunnel_clss_ipgre
,
295 #define ETH_P_8021Q 0x8100
296 #define ETH_P_8021AD 0x88A8 /* 802.1ad Service VLAN */
298 enum _ecore_status_t
ecore_sp_pf_start(struct ecore_hwfn
*p_hwfn
,
299 struct ecore_ptt
*p_ptt
,
300 struct ecore_tunnel_info
*p_tunn
,
301 bool allow_npar_tx_switch
)
303 struct pf_start_ramrod_data
*p_ramrod
= OSAL_NULL
;
304 u16 sb
= ecore_int_get_sp_sb_id(p_hwfn
);
305 u8 sb_index
= p_hwfn
->p_eq
->eq_sb_index
;
306 struct ecore_spq_entry
*p_ent
= OSAL_NULL
;
307 struct ecore_sp_init_data init_data
;
308 enum _ecore_status_t rc
= ECORE_NOTIMPL
;
312 /* update initial eq producer */
313 ecore_eq_prod_update(p_hwfn
,
314 ecore_chain_get_prod_idx(&p_hwfn
->p_eq
->chain
));
316 /* Initialize the SPQ entry for the ramrod */
317 OSAL_MEMSET(&init_data
, 0, sizeof(init_data
));
318 init_data
.cid
= ecore_spq_get_cid(p_hwfn
);
319 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
320 init_data
.comp_mode
= ECORE_SPQ_MODE_EBLOCK
;
322 rc
= ecore_sp_init_request(p_hwfn
, &p_ent
,
323 COMMON_RAMROD_PF_START
,
324 PROTOCOLID_COMMON
, &init_data
);
325 if (rc
!= ECORE_SUCCESS
)
328 /* Fill the ramrod data */
329 p_ramrod
= &p_ent
->ramrod
.pf_start
;
330 p_ramrod
->event_ring_sb_id
= OSAL_CPU_TO_LE16(sb
);
331 p_ramrod
->event_ring_sb_index
= sb_index
;
332 p_ramrod
->path_id
= ECORE_PATH_ID(p_hwfn
);
334 /* For easier debugging */
335 p_ramrod
->dont_log_ramrods
= 0;
336 p_ramrod
->log_type_mask
= OSAL_CPU_TO_LE16(0x8f);
338 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS
, &p_hwfn
->p_dev
->mf_bits
))
339 p_ramrod
->mf_mode
= MF_OVLAN
;
341 p_ramrod
->mf_mode
= MF_NPAR
;
343 p_ramrod
->outer_tag_config
.outer_tag
.tci
=
344 OSAL_CPU_TO_LE16(p_hwfn
->hw_info
.ovlan
);
345 if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING
, &p_hwfn
->p_dev
->mf_bits
)) {
346 p_ramrod
->outer_tag_config
.outer_tag
.tpid
= ETH_P_8021Q
;
347 } else if (OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING
,
348 &p_hwfn
->p_dev
->mf_bits
)) {
349 p_ramrod
->outer_tag_config
.outer_tag
.tpid
= ETH_P_8021AD
;
350 p_ramrod
->outer_tag_config
.enable_stag_pri_change
= 1;
353 p_ramrod
->outer_tag_config
.pri_map_valid
= 1;
354 for (i
= 0; i
< ECORE_MAX_PFC_PRIORITIES
; i
++)
355 p_ramrod
->outer_tag_config
.inner_to_outer_pri_map
[i
] = i
;
357 /* enable_stag_pri_change should be set if port is in BD mode or,
358 * UFP with Host Control mode or, UFP with DCB over base interface.
360 if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC
, &p_hwfn
->p_dev
->mf_bits
)) {
361 if ((p_hwfn
->ufp_info
.pri_type
== ECORE_UFP_PRI_OS
) ||
362 (p_hwfn
->p_dcbx_info
->results
.dcbx_enabled
))
363 p_ramrod
->outer_tag_config
.enable_stag_pri_change
= 1;
365 p_ramrod
->outer_tag_config
.enable_stag_pri_change
= 0;
368 /* Place EQ address in RAMROD */
369 DMA_REGPAIR_LE(p_ramrod
->event_ring_pbl_addr
,
370 p_hwfn
->p_eq
->chain
.pbl_sp
.p_phys_table
);
371 page_cnt
= (u8
)ecore_chain_get_page_cnt(&p_hwfn
->p_eq
->chain
);
372 p_ramrod
->event_ring_num_pages
= page_cnt
;
373 DMA_REGPAIR_LE(p_ramrod
->consolid_q_pbl_addr
,
374 p_hwfn
->p_consq
->chain
.pbl_sp
.p_phys_table
);
376 ecore_tunn_set_pf_start_params(p_hwfn
, p_tunn
,
377 &p_ramrod
->tunnel_config
);
379 if (OSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH
,
380 &p_hwfn
->p_dev
->mf_bits
))
381 p_ramrod
->allow_npar_tx_switching
= allow_npar_tx_switch
;
383 switch (p_hwfn
->hw_info
.personality
) {
385 p_ramrod
->personality
= PERSONALITY_ETH
;
388 DP_NOTICE(p_hwfn
, true, "Unknown personality %d\n",
389 p_hwfn
->hw_info
.personality
);
390 p_ramrod
->personality
= PERSONALITY_ETH
;
393 if (p_hwfn
->p_dev
->p_iov_info
) {
394 struct ecore_hw_sriov_info
*p_iov
= p_hwfn
->p_dev
->p_iov_info
;
396 p_ramrod
->base_vf_id
= (u8
)p_iov
->first_vf_in_pf
;
397 p_ramrod
->num_vfs
= (u8
)p_iov
->total_vfs
;
399 /* @@@TBD - update also the "ROCE_VER_KEY" entries when the FW RoCE HSI
400 * version is available.
402 p_ramrod
->hsi_fp_ver
.major_ver_arr
[ETH_VER_KEY
] = ETH_HSI_VER_MAJOR
;
403 p_ramrod
->hsi_fp_ver
.minor_ver_arr
[ETH_VER_KEY
] = ETH_HSI_VER_MINOR
;
405 DP_VERBOSE(p_hwfn
, ECORE_MSG_SPQ
,
406 "Setting event_ring_sb [id %04x index %02x], outer_tag.tpid [%d], outer_tag.tci [%d]\n",
407 sb
, sb_index
, p_ramrod
->outer_tag_config
.outer_tag
.tpid
,
408 p_ramrod
->outer_tag_config
.outer_tag
.tci
);
410 rc
= ecore_spq_post(p_hwfn
, p_ent
, OSAL_NULL
);
413 ecore_set_hw_tunn_mode_port(p_hwfn
, p_ptt
,
414 &p_hwfn
->p_dev
->tunnel
);
419 enum _ecore_status_t
ecore_sp_pf_update_dcbx(struct ecore_hwfn
*p_hwfn
)
421 struct ecore_spq_entry
*p_ent
= OSAL_NULL
;
422 struct ecore_sp_init_data init_data
;
423 enum _ecore_status_t rc
= ECORE_NOTIMPL
;
426 OSAL_MEMSET(&init_data
, 0, sizeof(init_data
));
427 init_data
.cid
= ecore_spq_get_cid(p_hwfn
);
428 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
429 init_data
.comp_mode
= ECORE_SPQ_MODE_CB
;
431 rc
= ecore_sp_init_request(p_hwfn
, &p_ent
,
432 COMMON_RAMROD_PF_UPDATE
, PROTOCOLID_COMMON
,
434 if (rc
!= ECORE_SUCCESS
)
437 ecore_dcbx_set_pf_update_params(&p_hwfn
->p_dcbx_info
->results
,
438 &p_ent
->ramrod
.pf_update
);
440 return ecore_spq_post(p_hwfn
, p_ent
, OSAL_NULL
);
443 enum _ecore_status_t
ecore_sp_pf_update_ufp(struct ecore_hwfn
*p_hwfn
)
445 struct ecore_spq_entry
*p_ent
= OSAL_NULL
;
446 struct ecore_sp_init_data init_data
;
447 enum _ecore_status_t rc
= ECORE_NOTIMPL
;
450 OSAL_MEMSET(&init_data
, 0, sizeof(init_data
));
451 init_data
.cid
= ecore_spq_get_cid(p_hwfn
);
452 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
453 init_data
.comp_mode
= ECORE_SPQ_MODE_CB
;
455 rc
= ecore_sp_init_request(p_hwfn
, &p_ent
,
456 COMMON_RAMROD_PF_UPDATE
, PROTOCOLID_COMMON
,
458 if (rc
!= ECORE_SUCCESS
)
461 p_ent
->ramrod
.pf_update
.update_enable_stag_pri_change
= true;
462 if ((p_hwfn
->ufp_info
.pri_type
== ECORE_UFP_PRI_OS
) ||
463 (p_hwfn
->p_dcbx_info
->results
.dcbx_enabled
))
464 p_ent
->ramrod
.pf_update
.enable_stag_pri_change
= 1;
466 p_ent
->ramrod
.pf_update
.enable_stag_pri_change
= 0;
468 return ecore_spq_post(p_hwfn
, p_ent
, OSAL_NULL
);
472 /* QM rate limiter resolution is 1.6Mbps */
473 #define QM_RL_RESOLUTION(mb_val) ((mb_val) * 10 / 16)
475 /* FW uses 1/64k to express gd */
476 #define FW_GD_RESOLUTION(gd) (64 * 1024 / (gd))
478 u16
ecore_sp_rl_mb_to_qm(u32 mb_val
)
480 return (u16
)OSAL_MIN_T(u32
, (u16
)(~0U), QM_RL_RESOLUTION(mb_val
));
483 u16
ecore_sp_rl_gd_denom(u32 gd
)
485 return gd
? (u16
)OSAL_MIN_T(u32
, (u16
)(~0U), FW_GD_RESOLUTION(gd
)) : 0;
488 enum _ecore_status_t
ecore_sp_rl_update(struct ecore_hwfn
*p_hwfn
,
489 struct ecore_rl_update_params
*params
)
491 struct ecore_spq_entry
*p_ent
= OSAL_NULL
;
492 enum _ecore_status_t rc
= ECORE_NOTIMPL
;
493 struct rl_update_ramrod_data
*rl_update
;
494 struct ecore_sp_init_data init_data
;
497 OSAL_MEMSET(&init_data
, 0, sizeof(init_data
));
498 init_data
.cid
= ecore_spq_get_cid(p_hwfn
);
499 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
500 init_data
.comp_mode
= ECORE_SPQ_MODE_EBLOCK
;
502 rc
= ecore_sp_init_request(p_hwfn
, &p_ent
,
503 COMMON_RAMROD_RL_UPDATE
, PROTOCOLID_COMMON
,
505 if (rc
!= ECORE_SUCCESS
)
508 rl_update
= &p_ent
->ramrod
.rl_update
;
510 rl_update
->qcn_update_param_flg
= params
->qcn_update_param_flg
;
511 rl_update
->dcqcn_update_param_flg
= params
->dcqcn_update_param_flg
;
512 rl_update
->rl_init_flg
= params
->rl_init_flg
;
513 rl_update
->rl_start_flg
= params
->rl_start_flg
;
514 rl_update
->rl_stop_flg
= params
->rl_stop_flg
;
515 rl_update
->rl_id_first
= params
->rl_id_first
;
516 rl_update
->rl_id_last
= params
->rl_id_last
;
517 rl_update
->rl_dc_qcn_flg
= params
->rl_dc_qcn_flg
;
518 rl_update
->dcqcn_reset_alpha_on_idle
=
519 params
->dcqcn_reset_alpha_on_idle
;
520 rl_update
->rl_bc_stage_th
= params
->rl_bc_stage_th
;
521 rl_update
->rl_timer_stage_th
= params
->rl_timer_stage_th
;
522 rl_update
->rl_bc_rate
= OSAL_CPU_TO_LE32(params
->rl_bc_rate
);
523 rl_update
->rl_max_rate
=
524 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params
->rl_max_rate
));
526 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params
->rl_r_ai
));
527 rl_update
->rl_r_hai
=
528 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params
->rl_r_hai
));
530 OSAL_CPU_TO_LE16(ecore_sp_rl_gd_denom(params
->dcqcn_gd
));
531 rl_update
->dcqcn_k_us
= OSAL_CPU_TO_LE32(params
->dcqcn_k_us
);
532 rl_update
->dcqcn_timeuot_us
=
533 OSAL_CPU_TO_LE32(params
->dcqcn_timeuot_us
);
534 rl_update
->qcn_timeuot_us
= OSAL_CPU_TO_LE32(params
->qcn_timeuot_us
);
536 DP_VERBOSE(p_hwfn
, ECORE_MSG_SPQ
, "rl_params: qcn_update_param_flg %x, dcqcn_update_param_flg %x, rl_init_flg %x, rl_start_flg %x, rl_stop_flg %x, rl_id_first %x, rl_id_last %x, rl_dc_qcn_flg %x,dcqcn_reset_alpha_on_idle %x, rl_bc_stage_th %x, rl_timer_stage_th %x, rl_bc_rate %x, rl_max_rate %x, rl_r_ai %x, rl_r_hai %x, dcqcn_g %x, dcqcn_k_us %x, dcqcn_timeuot_us %x, qcn_timeuot_us %x\n",
537 rl_update
->qcn_update_param_flg
,
538 rl_update
->dcqcn_update_param_flg
,
539 rl_update
->rl_init_flg
, rl_update
->rl_start_flg
,
540 rl_update
->rl_stop_flg
, rl_update
->rl_id_first
,
541 rl_update
->rl_id_last
, rl_update
->rl_dc_qcn_flg
,
542 rl_update
->dcqcn_reset_alpha_on_idle
,
543 rl_update
->rl_bc_stage_th
, rl_update
->rl_timer_stage_th
,
544 rl_update
->rl_bc_rate
, rl_update
->rl_max_rate
,
545 rl_update
->rl_r_ai
, rl_update
->rl_r_hai
,
546 rl_update
->dcqcn_g
, rl_update
->dcqcn_k_us
,
547 rl_update
->dcqcn_timeuot_us
, rl_update
->qcn_timeuot_us
);
549 return ecore_spq_post(p_hwfn
, p_ent
, OSAL_NULL
);
552 /* Set pf update ramrod command params */
554 ecore_sp_pf_update_tunn_cfg(struct ecore_hwfn
*p_hwfn
,
555 struct ecore_ptt
*p_ptt
,
556 struct ecore_tunnel_info
*p_tunn
,
557 enum spq_mode comp_mode
,
558 struct ecore_spq_comp_cb
*p_comp_data
)
560 struct ecore_spq_entry
*p_ent
= OSAL_NULL
;
561 struct ecore_sp_init_data init_data
;
562 enum _ecore_status_t rc
= ECORE_NOTIMPL
;
564 if (IS_VF(p_hwfn
->p_dev
))
565 return ecore_vf_pf_tunnel_param_update(p_hwfn
, p_tunn
);
567 if (ECORE_IS_BB_A0(p_hwfn
->p_dev
)) {
568 DP_NOTICE(p_hwfn
, true,
569 "A0 chip: tunnel pf update config is not supported\n");
577 OSAL_MEMSET(&init_data
, 0, sizeof(init_data
));
578 init_data
.cid
= ecore_spq_get_cid(p_hwfn
);
579 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
580 init_data
.comp_mode
= comp_mode
;
581 init_data
.p_comp_data
= p_comp_data
;
583 rc
= ecore_sp_init_request(p_hwfn
, &p_ent
,
584 COMMON_RAMROD_PF_UPDATE
, PROTOCOLID_COMMON
,
586 if (rc
!= ECORE_SUCCESS
)
589 ecore_tunn_set_pf_update_params(p_hwfn
, p_tunn
,
590 &p_ent
->ramrod
.pf_update
.tunnel_config
);
592 rc
= ecore_spq_post(p_hwfn
, p_ent
, OSAL_NULL
);
593 if (rc
!= ECORE_SUCCESS
)
596 ecore_set_hw_tunn_mode_port(p_hwfn
, p_ptt
, &p_hwfn
->p_dev
->tunnel
);
601 enum _ecore_status_t
ecore_sp_pf_stop(struct ecore_hwfn
*p_hwfn
)
603 struct ecore_spq_entry
*p_ent
= OSAL_NULL
;
604 struct ecore_sp_init_data init_data
;
605 enum _ecore_status_t rc
= ECORE_NOTIMPL
;
608 OSAL_MEMSET(&init_data
, 0, sizeof(init_data
));
609 init_data
.cid
= ecore_spq_get_cid(p_hwfn
);
610 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
611 init_data
.comp_mode
= ECORE_SPQ_MODE_EBLOCK
;
613 rc
= ecore_sp_init_request(p_hwfn
, &p_ent
,
614 COMMON_RAMROD_PF_STOP
, PROTOCOLID_COMMON
,
616 if (rc
!= ECORE_SUCCESS
)
619 return ecore_spq_post(p_hwfn
, p_ent
, OSAL_NULL
);
622 enum _ecore_status_t
ecore_sp_heartbeat_ramrod(struct ecore_hwfn
*p_hwfn
)
624 struct ecore_spq_entry
*p_ent
= OSAL_NULL
;
625 struct ecore_sp_init_data init_data
;
626 enum _ecore_status_t rc
;
629 OSAL_MEMSET(&init_data
, 0, sizeof(init_data
));
630 init_data
.cid
= ecore_spq_get_cid(p_hwfn
);
631 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
632 init_data
.comp_mode
= ECORE_SPQ_MODE_EBLOCK
;
634 rc
= ecore_sp_init_request(p_hwfn
, &p_ent
,
635 COMMON_RAMROD_EMPTY
, PROTOCOLID_COMMON
,
637 if (rc
!= ECORE_SUCCESS
)
640 return ecore_spq_post(p_hwfn
, p_ent
, OSAL_NULL
);
643 enum _ecore_status_t
ecore_sp_pf_update_stag(struct ecore_hwfn
*p_hwfn
)
645 struct ecore_spq_entry
*p_ent
= OSAL_NULL
;
646 struct ecore_sp_init_data init_data
;
647 enum _ecore_status_t rc
= ECORE_NOTIMPL
;
650 OSAL_MEMSET(&init_data
, 0, sizeof(init_data
));
651 init_data
.cid
= ecore_spq_get_cid(p_hwfn
);
652 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
653 init_data
.comp_mode
= ECORE_SPQ_MODE_CB
;
655 rc
= ecore_sp_init_request(p_hwfn
, &p_ent
,
656 COMMON_RAMROD_PF_UPDATE
, PROTOCOLID_COMMON
,
658 if (rc
!= ECORE_SUCCESS
)
661 p_ent
->ramrod
.pf_update
.update_mf_vlan_flag
= true;
662 p_ent
->ramrod
.pf_update
.mf_vlan
=
663 OSAL_CPU_TO_LE16(p_hwfn
->hw_info
.ovlan
);
665 return ecore_spq_post(p_hwfn
, p_ent
, OSAL_NULL
);