compiler/rustc_target/src/spec/powerpc_wrs_vxworks_spe.rs

   1 use crate::abi::Endian;
   2 use crate::spec::{LinkerFlavor, Target, TargetOptions};
   3
   4 pub fn target() -> Target {
   5     let mut base = super::vxworks_base::opts();
   6     base.pre_link_args.entry(LinkerFlavor::Gcc).or_default().push("-mspe".to_string());
   7     base.pre_link_args.entry(LinkerFlavor::Gcc).or_default().push("--secure-plt".to_string());
   8     base.max_atomic_width = Some(32);
   9
  10     Target {
  11         llvm_target: "powerpc-unknown-linux-gnuspe".to_string(),
  12         pointer_width: 32,
  13         data_layout: "E-m:e-p:32:32-i64:64-n32".to_string(),
  14         arch: "powerpc".to_string(),
  15         options: TargetOptions {
  16             abi: "spe".to_string(),
  17             endian: Endian::Big,
  18             // feature msync would disable instruction 'fsync' which is not supported by fsl_p1p2
  19             features: "+secure-plt,+msync".to_string(),
  20             ..base
  21         },
  22     }
  23 }