compiler/rustc_target/src/spec/thumbv7em_none_eabihf.rs

   1 // Targets the Cortex-M4F and Cortex-M7F processors (ARMv7E-M)
   2 //
   3 // This target assumes that the device does have a FPU (Floating Point Unit) and lowers all (single
   4 // precision) floating point operations to hardware instructions.
   5 //
   6 // Additionally, this target uses the "hard" floating convention (ABI) where floating point values
   7 // are passed to/from subroutines via FPU registers (S0, S1, D0, D1, etc.).
   8 //
   9 // To opt into double precision hardware support, use the `-C target-feature=+fp64` flag.
  10
  11 use crate::spec::{Target, TargetOptions};
  12
  13 pub fn target() -> Target {
  14     Target {
  15         llvm_target: "thumbv7em-none-eabihf".to_string(),
  16         pointer_width: 32,
  17         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".to_string(),
  18         arch: "arm".to_string(),
  19
  20         options: TargetOptions {
  21             abi: "eabihf".to_string(),
  22             // `+vfp4` is the lowest common denominator between the Cortex-M4 (vfp4-16) and the
  23             // Cortex-M7 (vfp5)
  24             // `-d32` both the Cortex-M4 and the Cortex-M7 only have 16 double-precision registers
  25             // available
  26             // `-fp64` The Cortex-M4 only supports single precision floating point operations
  27             // whereas in the Cortex-M7 double precision is optional
  28             //
  29             // Reference:
  30             // ARMv7-M Architecture Reference Manual - A2.5 The optional floating-point extension
  31             features: "+vfp4,-d32,-fp64".to_string(),
  32             max_atomic_width: Some(32),
  33             ..super::thumb_base::opts()
  34         },
  35     }
  36 }