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2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #if !defined(CONFIG_SOFTMMU)
39 #include <sys/ucontext.h>
43 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
44 // Work around ugly bugs in glibc that mangle global register contents
46 #define env cpu_single_env
49 int tb_invalidated_flag
;
51 //#define CONFIG_DEBUG_EXEC
52 //#define DEBUG_SIGNAL
54 int qemu_cpu_has_work(CPUState
*env
)
56 return cpu_has_work(env
);
59 void cpu_loop_exit(void)
61 env
->current_tb
= NULL
;
62 longjmp(env
->jmp_env
, 1);
65 /* exit the current TB from a signal handler. The host registers are
66 restored in a state compatible with the CPU emulator
68 void cpu_resume_from_signal(CPUState
*env1
, void *puc
)
70 #if !defined(CONFIG_SOFTMMU)
72 struct ucontext
*uc
= puc
;
73 #elif defined(__OpenBSD__)
74 struct sigcontext
*uc
= puc
;
80 /* XXX: restore cpu registers saved in host registers */
82 #if !defined(CONFIG_SOFTMMU)
84 /* XXX: use siglongjmp ? */
86 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
87 #elif defined(__OpenBSD__)
88 sigprocmask(SIG_SETMASK
, &uc
->sc_mask
, NULL
);
92 env
->exception_index
= -1;
93 longjmp(env
->jmp_env
, 1);
96 /* Execute the code without caching the generated code. An interpreter
97 could be used if available. */
98 static void cpu_exec_nocache(int max_cycles
, TranslationBlock
*orig_tb
)
100 unsigned long next_tb
;
101 TranslationBlock
*tb
;
103 /* Should never happen.
104 We only end up here when an existing TB is too long. */
105 if (max_cycles
> CF_COUNT_MASK
)
106 max_cycles
= CF_COUNT_MASK
;
108 tb
= tb_gen_code(env
, orig_tb
->pc
, orig_tb
->cs_base
, orig_tb
->flags
,
110 env
->current_tb
= tb
;
111 /* execute the generated code */
112 next_tb
= tcg_qemu_tb_exec(tb
->tc_ptr
);
113 env
->current_tb
= NULL
;
115 if ((next_tb
& 3) == 2) {
116 /* Restore PC. This may happen if async event occurs before
117 the TB starts executing. */
118 cpu_pc_from_tb(env
, tb
);
120 tb_phys_invalidate(tb
, -1);
124 static TranslationBlock
*tb_find_slow(target_ulong pc
,
125 target_ulong cs_base
,
128 TranslationBlock
*tb
, **ptb1
;
130 target_ulong phys_pc
, phys_page1
, phys_page2
, virt_page2
;
132 tb_invalidated_flag
= 0;
134 /* find translated block using physical mappings */
135 phys_pc
= get_phys_addr_code(env
, pc
);
136 phys_page1
= phys_pc
& TARGET_PAGE_MASK
;
138 h
= tb_phys_hash_func(phys_pc
);
139 ptb1
= &tb_phys_hash
[h
];
145 tb
->page_addr
[0] == phys_page1
&&
146 tb
->cs_base
== cs_base
&&
147 tb
->flags
== flags
) {
148 /* check next page if needed */
149 if (tb
->page_addr
[1] != -1) {
150 virt_page2
= (pc
& TARGET_PAGE_MASK
) +
152 phys_page2
= get_phys_addr_code(env
, virt_page2
);
153 if (tb
->page_addr
[1] == phys_page2
)
159 ptb1
= &tb
->phys_hash_next
;
162 /* if no translated code available, then translate it now */
163 tb
= tb_gen_code(env
, pc
, cs_base
, flags
, 0);
166 /* we add the TB in the virtual pc hash table */
167 env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)] = tb
;
171 static inline TranslationBlock
*tb_find_fast(void)
173 TranslationBlock
*tb
;
174 target_ulong cs_base
, pc
;
177 /* we record a subset of the CPU state. It will
178 always be the same before a given translated block
180 cpu_get_tb_cpu_state(env
, &pc
, &cs_base
, &flags
);
181 tb
= env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)];
182 if (unlikely(!tb
|| tb
->pc
!= pc
|| tb
->cs_base
!= cs_base
||
183 tb
->flags
!= flags
)) {
184 tb
= tb_find_slow(pc
, cs_base
, flags
);
189 static CPUDebugExcpHandler
*debug_excp_handler
;
191 CPUDebugExcpHandler
*cpu_set_debug_excp_handler(CPUDebugExcpHandler
*handler
)
193 CPUDebugExcpHandler
*old_handler
= debug_excp_handler
;
195 debug_excp_handler
= handler
;
199 static void cpu_handle_debug_exception(CPUState
*env
)
203 if (!env
->watchpoint_hit
)
204 QTAILQ_FOREACH(wp
, &env
->watchpoints
, entry
)
205 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
207 if (debug_excp_handler
)
208 debug_excp_handler(env
);
211 /* main execution loop */
213 int cpu_exec(CPUState
*env1
)
215 #define DECLARE_HOST_REGS 1
216 #include "hostregs_helper.h"
217 int ret
, interrupt_request
;
218 TranslationBlock
*tb
;
220 unsigned long next_tb
;
222 if (cpu_halted(env1
) == EXCP_HALTED
)
225 cpu_single_env
= env1
;
227 /* first we save global registers */
228 #define SAVE_HOST_REGS 1
229 #include "hostregs_helper.h"
232 #if defined(TARGET_I386)
233 /* put eflags in CPU temporary format */
234 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
235 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
236 CC_OP
= CC_OP_EFLAGS
;
237 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
238 #elif defined(TARGET_SPARC)
239 #elif defined(TARGET_M68K)
240 env
->cc_op
= CC_OP_FLAGS
;
241 env
->cc_dest
= env
->sr
& 0xf;
242 env
->cc_x
= (env
->sr
>> 4) & 1;
243 #elif defined(TARGET_ALPHA)
244 #elif defined(TARGET_ARM)
245 #elif defined(TARGET_PPC)
246 #elif defined(TARGET_MICROBLAZE)
247 #elif defined(TARGET_MIPS)
248 #elif defined(TARGET_SH4)
249 #elif defined(TARGET_CRIS)
250 #elif defined(TARGET_S390X)
253 #error unsupported target CPU
255 env
->exception_index
= -1;
257 /* prepare setjmp context for exception handling */
259 if (setjmp(env
->jmp_env
) == 0) {
260 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
262 env
= cpu_single_env
;
263 #define env cpu_single_env
265 assert (env
->current_tb
== NULL
);
266 /* if an exception is pending, we execute it here */
267 if (env
->exception_index
>= 0) {
268 if (env
->exception_index
>= EXCP_INTERRUPT
) {
269 /* exit request from the cpu execution loop */
270 ret
= env
->exception_index
;
271 if (ret
== EXCP_DEBUG
)
272 cpu_handle_debug_exception(env
);
275 #if defined(CONFIG_USER_ONLY)
276 /* if user mode only, we simulate a fake exception
277 which will be handled outside the cpu execution
279 #if defined(TARGET_I386)
280 do_interrupt_user(env
->exception_index
,
281 env
->exception_is_int
,
283 env
->exception_next_eip
);
284 /* successfully delivered */
285 env
->old_exception
= -1;
287 ret
= env
->exception_index
;
290 #if defined(TARGET_I386)
291 /* simulate a real cpu exception. On i386, it can
292 trigger new exceptions, but we do not handle
293 double or triple faults yet. */
294 do_interrupt(env
->exception_index
,
295 env
->exception_is_int
,
297 env
->exception_next_eip
, 0);
298 /* successfully delivered */
299 env
->old_exception
= -1;
300 #elif defined(TARGET_PPC)
302 #elif defined(TARGET_MICROBLAZE)
304 #elif defined(TARGET_MIPS)
306 #elif defined(TARGET_SPARC)
308 #elif defined(TARGET_ARM)
310 #elif defined(TARGET_SH4)
312 #elif defined(TARGET_ALPHA)
314 #elif defined(TARGET_CRIS)
316 #elif defined(TARGET_M68K)
321 env
->exception_index
= -1;
326 longjmp(env
->jmp_env
, 1);
329 next_tb
= 0; /* force lookup of first TB */
331 interrupt_request
= env
->interrupt_request
;
332 if (unlikely(interrupt_request
)) {
333 if (unlikely(env
->singlestep_enabled
& SSTEP_NOIRQ
)) {
334 /* Mask out external interrupts for this step. */
335 interrupt_request
&= ~(CPU_INTERRUPT_HARD
|
340 if (interrupt_request
& CPU_INTERRUPT_DEBUG
) {
341 env
->interrupt_request
&= ~CPU_INTERRUPT_DEBUG
;
342 env
->exception_index
= EXCP_DEBUG
;
345 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
346 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
347 defined(TARGET_MICROBLAZE)
348 if (interrupt_request
& CPU_INTERRUPT_HALT
) {
349 env
->interrupt_request
&= ~CPU_INTERRUPT_HALT
;
351 env
->exception_index
= EXCP_HLT
;
355 #if defined(TARGET_I386)
356 if (interrupt_request
& CPU_INTERRUPT_INIT
) {
357 svm_check_intercept(SVM_EXIT_INIT
);
359 env
->exception_index
= EXCP_HALTED
;
361 } else if (interrupt_request
& CPU_INTERRUPT_SIPI
) {
363 } else if (env
->hflags2
& HF2_GIF_MASK
) {
364 if ((interrupt_request
& CPU_INTERRUPT_SMI
) &&
365 !(env
->hflags
& HF_SMM_MASK
)) {
366 svm_check_intercept(SVM_EXIT_SMI
);
367 env
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
370 } else if ((interrupt_request
& CPU_INTERRUPT_NMI
) &&
371 !(env
->hflags2
& HF2_NMI_MASK
)) {
372 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
373 env
->hflags2
|= HF2_NMI_MASK
;
374 do_interrupt(EXCP02_NMI
, 0, 0, 0, 1);
376 } else if (interrupt_request
& CPU_INTERRUPT_MCE
) {
377 env
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
378 do_interrupt(EXCP12_MCHK
, 0, 0, 0, 0);
380 } else if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
381 (((env
->hflags2
& HF2_VINTR_MASK
) &&
382 (env
->hflags2
& HF2_HIF_MASK
)) ||
383 (!(env
->hflags2
& HF2_VINTR_MASK
) &&
384 (env
->eflags
& IF_MASK
&&
385 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
))))) {
387 svm_check_intercept(SVM_EXIT_INTR
);
388 env
->interrupt_request
&= ~(CPU_INTERRUPT_HARD
| CPU_INTERRUPT_VIRQ
);
389 intno
= cpu_get_pic_interrupt(env
);
390 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "Servicing hardware INT=0x%02x\n", intno
);
391 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
393 env
= cpu_single_env
;
394 #define env cpu_single_env
396 do_interrupt(intno
, 0, 0, 0, 1);
397 /* ensure that no TB jump will be modified as
398 the program flow was changed */
400 #if !defined(CONFIG_USER_ONLY)
401 } else if ((interrupt_request
& CPU_INTERRUPT_VIRQ
) &&
402 (env
->eflags
& IF_MASK
) &&
403 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
405 /* FIXME: this should respect TPR */
406 svm_check_intercept(SVM_EXIT_VINTR
);
407 intno
= ldl_phys(env
->vm_vmcb
+ offsetof(struct vmcb
, control
.int_vector
));
408 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "Servicing virtual hardware INT=0x%02x\n", intno
);
409 do_interrupt(intno
, 0, 0, 0, 1);
410 env
->interrupt_request
&= ~CPU_INTERRUPT_VIRQ
;
415 #elif defined(TARGET_PPC)
417 if ((interrupt_request
& CPU_INTERRUPT_RESET
)) {
421 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
422 ppc_hw_interrupt(env
);
423 if (env
->pending_interrupts
== 0)
424 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
427 #elif defined(TARGET_MICROBLAZE)
428 if ((interrupt_request
& CPU_INTERRUPT_HARD
)
429 && (env
->sregs
[SR_MSR
] & MSR_IE
)
430 && !(env
->sregs
[SR_MSR
] & (MSR_EIP
| MSR_BIP
))
431 && !(env
->iflags
& (D_FLAG
| IMM_FLAG
))) {
432 env
->exception_index
= EXCP_IRQ
;
436 #elif defined(TARGET_MIPS)
437 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
438 (env
->CP0_Status
& env
->CP0_Cause
& CP0Ca_IP_mask
) &&
439 (env
->CP0_Status
& (1 << CP0St_IE
)) &&
440 !(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
441 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
442 !(env
->hflags
& MIPS_HFLAG_DM
)) {
444 env
->exception_index
= EXCP_EXT_INTERRUPT
;
449 #elif defined(TARGET_SPARC)
450 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
451 if (cpu_interrupts_enabled(env
) &&
452 env
->interrupt_index
> 0) {
453 int pil
= env
->interrupt_index
& 0xf;
454 int type
= env
->interrupt_index
& 0xf0;
456 if (((type
== TT_EXTINT
) &&
457 cpu_pil_allowed(env
, pil
)) ||
459 env
->exception_index
= env
->interrupt_index
;
464 } else if (interrupt_request
& CPU_INTERRUPT_TIMER
) {
465 //do_interrupt(0, 0, 0, 0, 0);
466 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
468 #elif defined(TARGET_ARM)
469 if (interrupt_request
& CPU_INTERRUPT_FIQ
470 && !(env
->uncached_cpsr
& CPSR_F
)) {
471 env
->exception_index
= EXCP_FIQ
;
475 /* ARMv7-M interrupt return works by loading a magic value
476 into the PC. On real hardware the load causes the
477 return to occur. The qemu implementation performs the
478 jump normally, then does the exception return when the
479 CPU tries to execute code at the magic address.
480 This will cause the magic PC value to be pushed to
481 the stack if an interrupt occured at the wrong time.
482 We avoid this by disabling interrupts when
483 pc contains a magic address. */
484 if (interrupt_request
& CPU_INTERRUPT_HARD
485 && ((IS_M(env
) && env
->regs
[15] < 0xfffffff0)
486 || !(env
->uncached_cpsr
& CPSR_I
))) {
487 env
->exception_index
= EXCP_IRQ
;
491 #elif defined(TARGET_SH4)
492 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
496 #elif defined(TARGET_ALPHA)
497 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
501 #elif defined(TARGET_CRIS)
502 if (interrupt_request
& CPU_INTERRUPT_HARD
503 && (env
->pregs
[PR_CCS
] & I_FLAG
)) {
504 env
->exception_index
= EXCP_IRQ
;
508 if (interrupt_request
& CPU_INTERRUPT_NMI
509 && (env
->pregs
[PR_CCS
] & M_FLAG
)) {
510 env
->exception_index
= EXCP_NMI
;
514 #elif defined(TARGET_M68K)
515 if (interrupt_request
& CPU_INTERRUPT_HARD
516 && ((env
->sr
& SR_I
) >> SR_I_SHIFT
)
517 < env
->pending_level
) {
518 /* Real hardware gets the interrupt vector via an
519 IACK cycle at this point. Current emulated
520 hardware doesn't rely on this, so we
521 provide/save the vector when the interrupt is
523 env
->exception_index
= env
->pending_vector
;
528 /* Don't use the cached interupt_request value,
529 do_interrupt may have updated the EXITTB flag. */
530 if (env
->interrupt_request
& CPU_INTERRUPT_EXITTB
) {
531 env
->interrupt_request
&= ~CPU_INTERRUPT_EXITTB
;
532 /* ensure that no TB jump will be modified as
533 the program flow was changed */
537 if (unlikely(env
->exit_request
)) {
538 env
->exit_request
= 0;
539 env
->exception_index
= EXCP_INTERRUPT
;
542 #ifdef CONFIG_DEBUG_EXEC
543 if (qemu_loglevel_mask(CPU_LOG_TB_CPU
)) {
544 /* restore flags in standard format */
545 #if defined(TARGET_I386)
546 env
->eflags
= env
->eflags
| helper_cc_compute_all(CC_OP
) | (DF
& DF_MASK
);
547 log_cpu_state(env
, X86_DUMP_CCOP
);
548 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
549 #elif defined(TARGET_ARM)
550 log_cpu_state(env
, 0);
551 #elif defined(TARGET_SPARC)
552 log_cpu_state(env
, 0);
553 #elif defined(TARGET_PPC)
554 log_cpu_state(env
, 0);
555 #elif defined(TARGET_M68K)
556 cpu_m68k_flush_flags(env
, env
->cc_op
);
557 env
->cc_op
= CC_OP_FLAGS
;
558 env
->sr
= (env
->sr
& 0xffe0)
559 | env
->cc_dest
| (env
->cc_x
<< 4);
560 log_cpu_state(env
, 0);
561 #elif defined(TARGET_MICROBLAZE)
562 log_cpu_state(env
, 0);
563 #elif defined(TARGET_MIPS)
564 log_cpu_state(env
, 0);
565 #elif defined(TARGET_SH4)
566 log_cpu_state(env
, 0);
567 #elif defined(TARGET_ALPHA)
568 log_cpu_state(env
, 0);
569 #elif defined(TARGET_CRIS)
570 log_cpu_state(env
, 0);
572 #error unsupported target CPU
578 /* Note: we do it here to avoid a gcc bug on Mac OS X when
579 doing it in tb_find_slow */
580 if (tb_invalidated_flag
) {
581 /* as some TB could have been invalidated because
582 of memory exceptions while generating the code, we
583 must recompute the hash index here */
585 tb_invalidated_flag
= 0;
587 #ifdef CONFIG_DEBUG_EXEC
588 qemu_log_mask(CPU_LOG_EXEC
, "Trace 0x%08lx [" TARGET_FMT_lx
"] %s\n",
589 (long)tb
->tc_ptr
, tb
->pc
,
590 lookup_symbol(tb
->pc
));
592 /* see if we can patch the calling TB. When the TB
593 spans two pages, we cannot safely do a direct
595 if (next_tb
!= 0 && tb
->page_addr
[1] == -1) {
596 tb_add_jump((TranslationBlock
*)(next_tb
& ~3), next_tb
& 3, tb
);
598 spin_unlock(&tb_lock
);
599 env
->current_tb
= tb
;
600 assert (env
->current_tb
);
602 /* cpu_interrupt might be called while translating the
603 TB, but before it is linked into a potentially
604 infinite loop and becomes env->current_tb. Avoid
605 starting execution if there is a pending interrupt. */
606 if (unlikely (env
->exit_request
))
607 env
->current_tb
= NULL
;
609 while (env
->current_tb
) {
611 /* execute the generated code */
612 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
614 env
= cpu_single_env
;
615 #define env cpu_single_env
617 next_tb
= tcg_qemu_tb_exec(tc_ptr
);
618 env
->current_tb
= NULL
;
619 if ((next_tb
& 3) == 2) {
620 /* Instruction counter expired. */
622 tb
= (TranslationBlock
*)(long)(next_tb
& ~3);
624 cpu_pc_from_tb(env
, tb
);
625 insns_left
= env
->icount_decr
.u32
;
626 if (env
->icount_extra
&& insns_left
>= 0) {
627 /* Refill decrementer and continue execution. */
628 env
->icount_extra
+= insns_left
;
629 if (env
->icount_extra
> 0xffff) {
632 insns_left
= env
->icount_extra
;
634 env
->icount_extra
-= insns_left
;
635 env
->icount_decr
.u16
.low
= insns_left
;
637 if (insns_left
> 0) {
638 /* Execute remaining instructions. */
639 cpu_exec_nocache(insns_left
, tb
);
641 env
->exception_index
= EXCP_INTERRUPT
;
646 assert (env
->current_tb
== NULL
);
648 /* reset soft MMU for next block (it can currently
649 only be set by a memory fault) */
655 #if defined(TARGET_I386)
656 /* restore flags in standard format */
657 env
->eflags
= env
->eflags
| helper_cc_compute_all(CC_OP
) | (DF
& DF_MASK
);
658 #elif defined(TARGET_ARM)
659 /* XXX: Save/restore host fpu exception state?. */
660 #elif defined(TARGET_SPARC)
661 #elif defined(TARGET_PPC)
662 #elif defined(TARGET_M68K)
663 cpu_m68k_flush_flags(env
, env
->cc_op
);
664 env
->cc_op
= CC_OP_FLAGS
;
665 env
->sr
= (env
->sr
& 0xffe0)
666 | env
->cc_dest
| (env
->cc_x
<< 4);
667 #elif defined(TARGET_MICROBLAZE)
668 #elif defined(TARGET_MIPS)
669 #elif defined(TARGET_SH4)
670 #elif defined(TARGET_ALPHA)
671 #elif defined(TARGET_CRIS)
672 #elif defined(TARGET_S390X)
675 #error unsupported target CPU
678 /* restore global registers */
679 #include "hostregs_helper.h"
681 /* fail safe : never use cpu_single_env outside cpu_exec() */
682 cpu_single_env
= NULL
;
686 /* must only be called from the generated code as an exception can be
688 void tb_invalidate_page_range(target_ulong start
, target_ulong end
)
690 /* XXX: cannot enable it yet because it yields to MMU exception
691 where NIP != read address on PowerPC */
693 target_ulong phys_addr
;
694 phys_addr
= get_phys_addr_code(env
, start
);
695 tb_invalidate_phys_page_range(phys_addr
, phys_addr
+ end
- start
, 0);
699 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
701 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
)
703 CPUX86State
*saved_env
;
707 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
709 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
710 (selector
<< 4), 0xffff, 0);
712 helper_load_seg(seg_reg
, selector
);
717 void cpu_x86_fsave(CPUX86State
*s
, target_ulong ptr
, int data32
)
719 CPUX86State
*saved_env
;
724 helper_fsave(ptr
, data32
);
729 void cpu_x86_frstor(CPUX86State
*s
, target_ulong ptr
, int data32
)
731 CPUX86State
*saved_env
;
736 helper_frstor(ptr
, data32
);
741 #endif /* TARGET_I386 */
743 #if !defined(CONFIG_SOFTMMU)
745 #if defined(TARGET_I386)
746 #define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
748 #define EXCEPTION_ACTION cpu_loop_exit()
751 /* 'pc' is the host PC at which the exception was raised. 'address' is
752 the effective address of the memory exception. 'is_write' is 1 if a
753 write caused the exception and otherwise 0'. 'old_set' is the
754 signal set which should be restored */
755 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
756 int is_write
, sigset_t
*old_set
,
759 TranslationBlock
*tb
;
763 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
764 #if defined(DEBUG_SIGNAL)
765 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
766 pc
, address
, is_write
, *(unsigned long *)old_set
);
768 /* XXX: locking issue */
769 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
773 /* see if it is an MMU fault */
774 ret
= cpu_handle_mmu_fault(env
, address
, is_write
, MMU_USER_IDX
, 0);
776 return 0; /* not an MMU fault */
778 return 1; /* the MMU fault was handled without causing real CPU fault */
779 /* now we have a real cpu fault */
782 /* the PC is inside the translated code. It means that we have
783 a virtual CPU fault */
784 cpu_restore_state(tb
, env
, pc
, puc
);
787 /* we restore the process signal mask as the sigreturn should
788 do it (XXX: use sigsetjmp) */
789 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
792 /* never comes here */
796 #if defined(__i386__)
798 #if defined(__APPLE__)
799 # include <sys/ucontext.h>
801 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
802 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
803 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
804 # define MASK_sig(context) ((context)->uc_sigmask)
805 #elif defined (__NetBSD__)
806 # include <ucontext.h>
808 # define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
809 # define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
810 # define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
811 # define MASK_sig(context) ((context)->uc_sigmask)
812 #elif defined (__FreeBSD__) || defined(__DragonFly__)
813 # include <ucontext.h>
815 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
816 # define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
817 # define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
818 # define MASK_sig(context) ((context)->uc_sigmask)
819 #elif defined(__OpenBSD__)
820 # define EIP_sig(context) ((context)->sc_eip)
821 # define TRAP_sig(context) ((context)->sc_trapno)
822 # define ERROR_sig(context) ((context)->sc_err)
823 # define MASK_sig(context) ((context)->sc_mask)
825 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
826 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
827 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
828 # define MASK_sig(context) ((context)->uc_sigmask)
831 int cpu_signal_handler(int host_signum
, void *pinfo
,
834 siginfo_t
*info
= pinfo
;
835 #if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
836 ucontext_t
*uc
= puc
;
837 #elif defined(__OpenBSD__)
838 struct sigcontext
*uc
= puc
;
840 struct ucontext
*uc
= puc
;
849 #define REG_TRAPNO TRAPNO
852 trapno
= TRAP_sig(uc
);
853 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
855 (ERROR_sig(uc
) >> 1) & 1 : 0,
859 #elif defined(__x86_64__)
862 #define PC_sig(context) _UC_MACHINE_PC(context)
863 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
864 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
865 #define MASK_sig(context) ((context)->uc_sigmask)
866 #elif defined(__OpenBSD__)
867 #define PC_sig(context) ((context)->sc_rip)
868 #define TRAP_sig(context) ((context)->sc_trapno)
869 #define ERROR_sig(context) ((context)->sc_err)
870 #define MASK_sig(context) ((context)->sc_mask)
871 #elif defined (__FreeBSD__) || defined(__DragonFly__)
872 #include <ucontext.h>
874 #define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
875 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
876 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
877 #define MASK_sig(context) ((context)->uc_sigmask)
879 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
880 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
881 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
882 #define MASK_sig(context) ((context)->uc_sigmask)
885 int cpu_signal_handler(int host_signum
, void *pinfo
,
888 siginfo_t
*info
= pinfo
;
890 #if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
891 ucontext_t
*uc
= puc
;
892 #elif defined(__OpenBSD__)
893 struct sigcontext
*uc
= puc
;
895 struct ucontext
*uc
= puc
;
899 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
900 TRAP_sig(uc
) == 0xe ?
901 (ERROR_sig(uc
) >> 1) & 1 : 0,
905 #elif defined(_ARCH_PPC)
907 /***********************************************************************
908 * signal context platform-specific definitions
912 /* All Registers access - only for local access */
913 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
914 /* Gpr Registers access */
915 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
916 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
917 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
918 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
919 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
920 # define LR_sig(context) REG_sig(link, context) /* Link register */
921 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
922 /* Float Registers access */
923 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
924 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
925 /* Exception Registers access */
926 # define DAR_sig(context) REG_sig(dar, context)
927 # define DSISR_sig(context) REG_sig(dsisr, context)
928 # define TRAP_sig(context) REG_sig(trap, context)
932 # include <sys/ucontext.h>
933 typedef struct ucontext SIGCONTEXT
;
934 /* All Registers access - only for local access */
935 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
936 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
937 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
938 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
939 /* Gpr Registers access */
940 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
941 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
942 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
943 # define CTR_sig(context) REG_sig(ctr, context)
944 # define XER_sig(context) REG_sig(xer, context) /* Link register */
945 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
946 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
947 /* Float Registers access */
948 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
949 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
950 /* Exception Registers access */
951 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
952 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
953 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
954 #endif /* __APPLE__ */
956 int cpu_signal_handler(int host_signum
, void *pinfo
,
959 siginfo_t
*info
= pinfo
;
960 struct ucontext
*uc
= puc
;
968 if (DSISR_sig(uc
) & 0x00800000)
971 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000))
974 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
975 is_write
, &uc
->uc_sigmask
, puc
);
978 #elif defined(__alpha__)
980 int cpu_signal_handler(int host_signum
, void *pinfo
,
983 siginfo_t
*info
= pinfo
;
984 struct ucontext
*uc
= puc
;
985 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
989 /* XXX: need kernel patch to get write flag faster */
990 switch (insn
>> 26) {
1005 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1006 is_write
, &uc
->uc_sigmask
, puc
);
1008 #elif defined(__sparc__)
1010 int cpu_signal_handler(int host_signum
, void *pinfo
,
1013 siginfo_t
*info
= pinfo
;
1016 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
1017 uint32_t *regs
= (uint32_t *)(info
+ 1);
1018 void *sigmask
= (regs
+ 20);
1019 /* XXX: is there a standard glibc define ? */
1020 unsigned long pc
= regs
[1];
1023 struct sigcontext
*sc
= puc
;
1024 unsigned long pc
= sc
->sigc_regs
.tpc
;
1025 void *sigmask
= (void *)sc
->sigc_mask
;
1026 #elif defined(__OpenBSD__)
1027 struct sigcontext
*uc
= puc
;
1028 unsigned long pc
= uc
->sc_pc
;
1029 void *sigmask
= (void *)(long)uc
->sc_mask
;
1033 /* XXX: need kernel patch to get write flag faster */
1035 insn
= *(uint32_t *)pc
;
1036 if ((insn
>> 30) == 3) {
1037 switch((insn
>> 19) & 0x3f) {
1061 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1062 is_write
, sigmask
, NULL
);
1065 #elif defined(__arm__)
1067 int cpu_signal_handler(int host_signum
, void *pinfo
,
1070 siginfo_t
*info
= pinfo
;
1071 struct ucontext
*uc
= puc
;
1075 #if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
1076 pc
= uc
->uc_mcontext
.gregs
[R15
];
1078 pc
= uc
->uc_mcontext
.arm_pc
;
1080 /* XXX: compute is_write */
1082 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1084 &uc
->uc_sigmask
, puc
);
1087 #elif defined(__mc68000)
1089 int cpu_signal_handler(int host_signum
, void *pinfo
,
1092 siginfo_t
*info
= pinfo
;
1093 struct ucontext
*uc
= puc
;
1097 pc
= uc
->uc_mcontext
.gregs
[16];
1098 /* XXX: compute is_write */
1100 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1102 &uc
->uc_sigmask
, puc
);
1105 #elif defined(__ia64)
1108 /* This ought to be in <bits/siginfo.h>... */
1109 # define __ISR_VALID 1
1112 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
1114 siginfo_t
*info
= pinfo
;
1115 struct ucontext
*uc
= puc
;
1119 ip
= uc
->uc_mcontext
.sc_ip
;
1120 switch (host_signum
) {
1126 if (info
->si_code
&& (info
->si_segvflags
& __ISR_VALID
))
1127 /* ISR.W (write-access) is bit 33: */
1128 is_write
= (info
->si_isr
>> 33) & 1;
1134 return handle_cpu_signal(ip
, (unsigned long)info
->si_addr
,
1136 &uc
->uc_sigmask
, puc
);
1139 #elif defined(__s390__)
1141 int cpu_signal_handler(int host_signum
, void *pinfo
,
1144 siginfo_t
*info
= pinfo
;
1145 struct ucontext
*uc
= puc
;
1149 pc
= uc
->uc_mcontext
.psw
.addr
;
1150 /* XXX: compute is_write */
1152 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1153 is_write
, &uc
->uc_sigmask
, puc
);
1156 #elif defined(__mips__)
1158 int cpu_signal_handler(int host_signum
, void *pinfo
,
1161 siginfo_t
*info
= pinfo
;
1162 struct ucontext
*uc
= puc
;
1163 greg_t pc
= uc
->uc_mcontext
.pc
;
1166 /* XXX: compute is_write */
1168 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1169 is_write
, &uc
->uc_sigmask
, puc
);
1172 #elif defined(__hppa__)
1174 int cpu_signal_handler(int host_signum
, void *pinfo
,
1177 struct siginfo
*info
= pinfo
;
1178 struct ucontext
*uc
= puc
;
1182 pc
= uc
->uc_mcontext
.sc_iaoq
[0];
1183 /* FIXME: compute is_write */
1185 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1187 &uc
->uc_sigmask
, puc
);
1192 #error host CPU specific signal handler needed
1196 #endif /* !defined(CONFIG_SOFTMMU) */