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Add missing svm.h header, and add a Changelog entry.
[mirror_qemu.git] / cpu-exec.c
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 void cpu_loop_exit(void)
44 {
45 /* NOTE: the register at this point must be saved by hand because
46 longjmp restore them */
47 regs_to_env();
48 longjmp(env->jmp_env, 1);
49 }
50
51 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
52 #define reg_T2
53 #endif
54
55 /* exit the current TB from a signal handler. The host registers are
56 restored in a state compatible with the CPU emulator
57 */
58 void cpu_resume_from_signal(CPUState *env1, void *puc)
59 {
60 #if !defined(CONFIG_SOFTMMU)
61 struct ucontext *uc = puc;
62 #endif
63
64 env = env1;
65
66 /* XXX: restore cpu registers saved in host registers */
67
68 #if !defined(CONFIG_SOFTMMU)
69 if (puc) {
70 /* XXX: use siglongjmp ? */
71 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
72 }
73 #endif
74 longjmp(env->jmp_env, 1);
75 }
76
77
78 static TranslationBlock *tb_find_slow(target_ulong pc,
79 target_ulong cs_base,
80 uint64_t flags)
81 {
82 TranslationBlock *tb, **ptb1;
83 int code_gen_size;
84 unsigned int h;
85 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
86 uint8_t *tc_ptr;
87
88 spin_lock(&tb_lock);
89
90 tb_invalidated_flag = 0;
91
92 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93
94 /* find translated block using physical mappings */
95 phys_pc = get_phys_addr_code(env, pc);
96 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 phys_page2 = -1;
98 h = tb_phys_hash_func(phys_pc);
99 ptb1 = &tb_phys_hash[h];
100 for(;;) {
101 tb = *ptb1;
102 if (!tb)
103 goto not_found;
104 if (tb->pc == pc &&
105 tb->page_addr[0] == phys_page1 &&
106 tb->cs_base == cs_base &&
107 tb->flags == flags) {
108 /* check next page if needed */
109 if (tb->page_addr[1] != -1) {
110 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 TARGET_PAGE_SIZE;
112 phys_page2 = get_phys_addr_code(env, virt_page2);
113 if (tb->page_addr[1] == phys_page2)
114 goto found;
115 } else {
116 goto found;
117 }
118 }
119 ptb1 = &tb->phys_hash_next;
120 }
121 not_found:
122 /* if no translated code available, then translate it now */
123 tb = tb_alloc(pc);
124 if (!tb) {
125 /* flush must be done */
126 tb_flush(env);
127 /* cannot fail at this point */
128 tb = tb_alloc(pc);
129 /* don't forget to invalidate previous TB info */
130 tb_invalidated_flag = 1;
131 }
132 tc_ptr = code_gen_ptr;
133 tb->tc_ptr = tc_ptr;
134 tb->cs_base = cs_base;
135 tb->flags = flags;
136 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
137 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138
139 /* check next page if needed */
140 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
143 phys_page2 = get_phys_addr_code(env, virt_page2);
144 }
145 tb_link_phys(tb, phys_pc, phys_page2);
146
147 found:
148 /* we add the TB in the virtual pc hash table */
149 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
150 spin_unlock(&tb_lock);
151 return tb;
152 }
153
154 static inline TranslationBlock *tb_find_fast(void)
155 {
156 TranslationBlock *tb;
157 target_ulong cs_base, pc;
158 uint64_t flags;
159
160 /* we record a subset of the CPU state. It will
161 always be the same before a given translated block
162 is executed. */
163 #if defined(TARGET_I386)
164 flags = env->hflags;
165 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
166 flags |= env->intercept;
167 cs_base = env->segs[R_CS].base;
168 pc = cs_base + env->eip;
169 #elif defined(TARGET_ARM)
170 flags = env->thumb | (env->vfp.vec_len << 1)
171 | (env->vfp.vec_stride << 4);
172 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
173 flags |= (1 << 6);
174 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
175 flags |= (1 << 7);
176 cs_base = 0;
177 pc = env->regs[15];
178 #elif defined(TARGET_SPARC)
179 #ifdef TARGET_SPARC64
180 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
181 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
182 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
183 #else
184 // FPU enable . MMU enabled . MMU no-fault . Supervisor
185 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
186 | env->psrs;
187 #endif
188 cs_base = env->npc;
189 pc = env->pc;
190 #elif defined(TARGET_PPC)
191 flags = env->hflags;
192 cs_base = 0;
193 pc = env->nip;
194 #elif defined(TARGET_MIPS)
195 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
196 cs_base = 0;
197 pc = env->PC[env->current_tc];
198 #elif defined(TARGET_M68K)
199 flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
200 | (env->sr & SR_S) /* Bit 13 */
201 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
202 cs_base = 0;
203 pc = env->pc;
204 #elif defined(TARGET_SH4)
205 flags = env->sr & (SR_MD | SR_RB);
206 cs_base = 0; /* XXXXX */
207 pc = env->pc;
208 #elif defined(TARGET_ALPHA)
209 flags = env->ps;
210 cs_base = 0;
211 pc = env->pc;
212 #else
213 #error unsupported CPU
214 #endif
215 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
216 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
217 tb->flags != flags, 0)) {
218 tb = tb_find_slow(pc, cs_base, flags);
219 /* Note: we do it here to avoid a gcc bug on Mac OS X when
220 doing it in tb_find_slow */
221 if (tb_invalidated_flag) {
222 /* as some TB could have been invalidated because
223 of memory exceptions while generating the code, we
224 must recompute the hash index here */
225 T0 = 0;
226 }
227 }
228 return tb;
229 }
230
231
232 /* main execution loop */
233
234 int cpu_exec(CPUState *env1)
235 {
236 #define DECLARE_HOST_REGS 1
237 #include "hostregs_helper.h"
238 #if defined(TARGET_SPARC)
239 #if defined(reg_REGWPTR)
240 uint32_t *saved_regwptr;
241 #endif
242 #endif
243 #if defined(__sparc__) && !defined(HOST_SOLARIS)
244 int saved_i7;
245 target_ulong tmp_T0;
246 #endif
247 int ret, interrupt_request;
248 void (*gen_func)(void);
249 TranslationBlock *tb;
250 uint8_t *tc_ptr;
251
252 if (cpu_halted(env1) == EXCP_HALTED)
253 return EXCP_HALTED;
254
255 cpu_single_env = env1;
256
257 /* first we save global registers */
258 #define SAVE_HOST_REGS 1
259 #include "hostregs_helper.h"
260 env = env1;
261 #if defined(__sparc__) && !defined(HOST_SOLARIS)
262 /* we also save i7 because longjmp may not restore it */
263 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
264 #endif
265
266 env_to_regs();
267 #if defined(TARGET_I386)
268 /* put eflags in CPU temporary format */
269 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
270 DF = 1 - (2 * ((env->eflags >> 10) & 1));
271 CC_OP = CC_OP_EFLAGS;
272 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
273 #elif defined(TARGET_SPARC)
274 #if defined(reg_REGWPTR)
275 saved_regwptr = REGWPTR;
276 #endif
277 #elif defined(TARGET_M68K)
278 env->cc_op = CC_OP_FLAGS;
279 env->cc_dest = env->sr & 0xf;
280 env->cc_x = (env->sr >> 4) & 1;
281 #elif defined(TARGET_ALPHA)
282 #elif defined(TARGET_ARM)
283 #elif defined(TARGET_PPC)
284 #elif defined(TARGET_MIPS)
285 #elif defined(TARGET_SH4)
286 /* XXXXX */
287 #else
288 #error unsupported target CPU
289 #endif
290 env->exception_index = -1;
291
292 /* prepare setjmp context for exception handling */
293 for(;;) {
294 if (setjmp(env->jmp_env) == 0) {
295 env->current_tb = NULL;
296 /* if an exception is pending, we execute it here */
297 if (env->exception_index >= 0) {
298 if (env->exception_index >= EXCP_INTERRUPT) {
299 /* exit request from the cpu execution loop */
300 ret = env->exception_index;
301 break;
302 } else if (env->user_mode_only) {
303 /* if user mode only, we simulate a fake exception
304 which will be handled outside the cpu execution
305 loop */
306 #if defined(TARGET_I386)
307 do_interrupt_user(env->exception_index,
308 env->exception_is_int,
309 env->error_code,
310 env->exception_next_eip);
311 #endif
312 ret = env->exception_index;
313 break;
314 } else {
315 #if defined(TARGET_I386)
316 /* simulate a real cpu exception. On i386, it can
317 trigger new exceptions, but we do not handle
318 double or triple faults yet. */
319 do_interrupt(env->exception_index,
320 env->exception_is_int,
321 env->error_code,
322 env->exception_next_eip, 0);
323 /* successfully delivered */
324 env->old_exception = -1;
325 #elif defined(TARGET_PPC)
326 do_interrupt(env);
327 #elif defined(TARGET_MIPS)
328 do_interrupt(env);
329 #elif defined(TARGET_SPARC)
330 do_interrupt(env->exception_index);
331 #elif defined(TARGET_ARM)
332 do_interrupt(env);
333 #elif defined(TARGET_SH4)
334 do_interrupt(env);
335 #elif defined(TARGET_ALPHA)
336 do_interrupt(env);
337 #elif defined(TARGET_M68K)
338 do_interrupt(0);
339 #endif
340 }
341 env->exception_index = -1;
342 }
343 #ifdef USE_KQEMU
344 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
345 int ret;
346 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
347 ret = kqemu_cpu_exec(env);
348 /* put eflags in CPU temporary format */
349 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
350 DF = 1 - (2 * ((env->eflags >> 10) & 1));
351 CC_OP = CC_OP_EFLAGS;
352 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
353 if (ret == 1) {
354 /* exception */
355 longjmp(env->jmp_env, 1);
356 } else if (ret == 2) {
357 /* softmmu execution needed */
358 } else {
359 if (env->interrupt_request != 0) {
360 /* hardware interrupt will be executed just after */
361 } else {
362 /* otherwise, we restart */
363 longjmp(env->jmp_env, 1);
364 }
365 }
366 }
367 #endif
368
369 T0 = 0; /* force lookup of first TB */
370 for(;;) {
371 #if defined(__sparc__) && !defined(HOST_SOLARIS)
372 /* g1 can be modified by some libc? functions */
373 tmp_T0 = T0;
374 #endif
375 interrupt_request = env->interrupt_request;
376 if (__builtin_expect(interrupt_request, 0)
377 #if defined(TARGET_I386)
378 && env->hflags & HF_GIF_MASK
379 #endif
380 ) {
381 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
382 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
383 env->exception_index = EXCP_DEBUG;
384 cpu_loop_exit();
385 }
386 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
387 defined(TARGET_PPC) || defined(TARGET_ALPHA)
388 if (interrupt_request & CPU_INTERRUPT_HALT) {
389 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
390 env->halted = 1;
391 env->exception_index = EXCP_HLT;
392 cpu_loop_exit();
393 }
394 #endif
395 #if defined(TARGET_I386)
396 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
397 !(env->hflags & HF_SMM_MASK)) {
398 svm_check_intercept(SVM_EXIT_SMI);
399 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
400 do_smm_enter();
401 #if defined(__sparc__) && !defined(HOST_SOLARIS)
402 tmp_T0 = 0;
403 #else
404 T0 = 0;
405 #endif
406 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
407 (env->eflags & IF_MASK || env->hflags & HF_HIF_MASK) &&
408 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
409 int intno;
410 svm_check_intercept(SVM_EXIT_INTR);
411 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
412 intno = cpu_get_pic_interrupt(env);
413 if (loglevel & CPU_LOG_TB_IN_ASM) {
414 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
415 }
416 do_interrupt(intno, 0, 0, 0, 1);
417 /* ensure that no TB jump will be modified as
418 the program flow was changed */
419 #if defined(__sparc__) && !defined(HOST_SOLARIS)
420 tmp_T0 = 0;
421 #else
422 T0 = 0;
423 #endif
424 #if !defined(CONFIG_USER_ONLY)
425 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
426 (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
427 int intno;
428 /* FIXME: this should respect TPR */
429 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
430 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl),
431 ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)) & ~V_IRQ_MASK);
432 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
433 if (loglevel & CPU_LOG_TB_IN_ASM)
434 fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno);
435 do_interrupt(intno, 0, 0, -1, 1);
436 #if defined(__sparc__) && !defined(HOST_SOLARIS)
437 tmp_T0 = 0;
438 #else
439 T0 = 0;
440 #endif
441 #endif
442 }
443 #elif defined(TARGET_PPC)
444 #if 0
445 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
446 cpu_ppc_reset(env);
447 }
448 #endif
449 if (interrupt_request & CPU_INTERRUPT_HARD) {
450 ppc_hw_interrupt(env);
451 if (env->pending_interrupts == 0)
452 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
453 #if defined(__sparc__) && !defined(HOST_SOLARIS)
454 tmp_T0 = 0;
455 #else
456 T0 = 0;
457 #endif
458 }
459 #elif defined(TARGET_MIPS)
460 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
461 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
462 (env->CP0_Status & (1 << CP0St_IE)) &&
463 !(env->CP0_Status & (1 << CP0St_EXL)) &&
464 !(env->CP0_Status & (1 << CP0St_ERL)) &&
465 !(env->hflags & MIPS_HFLAG_DM)) {
466 /* Raise it */
467 env->exception_index = EXCP_EXT_INTERRUPT;
468 env->error_code = 0;
469 do_interrupt(env);
470 #if defined(__sparc__) && !defined(HOST_SOLARIS)
471 tmp_T0 = 0;
472 #else
473 T0 = 0;
474 #endif
475 }
476 #elif defined(TARGET_SPARC)
477 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
478 (env->psret != 0)) {
479 int pil = env->interrupt_index & 15;
480 int type = env->interrupt_index & 0xf0;
481
482 if (((type == TT_EXTINT) &&
483 (pil == 15 || pil > env->psrpil)) ||
484 type != TT_EXTINT) {
485 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
486 do_interrupt(env->interrupt_index);
487 env->interrupt_index = 0;
488 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
489 cpu_check_irqs(env);
490 #endif
491 #if defined(__sparc__) && !defined(HOST_SOLARIS)
492 tmp_T0 = 0;
493 #else
494 T0 = 0;
495 #endif
496 }
497 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
498 //do_interrupt(0, 0, 0, 0, 0);
499 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
500 }
501 #elif defined(TARGET_ARM)
502 if (interrupt_request & CPU_INTERRUPT_FIQ
503 && !(env->uncached_cpsr & CPSR_F)) {
504 env->exception_index = EXCP_FIQ;
505 do_interrupt(env);
506 }
507 if (interrupt_request & CPU_INTERRUPT_HARD
508 && !(env->uncached_cpsr & CPSR_I)) {
509 env->exception_index = EXCP_IRQ;
510 do_interrupt(env);
511 }
512 #elif defined(TARGET_SH4)
513 /* XXXXX */
514 #elif defined(TARGET_ALPHA)
515 if (interrupt_request & CPU_INTERRUPT_HARD) {
516 do_interrupt(env);
517 }
518 #elif defined(TARGET_M68K)
519 if (interrupt_request & CPU_INTERRUPT_HARD
520 && ((env->sr & SR_I) >> SR_I_SHIFT)
521 < env->pending_level) {
522 /* Real hardware gets the interrupt vector via an
523 IACK cycle at this point. Current emulated
524 hardware doesn't rely on this, so we
525 provide/save the vector when the interrupt is
526 first signalled. */
527 env->exception_index = env->pending_vector;
528 do_interrupt(1);
529 }
530 #endif
531 /* Don't use the cached interupt_request value,
532 do_interrupt may have updated the EXITTB flag. */
533 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
534 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
535 /* ensure that no TB jump will be modified as
536 the program flow was changed */
537 #if defined(__sparc__) && !defined(HOST_SOLARIS)
538 tmp_T0 = 0;
539 #else
540 T0 = 0;
541 #endif
542 }
543 if (interrupt_request & CPU_INTERRUPT_EXIT) {
544 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
545 env->exception_index = EXCP_INTERRUPT;
546 cpu_loop_exit();
547 }
548 }
549 #ifdef DEBUG_EXEC
550 if ((loglevel & CPU_LOG_TB_CPU)) {
551 /* restore flags in standard format */
552 regs_to_env();
553 #if defined(TARGET_I386)
554 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
555 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
556 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
557 #elif defined(TARGET_ARM)
558 cpu_dump_state(env, logfile, fprintf, 0);
559 #elif defined(TARGET_SPARC)
560 REGWPTR = env->regbase + (env->cwp * 16);
561 env->regwptr = REGWPTR;
562 cpu_dump_state(env, logfile, fprintf, 0);
563 #elif defined(TARGET_PPC)
564 cpu_dump_state(env, logfile, fprintf, 0);
565 #elif defined(TARGET_M68K)
566 cpu_m68k_flush_flags(env, env->cc_op);
567 env->cc_op = CC_OP_FLAGS;
568 env->sr = (env->sr & 0xffe0)
569 | env->cc_dest | (env->cc_x << 4);
570 cpu_dump_state(env, logfile, fprintf, 0);
571 #elif defined(TARGET_MIPS)
572 cpu_dump_state(env, logfile, fprintf, 0);
573 #elif defined(TARGET_SH4)
574 cpu_dump_state(env, logfile, fprintf, 0);
575 #elif defined(TARGET_ALPHA)
576 cpu_dump_state(env, logfile, fprintf, 0);
577 #else
578 #error unsupported target CPU
579 #endif
580 }
581 #endif
582 tb = tb_find_fast();
583 #ifdef DEBUG_EXEC
584 if ((loglevel & CPU_LOG_EXEC)) {
585 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
586 (long)tb->tc_ptr, tb->pc,
587 lookup_symbol(tb->pc));
588 }
589 #endif
590 #if defined(__sparc__) && !defined(HOST_SOLARIS)
591 T0 = tmp_T0;
592 #endif
593 /* see if we can patch the calling TB. When the TB
594 spans two pages, we cannot safely do a direct
595 jump. */
596 {
597 if (T0 != 0 &&
598 #if USE_KQEMU
599 (env->kqemu_enabled != 2) &&
600 #endif
601 tb->page_addr[1] == -1
602 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
603 && (tb->cflags & CF_CODE_COPY) ==
604 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
605 #endif
606 ) {
607 spin_lock(&tb_lock);
608 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
609 #if defined(USE_CODE_COPY)
610 /* propagates the FP use info */
611 ((TranslationBlock *)(T0 & ~3))->cflags |=
612 (tb->cflags & CF_FP_USED);
613 #endif
614 spin_unlock(&tb_lock);
615 }
616 }
617 tc_ptr = tb->tc_ptr;
618 env->current_tb = tb;
619 /* execute the generated code */
620 gen_func = (void *)tc_ptr;
621 #if defined(__sparc__)
622 __asm__ __volatile__("call %0\n\t"
623 "mov %%o7,%%i0"
624 : /* no outputs */
625 : "r" (gen_func)
626 : "i0", "i1", "i2", "i3", "i4", "i5",
627 "o0", "o1", "o2", "o3", "o4", "o5",
628 "l0", "l1", "l2", "l3", "l4", "l5",
629 "l6", "l7");
630 #elif defined(__arm__)
631 asm volatile ("mov pc, %0\n\t"
632 ".global exec_loop\n\t"
633 "exec_loop:\n\t"
634 : /* no outputs */
635 : "r" (gen_func)
636 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
637 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
638 {
639 if (!(tb->cflags & CF_CODE_COPY)) {
640 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
641 save_native_fp_state(env);
642 }
643 gen_func();
644 } else {
645 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
646 restore_native_fp_state(env);
647 }
648 /* we work with native eflags */
649 CC_SRC = cc_table[CC_OP].compute_all();
650 CC_OP = CC_OP_EFLAGS;
651 asm(".globl exec_loop\n"
652 "\n"
653 "debug1:\n"
654 " pushl %%ebp\n"
655 " fs movl %10, %9\n"
656 " fs movl %11, %%eax\n"
657 " andl $0x400, %%eax\n"
658 " fs orl %8, %%eax\n"
659 " pushl %%eax\n"
660 " popf\n"
661 " fs movl %%esp, %12\n"
662 " fs movl %0, %%eax\n"
663 " fs movl %1, %%ecx\n"
664 " fs movl %2, %%edx\n"
665 " fs movl %3, %%ebx\n"
666 " fs movl %4, %%esp\n"
667 " fs movl %5, %%ebp\n"
668 " fs movl %6, %%esi\n"
669 " fs movl %7, %%edi\n"
670 " fs jmp *%9\n"
671 "exec_loop:\n"
672 " fs movl %%esp, %4\n"
673 " fs movl %12, %%esp\n"
674 " fs movl %%eax, %0\n"
675 " fs movl %%ecx, %1\n"
676 " fs movl %%edx, %2\n"
677 " fs movl %%ebx, %3\n"
678 " fs movl %%ebp, %5\n"
679 " fs movl %%esi, %6\n"
680 " fs movl %%edi, %7\n"
681 " pushf\n"
682 " popl %%eax\n"
683 " movl %%eax, %%ecx\n"
684 " andl $0x400, %%ecx\n"
685 " shrl $9, %%ecx\n"
686 " andl $0x8d5, %%eax\n"
687 " fs movl %%eax, %8\n"
688 " movl $1, %%eax\n"
689 " subl %%ecx, %%eax\n"
690 " fs movl %%eax, %11\n"
691 " fs movl %9, %%ebx\n" /* get T0 value */
692 " popl %%ebp\n"
693 :
694 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
695 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
696 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
697 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
698 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
699 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
700 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
701 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
702 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
703 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
704 "a" (gen_func),
705 "m" (*(uint8_t *)offsetof(CPUState, df)),
706 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
707 : "%ecx", "%edx"
708 );
709 }
710 }
711 #elif defined(__ia64)
712 struct fptr {
713 void *ip;
714 void *gp;
715 } fp;
716
717 fp.ip = tc_ptr;
718 fp.gp = code_gen_buffer + 2 * (1 << 20);
719 (*(void (*)(void)) &fp)();
720 #else
721 gen_func();
722 #endif
723 env->current_tb = NULL;
724 /* reset soft MMU for next block (it can currently
725 only be set by a memory fault) */
726 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
727 if (env->hflags & HF_SOFTMMU_MASK) {
728 env->hflags &= ~HF_SOFTMMU_MASK;
729 /* do not allow linking to another block */
730 T0 = 0;
731 }
732 #endif
733 #if defined(USE_KQEMU)
734 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
735 if (kqemu_is_ok(env) &&
736 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
737 cpu_loop_exit();
738 }
739 #endif
740 } /* for(;;) */
741 } else {
742 env_to_regs();
743 }
744 } /* for(;;) */
745
746
747 #if defined(TARGET_I386)
748 #if defined(USE_CODE_COPY)
749 if (env->native_fp_regs) {
750 save_native_fp_state(env);
751 }
752 #endif
753 /* restore flags in standard format */
754 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
755 #elif defined(TARGET_ARM)
756 /* XXX: Save/restore host fpu exception state?. */
757 #elif defined(TARGET_SPARC)
758 #if defined(reg_REGWPTR)
759 REGWPTR = saved_regwptr;
760 #endif
761 #elif defined(TARGET_PPC)
762 #elif defined(TARGET_M68K)
763 cpu_m68k_flush_flags(env, env->cc_op);
764 env->cc_op = CC_OP_FLAGS;
765 env->sr = (env->sr & 0xffe0)
766 | env->cc_dest | (env->cc_x << 4);
767 #elif defined(TARGET_MIPS)
768 #elif defined(TARGET_SH4)
769 #elif defined(TARGET_ALPHA)
770 /* XXXXX */
771 #else
772 #error unsupported target CPU
773 #endif
774
775 /* restore global registers */
776 #if defined(__sparc__) && !defined(HOST_SOLARIS)
777 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
778 #endif
779 #include "hostregs_helper.h"
780
781 /* fail safe : never use cpu_single_env outside cpu_exec() */
782 cpu_single_env = NULL;
783 return ret;
784 }
785
786 /* must only be called from the generated code as an exception can be
787 generated */
788 void tb_invalidate_page_range(target_ulong start, target_ulong end)
789 {
790 /* XXX: cannot enable it yet because it yields to MMU exception
791 where NIP != read address on PowerPC */
792 #if 0
793 target_ulong phys_addr;
794 phys_addr = get_phys_addr_code(env, start);
795 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
796 #endif
797 }
798
799 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
800
801 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
802 {
803 CPUX86State *saved_env;
804
805 saved_env = env;
806 env = s;
807 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
808 selector &= 0xffff;
809 cpu_x86_load_seg_cache(env, seg_reg, selector,
810 (selector << 4), 0xffff, 0);
811 } else {
812 load_seg(seg_reg, selector);
813 }
814 env = saved_env;
815 }
816
817 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
818 {
819 CPUX86State *saved_env;
820
821 saved_env = env;
822 env = s;
823
824 helper_fsave((target_ulong)ptr, data32);
825
826 env = saved_env;
827 }
828
829 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
830 {
831 CPUX86State *saved_env;
832
833 saved_env = env;
834 env = s;
835
836 helper_frstor((target_ulong)ptr, data32);
837
838 env = saved_env;
839 }
840
841 #endif /* TARGET_I386 */
842
843 #if !defined(CONFIG_SOFTMMU)
844
845 #if defined(TARGET_I386)
846
847 /* 'pc' is the host PC at which the exception was raised. 'address' is
848 the effective address of the memory exception. 'is_write' is 1 if a
849 write caused the exception and otherwise 0'. 'old_set' is the
850 signal set which should be restored */
851 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
852 int is_write, sigset_t *old_set,
853 void *puc)
854 {
855 TranslationBlock *tb;
856 int ret;
857
858 if (cpu_single_env)
859 env = cpu_single_env; /* XXX: find a correct solution for multithread */
860 #if defined(DEBUG_SIGNAL)
861 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
862 pc, address, is_write, *(unsigned long *)old_set);
863 #endif
864 /* XXX: locking issue */
865 if (is_write && page_unprotect(h2g(address), pc, puc)) {
866 return 1;
867 }
868
869 /* see if it is an MMU fault */
870 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
871 ((env->hflags & HF_CPL_MASK) == 3), 0);
872 if (ret < 0)
873 return 0; /* not an MMU fault */
874 if (ret == 0)
875 return 1; /* the MMU fault was handled without causing real CPU fault */
876 /* now we have a real cpu fault */
877 tb = tb_find_pc(pc);
878 if (tb) {
879 /* the PC is inside the translated code. It means that we have
880 a virtual CPU fault */
881 cpu_restore_state(tb, env, pc, puc);
882 }
883 if (ret == 1) {
884 #if 0
885 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
886 env->eip, env->cr[2], env->error_code);
887 #endif
888 /* we restore the process signal mask as the sigreturn should
889 do it (XXX: use sigsetjmp) */
890 sigprocmask(SIG_SETMASK, old_set, NULL);
891 raise_exception_err(env->exception_index, env->error_code);
892 } else {
893 /* activate soft MMU for this block */
894 env->hflags |= HF_SOFTMMU_MASK;
895 cpu_resume_from_signal(env, puc);
896 }
897 /* never comes here */
898 return 1;
899 }
900
901 #elif defined(TARGET_ARM)
902 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
903 int is_write, sigset_t *old_set,
904 void *puc)
905 {
906 TranslationBlock *tb;
907 int ret;
908
909 if (cpu_single_env)
910 env = cpu_single_env; /* XXX: find a correct solution for multithread */
911 #if defined(DEBUG_SIGNAL)
912 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
913 pc, address, is_write, *(unsigned long *)old_set);
914 #endif
915 /* XXX: locking issue */
916 if (is_write && page_unprotect(h2g(address), pc, puc)) {
917 return 1;
918 }
919 /* see if it is an MMU fault */
920 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
921 if (ret < 0)
922 return 0; /* not an MMU fault */
923 if (ret == 0)
924 return 1; /* the MMU fault was handled without causing real CPU fault */
925 /* now we have a real cpu fault */
926 tb = tb_find_pc(pc);
927 if (tb) {
928 /* the PC is inside the translated code. It means that we have
929 a virtual CPU fault */
930 cpu_restore_state(tb, env, pc, puc);
931 }
932 /* we restore the process signal mask as the sigreturn should
933 do it (XXX: use sigsetjmp) */
934 sigprocmask(SIG_SETMASK, old_set, NULL);
935 cpu_loop_exit();
936 }
937 #elif defined(TARGET_SPARC)
938 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
939 int is_write, sigset_t *old_set,
940 void *puc)
941 {
942 TranslationBlock *tb;
943 int ret;
944
945 if (cpu_single_env)
946 env = cpu_single_env; /* XXX: find a correct solution for multithread */
947 #if defined(DEBUG_SIGNAL)
948 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
949 pc, address, is_write, *(unsigned long *)old_set);
950 #endif
951 /* XXX: locking issue */
952 if (is_write && page_unprotect(h2g(address), pc, puc)) {
953 return 1;
954 }
955 /* see if it is an MMU fault */
956 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
957 if (ret < 0)
958 return 0; /* not an MMU fault */
959 if (ret == 0)
960 return 1; /* the MMU fault was handled without causing real CPU fault */
961 /* now we have a real cpu fault */
962 tb = tb_find_pc(pc);
963 if (tb) {
964 /* the PC is inside the translated code. It means that we have
965 a virtual CPU fault */
966 cpu_restore_state(tb, env, pc, puc);
967 }
968 /* we restore the process signal mask as the sigreturn should
969 do it (XXX: use sigsetjmp) */
970 sigprocmask(SIG_SETMASK, old_set, NULL);
971 cpu_loop_exit();
972 }
973 #elif defined (TARGET_PPC)
974 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
975 int is_write, sigset_t *old_set,
976 void *puc)
977 {
978 TranslationBlock *tb;
979 int ret;
980
981 if (cpu_single_env)
982 env = cpu_single_env; /* XXX: find a correct solution for multithread */
983 #if defined(DEBUG_SIGNAL)
984 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
985 pc, address, is_write, *(unsigned long *)old_set);
986 #endif
987 /* XXX: locking issue */
988 if (is_write && page_unprotect(h2g(address), pc, puc)) {
989 return 1;
990 }
991
992 /* see if it is an MMU fault */
993 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
994 if (ret < 0)
995 return 0; /* not an MMU fault */
996 if (ret == 0)
997 return 1; /* the MMU fault was handled without causing real CPU fault */
998
999 /* now we have a real cpu fault */
1000 tb = tb_find_pc(pc);
1001 if (tb) {
1002 /* the PC is inside the translated code. It means that we have
1003 a virtual CPU fault */
1004 cpu_restore_state(tb, env, pc, puc);
1005 }
1006 if (ret == 1) {
1007 #if 0
1008 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1009 env->nip, env->error_code, tb);
1010 #endif
1011 /* we restore the process signal mask as the sigreturn should
1012 do it (XXX: use sigsetjmp) */
1013 sigprocmask(SIG_SETMASK, old_set, NULL);
1014 do_raise_exception_err(env->exception_index, env->error_code);
1015 } else {
1016 /* activate soft MMU for this block */
1017 cpu_resume_from_signal(env, puc);
1018 }
1019 /* never comes here */
1020 return 1;
1021 }
1022
1023 #elif defined(TARGET_M68K)
1024 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1025 int is_write, sigset_t *old_set,
1026 void *puc)
1027 {
1028 TranslationBlock *tb;
1029 int ret;
1030
1031 if (cpu_single_env)
1032 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1033 #if defined(DEBUG_SIGNAL)
1034 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1035 pc, address, is_write, *(unsigned long *)old_set);
1036 #endif
1037 /* XXX: locking issue */
1038 if (is_write && page_unprotect(address, pc, puc)) {
1039 return 1;
1040 }
1041 /* see if it is an MMU fault */
1042 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1043 if (ret < 0)
1044 return 0; /* not an MMU fault */
1045 if (ret == 0)
1046 return 1; /* the MMU fault was handled without causing real CPU fault */
1047 /* now we have a real cpu fault */
1048 tb = tb_find_pc(pc);
1049 if (tb) {
1050 /* the PC is inside the translated code. It means that we have
1051 a virtual CPU fault */
1052 cpu_restore_state(tb, env, pc, puc);
1053 }
1054 /* we restore the process signal mask as the sigreturn should
1055 do it (XXX: use sigsetjmp) */
1056 sigprocmask(SIG_SETMASK, old_set, NULL);
1057 cpu_loop_exit();
1058 /* never comes here */
1059 return 1;
1060 }
1061
1062 #elif defined (TARGET_MIPS)
1063 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1064 int is_write, sigset_t *old_set,
1065 void *puc)
1066 {
1067 TranslationBlock *tb;
1068 int ret;
1069
1070 if (cpu_single_env)
1071 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1072 #if defined(DEBUG_SIGNAL)
1073 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1074 pc, address, is_write, *(unsigned long *)old_set);
1075 #endif
1076 /* XXX: locking issue */
1077 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1078 return 1;
1079 }
1080
1081 /* see if it is an MMU fault */
1082 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1083 if (ret < 0)
1084 return 0; /* not an MMU fault */
1085 if (ret == 0)
1086 return 1; /* the MMU fault was handled without causing real CPU fault */
1087
1088 /* now we have a real cpu fault */
1089 tb = tb_find_pc(pc);
1090 if (tb) {
1091 /* the PC is inside the translated code. It means that we have
1092 a virtual CPU fault */
1093 cpu_restore_state(tb, env, pc, puc);
1094 }
1095 if (ret == 1) {
1096 #if 0
1097 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1098 env->PC, env->error_code, tb);
1099 #endif
1100 /* we restore the process signal mask as the sigreturn should
1101 do it (XXX: use sigsetjmp) */
1102 sigprocmask(SIG_SETMASK, old_set, NULL);
1103 do_raise_exception_err(env->exception_index, env->error_code);
1104 } else {
1105 /* activate soft MMU for this block */
1106 cpu_resume_from_signal(env, puc);
1107 }
1108 /* never comes here */
1109 return 1;
1110 }
1111
1112 #elif defined (TARGET_SH4)
1113 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1114 int is_write, sigset_t *old_set,
1115 void *puc)
1116 {
1117 TranslationBlock *tb;
1118 int ret;
1119
1120 if (cpu_single_env)
1121 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1122 #if defined(DEBUG_SIGNAL)
1123 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1124 pc, address, is_write, *(unsigned long *)old_set);
1125 #endif
1126 /* XXX: locking issue */
1127 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1128 return 1;
1129 }
1130
1131 /* see if it is an MMU fault */
1132 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1133 if (ret < 0)
1134 return 0; /* not an MMU fault */
1135 if (ret == 0)
1136 return 1; /* the MMU fault was handled without causing real CPU fault */
1137
1138 /* now we have a real cpu fault */
1139 tb = tb_find_pc(pc);
1140 if (tb) {
1141 /* the PC is inside the translated code. It means that we have
1142 a virtual CPU fault */
1143 cpu_restore_state(tb, env, pc, puc);
1144 }
1145 #if 0
1146 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1147 env->nip, env->error_code, tb);
1148 #endif
1149 /* we restore the process signal mask as the sigreturn should
1150 do it (XXX: use sigsetjmp) */
1151 sigprocmask(SIG_SETMASK, old_set, NULL);
1152 cpu_loop_exit();
1153 /* never comes here */
1154 return 1;
1155 }
1156
1157 #elif defined (TARGET_ALPHA)
1158 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1159 int is_write, sigset_t *old_set,
1160 void *puc)
1161 {
1162 TranslationBlock *tb;
1163 int ret;
1164
1165 if (cpu_single_env)
1166 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1167 #if defined(DEBUG_SIGNAL)
1168 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1169 pc, address, is_write, *(unsigned long *)old_set);
1170 #endif
1171 /* XXX: locking issue */
1172 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1173 return 1;
1174 }
1175
1176 /* see if it is an MMU fault */
1177 ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0);
1178 if (ret < 0)
1179 return 0; /* not an MMU fault */
1180 if (ret == 0)
1181 return 1; /* the MMU fault was handled without causing real CPU fault */
1182
1183 /* now we have a real cpu fault */
1184 tb = tb_find_pc(pc);
1185 if (tb) {
1186 /* the PC is inside the translated code. It means that we have
1187 a virtual CPU fault */
1188 cpu_restore_state(tb, env, pc, puc);
1189 }
1190 #if 0
1191 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1192 env->nip, env->error_code, tb);
1193 #endif
1194 /* we restore the process signal mask as the sigreturn should
1195 do it (XXX: use sigsetjmp) */
1196 sigprocmask(SIG_SETMASK, old_set, NULL);
1197 cpu_loop_exit();
1198 /* never comes here */
1199 return 1;
1200 }
1201 #else
1202 #error unsupported target CPU
1203 #endif
1204
1205 #if defined(__i386__)
1206
1207 #if defined(__APPLE__)
1208 # include <sys/ucontext.h>
1209
1210 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1211 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1212 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1213 #else
1214 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1215 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1216 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1217 #endif
1218
1219 #if defined(USE_CODE_COPY)
1220 static void cpu_send_trap(unsigned long pc, int trap,
1221 struct ucontext *uc)
1222 {
1223 TranslationBlock *tb;
1224
1225 if (cpu_single_env)
1226 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1227 /* now we have a real cpu fault */
1228 tb = tb_find_pc(pc);
1229 if (tb) {
1230 /* the PC is inside the translated code. It means that we have
1231 a virtual CPU fault */
1232 cpu_restore_state(tb, env, pc, uc);
1233 }
1234 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1235 raise_exception_err(trap, env->error_code);
1236 }
1237 #endif
1238
1239 int cpu_signal_handler(int host_signum, void *pinfo,
1240 void *puc)
1241 {
1242 siginfo_t *info = pinfo;
1243 struct ucontext *uc = puc;
1244 unsigned long pc;
1245 int trapno;
1246
1247 #ifndef REG_EIP
1248 /* for glibc 2.1 */
1249 #define REG_EIP EIP
1250 #define REG_ERR ERR
1251 #define REG_TRAPNO TRAPNO
1252 #endif
1253 pc = EIP_sig(uc);
1254 trapno = TRAP_sig(uc);
1255 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1256 if (trapno == 0x00 || trapno == 0x05) {
1257 /* send division by zero or bound exception */
1258 cpu_send_trap(pc, trapno, uc);
1259 return 1;
1260 } else
1261 #endif
1262 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1263 trapno == 0xe ?
1264 (ERROR_sig(uc) >> 1) & 1 : 0,
1265 &uc->uc_sigmask, puc);
1266 }
1267
1268 #elif defined(__x86_64__)
1269
1270 int cpu_signal_handler(int host_signum, void *pinfo,
1271 void *puc)
1272 {
1273 siginfo_t *info = pinfo;
1274 struct ucontext *uc = puc;
1275 unsigned long pc;
1276
1277 pc = uc->uc_mcontext.gregs[REG_RIP];
1278 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1279 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1280 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1281 &uc->uc_sigmask, puc);
1282 }
1283
1284 #elif defined(__powerpc__)
1285
1286 /***********************************************************************
1287 * signal context platform-specific definitions
1288 * From Wine
1289 */
1290 #ifdef linux
1291 /* All Registers access - only for local access */
1292 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1293 /* Gpr Registers access */
1294 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1295 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1296 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1297 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1298 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1299 # define LR_sig(context) REG_sig(link, context) /* Link register */
1300 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1301 /* Float Registers access */
1302 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1303 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1304 /* Exception Registers access */
1305 # define DAR_sig(context) REG_sig(dar, context)
1306 # define DSISR_sig(context) REG_sig(dsisr, context)
1307 # define TRAP_sig(context) REG_sig(trap, context)
1308 #endif /* linux */
1309
1310 #ifdef __APPLE__
1311 # include <sys/ucontext.h>
1312 typedef struct ucontext SIGCONTEXT;
1313 /* All Registers access - only for local access */
1314 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1315 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1316 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1317 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1318 /* Gpr Registers access */
1319 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1320 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1321 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1322 # define CTR_sig(context) REG_sig(ctr, context)
1323 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1324 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1325 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1326 /* Float Registers access */
1327 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1328 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1329 /* Exception Registers access */
1330 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1331 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1332 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1333 #endif /* __APPLE__ */
1334
1335 int cpu_signal_handler(int host_signum, void *pinfo,
1336 void *puc)
1337 {
1338 siginfo_t *info = pinfo;
1339 struct ucontext *uc = puc;
1340 unsigned long pc;
1341 int is_write;
1342
1343 pc = IAR_sig(uc);
1344 is_write = 0;
1345 #if 0
1346 /* ppc 4xx case */
1347 if (DSISR_sig(uc) & 0x00800000)
1348 is_write = 1;
1349 #else
1350 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1351 is_write = 1;
1352 #endif
1353 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1354 is_write, &uc->uc_sigmask, puc);
1355 }
1356
1357 #elif defined(__alpha__)
1358
1359 int cpu_signal_handler(int host_signum, void *pinfo,
1360 void *puc)
1361 {
1362 siginfo_t *info = pinfo;
1363 struct ucontext *uc = puc;
1364 uint32_t *pc = uc->uc_mcontext.sc_pc;
1365 uint32_t insn = *pc;
1366 int is_write = 0;
1367
1368 /* XXX: need kernel patch to get write flag faster */
1369 switch (insn >> 26) {
1370 case 0x0d: // stw
1371 case 0x0e: // stb
1372 case 0x0f: // stq_u
1373 case 0x24: // stf
1374 case 0x25: // stg
1375 case 0x26: // sts
1376 case 0x27: // stt
1377 case 0x2c: // stl
1378 case 0x2d: // stq
1379 case 0x2e: // stl_c
1380 case 0x2f: // stq_c
1381 is_write = 1;
1382 }
1383
1384 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1385 is_write, &uc->uc_sigmask, puc);
1386 }
1387 #elif defined(__sparc__)
1388
1389 int cpu_signal_handler(int host_signum, void *pinfo,
1390 void *puc)
1391 {
1392 siginfo_t *info = pinfo;
1393 uint32_t *regs = (uint32_t *)(info + 1);
1394 void *sigmask = (regs + 20);
1395 unsigned long pc;
1396 int is_write;
1397 uint32_t insn;
1398
1399 /* XXX: is there a standard glibc define ? */
1400 pc = regs[1];
1401 /* XXX: need kernel patch to get write flag faster */
1402 is_write = 0;
1403 insn = *(uint32_t *)pc;
1404 if ((insn >> 30) == 3) {
1405 switch((insn >> 19) & 0x3f) {
1406 case 0x05: // stb
1407 case 0x06: // sth
1408 case 0x04: // st
1409 case 0x07: // std
1410 case 0x24: // stf
1411 case 0x27: // stdf
1412 case 0x25: // stfsr
1413 is_write = 1;
1414 break;
1415 }
1416 }
1417 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1418 is_write, sigmask, NULL);
1419 }
1420
1421 #elif defined(__arm__)
1422
1423 int cpu_signal_handler(int host_signum, void *pinfo,
1424 void *puc)
1425 {
1426 siginfo_t *info = pinfo;
1427 struct ucontext *uc = puc;
1428 unsigned long pc;
1429 int is_write;
1430
1431 pc = uc->uc_mcontext.gregs[R15];
1432 /* XXX: compute is_write */
1433 is_write = 0;
1434 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1435 is_write,
1436 &uc->uc_sigmask, puc);
1437 }
1438
1439 #elif defined(__mc68000)
1440
1441 int cpu_signal_handler(int host_signum, void *pinfo,
1442 void *puc)
1443 {
1444 siginfo_t *info = pinfo;
1445 struct ucontext *uc = puc;
1446 unsigned long pc;
1447 int is_write;
1448
1449 pc = uc->uc_mcontext.gregs[16];
1450 /* XXX: compute is_write */
1451 is_write = 0;
1452 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1453 is_write,
1454 &uc->uc_sigmask, puc);
1455 }
1456
1457 #elif defined(__ia64)
1458
1459 #ifndef __ISR_VALID
1460 /* This ought to be in <bits/siginfo.h>... */
1461 # define __ISR_VALID 1
1462 #endif
1463
1464 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1465 {
1466 siginfo_t *info = pinfo;
1467 struct ucontext *uc = puc;
1468 unsigned long ip;
1469 int is_write = 0;
1470
1471 ip = uc->uc_mcontext.sc_ip;
1472 switch (host_signum) {
1473 case SIGILL:
1474 case SIGFPE:
1475 case SIGSEGV:
1476 case SIGBUS:
1477 case SIGTRAP:
1478 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1479 /* ISR.W (write-access) is bit 33: */
1480 is_write = (info->si_isr >> 33) & 1;
1481 break;
1482
1483 default:
1484 break;
1485 }
1486 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1487 is_write,
1488 &uc->uc_sigmask, puc);
1489 }
1490
1491 #elif defined(__s390__)
1492
1493 int cpu_signal_handler(int host_signum, void *pinfo,
1494 void *puc)
1495 {
1496 siginfo_t *info = pinfo;
1497 struct ucontext *uc = puc;
1498 unsigned long pc;
1499 int is_write;
1500
1501 pc = uc->uc_mcontext.psw.addr;
1502 /* XXX: compute is_write */
1503 is_write = 0;
1504 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1505 is_write, &uc->uc_sigmask, puc);
1506 }
1507
1508 #elif defined(__mips__)
1509
1510 int cpu_signal_handler(int host_signum, void *pinfo,
1511 void *puc)
1512 {
1513 siginfo_t *info = pinfo;
1514 struct ucontext *uc = puc;
1515 greg_t pc = uc->uc_mcontext.pc;
1516 int is_write;
1517
1518 /* XXX: compute is_write */
1519 is_write = 0;
1520 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1521 is_write, &uc->uc_sigmask, puc);
1522 }
1523
1524 #else
1525
1526 #error host CPU specific signal handler needed
1527
1528 #endif
1529
1530 #endif /* !defined(CONFIG_SOFTMMU) */
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