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2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag
;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env
->jmp_env
, 1);
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
57 void cpu_resume_from_signal(CPUState
*env1
, void *puc
)
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext
*uc
= puc
;
65 /* XXX: restore cpu registers saved in host registers */
67 #if !defined(CONFIG_SOFTMMU)
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
73 longjmp(env
->jmp_env
, 1);
76 /* main execution loop */
78 int cpu_exec(CPUState
*env1
)
80 int saved_T0
, saved_T1
;
85 #if defined(TARGET_I386)
110 #elif defined(TARGET_SPARC)
111 #if defined(reg_REGWPTR)
112 uint32_t *saved_regwptr
;
116 int saved_i7
, tmp_T0
;
118 int code_gen_size
, ret
, interrupt_request
;
119 void (*gen_func
)(void);
120 TranslationBlock
*tb
, **ptb
;
121 target_ulong cs_base
, pc
;
125 /* first we save global registers */
134 /* we also save i7 because longjmp may not restore it */
135 asm volatile ("mov %%i7, %0" : "=r" (saved_i7
));
138 #if defined(TARGET_I386)
165 /* put eflags in CPU temporary format */
166 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
167 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
168 CC_OP
= CC_OP_EFLAGS
;
169 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
170 #elif defined(TARGET_ARM)
174 env
->CF
= (psr
>> 29) & 1;
175 env
->NZF
= (psr
& 0xc0000000) ^ 0x40000000;
176 env
->VF
= (psr
<< 3) & 0x80000000;
177 env
->QF
= (psr
>> 27) & 1;
178 env
->cpsr
= psr
& ~CACHED_CPSR_BITS
;
180 #elif defined(TARGET_SPARC)
181 #if defined(reg_REGWPTR)
182 saved_regwptr
= REGWPTR
;
184 #elif defined(TARGET_PPC)
185 #elif defined(TARGET_MIPS)
187 #error unsupported target CPU
189 env
->exception_index
= -1;
191 /* prepare setjmp context for exception handling */
193 if (setjmp(env
->jmp_env
) == 0) {
194 env
->current_tb
= NULL
;
195 /* if an exception is pending, we execute it here */
196 if (env
->exception_index
>= 0) {
197 if (env
->exception_index
>= EXCP_INTERRUPT
) {
198 /* exit request from the cpu execution loop */
199 ret
= env
->exception_index
;
201 } else if (env
->user_mode_only
) {
202 /* if user mode only, we simulate a fake exception
203 which will be hanlded outside the cpu execution
205 #if defined(TARGET_I386)
206 do_interrupt_user(env
->exception_index
,
207 env
->exception_is_int
,
209 env
->exception_next_eip
);
211 ret
= env
->exception_index
;
214 #if defined(TARGET_I386)
215 /* simulate a real cpu exception. On i386, it can
216 trigger new exceptions, but we do not handle
217 double or triple faults yet. */
218 do_interrupt(env
->exception_index
,
219 env
->exception_is_int
,
221 env
->exception_next_eip
, 0);
222 #elif defined(TARGET_PPC)
224 #elif defined(TARGET_MIPS)
226 #elif defined(TARGET_SPARC)
227 do_interrupt(env
->exception_index
);
230 env
->exception_index
= -1;
233 if (kqemu_is_ok(env
) && env
->interrupt_request
== 0) {
235 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
236 ret
= kqemu_cpu_exec(env
);
237 /* put eflags in CPU temporary format */
238 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
239 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
240 CC_OP
= CC_OP_EFLAGS
;
241 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
244 longjmp(env
->jmp_env
, 1);
245 } else if (ret
== 2) {
246 /* softmmu execution needed */
248 if (env
->interrupt_request
!= 0) {
249 /* hardware interrupt will be executed just after */
251 /* otherwise, we restart */
252 longjmp(env
->jmp_env
, 1);
258 T0
= 0; /* force lookup of first TB */
261 /* g1 can be modified by some libc? functions */
264 interrupt_request
= env
->interrupt_request
;
265 if (__builtin_expect(interrupt_request
, 0)) {
266 #if defined(TARGET_I386)
267 /* if hardware interrupt pending, we execute it */
268 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
269 (env
->eflags
& IF_MASK
) &&
270 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
272 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
273 intno
= cpu_get_pic_interrupt(env
);
274 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
275 fprintf(logfile
, "Servicing hardware INT=0x%02x\n", intno
);
277 do_interrupt(intno
, 0, 0, 0, 1);
278 /* ensure that no TB jump will be modified as
279 the program flow was changed */
286 #elif defined(TARGET_PPC)
288 if ((interrupt_request
& CPU_INTERRUPT_RESET
)) {
293 if ((interrupt_request
& CPU_INTERRUPT_HARD
)) {
295 env
->exception_index
= EXCP_EXTERNAL
;
298 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
299 } else if ((interrupt_request
& CPU_INTERRUPT_TIMER
)) {
301 env
->exception_index
= EXCP_DECR
;
304 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
307 #elif defined(TARGET_MIPS)
308 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
309 (env
->CP0_Status
& (1 << CP0St_IE
)) &&
310 (env
->CP0_Cause
& 0x0000FF00) &&
311 !(env
->hflags
& MIPS_HFLAG_EXL
) &&
312 !(env
->hflags
& MIPS_HFLAG_ERL
) &&
313 !(env
->hflags
& MIPS_HFLAG_DM
)) {
315 env
->exception_index
= EXCP_EXT_INTERRUPT
;
318 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
320 #elif defined(TARGET_SPARC)
321 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
323 int pil
= env
->interrupt_index
& 15;
324 int type
= env
->interrupt_index
& 0xf0;
326 if (((type
== TT_EXTINT
) &&
327 (pil
== 15 || pil
> env
->psrpil
)) ||
329 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
330 do_interrupt(env
->interrupt_index
);
331 env
->interrupt_index
= 0;
333 } else if (interrupt_request
& CPU_INTERRUPT_TIMER
) {
334 //do_interrupt(0, 0, 0, 0, 0);
335 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
338 if (interrupt_request
& CPU_INTERRUPT_EXITTB
) {
339 env
->interrupt_request
&= ~CPU_INTERRUPT_EXITTB
;
340 /* ensure that no TB jump will be modified as
341 the program flow was changed */
348 if (interrupt_request
& CPU_INTERRUPT_EXIT
) {
349 env
->interrupt_request
&= ~CPU_INTERRUPT_EXIT
;
350 env
->exception_index
= EXCP_INTERRUPT
;
355 if ((loglevel
& CPU_LOG_EXEC
)) {
356 #if defined(TARGET_I386)
357 /* restore flags in standard format */
359 env
->regs
[R_EAX
] = EAX
;
362 env
->regs
[R_EBX
] = EBX
;
365 env
->regs
[R_ECX
] = ECX
;
368 env
->regs
[R_EDX
] = EDX
;
371 env
->regs
[R_ESI
] = ESI
;
374 env
->regs
[R_EDI
] = EDI
;
377 env
->regs
[R_EBP
] = EBP
;
380 env
->regs
[R_ESP
] = ESP
;
382 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
383 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
384 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
385 #elif defined(TARGET_ARM)
386 env
->cpsr
= compute_cpsr();
387 cpu_dump_state(env
, logfile
, fprintf
, 0);
388 env
->cpsr
&= ~CACHED_CPSR_BITS
;
389 #elif defined(TARGET_SPARC)
390 REGWPTR
= env
->regbase
+ (env
->cwp
* 16);
391 env
->regwptr
= REGWPTR
;
392 cpu_dump_state(env
, logfile
, fprintf
, 0);
393 #elif defined(TARGET_PPC)
394 cpu_dump_state(env
, logfile
, fprintf
, 0);
395 #elif defined(TARGET_MIPS)
396 cpu_dump_state(env
, logfile
, fprintf
, 0);
398 #error unsupported target CPU
402 /* we record a subset of the CPU state. It will
403 always be the same before a given translated block
405 #if defined(TARGET_I386)
407 flags
|= (env
->eflags
& (IOPL_MASK
| TF_MASK
| VM_MASK
));
408 cs_base
= env
->segs
[R_CS
].base
;
409 pc
= cs_base
+ env
->eip
;
410 #elif defined(TARGET_ARM)
411 flags
= env
->thumb
| (env
->vfp
.vec_len
<< 1)
412 | (env
->vfp
.vec_stride
<< 4);
415 #elif defined(TARGET_SPARC)
416 #ifdef TARGET_SPARC64
417 flags
= (env
->pstate
<< 2) | ((env
->lsu
& (DMMU_E
| IMMU_E
)) >> 2);
419 flags
= env
->psrs
| ((env
->mmuregs
[0] & (MMU_E
| MMU_NF
)) << 1);
423 #elif defined(TARGET_PPC)
424 flags
= (msr_pr
<< MSR_PR
) | (msr_fp
<< MSR_FP
) |
425 (msr_se
<< MSR_SE
) | (msr_le
<< MSR_LE
);
428 #elif defined(TARGET_MIPS)
429 flags
= env
->hflags
& MIPS_HFLAGS_TMASK
;
433 #error unsupported CPU
435 tb
= tb_find(&ptb
, pc
, cs_base
,
438 TranslationBlock
**ptb1
;
440 target_ulong phys_pc
, phys_page1
, phys_page2
, virt_page2
;
445 tb_invalidated_flag
= 0;
447 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
449 /* find translated block using physical mappings */
450 phys_pc
= get_phys_addr_code(env
, pc
);
451 phys_page1
= phys_pc
& TARGET_PAGE_MASK
;
453 h
= tb_phys_hash_func(phys_pc
);
454 ptb1
= &tb_phys_hash
[h
];
460 tb
->page_addr
[0] == phys_page1
&&
461 tb
->cs_base
== cs_base
&&
462 tb
->flags
== flags
) {
463 /* check next page if needed */
464 if (tb
->page_addr
[1] != -1) {
465 virt_page2
= (pc
& TARGET_PAGE_MASK
) +
467 phys_page2
= get_phys_addr_code(env
, virt_page2
);
468 if (tb
->page_addr
[1] == phys_page2
)
474 ptb1
= &tb
->phys_hash_next
;
477 /* if no translated code available, then translate it now */
480 /* flush must be done */
482 /* cannot fail at this point */
484 /* don't forget to invalidate previous TB info */
485 ptb
= &tb_hash
[tb_hash_func(pc
)];
488 tc_ptr
= code_gen_ptr
;
490 tb
->cs_base
= cs_base
;
492 cpu_gen_code(env
, tb
, CODE_GEN_MAX_SIZE
, &code_gen_size
);
493 code_gen_ptr
= (void *)(((unsigned long)code_gen_ptr
+ code_gen_size
+ CODE_GEN_ALIGN
- 1) & ~(CODE_GEN_ALIGN
- 1));
495 /* check next page if needed */
496 virt_page2
= (pc
+ tb
->size
- 1) & TARGET_PAGE_MASK
;
498 if ((pc
& TARGET_PAGE_MASK
) != virt_page2
) {
499 phys_page2
= get_phys_addr_code(env
, virt_page2
);
501 tb_link_phys(tb
, phys_pc
, phys_page2
);
504 if (tb_invalidated_flag
) {
505 /* as some TB could have been invalidated because
506 of memory exceptions while generating the code, we
507 must recompute the hash index here */
508 ptb
= &tb_hash
[tb_hash_func(pc
)];
510 ptb
= &(*ptb
)->hash_next
;
513 /* we add the TB in the virtual pc hash table */
515 tb
->hash_next
= NULL
;
517 spin_unlock(&tb_lock
);
520 if ((loglevel
& CPU_LOG_EXEC
)) {
521 fprintf(logfile
, "Trace 0x%08lx [" TARGET_FMT_lx
"] %s\n",
522 (long)tb
->tc_ptr
, tb
->pc
,
523 lookup_symbol(tb
->pc
));
529 /* see if we can patch the calling TB. */
532 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
533 && (tb
->cflags
& CF_CODE_COPY
) ==
534 (((TranslationBlock
*)(T0
& ~3))->cflags
& CF_CODE_COPY
)
538 tb_add_jump((TranslationBlock
*)(long)(T0
& ~3), T0
& 3, tb
);
539 #if defined(USE_CODE_COPY)
540 /* propagates the FP use info */
541 ((TranslationBlock
*)(T0
& ~3))->cflags
|=
542 (tb
->cflags
& CF_FP_USED
);
544 spin_unlock(&tb_lock
);
548 env
->current_tb
= tb
;
549 /* execute the generated code */
550 gen_func
= (void *)tc_ptr
;
551 #if defined(__sparc__)
552 __asm__
__volatile__("call %0\n\t"
556 : "i0", "i1", "i2", "i3", "i4", "i5");
557 #elif defined(__arm__)
558 asm volatile ("mov pc, %0\n\t"
559 ".global exec_loop\n\t"
563 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
564 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
566 if (!(tb
->cflags
& CF_CODE_COPY
)) {
567 if ((tb
->cflags
& CF_FP_USED
) && env
->native_fp_regs
) {
568 save_native_fp_state(env
);
572 if ((tb
->cflags
& CF_FP_USED
) && !env
->native_fp_regs
) {
573 restore_native_fp_state(env
);
575 /* we work with native eflags */
576 CC_SRC
= cc_table
[CC_OP
].compute_all();
577 CC_OP
= CC_OP_EFLAGS
;
578 asm(".globl exec_loop\n"
583 " fs movl %11, %%eax\n"
584 " andl $0x400, %%eax\n"
585 " fs orl %8, %%eax\n"
588 " fs movl %%esp, %12\n"
589 " fs movl %0, %%eax\n"
590 " fs movl %1, %%ecx\n"
591 " fs movl %2, %%edx\n"
592 " fs movl %3, %%ebx\n"
593 " fs movl %4, %%esp\n"
594 " fs movl %5, %%ebp\n"
595 " fs movl %6, %%esi\n"
596 " fs movl %7, %%edi\n"
599 " fs movl %%esp, %4\n"
600 " fs movl %12, %%esp\n"
601 " fs movl %%eax, %0\n"
602 " fs movl %%ecx, %1\n"
603 " fs movl %%edx, %2\n"
604 " fs movl %%ebx, %3\n"
605 " fs movl %%ebp, %5\n"
606 " fs movl %%esi, %6\n"
607 " fs movl %%edi, %7\n"
610 " movl %%eax, %%ecx\n"
611 " andl $0x400, %%ecx\n"
613 " andl $0x8d5, %%eax\n"
614 " fs movl %%eax, %8\n"
616 " subl %%ecx, %%eax\n"
617 " fs movl %%eax, %11\n"
618 " fs movl %9, %%ebx\n" /* get T0 value */
621 : "m" (*(uint8_t *)offsetof(CPUState
, regs
[0])),
622 "m" (*(uint8_t *)offsetof(CPUState
, regs
[1])),
623 "m" (*(uint8_t *)offsetof(CPUState
, regs
[2])),
624 "m" (*(uint8_t *)offsetof(CPUState
, regs
[3])),
625 "m" (*(uint8_t *)offsetof(CPUState
, regs
[4])),
626 "m" (*(uint8_t *)offsetof(CPUState
, regs
[5])),
627 "m" (*(uint8_t *)offsetof(CPUState
, regs
[6])),
628 "m" (*(uint8_t *)offsetof(CPUState
, regs
[7])),
629 "m" (*(uint8_t *)offsetof(CPUState
, cc_src
)),
630 "m" (*(uint8_t *)offsetof(CPUState
, tmp0
)),
632 "m" (*(uint8_t *)offsetof(CPUState
, df
)),
633 "m" (*(uint8_t *)offsetof(CPUState
, saved_esp
))
638 #elif defined(__ia64)
645 fp
.gp
= code_gen_buffer
+ 2 * (1 << 20);
646 (*(void (*)(void)) &fp
)();
650 env
->current_tb
= NULL
;
651 /* reset soft MMU for next block (it can currently
652 only be set by a memory fault) */
653 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
654 if (env
->hflags
& HF_SOFTMMU_MASK
) {
655 env
->hflags
&= ~HF_SOFTMMU_MASK
;
656 /* do not allow linking to another block */
667 #if defined(TARGET_I386)
668 #if defined(USE_CODE_COPY)
669 if (env
->native_fp_regs
) {
670 save_native_fp_state(env
);
673 /* restore flags in standard format */
674 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
676 /* restore global registers */
701 #elif defined(TARGET_ARM)
702 env
->cpsr
= compute_cpsr();
703 /* XXX: Save/restore host fpu exception state?. */
704 #elif defined(TARGET_SPARC)
705 #if defined(reg_REGWPTR)
706 REGWPTR
= saved_regwptr
;
708 #elif defined(TARGET_PPC)
709 #elif defined(TARGET_MIPS)
711 #error unsupported target CPU
714 asm volatile ("mov %0, %%i7" : : "r" (saved_i7
));
725 /* must only be called from the generated code as an exception can be
727 void tb_invalidate_page_range(target_ulong start
, target_ulong end
)
729 /* XXX: cannot enable it yet because it yields to MMU exception
730 where NIP != read address on PowerPC */
732 target_ulong phys_addr
;
733 phys_addr
= get_phys_addr_code(env
, start
);
734 tb_invalidate_phys_page_range(phys_addr
, phys_addr
+ end
- start
, 0);
738 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
740 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
)
742 CPUX86State
*saved_env
;
746 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
748 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
749 (selector
<< 4), 0xffff, 0);
751 load_seg(seg_reg
, selector
);
756 void cpu_x86_fsave(CPUX86State
*s
, uint8_t *ptr
, int data32
)
758 CPUX86State
*saved_env
;
763 helper_fsave((target_ulong
)ptr
, data32
);
768 void cpu_x86_frstor(CPUX86State
*s
, uint8_t *ptr
, int data32
)
770 CPUX86State
*saved_env
;
775 helper_frstor((target_ulong
)ptr
, data32
);
780 #endif /* TARGET_I386 */
782 #if !defined(CONFIG_SOFTMMU)
784 #if defined(TARGET_I386)
786 /* 'pc' is the host PC at which the exception was raised. 'address' is
787 the effective address of the memory exception. 'is_write' is 1 if a
788 write caused the exception and otherwise 0'. 'old_set' is the
789 signal set which should be restored */
790 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
791 int is_write
, sigset_t
*old_set
,
794 TranslationBlock
*tb
;
798 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
799 #if defined(DEBUG_SIGNAL)
800 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
801 pc
, address
, is_write
, *(unsigned long *)old_set
);
803 /* XXX: locking issue */
804 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
808 /* see if it is an MMU fault */
809 ret
= cpu_x86_handle_mmu_fault(env
, address
, is_write
,
810 ((env
->hflags
& HF_CPL_MASK
) == 3), 0);
812 return 0; /* not an MMU fault */
814 return 1; /* the MMU fault was handled without causing real CPU fault */
815 /* now we have a real cpu fault */
818 /* the PC is inside the translated code. It means that we have
819 a virtual CPU fault */
820 cpu_restore_state(tb
, env
, pc
, puc
);
824 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
825 env
->eip
, env
->cr
[2], env
->error_code
);
827 /* we restore the process signal mask as the sigreturn should
828 do it (XXX: use sigsetjmp) */
829 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
830 raise_exception_err(EXCP0E_PAGE
, env
->error_code
);
832 /* activate soft MMU for this block */
833 env
->hflags
|= HF_SOFTMMU_MASK
;
834 cpu_resume_from_signal(env
, puc
);
836 /* never comes here */
840 #elif defined(TARGET_ARM)
841 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
842 int is_write
, sigset_t
*old_set
,
845 TranslationBlock
*tb
;
849 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
850 #if defined(DEBUG_SIGNAL)
851 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
852 pc
, address
, is_write
, *(unsigned long *)old_set
);
854 /* XXX: locking issue */
855 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
858 /* see if it is an MMU fault */
859 ret
= cpu_arm_handle_mmu_fault(env
, address
, is_write
, 1, 0);
861 return 0; /* not an MMU fault */
863 return 1; /* the MMU fault was handled without causing real CPU fault */
864 /* now we have a real cpu fault */
867 /* the PC is inside the translated code. It means that we have
868 a virtual CPU fault */
869 cpu_restore_state(tb
, env
, pc
, puc
);
871 /* we restore the process signal mask as the sigreturn should
872 do it (XXX: use sigsetjmp) */
873 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
876 #elif defined(TARGET_SPARC)
877 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
878 int is_write
, sigset_t
*old_set
,
881 TranslationBlock
*tb
;
885 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
886 #if defined(DEBUG_SIGNAL)
887 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
888 pc
, address
, is_write
, *(unsigned long *)old_set
);
890 /* XXX: locking issue */
891 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
894 /* see if it is an MMU fault */
895 ret
= cpu_sparc_handle_mmu_fault(env
, address
, is_write
, 1, 0);
897 return 0; /* not an MMU fault */
899 return 1; /* the MMU fault was handled without causing real CPU fault */
900 /* now we have a real cpu fault */
903 /* the PC is inside the translated code. It means that we have
904 a virtual CPU fault */
905 cpu_restore_state(tb
, env
, pc
, puc
);
907 /* we restore the process signal mask as the sigreturn should
908 do it (XXX: use sigsetjmp) */
909 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
912 #elif defined (TARGET_PPC)
913 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
914 int is_write
, sigset_t
*old_set
,
917 TranslationBlock
*tb
;
921 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
922 #if defined(DEBUG_SIGNAL)
923 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
924 pc
, address
, is_write
, *(unsigned long *)old_set
);
926 /* XXX: locking issue */
927 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
931 /* see if it is an MMU fault */
932 ret
= cpu_ppc_handle_mmu_fault(env
, address
, is_write
, msr_pr
, 0);
934 return 0; /* not an MMU fault */
936 return 1; /* the MMU fault was handled without causing real CPU fault */
938 /* now we have a real cpu fault */
941 /* the PC is inside the translated code. It means that we have
942 a virtual CPU fault */
943 cpu_restore_state(tb
, env
, pc
, puc
);
947 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
948 env
->nip
, env
->error_code
, tb
);
950 /* we restore the process signal mask as the sigreturn should
951 do it (XXX: use sigsetjmp) */
952 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
953 do_raise_exception_err(env
->exception_index
, env
->error_code
);
955 /* activate soft MMU for this block */
956 cpu_resume_from_signal(env
, puc
);
958 /* never comes here */
962 #elif defined (TARGET_MIPS)
963 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
964 int is_write
, sigset_t
*old_set
,
967 TranslationBlock
*tb
;
971 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
972 #if defined(DEBUG_SIGNAL)
973 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
974 pc
, address
, is_write
, *(unsigned long *)old_set
);
976 /* XXX: locking issue */
977 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
981 /* see if it is an MMU fault */
982 ret
= cpu_ppc_handle_mmu_fault(env
, address
, is_write
, msr_pr
, 0);
984 return 0; /* not an MMU fault */
986 return 1; /* the MMU fault was handled without causing real CPU fault */
988 /* now we have a real cpu fault */
991 /* the PC is inside the translated code. It means that we have
992 a virtual CPU fault */
993 cpu_restore_state(tb
, env
, pc
, puc
);
997 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
998 env
->nip
, env
->error_code
, tb
);
1000 /* we restore the process signal mask as the sigreturn should
1001 do it (XXX: use sigsetjmp) */
1002 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1003 do_raise_exception_err(env
->exception_index
, env
->error_code
);
1005 /* activate soft MMU for this block */
1006 cpu_resume_from_signal(env
, puc
);
1008 /* never comes here */
1013 #error unsupported target CPU
1016 #if defined(__i386__)
1018 #if defined(USE_CODE_COPY)
1019 static void cpu_send_trap(unsigned long pc
, int trap
,
1020 struct ucontext
*uc
)
1022 TranslationBlock
*tb
;
1025 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1026 /* now we have a real cpu fault */
1027 tb
= tb_find_pc(pc
);
1029 /* the PC is inside the translated code. It means that we have
1030 a virtual CPU fault */
1031 cpu_restore_state(tb
, env
, pc
, uc
);
1033 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
1034 raise_exception_err(trap
, env
->error_code
);
1038 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1041 struct ucontext
*uc
= puc
;
1049 #define REG_TRAPNO TRAPNO
1051 pc
= uc
->uc_mcontext
.gregs
[REG_EIP
];
1052 trapno
= uc
->uc_mcontext
.gregs
[REG_TRAPNO
];
1053 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1054 if (trapno
== 0x00 || trapno
== 0x05) {
1055 /* send division by zero or bound exception */
1056 cpu_send_trap(pc
, trapno
, uc
);
1060 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1062 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
1063 &uc
->uc_sigmask
, puc
);
1066 #elif defined(__x86_64__)
1068 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1071 struct ucontext
*uc
= puc
;
1074 pc
= uc
->uc_mcontext
.gregs
[REG_RIP
];
1075 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1076 uc
->uc_mcontext
.gregs
[REG_TRAPNO
] == 0xe ?
1077 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
1078 &uc
->uc_sigmask
, puc
);
1081 #elif defined(__powerpc__)
1083 /***********************************************************************
1084 * signal context platform-specific definitions
1088 /* All Registers access - only for local access */
1089 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1090 /* Gpr Registers access */
1091 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1092 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1093 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1094 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1095 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1096 # define LR_sig(context) REG_sig(link, context) /* Link register */
1097 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1098 /* Float Registers access */
1099 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1100 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1101 /* Exception Registers access */
1102 # define DAR_sig(context) REG_sig(dar, context)
1103 # define DSISR_sig(context) REG_sig(dsisr, context)
1104 # define TRAP_sig(context) REG_sig(trap, context)
1108 # include <sys/ucontext.h>
1109 typedef struct ucontext SIGCONTEXT
;
1110 /* All Registers access - only for local access */
1111 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1112 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1113 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1114 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1115 /* Gpr Registers access */
1116 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1117 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1118 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1119 # define CTR_sig(context) REG_sig(ctr, context)
1120 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1121 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1122 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1123 /* Float Registers access */
1124 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1125 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1126 /* Exception Registers access */
1127 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1128 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1129 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1130 #endif /* __APPLE__ */
1132 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1135 struct ucontext
*uc
= puc
;
1143 if (DSISR_sig(uc
) & 0x00800000)
1146 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000))
1149 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1150 is_write
, &uc
->uc_sigmask
, puc
);
1153 #elif defined(__alpha__)
1155 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1158 struct ucontext
*uc
= puc
;
1159 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
1160 uint32_t insn
= *pc
;
1163 /* XXX: need kernel patch to get write flag faster */
1164 switch (insn
>> 26) {
1179 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1180 is_write
, &uc
->uc_sigmask
, puc
);
1182 #elif defined(__sparc__)
1184 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1187 uint32_t *regs
= (uint32_t *)(info
+ 1);
1188 void *sigmask
= (regs
+ 20);
1193 /* XXX: is there a standard glibc define ? */
1195 /* XXX: need kernel patch to get write flag faster */
1197 insn
= *(uint32_t *)pc
;
1198 if ((insn
>> 30) == 3) {
1199 switch((insn
>> 19) & 0x3f) {
1211 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1212 is_write
, sigmask
, NULL
);
1215 #elif defined(__arm__)
1217 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1220 struct ucontext
*uc
= puc
;
1224 pc
= uc
->uc_mcontext
.gregs
[R15
];
1225 /* XXX: compute is_write */
1227 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1232 #elif defined(__mc68000)
1234 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1237 struct ucontext
*uc
= puc
;
1241 pc
= uc
->uc_mcontext
.gregs
[16];
1242 /* XXX: compute is_write */
1244 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1246 &uc
->uc_sigmask
, puc
);
1249 #elif defined(__ia64)
1252 /* This ought to be in <bits/siginfo.h>... */
1253 # define __ISR_VALID 1
1254 # define si_flags _sifields._sigfault._si_pad0
1257 int cpu_signal_handler(int host_signum
, struct siginfo
*info
, void *puc
)
1259 struct ucontext
*uc
= puc
;
1263 ip
= uc
->uc_mcontext
.sc_ip
;
1264 switch (host_signum
) {
1270 if (info
->si_code
&& (info
->si_flags
& __ISR_VALID
))
1271 /* ISR.W (write-access) is bit 33: */
1272 is_write
= (info
->si_isr
>> 33) & 1;
1278 return handle_cpu_signal(ip
, (unsigned long)info
->si_addr
,
1280 &uc
->uc_sigmask
, puc
);
1283 #elif defined(__s390__)
1285 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1288 struct ucontext
*uc
= puc
;
1292 pc
= uc
->uc_mcontext
.psw
.addr
;
1293 /* XXX: compute is_write */
1295 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1297 &uc
->uc_sigmask
, puc
);
1302 #error host CPU specific signal handler needed
1306 #endif /* !defined(CONFIG_SOFTMMU) */