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ARM system emulation (Paul Brook)
[mirror_qemu.git] / cpu-exec.c
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
46 {
47 longjmp(env->jmp_env, 1);
48 }
49 #endif
50 #ifndef TARGET_SPARC
51 #define reg_T2
52 #endif
53
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
58 {
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61 #endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67 #if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72 #endif
73 longjmp(env->jmp_env, 1);
74 }
75
76
77 static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80 {
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
129 T0 = 0;
130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
147 if (tb_invalidated_flag) {
148 /* as some TB could have been invalidated because
149 of memory exceptions while generating the code, we
150 must recompute the hash index here */
151 T0 = 0;
152 }
153 /* we add the TB in the virtual pc hash table */
154 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
155 spin_unlock(&tb_lock);
156 return tb;
157 }
158
159 static inline TranslationBlock *tb_find_fast(void)
160 {
161 TranslationBlock *tb;
162 target_ulong cs_base, pc;
163 unsigned int flags;
164
165 /* we record a subset of the CPU state. It will
166 always be the same before a given translated block
167 is executed. */
168 #if defined(TARGET_I386)
169 flags = env->hflags;
170 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
171 cs_base = env->segs[R_CS].base;
172 pc = cs_base + env->eip;
173 #elif defined(TARGET_ARM)
174 flags = env->thumb | (env->vfp.vec_len << 1)
175 | (env->vfp.vec_stride << 4);
176 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
177 flags |= (1 << 6);
178 cs_base = 0;
179 pc = env->regs[15];
180 #elif defined(TARGET_SPARC)
181 #ifdef TARGET_SPARC64
182 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
183 #else
184 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
185 #endif
186 cs_base = env->npc;
187 pc = env->pc;
188 #elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193 #elif defined(TARGET_MIPS)
194 flags = env->hflags & MIPS_HFLAGS_TMASK;
195 cs_base = NULL;
196 pc = env->PC;
197 #else
198 #error unsupported CPU
199 #endif
200 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
201 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
202 tb->flags != flags, 0)) {
203 tb = tb_find_slow(pc, cs_base, flags);
204 }
205 return tb;
206 }
207
208
209 /* main execution loop */
210
211 int cpu_exec(CPUState *env1)
212 {
213 int saved_T0, saved_T1;
214 #if defined(reg_T2)
215 int saved_T2;
216 #endif
217 CPUState *saved_env;
218 #if defined(TARGET_I386)
219 #ifdef reg_EAX
220 int saved_EAX;
221 #endif
222 #ifdef reg_ECX
223 int saved_ECX;
224 #endif
225 #ifdef reg_EDX
226 int saved_EDX;
227 #endif
228 #ifdef reg_EBX
229 int saved_EBX;
230 #endif
231 #ifdef reg_ESP
232 int saved_ESP;
233 #endif
234 #ifdef reg_EBP
235 int saved_EBP;
236 #endif
237 #ifdef reg_ESI
238 int saved_ESI;
239 #endif
240 #ifdef reg_EDI
241 int saved_EDI;
242 #endif
243 #elif defined(TARGET_SPARC)
244 #if defined(reg_REGWPTR)
245 uint32_t *saved_regwptr;
246 #endif
247 #endif
248 #ifdef __sparc__
249 int saved_i7, tmp_T0;
250 #endif
251 int ret, interrupt_request;
252 void (*gen_func)(void);
253 TranslationBlock *tb;
254 uint8_t *tc_ptr;
255
256 #if defined(TARGET_I386)
257 /* handle exit of HALTED state */
258 if (env1->hflags & HF_HALTED_MASK) {
259 /* disable halt condition */
260 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
261 (env1->eflags & IF_MASK)) {
262 env1->hflags &= ~HF_HALTED_MASK;
263 } else {
264 return EXCP_HALTED;
265 }
266 }
267 #elif defined(TARGET_PPC)
268 if (env1->msr[MSR_POW]) {
269 if (env1->msr[MSR_EE] &&
270 (env1->interrupt_request &
271 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
272 env1->msr[MSR_POW] = 0;
273 } else {
274 return EXCP_HALTED;
275 }
276 }
277 #endif
278
279 cpu_single_env = env1;
280
281 /* first we save global registers */
282 saved_env = env;
283 env = env1;
284 saved_T0 = T0;
285 saved_T1 = T1;
286 #if defined(reg_T2)
287 saved_T2 = T2;
288 #endif
289 #ifdef __sparc__
290 /* we also save i7 because longjmp may not restore it */
291 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
292 #endif
293
294 #if defined(TARGET_I386)
295 #ifdef reg_EAX
296 saved_EAX = EAX;
297 #endif
298 #ifdef reg_ECX
299 saved_ECX = ECX;
300 #endif
301 #ifdef reg_EDX
302 saved_EDX = EDX;
303 #endif
304 #ifdef reg_EBX
305 saved_EBX = EBX;
306 #endif
307 #ifdef reg_ESP
308 saved_ESP = ESP;
309 #endif
310 #ifdef reg_EBP
311 saved_EBP = EBP;
312 #endif
313 #ifdef reg_ESI
314 saved_ESI = ESI;
315 #endif
316 #ifdef reg_EDI
317 saved_EDI = EDI;
318 #endif
319
320 env_to_regs();
321 /* put eflags in CPU temporary format */
322 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
323 DF = 1 - (2 * ((env->eflags >> 10) & 1));
324 CC_OP = CC_OP_EFLAGS;
325 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
326 #elif defined(TARGET_ARM)
327 #elif defined(TARGET_SPARC)
328 #if defined(reg_REGWPTR)
329 saved_regwptr = REGWPTR;
330 #endif
331 #elif defined(TARGET_PPC)
332 #elif defined(TARGET_MIPS)
333 #else
334 #error unsupported target CPU
335 #endif
336 env->exception_index = -1;
337
338 /* prepare setjmp context for exception handling */
339 for(;;) {
340 if (setjmp(env->jmp_env) == 0) {
341 env->current_tb = NULL;
342 /* if an exception is pending, we execute it here */
343 if (env->exception_index >= 0) {
344 if (env->exception_index >= EXCP_INTERRUPT) {
345 /* exit request from the cpu execution loop */
346 ret = env->exception_index;
347 break;
348 } else if (env->user_mode_only) {
349 /* if user mode only, we simulate a fake exception
350 which will be hanlded outside the cpu execution
351 loop */
352 #if defined(TARGET_I386)
353 do_interrupt_user(env->exception_index,
354 env->exception_is_int,
355 env->error_code,
356 env->exception_next_eip);
357 #endif
358 ret = env->exception_index;
359 break;
360 } else {
361 #if defined(TARGET_I386)
362 /* simulate a real cpu exception. On i386, it can
363 trigger new exceptions, but we do not handle
364 double or triple faults yet. */
365 do_interrupt(env->exception_index,
366 env->exception_is_int,
367 env->error_code,
368 env->exception_next_eip, 0);
369 #elif defined(TARGET_PPC)
370 do_interrupt(env);
371 #elif defined(TARGET_MIPS)
372 do_interrupt(env);
373 #elif defined(TARGET_SPARC)
374 do_interrupt(env->exception_index);
375 #elif defined(TARGET_ARM)
376 do_interrupt(env);
377 #endif
378 }
379 env->exception_index = -1;
380 }
381 #ifdef USE_KQEMU
382 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
383 int ret;
384 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
385 ret = kqemu_cpu_exec(env);
386 /* put eflags in CPU temporary format */
387 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
388 DF = 1 - (2 * ((env->eflags >> 10) & 1));
389 CC_OP = CC_OP_EFLAGS;
390 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
391 if (ret == 1) {
392 /* exception */
393 longjmp(env->jmp_env, 1);
394 } else if (ret == 2) {
395 /* softmmu execution needed */
396 } else {
397 if (env->interrupt_request != 0) {
398 /* hardware interrupt will be executed just after */
399 } else {
400 /* otherwise, we restart */
401 longjmp(env->jmp_env, 1);
402 }
403 }
404 }
405 #endif
406
407 T0 = 0; /* force lookup of first TB */
408 for(;;) {
409 #ifdef __sparc__
410 /* g1 can be modified by some libc? functions */
411 tmp_T0 = T0;
412 #endif
413 interrupt_request = env->interrupt_request;
414 if (__builtin_expect(interrupt_request, 0)) {
415 #if defined(TARGET_I386)
416 /* if hardware interrupt pending, we execute it */
417 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
418 (env->eflags & IF_MASK) &&
419 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
420 int intno;
421 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
422 intno = cpu_get_pic_interrupt(env);
423 if (loglevel & CPU_LOG_TB_IN_ASM) {
424 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
425 }
426 do_interrupt(intno, 0, 0, 0, 1);
427 /* ensure that no TB jump will be modified as
428 the program flow was changed */
429 #ifdef __sparc__
430 tmp_T0 = 0;
431 #else
432 T0 = 0;
433 #endif
434 }
435 #elif defined(TARGET_PPC)
436 #if 0
437 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
438 cpu_ppc_reset(env);
439 }
440 #endif
441 if (msr_ee != 0) {
442 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
443 /* Raise it */
444 env->exception_index = EXCP_EXTERNAL;
445 env->error_code = 0;
446 do_interrupt(env);
447 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
448 #ifdef __sparc__
449 tmp_T0 = 0;
450 #else
451 T0 = 0;
452 #endif
453 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
454 /* Raise it */
455 env->exception_index = EXCP_DECR;
456 env->error_code = 0;
457 do_interrupt(env);
458 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
459 #ifdef __sparc__
460 tmp_T0 = 0;
461 #else
462 T0 = 0;
463 #endif
464 }
465 }
466 #elif defined(TARGET_MIPS)
467 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
468 (env->CP0_Status & (1 << CP0St_IE)) &&
469 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
470 !(env->hflags & MIPS_HFLAG_EXL) &&
471 !(env->hflags & MIPS_HFLAG_ERL) &&
472 !(env->hflags & MIPS_HFLAG_DM)) {
473 /* Raise it */
474 env->exception_index = EXCP_EXT_INTERRUPT;
475 env->error_code = 0;
476 do_interrupt(env);
477 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
478 #ifdef __sparc__
479 tmp_T0 = 0;
480 #else
481 T0 = 0;
482 #endif
483 }
484 #elif defined(TARGET_SPARC)
485 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
486 (env->psret != 0)) {
487 int pil = env->interrupt_index & 15;
488 int type = env->interrupt_index & 0xf0;
489
490 if (((type == TT_EXTINT) &&
491 (pil == 15 || pil > env->psrpil)) ||
492 type != TT_EXTINT) {
493 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
494 do_interrupt(env->interrupt_index);
495 env->interrupt_index = 0;
496 #ifdef __sparc__
497 tmp_T0 = 0;
498 #else
499 T0 = 0;
500 #endif
501 }
502 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
503 //do_interrupt(0, 0, 0, 0, 0);
504 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
505 }
506 #elif defined(TARGET_ARM)
507 if (interrupt_request & CPU_INTERRUPT_FIQ
508 && !(env->uncached_cpsr & CPSR_F)) {
509 env->exception_index = EXCP_FIQ;
510 do_interrupt(env);
511 }
512 if (interrupt_request & CPU_INTERRUPT_HARD
513 && !(env->uncached_cpsr & CPSR_I)) {
514 env->exception_index = EXCP_IRQ;
515 do_interrupt(env);
516 }
517 #endif
518 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
519 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
520 /* ensure that no TB jump will be modified as
521 the program flow was changed */
522 #ifdef __sparc__
523 tmp_T0 = 0;
524 #else
525 T0 = 0;
526 #endif
527 }
528 if (interrupt_request & CPU_INTERRUPT_EXIT) {
529 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
530 env->exception_index = EXCP_INTERRUPT;
531 cpu_loop_exit();
532 }
533 }
534 #ifdef DEBUG_EXEC
535 if ((loglevel & CPU_LOG_TB_CPU)) {
536 #if defined(TARGET_I386)
537 /* restore flags in standard format */
538 #ifdef reg_EAX
539 env->regs[R_EAX] = EAX;
540 #endif
541 #ifdef reg_EBX
542 env->regs[R_EBX] = EBX;
543 #endif
544 #ifdef reg_ECX
545 env->regs[R_ECX] = ECX;
546 #endif
547 #ifdef reg_EDX
548 env->regs[R_EDX] = EDX;
549 #endif
550 #ifdef reg_ESI
551 env->regs[R_ESI] = ESI;
552 #endif
553 #ifdef reg_EDI
554 env->regs[R_EDI] = EDI;
555 #endif
556 #ifdef reg_EBP
557 env->regs[R_EBP] = EBP;
558 #endif
559 #ifdef reg_ESP
560 env->regs[R_ESP] = ESP;
561 #endif
562 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
563 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
564 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
565 #elif defined(TARGET_ARM)
566 cpu_dump_state(env, logfile, fprintf, 0);
567 #elif defined(TARGET_SPARC)
568 REGWPTR = env->regbase + (env->cwp * 16);
569 env->regwptr = REGWPTR;
570 cpu_dump_state(env, logfile, fprintf, 0);
571 #elif defined(TARGET_PPC)
572 cpu_dump_state(env, logfile, fprintf, 0);
573 #elif defined(TARGET_MIPS)
574 cpu_dump_state(env, logfile, fprintf, 0);
575 #else
576 #error unsupported target CPU
577 #endif
578 }
579 #endif
580 tb = tb_find_fast();
581 #ifdef DEBUG_EXEC
582 if ((loglevel & CPU_LOG_EXEC)) {
583 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
584 (long)tb->tc_ptr, tb->pc,
585 lookup_symbol(tb->pc));
586 }
587 #endif
588 #ifdef __sparc__
589 T0 = tmp_T0;
590 #endif
591 /* see if we can patch the calling TB. When the TB
592 spans two pages, we cannot safely do a direct
593 jump. */
594 {
595 if (T0 != 0 &&
596 tb->page_addr[1] == -1
597 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
598 && (tb->cflags & CF_CODE_COPY) ==
599 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
600 #endif
601 ) {
602 spin_lock(&tb_lock);
603 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
604 #if defined(USE_CODE_COPY)
605 /* propagates the FP use info */
606 ((TranslationBlock *)(T0 & ~3))->cflags |=
607 (tb->cflags & CF_FP_USED);
608 #endif
609 spin_unlock(&tb_lock);
610 }
611 }
612 tc_ptr = tb->tc_ptr;
613 env->current_tb = tb;
614 /* execute the generated code */
615 gen_func = (void *)tc_ptr;
616 #if defined(__sparc__)
617 __asm__ __volatile__("call %0\n\t"
618 "mov %%o7,%%i0"
619 : /* no outputs */
620 : "r" (gen_func)
621 : "i0", "i1", "i2", "i3", "i4", "i5");
622 #elif defined(__arm__)
623 asm volatile ("mov pc, %0\n\t"
624 ".global exec_loop\n\t"
625 "exec_loop:\n\t"
626 : /* no outputs */
627 : "r" (gen_func)
628 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
629 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
630 {
631 if (!(tb->cflags & CF_CODE_COPY)) {
632 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
633 save_native_fp_state(env);
634 }
635 gen_func();
636 } else {
637 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
638 restore_native_fp_state(env);
639 }
640 /* we work with native eflags */
641 CC_SRC = cc_table[CC_OP].compute_all();
642 CC_OP = CC_OP_EFLAGS;
643 asm(".globl exec_loop\n"
644 "\n"
645 "debug1:\n"
646 " pushl %%ebp\n"
647 " fs movl %10, %9\n"
648 " fs movl %11, %%eax\n"
649 " andl $0x400, %%eax\n"
650 " fs orl %8, %%eax\n"
651 " pushl %%eax\n"
652 " popf\n"
653 " fs movl %%esp, %12\n"
654 " fs movl %0, %%eax\n"
655 " fs movl %1, %%ecx\n"
656 " fs movl %2, %%edx\n"
657 " fs movl %3, %%ebx\n"
658 " fs movl %4, %%esp\n"
659 " fs movl %5, %%ebp\n"
660 " fs movl %6, %%esi\n"
661 " fs movl %7, %%edi\n"
662 " fs jmp *%9\n"
663 "exec_loop:\n"
664 " fs movl %%esp, %4\n"
665 " fs movl %12, %%esp\n"
666 " fs movl %%eax, %0\n"
667 " fs movl %%ecx, %1\n"
668 " fs movl %%edx, %2\n"
669 " fs movl %%ebx, %3\n"
670 " fs movl %%ebp, %5\n"
671 " fs movl %%esi, %6\n"
672 " fs movl %%edi, %7\n"
673 " pushf\n"
674 " popl %%eax\n"
675 " movl %%eax, %%ecx\n"
676 " andl $0x400, %%ecx\n"
677 " shrl $9, %%ecx\n"
678 " andl $0x8d5, %%eax\n"
679 " fs movl %%eax, %8\n"
680 " movl $1, %%eax\n"
681 " subl %%ecx, %%eax\n"
682 " fs movl %%eax, %11\n"
683 " fs movl %9, %%ebx\n" /* get T0 value */
684 " popl %%ebp\n"
685 :
686 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
687 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
688 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
689 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
690 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
691 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
692 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
693 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
694 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
695 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
696 "a" (gen_func),
697 "m" (*(uint8_t *)offsetof(CPUState, df)),
698 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
699 : "%ecx", "%edx"
700 );
701 }
702 }
703 #elif defined(__ia64)
704 struct fptr {
705 void *ip;
706 void *gp;
707 } fp;
708
709 fp.ip = tc_ptr;
710 fp.gp = code_gen_buffer + 2 * (1 << 20);
711 (*(void (*)(void)) &fp)();
712 #else
713 gen_func();
714 #endif
715 env->current_tb = NULL;
716 /* reset soft MMU for next block (it can currently
717 only be set by a memory fault) */
718 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
719 if (env->hflags & HF_SOFTMMU_MASK) {
720 env->hflags &= ~HF_SOFTMMU_MASK;
721 /* do not allow linking to another block */
722 T0 = 0;
723 }
724 #endif
725 }
726 } else {
727 env_to_regs();
728 }
729 } /* for(;;) */
730
731
732 #if defined(TARGET_I386)
733 #if defined(USE_CODE_COPY)
734 if (env->native_fp_regs) {
735 save_native_fp_state(env);
736 }
737 #endif
738 /* restore flags in standard format */
739 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
740
741 /* restore global registers */
742 #ifdef reg_EAX
743 EAX = saved_EAX;
744 #endif
745 #ifdef reg_ECX
746 ECX = saved_ECX;
747 #endif
748 #ifdef reg_EDX
749 EDX = saved_EDX;
750 #endif
751 #ifdef reg_EBX
752 EBX = saved_EBX;
753 #endif
754 #ifdef reg_ESP
755 ESP = saved_ESP;
756 #endif
757 #ifdef reg_EBP
758 EBP = saved_EBP;
759 #endif
760 #ifdef reg_ESI
761 ESI = saved_ESI;
762 #endif
763 #ifdef reg_EDI
764 EDI = saved_EDI;
765 #endif
766 #elif defined(TARGET_ARM)
767 /* XXX: Save/restore host fpu exception state?. */
768 #elif defined(TARGET_SPARC)
769 #if defined(reg_REGWPTR)
770 REGWPTR = saved_regwptr;
771 #endif
772 #elif defined(TARGET_PPC)
773 #elif defined(TARGET_MIPS)
774 #else
775 #error unsupported target CPU
776 #endif
777 #ifdef __sparc__
778 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
779 #endif
780 T0 = saved_T0;
781 T1 = saved_T1;
782 #if defined(reg_T2)
783 T2 = saved_T2;
784 #endif
785 env = saved_env;
786 /* fail safe : never use cpu_single_env outside cpu_exec() */
787 cpu_single_env = NULL;
788 return ret;
789 }
790
791 /* must only be called from the generated code as an exception can be
792 generated */
793 void tb_invalidate_page_range(target_ulong start, target_ulong end)
794 {
795 /* XXX: cannot enable it yet because it yields to MMU exception
796 where NIP != read address on PowerPC */
797 #if 0
798 target_ulong phys_addr;
799 phys_addr = get_phys_addr_code(env, start);
800 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
801 #endif
802 }
803
804 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
805
806 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
807 {
808 CPUX86State *saved_env;
809
810 saved_env = env;
811 env = s;
812 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
813 selector &= 0xffff;
814 cpu_x86_load_seg_cache(env, seg_reg, selector,
815 (selector << 4), 0xffff, 0);
816 } else {
817 load_seg(seg_reg, selector);
818 }
819 env = saved_env;
820 }
821
822 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
823 {
824 CPUX86State *saved_env;
825
826 saved_env = env;
827 env = s;
828
829 helper_fsave((target_ulong)ptr, data32);
830
831 env = saved_env;
832 }
833
834 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
835 {
836 CPUX86State *saved_env;
837
838 saved_env = env;
839 env = s;
840
841 helper_frstor((target_ulong)ptr, data32);
842
843 env = saved_env;
844 }
845
846 #endif /* TARGET_I386 */
847
848 #if !defined(CONFIG_SOFTMMU)
849
850 #if defined(TARGET_I386)
851
852 /* 'pc' is the host PC at which the exception was raised. 'address' is
853 the effective address of the memory exception. 'is_write' is 1 if a
854 write caused the exception and otherwise 0'. 'old_set' is the
855 signal set which should be restored */
856 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
857 int is_write, sigset_t *old_set,
858 void *puc)
859 {
860 TranslationBlock *tb;
861 int ret;
862
863 if (cpu_single_env)
864 env = cpu_single_env; /* XXX: find a correct solution for multithread */
865 #if defined(DEBUG_SIGNAL)
866 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
867 pc, address, is_write, *(unsigned long *)old_set);
868 #endif
869 /* XXX: locking issue */
870 if (is_write && page_unprotect(address, pc, puc)) {
871 return 1;
872 }
873
874 /* see if it is an MMU fault */
875 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
876 ((env->hflags & HF_CPL_MASK) == 3), 0);
877 if (ret < 0)
878 return 0; /* not an MMU fault */
879 if (ret == 0)
880 return 1; /* the MMU fault was handled without causing real CPU fault */
881 /* now we have a real cpu fault */
882 tb = tb_find_pc(pc);
883 if (tb) {
884 /* the PC is inside the translated code. It means that we have
885 a virtual CPU fault */
886 cpu_restore_state(tb, env, pc, puc);
887 }
888 if (ret == 1) {
889 #if 0
890 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
891 env->eip, env->cr[2], env->error_code);
892 #endif
893 /* we restore the process signal mask as the sigreturn should
894 do it (XXX: use sigsetjmp) */
895 sigprocmask(SIG_SETMASK, old_set, NULL);
896 raise_exception_err(EXCP0E_PAGE, env->error_code);
897 } else {
898 /* activate soft MMU for this block */
899 env->hflags |= HF_SOFTMMU_MASK;
900 cpu_resume_from_signal(env, puc);
901 }
902 /* never comes here */
903 return 1;
904 }
905
906 #elif defined(TARGET_ARM)
907 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
908 int is_write, sigset_t *old_set,
909 void *puc)
910 {
911 TranslationBlock *tb;
912 int ret;
913
914 if (cpu_single_env)
915 env = cpu_single_env; /* XXX: find a correct solution for multithread */
916 #if defined(DEBUG_SIGNAL)
917 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
918 pc, address, is_write, *(unsigned long *)old_set);
919 #endif
920 /* XXX: locking issue */
921 if (is_write && page_unprotect(address, pc, puc)) {
922 return 1;
923 }
924 /* see if it is an MMU fault */
925 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
926 if (ret < 0)
927 return 0; /* not an MMU fault */
928 if (ret == 0)
929 return 1; /* the MMU fault was handled without causing real CPU fault */
930 /* now we have a real cpu fault */
931 tb = tb_find_pc(pc);
932 if (tb) {
933 /* the PC is inside the translated code. It means that we have
934 a virtual CPU fault */
935 cpu_restore_state(tb, env, pc, puc);
936 }
937 /* we restore the process signal mask as the sigreturn should
938 do it (XXX: use sigsetjmp) */
939 sigprocmask(SIG_SETMASK, old_set, NULL);
940 cpu_loop_exit();
941 }
942 #elif defined(TARGET_SPARC)
943 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
944 int is_write, sigset_t *old_set,
945 void *puc)
946 {
947 TranslationBlock *tb;
948 int ret;
949
950 if (cpu_single_env)
951 env = cpu_single_env; /* XXX: find a correct solution for multithread */
952 #if defined(DEBUG_SIGNAL)
953 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
954 pc, address, is_write, *(unsigned long *)old_set);
955 #endif
956 /* XXX: locking issue */
957 if (is_write && page_unprotect(address, pc, puc)) {
958 return 1;
959 }
960 /* see if it is an MMU fault */
961 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
962 if (ret < 0)
963 return 0; /* not an MMU fault */
964 if (ret == 0)
965 return 1; /* the MMU fault was handled without causing real CPU fault */
966 /* now we have a real cpu fault */
967 tb = tb_find_pc(pc);
968 if (tb) {
969 /* the PC is inside the translated code. It means that we have
970 a virtual CPU fault */
971 cpu_restore_state(tb, env, pc, puc);
972 }
973 /* we restore the process signal mask as the sigreturn should
974 do it (XXX: use sigsetjmp) */
975 sigprocmask(SIG_SETMASK, old_set, NULL);
976 cpu_loop_exit();
977 }
978 #elif defined (TARGET_PPC)
979 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
980 int is_write, sigset_t *old_set,
981 void *puc)
982 {
983 TranslationBlock *tb;
984 int ret;
985
986 if (cpu_single_env)
987 env = cpu_single_env; /* XXX: find a correct solution for multithread */
988 #if defined(DEBUG_SIGNAL)
989 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
990 pc, address, is_write, *(unsigned long *)old_set);
991 #endif
992 /* XXX: locking issue */
993 if (is_write && page_unprotect(address, pc, puc)) {
994 return 1;
995 }
996
997 /* see if it is an MMU fault */
998 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
999 if (ret < 0)
1000 return 0; /* not an MMU fault */
1001 if (ret == 0)
1002 return 1; /* the MMU fault was handled without causing real CPU fault */
1003
1004 /* now we have a real cpu fault */
1005 tb = tb_find_pc(pc);
1006 if (tb) {
1007 /* the PC is inside the translated code. It means that we have
1008 a virtual CPU fault */
1009 cpu_restore_state(tb, env, pc, puc);
1010 }
1011 if (ret == 1) {
1012 #if 0
1013 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1014 env->nip, env->error_code, tb);
1015 #endif
1016 /* we restore the process signal mask as the sigreturn should
1017 do it (XXX: use sigsetjmp) */
1018 sigprocmask(SIG_SETMASK, old_set, NULL);
1019 do_raise_exception_err(env->exception_index, env->error_code);
1020 } else {
1021 /* activate soft MMU for this block */
1022 cpu_resume_from_signal(env, puc);
1023 }
1024 /* never comes here */
1025 return 1;
1026 }
1027
1028 #elif defined (TARGET_MIPS)
1029 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1030 int is_write, sigset_t *old_set,
1031 void *puc)
1032 {
1033 TranslationBlock *tb;
1034 int ret;
1035
1036 if (cpu_single_env)
1037 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1038 #if defined(DEBUG_SIGNAL)
1039 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1040 pc, address, is_write, *(unsigned long *)old_set);
1041 #endif
1042 /* XXX: locking issue */
1043 if (is_write && page_unprotect(address, pc, puc)) {
1044 return 1;
1045 }
1046
1047 /* see if it is an MMU fault */
1048 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1049 if (ret < 0)
1050 return 0; /* not an MMU fault */
1051 if (ret == 0)
1052 return 1; /* the MMU fault was handled without causing real CPU fault */
1053
1054 /* now we have a real cpu fault */
1055 tb = tb_find_pc(pc);
1056 if (tb) {
1057 /* the PC is inside the translated code. It means that we have
1058 a virtual CPU fault */
1059 cpu_restore_state(tb, env, pc, puc);
1060 }
1061 if (ret == 1) {
1062 #if 0
1063 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1064 env->nip, env->error_code, tb);
1065 #endif
1066 /* we restore the process signal mask as the sigreturn should
1067 do it (XXX: use sigsetjmp) */
1068 sigprocmask(SIG_SETMASK, old_set, NULL);
1069 do_raise_exception_err(env->exception_index, env->error_code);
1070 } else {
1071 /* activate soft MMU for this block */
1072 cpu_resume_from_signal(env, puc);
1073 }
1074 /* never comes here */
1075 return 1;
1076 }
1077
1078 #else
1079 #error unsupported target CPU
1080 #endif
1081
1082 #if defined(__i386__)
1083
1084 #if defined(USE_CODE_COPY)
1085 static void cpu_send_trap(unsigned long pc, int trap,
1086 struct ucontext *uc)
1087 {
1088 TranslationBlock *tb;
1089
1090 if (cpu_single_env)
1091 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1092 /* now we have a real cpu fault */
1093 tb = tb_find_pc(pc);
1094 if (tb) {
1095 /* the PC is inside the translated code. It means that we have
1096 a virtual CPU fault */
1097 cpu_restore_state(tb, env, pc, uc);
1098 }
1099 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1100 raise_exception_err(trap, env->error_code);
1101 }
1102 #endif
1103
1104 int cpu_signal_handler(int host_signum, struct siginfo *info,
1105 void *puc)
1106 {
1107 struct ucontext *uc = puc;
1108 unsigned long pc;
1109 int trapno;
1110
1111 #ifndef REG_EIP
1112 /* for glibc 2.1 */
1113 #define REG_EIP EIP
1114 #define REG_ERR ERR
1115 #define REG_TRAPNO TRAPNO
1116 #endif
1117 pc = uc->uc_mcontext.gregs[REG_EIP];
1118 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1119 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1120 if (trapno == 0x00 || trapno == 0x05) {
1121 /* send division by zero or bound exception */
1122 cpu_send_trap(pc, trapno, uc);
1123 return 1;
1124 } else
1125 #endif
1126 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1127 trapno == 0xe ?
1128 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1129 &uc->uc_sigmask, puc);
1130 }
1131
1132 #elif defined(__x86_64__)
1133
1134 int cpu_signal_handler(int host_signum, struct siginfo *info,
1135 void *puc)
1136 {
1137 struct ucontext *uc = puc;
1138 unsigned long pc;
1139
1140 pc = uc->uc_mcontext.gregs[REG_RIP];
1141 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1142 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1143 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1144 &uc->uc_sigmask, puc);
1145 }
1146
1147 #elif defined(__powerpc__)
1148
1149 /***********************************************************************
1150 * signal context platform-specific definitions
1151 * From Wine
1152 */
1153 #ifdef linux
1154 /* All Registers access - only for local access */
1155 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1156 /* Gpr Registers access */
1157 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1158 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1159 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1160 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1161 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1162 # define LR_sig(context) REG_sig(link, context) /* Link register */
1163 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1164 /* Float Registers access */
1165 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1166 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1167 /* Exception Registers access */
1168 # define DAR_sig(context) REG_sig(dar, context)
1169 # define DSISR_sig(context) REG_sig(dsisr, context)
1170 # define TRAP_sig(context) REG_sig(trap, context)
1171 #endif /* linux */
1172
1173 #ifdef __APPLE__
1174 # include <sys/ucontext.h>
1175 typedef struct ucontext SIGCONTEXT;
1176 /* All Registers access - only for local access */
1177 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1178 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1179 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1180 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1181 /* Gpr Registers access */
1182 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1183 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1184 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1185 # define CTR_sig(context) REG_sig(ctr, context)
1186 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1187 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1188 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1189 /* Float Registers access */
1190 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1191 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1192 /* Exception Registers access */
1193 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1194 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1195 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1196 #endif /* __APPLE__ */
1197
1198 int cpu_signal_handler(int host_signum, struct siginfo *info,
1199 void *puc)
1200 {
1201 struct ucontext *uc = puc;
1202 unsigned long pc;
1203 int is_write;
1204
1205 pc = IAR_sig(uc);
1206 is_write = 0;
1207 #if 0
1208 /* ppc 4xx case */
1209 if (DSISR_sig(uc) & 0x00800000)
1210 is_write = 1;
1211 #else
1212 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1213 is_write = 1;
1214 #endif
1215 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1216 is_write, &uc->uc_sigmask, puc);
1217 }
1218
1219 #elif defined(__alpha__)
1220
1221 int cpu_signal_handler(int host_signum, struct siginfo *info,
1222 void *puc)
1223 {
1224 struct ucontext *uc = puc;
1225 uint32_t *pc = uc->uc_mcontext.sc_pc;
1226 uint32_t insn = *pc;
1227 int is_write = 0;
1228
1229 /* XXX: need kernel patch to get write flag faster */
1230 switch (insn >> 26) {
1231 case 0x0d: // stw
1232 case 0x0e: // stb
1233 case 0x0f: // stq_u
1234 case 0x24: // stf
1235 case 0x25: // stg
1236 case 0x26: // sts
1237 case 0x27: // stt
1238 case 0x2c: // stl
1239 case 0x2d: // stq
1240 case 0x2e: // stl_c
1241 case 0x2f: // stq_c
1242 is_write = 1;
1243 }
1244
1245 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1246 is_write, &uc->uc_sigmask, puc);
1247 }
1248 #elif defined(__sparc__)
1249
1250 int cpu_signal_handler(int host_signum, struct siginfo *info,
1251 void *puc)
1252 {
1253 uint32_t *regs = (uint32_t *)(info + 1);
1254 void *sigmask = (regs + 20);
1255 unsigned long pc;
1256 int is_write;
1257 uint32_t insn;
1258
1259 /* XXX: is there a standard glibc define ? */
1260 pc = regs[1];
1261 /* XXX: need kernel patch to get write flag faster */
1262 is_write = 0;
1263 insn = *(uint32_t *)pc;
1264 if ((insn >> 30) == 3) {
1265 switch((insn >> 19) & 0x3f) {
1266 case 0x05: // stb
1267 case 0x06: // sth
1268 case 0x04: // st
1269 case 0x07: // std
1270 case 0x24: // stf
1271 case 0x27: // stdf
1272 case 0x25: // stfsr
1273 is_write = 1;
1274 break;
1275 }
1276 }
1277 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1278 is_write, sigmask, NULL);
1279 }
1280
1281 #elif defined(__arm__)
1282
1283 int cpu_signal_handler(int host_signum, struct siginfo *info,
1284 void *puc)
1285 {
1286 struct ucontext *uc = puc;
1287 unsigned long pc;
1288 int is_write;
1289
1290 pc = uc->uc_mcontext.gregs[R15];
1291 /* XXX: compute is_write */
1292 is_write = 0;
1293 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1294 is_write,
1295 &uc->uc_sigmask);
1296 }
1297
1298 #elif defined(__mc68000)
1299
1300 int cpu_signal_handler(int host_signum, struct siginfo *info,
1301 void *puc)
1302 {
1303 struct ucontext *uc = puc;
1304 unsigned long pc;
1305 int is_write;
1306
1307 pc = uc->uc_mcontext.gregs[16];
1308 /* XXX: compute is_write */
1309 is_write = 0;
1310 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1311 is_write,
1312 &uc->uc_sigmask, puc);
1313 }
1314
1315 #elif defined(__ia64)
1316
1317 #ifndef __ISR_VALID
1318 /* This ought to be in <bits/siginfo.h>... */
1319 # define __ISR_VALID 1
1320 # define si_flags _sifields._sigfault._si_pad0
1321 #endif
1322
1323 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1324 {
1325 struct ucontext *uc = puc;
1326 unsigned long ip;
1327 int is_write = 0;
1328
1329 ip = uc->uc_mcontext.sc_ip;
1330 switch (host_signum) {
1331 case SIGILL:
1332 case SIGFPE:
1333 case SIGSEGV:
1334 case SIGBUS:
1335 case SIGTRAP:
1336 if (info->si_code && (info->si_flags & __ISR_VALID))
1337 /* ISR.W (write-access) is bit 33: */
1338 is_write = (info->si_isr >> 33) & 1;
1339 break;
1340
1341 default:
1342 break;
1343 }
1344 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1345 is_write,
1346 &uc->uc_sigmask, puc);
1347 }
1348
1349 #elif defined(__s390__)
1350
1351 int cpu_signal_handler(int host_signum, struct siginfo *info,
1352 void *puc)
1353 {
1354 struct ucontext *uc = puc;
1355 unsigned long pc;
1356 int is_write;
1357
1358 pc = uc->uc_mcontext.psw.addr;
1359 /* XXX: compute is_write */
1360 is_write = 0;
1361 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1362 is_write,
1363 &uc->uc_sigmask, puc);
1364 }
1365
1366 #else
1367
1368 #error host CPU specific signal handler needed
1369
1370 #endif
1371
1372 #endif /* !defined(CONFIG_SOFTMMU) */
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