cpu-exec.c

   1 /*
   2  *  emulator main execution loop
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "tcg.h"
  23 #include "qemu/atomic.h"
  24 #include "sysemu/qtest.h"
  25
  26 //#define CONFIG_DEBUG_EXEC
  27
  28 bool qemu_cpu_has_work(CPUState *cpu)
  29 {
  30     return cpu_has_work(cpu);
  31 }
  32
  33 void cpu_loop_exit(CPUArchState *env)
  34 {
  35     CPUState *cpu = ENV_GET_CPU(env);
  36
  37     cpu->current_tb = NULL;
  38     siglongjmp(env->jmp_env, 1);
  39 }
  40
  41 /* exit the current TB from a signal handler. The host registers are
  42    restored in a state compatible with the CPU emulator
  43  */
  44 #if defined(CONFIG_SOFTMMU)
  45 void cpu_resume_from_signal(CPUArchState *env, void *puc)
  46 {
  47     /* XXX: restore cpu registers saved in host registers */
  48
  49     env->exception_index = -1;
  50     siglongjmp(env->jmp_env, 1);
  51 }
  52 #endif
  53
  54 /* Execute a TB, and fix up the CPU state afterwards if necessary */
  55 static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
  56 {
  57     CPUArchState *env = cpu->env_ptr;
  58     tcg_target_ulong next_tb = tcg_qemu_tb_exec(env, tb_ptr);
  59     if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
  60         /* We didn't start executing this TB (eg because the instruction
  61          * counter hit zero); we must restore the guest PC to the address
  62          * of the start of the TB.
  63          */
  64         TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
  65         cpu_pc_from_tb(env, tb);
  66     }
  67     return next_tb;
  68 }
  69
  70 /* Execute the code without caching the generated code. An interpreter
  71    could be used if available. */
  72 static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
  73                              TranslationBlock *orig_tb)
  74 {
  75     CPUState *cpu = ENV_GET_CPU(env);
  76     TranslationBlock *tb;
  77
  78     /* Should never happen.
  79        We only end up here when an existing TB is too long.  */
  80     if (max_cycles > CF_COUNT_MASK)
  81         max_cycles = CF_COUNT_MASK;
  82
  83     tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
  84                      max_cycles);
  85     cpu->current_tb = tb;
  86     /* execute the generated code */
  87     cpu_tb_exec(cpu, tb->tc_ptr);
  88     cpu->current_tb = NULL;
  89     tb_phys_invalidate(tb, -1);
  90     tb_free(tb);
  91 }
  92
  93 static TranslationBlock *tb_find_slow(CPUArchState *env,
  94                                       target_ulong pc,
  95                                       target_ulong cs_base,
  96                                       uint64_t flags)
  97 {
  98     TranslationBlock *tb, **ptb1;
  99     unsigned int h;
 100     tb_page_addr_t phys_pc, phys_page1;
 101     target_ulong virt_page2;
 102
 103     tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
 104
 105     /* find translated block using physical mappings */
 106     phys_pc = get_page_addr_code(env, pc);
 107     phys_page1 = phys_pc & TARGET_PAGE_MASK;
 108     h = tb_phys_hash_func(phys_pc);
 109     ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
 110     for(;;) {
 111         tb = *ptb1;
 112         if (!tb)
 113             goto not_found;
 114         if (tb->pc == pc &&
 115             tb->page_addr[0] == phys_page1 &&
 116             tb->cs_base == cs_base &&
 117             tb->flags == flags) {
 118             /* check next page if needed */
 119             if (tb->page_addr[1] != -1) {
 120                 tb_page_addr_t phys_page2;
 121
 122                 virt_page2 = (pc & TARGET_PAGE_MASK) +
 123                     TARGET_PAGE_SIZE;
 124                 phys_page2 = get_page_addr_code(env, virt_page2);
 125                 if (tb->page_addr[1] == phys_page2)
 126                     goto found;
 127             } else {
 128                 goto found;
 129             }
 130         }
 131         ptb1 = &tb->phys_hash_next;
 132     }
 133  not_found:
 134    /* if no translated code available, then translate it now */
 135     tb = tb_gen_code(env, pc, cs_base, flags, 0);
 136
 137  found:
 138     /* Move the last found TB to the head of the list */
 139     if (likely(*ptb1)) {
 140         *ptb1 = tb->phys_hash_next;
 141         tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
 142         tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
 143     }
 144     /* we add the TB in the virtual pc hash table */
 145     env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
 146     return tb;
 147 }
 148
 149 static inline TranslationBlock *tb_find_fast(CPUArchState *env)
 150 {
 151     TranslationBlock *tb;
 152     target_ulong cs_base, pc;
 153     int flags;
 154
 155     /* we record a subset of the CPU state. It will
 156        always be the same before a given translated block
 157        is executed. */
 158     cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
 159     tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
 160     if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
 161                  tb->flags != flags)) {
 162         tb = tb_find_slow(env, pc, cs_base, flags);
 163     }
 164     return tb;
 165 }
 166
 167 static CPUDebugExcpHandler *debug_excp_handler;
 168
 169 void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
 170 {
 171     debug_excp_handler = handler;
 172 }
 173
 174 static void cpu_handle_debug_exception(CPUArchState *env)
 175 {
 176     CPUWatchpoint *wp;
 177
 178     if (!env->watchpoint_hit) {
 179         QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
 180             wp->flags &= ~BP_WATCHPOINT_HIT;
 181         }
 182     }
 183     if (debug_excp_handler) {
 184         debug_excp_handler(env);
 185     }
 186 }
 187
 188 /* main execution loop */
 189
 190 volatile sig_atomic_t exit_request;
 191
 192 int cpu_exec(CPUArchState *env)
 193 {
 194     CPUState *cpu = ENV_GET_CPU(env);
 195     int ret, interrupt_request;
 196     TranslationBlock *tb;
 197     uint8_t *tc_ptr;
 198     tcg_target_ulong next_tb;
 199
 200     if (env->halted) {
 201         if (!cpu_has_work(cpu)) {
 202             return EXCP_HALTED;
 203         }
 204
 205         env->halted = 0;
 206     }
 207
 208     cpu_single_env = env;
 209
 210     if (unlikely(exit_request)) {
 211         cpu->exit_request = 1;
 212     }
 213
 214 #if defined(TARGET_I386)
 215     /* put eflags in CPU temporary format */
 216     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 217     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 218     CC_OP = CC_OP_EFLAGS;
 219     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 220 #elif defined(TARGET_SPARC)
 221 #elif defined(TARGET_M68K)
 222     env->cc_op = CC_OP_FLAGS;
 223     env->cc_dest = env->sr & 0xf;
 224     env->cc_x = (env->sr >> 4) & 1;
 225 #elif defined(TARGET_ALPHA)
 226 #elif defined(TARGET_ARM)
 227 #elif defined(TARGET_UNICORE32)
 228 #elif defined(TARGET_PPC)
 229     env->reserve_addr = -1;
 230 #elif defined(TARGET_LM32)
 231 #elif defined(TARGET_MICROBLAZE)
 232 #elif defined(TARGET_MIPS)
 233 #elif defined(TARGET_OPENRISC)
 234 #elif defined(TARGET_SH4)
 235 #elif defined(TARGET_CRIS)
 236 #elif defined(TARGET_S390X)
 237 #elif defined(TARGET_XTENSA)
 238     /* XXXXX */
 239 #else
 240 #error unsupported target CPU
 241 #endif
 242     env->exception_index = -1;
 243
 244     /* prepare setjmp context for exception handling */
 245     for(;;) {
 246         if (sigsetjmp(env->jmp_env, 0) == 0) {
 247             /* if an exception is pending, we execute it here */
 248             if (env->exception_index >= 0) {
 249                 if (env->exception_index >= EXCP_INTERRUPT) {
 250                     /* exit request from the cpu execution loop */
 251                     ret = env->exception_index;
 252                     if (ret == EXCP_DEBUG) {
 253                         cpu_handle_debug_exception(env);
 254                     }
 255                     break;
 256                 } else {
 257 #if defined(CONFIG_USER_ONLY)
 258                     /* if user mode only, we simulate a fake exception
 259                        which will be handled outside the cpu execution
 260                        loop */
 261 #if defined(TARGET_I386)
 262                     do_interrupt(env);
 263 #endif
 264                     ret = env->exception_index;
 265                     break;
 266 #else
 267                     do_interrupt(env);
 268                     env->exception_index = -1;
 269 #endif
 270                 }
 271             }
 272
 273             next_tb = 0; /* force lookup of first TB */
 274             for(;;) {
 275                 interrupt_request = env->interrupt_request;
 276                 if (unlikely(interrupt_request)) {
 277                     if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
 278                         /* Mask out external interrupts for this step. */
 279                         interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
 280                     }
 281                     if (interrupt_request & CPU_INTERRUPT_DEBUG) {
 282                         env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
 283                         env->exception_index = EXCP_DEBUG;
 284                         cpu_loop_exit(env);
 285                     }
 286 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
 287     defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
 288     defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
 289                     if (interrupt_request & CPU_INTERRUPT_HALT) {
 290                         env->interrupt_request &= ~CPU_INTERRUPT_HALT;
 291                         env->halted = 1;
 292                         env->exception_index = EXCP_HLT;
 293                         cpu_loop_exit(env);
 294                     }
 295 #endif
 296 #if defined(TARGET_I386)
 297 #if !defined(CONFIG_USER_ONLY)
 298                     if (interrupt_request & CPU_INTERRUPT_POLL) {
 299                         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
 300                         apic_poll_irq(env->apic_state);
 301                     }
 302 #endif
 303                     if (interrupt_request & CPU_INTERRUPT_INIT) {
 304                             cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
 305                                                           0);
 306                             do_cpu_init(x86_env_get_cpu(env));
 307                             env->exception_index = EXCP_HALTED;
 308                             cpu_loop_exit(env);
 309                     } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
 310                             do_cpu_sipi(x86_env_get_cpu(env));
 311                     } else if (env->hflags2 & HF2_GIF_MASK) {
 312                         if ((interrupt_request & CPU_INTERRUPT_SMI) &&
 313                             !(env->hflags & HF_SMM_MASK)) {
 314                             cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
 315                                                           0);
 316                             env->interrupt_request &= ~CPU_INTERRUPT_SMI;
 317                             do_smm_enter(env);
 318                             next_tb = 0;
 319                         } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
 320                                    !(env->hflags2 & HF2_NMI_MASK)) {
 321                             env->interrupt_request &= ~CPU_INTERRUPT_NMI;
 322                             env->hflags2 |= HF2_NMI_MASK;
 323                             do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
 324                             next_tb = 0;
 325                         } else if (interrupt_request & CPU_INTERRUPT_MCE) {
 326                             env->interrupt_request &= ~CPU_INTERRUPT_MCE;
 327                             do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
 328                             next_tb = 0;
 329                         } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 330                                    (((env->hflags2 & HF2_VINTR_MASK) &&
 331                                      (env->hflags2 & HF2_HIF_MASK)) ||
 332                                     (!(env->hflags2 & HF2_VINTR_MASK) &&
 333                                      (env->eflags & IF_MASK &&
 334                                       !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
 335                             int intno;
 336                             cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
 337                                                           0);
 338                             env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
 339                             intno = cpu_get_pic_interrupt(env);
 340                             qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
 341                             do_interrupt_x86_hardirq(env, intno, 1);
 342                             /* ensure that no TB jump will be modified as
 343                                the program flow was changed */
 344                             next_tb = 0;
 345 #if !defined(CONFIG_USER_ONLY)
 346                         } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
 347                                    (env->eflags & IF_MASK) &&
 348                                    !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
 349                             int intno;
 350                             /* FIXME: this should respect TPR */
 351                             cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
 352                                                           0);
 353                             intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
 354                             qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
 355                             do_interrupt_x86_hardirq(env, intno, 1);
 356                             env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
 357                             next_tb = 0;
 358 #endif
 359                         }
 360                     }
 361 #elif defined(TARGET_PPC)
 362                     if ((interrupt_request & CPU_INTERRUPT_RESET)) {
 363                         cpu_reset(cpu);
 364                     }
 365                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 366                         ppc_hw_interrupt(env);
 367                         if (env->pending_interrupts == 0)
 368                             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 369                         next_tb = 0;
 370                     }
 371 #elif defined(TARGET_LM32)
 372                     if ((interrupt_request & CPU_INTERRUPT_HARD)
 373                         && (env->ie & IE_IE)) {
 374                         env->exception_index = EXCP_IRQ;
 375                         do_interrupt(env);
 376                         next_tb = 0;
 377                     }
 378 #elif defined(TARGET_MICROBLAZE)
 379                     if ((interrupt_request & CPU_INTERRUPT_HARD)
 380                         && (env->sregs[SR_MSR] & MSR_IE)
 381                         && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
 382                         && !(env->iflags & (D_FLAG | IMM_FLAG))) {
 383                         env->exception_index = EXCP_IRQ;
 384                         do_interrupt(env);
 385                         next_tb = 0;
 386                     }
 387 #elif defined(TARGET_MIPS)
 388                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 389                         cpu_mips_hw_interrupts_pending(env)) {
 390                         /* Raise it */
 391                         env->exception_index = EXCP_EXT_INTERRUPT;
 392                         env->error_code = 0;
 393                         do_interrupt(env);
 394                         next_tb = 0;
 395                     }
 396 #elif defined(TARGET_OPENRISC)
 397                     {
 398                         int idx = -1;
 399                         if ((interrupt_request & CPU_INTERRUPT_HARD)
 400                             && (env->sr & SR_IEE)) {
 401                             idx = EXCP_INT;
 402                         }
 403                         if ((interrupt_request & CPU_INTERRUPT_TIMER)
 404                             && (env->sr & SR_TEE)) {
 405                             idx = EXCP_TICK;
 406                         }
 407                         if (idx >= 0) {
 408                             env->exception_index = idx;
 409                             do_interrupt(env);
 410                             next_tb = 0;
 411                         }
 412                     }
 413 #elif defined(TARGET_SPARC)
 414                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 415                         if (cpu_interrupts_enabled(env) &&
 416                             env->interrupt_index > 0) {
 417                             int pil = env->interrupt_index & 0xf;
 418                             int type = env->interrupt_index & 0xf0;
 419
 420                             if (((type == TT_EXTINT) &&
 421                                   cpu_pil_allowed(env, pil)) ||
 422                                   type != TT_EXTINT) {
 423                                 env->exception_index = env->interrupt_index;
 424                                 do_interrupt(env);
 425                                 next_tb = 0;
 426                             }
 427                         }
 428                     }
 429 #elif defined(TARGET_ARM)
 430                     if (interrupt_request & CPU_INTERRUPT_FIQ
 431                         && !(env->uncached_cpsr & CPSR_F)) {
 432                         env->exception_index = EXCP_FIQ;
 433                         do_interrupt(env);
 434                         next_tb = 0;
 435                     }
 436                     /* ARMv7-M interrupt return works by loading a magic value
 437                        into the PC.  On real hardware the load causes the
 438                        return to occur.  The qemu implementation performs the
 439                        jump normally, then does the exception return when the
 440                        CPU tries to execute code at the magic address.
 441                        This will cause the magic PC value to be pushed to
 442                        the stack if an interrupt occurred at the wrong time.
 443                        We avoid this by disabling interrupts when
 444                        pc contains a magic address.  */
 445                     if (interrupt_request & CPU_INTERRUPT_HARD
 446                         && ((IS_M(env) && env->regs[15] < 0xfffffff0)
 447                             || !(env->uncached_cpsr & CPSR_I))) {
 448                         env->exception_index = EXCP_IRQ;
 449                         do_interrupt(env);
 450                         next_tb = 0;
 451                     }
 452 #elif defined(TARGET_UNICORE32)
 453                     if (interrupt_request & CPU_INTERRUPT_HARD
 454                         && !(env->uncached_asr & ASR_I)) {
 455                         env->exception_index = UC32_EXCP_INTR;
 456                         do_interrupt(env);
 457                         next_tb = 0;
 458                     }
 459 #elif defined(TARGET_SH4)
 460                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 461                         do_interrupt(env);
 462                         next_tb = 0;
 463                     }
 464 #elif defined(TARGET_ALPHA)
 465                     {
 466                         int idx = -1;
 467                         /* ??? This hard-codes the OSF/1 interrupt levels.  */
 468                         switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
 469                         case 0 ... 3:
 470                             if (interrupt_request & CPU_INTERRUPT_HARD) {
 471                                 idx = EXCP_DEV_INTERRUPT;
 472                             }
 473                             /* FALLTHRU */
 474                         case 4:
 475                             if (interrupt_request & CPU_INTERRUPT_TIMER) {
 476                                 idx = EXCP_CLK_INTERRUPT;
 477                             }
 478                             /* FALLTHRU */
 479                         case 5:
 480                             if (interrupt_request & CPU_INTERRUPT_SMP) {
 481                                 idx = EXCP_SMP_INTERRUPT;
 482                             }
 483                             /* FALLTHRU */
 484                         case 6:
 485                             if (interrupt_request & CPU_INTERRUPT_MCHK) {
 486                                 idx = EXCP_MCHK;
 487                             }
 488                         }
 489                         if (idx >= 0) {
 490                             env->exception_index = idx;
 491                             env->error_code = 0;
 492                             do_interrupt(env);
 493                             next_tb = 0;
 494                         }
 495                     }
 496 #elif defined(TARGET_CRIS)
 497                     if (interrupt_request & CPU_INTERRUPT_HARD
 498                         && (env->pregs[PR_CCS] & I_FLAG)
 499                         && !env->locked_irq) {
 500                         env->exception_index = EXCP_IRQ;
 501                         do_interrupt(env);
 502                         next_tb = 0;
 503                     }
 504                     if (interrupt_request & CPU_INTERRUPT_NMI) {
 505                         unsigned int m_flag_archval;
 506                         if (env->pregs[PR_VR] < 32) {
 507                             m_flag_archval = M_FLAG_V10;
 508                         } else {
 509                             m_flag_archval = M_FLAG_V32;
 510                         }
 511                         if ((env->pregs[PR_CCS] & m_flag_archval)) {
 512                             env->exception_index = EXCP_NMI;
 513                             do_interrupt(env);
 514                             next_tb = 0;
 515                         }
 516                     }
 517 #elif defined(TARGET_M68K)
 518                     if (interrupt_request & CPU_INTERRUPT_HARD
 519                         && ((env->sr & SR_I) >> SR_I_SHIFT)
 520                             < env->pending_level) {
 521                         /* Real hardware gets the interrupt vector via an
 522                            IACK cycle at this point.  Current emulated
 523                            hardware doesn't rely on this, so we
 524                            provide/save the vector when the interrupt is
 525                            first signalled.  */
 526                         env->exception_index = env->pending_vector;
 527                         do_interrupt_m68k_hardirq(env);
 528                         next_tb = 0;
 529                     }
 530 #elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
 531                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 532                         (env->psw.mask & PSW_MASK_EXT)) {
 533                         do_interrupt(env);
 534                         next_tb = 0;
 535                     }
 536 #elif defined(TARGET_XTENSA)
 537                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 538                         env->exception_index = EXC_IRQ;
 539                         do_interrupt(env);
 540                         next_tb = 0;
 541                     }
 542 #endif
 543                    /* Don't use the cached interrupt_request value,
 544                       do_interrupt may have updated the EXITTB flag. */
 545                     if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
 546                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
 547                         /* ensure that no TB jump will be modified as
 548                            the program flow was changed */
 549                         next_tb = 0;
 550                     }
 551                 }
 552                 if (unlikely(cpu->exit_request)) {
 553                     cpu->exit_request = 0;
 554                     env->exception_index = EXCP_INTERRUPT;
 555                     cpu_loop_exit(env);
 556                 }
 557 #if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
 558                 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
 559                     /* restore flags in standard format */
 560 #if defined(TARGET_I386)
 561                     env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
 562                         | (DF & DF_MASK);
 563                     log_cpu_state(env, CPU_DUMP_CCOP);
 564                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 565 #elif defined(TARGET_M68K)
 566                     cpu_m68k_flush_flags(env, env->cc_op);
 567                     env->cc_op = CC_OP_FLAGS;
 568                     env->sr = (env->sr & 0xffe0)
 569                               | env->cc_dest | (env->cc_x << 4);
 570                     log_cpu_state(env, 0);
 571 #else
 572                     log_cpu_state(env, 0);
 573 #endif
 574                 }
 575 #endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
 576                 spin_lock(&tcg_ctx.tb_ctx.tb_lock);
 577                 tb = tb_find_fast(env);
 578                 /* Note: we do it here to avoid a gcc bug on Mac OS X when
 579                    doing it in tb_find_slow */
 580                 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
 581                     /* as some TB could have been invalidated because
 582                        of memory exceptions while generating the code, we
 583                        must recompute the hash index here */
 584                     next_tb = 0;
 585                     tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
 586                 }
 587 #ifdef CONFIG_DEBUG_EXEC
 588                 qemu_log_mask(CPU_LOG_EXEC, "Trace %p [" TARGET_FMT_lx "] %s\n",
 589                              tb->tc_ptr, tb->pc,
 590                              lookup_symbol(tb->pc));
 591 #endif
 592                 /* see if we can patch the calling TB. When the TB
 593                    spans two pages, we cannot safely do a direct
 594                    jump. */
 595                 if (next_tb != 0 && tb->page_addr[1] == -1) {
 596                     tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
 597                                 next_tb & TB_EXIT_MASK, tb);
 598                 }
 599                 spin_unlock(&tcg_ctx.tb_ctx.tb_lock);
 600
 601                 /* cpu_interrupt might be called while translating the
 602                    TB, but before it is linked into a potentially
 603                    infinite loop and becomes env->current_tb. Avoid
 604                    starting execution if there is a pending interrupt. */
 605                 cpu->current_tb = tb;
 606                 barrier();
 607                 if (likely(!cpu->exit_request)) {
 608                     tc_ptr = tb->tc_ptr;
 609                     /* execute the generated code */
 610                     next_tb = cpu_tb_exec(cpu, tc_ptr);
 611                     if ((next_tb & TB_EXIT_MASK) == TB_EXIT_ICOUNT_EXPIRED) {
 612                         /* Instruction counter expired.  */
 613                         int insns_left;
 614                         tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
 615                         insns_left = env->icount_decr.u32;
 616                         if (env->icount_extra && insns_left >= 0) {
 617                             /* Refill decrementer and continue execution.  */
 618                             env->icount_extra += insns_left;
 619                             if (env->icount_extra > 0xffff) {
 620                                 insns_left = 0xffff;
 621                             } else {
 622                                 insns_left = env->icount_extra;
 623                             }
 624                             env->icount_extra -= insns_left;
 625                             env->icount_decr.u16.low = insns_left;
 626                         } else {
 627                             if (insns_left > 0) {
 628                                 /* Execute remaining instructions.  */
 629                                 cpu_exec_nocache(env, insns_left, tb);
 630                             }
 631                             env->exception_index = EXCP_INTERRUPT;
 632                             next_tb = 0;
 633                             cpu_loop_exit(env);
 634                         }
 635                     }
 636                 }
 637                 cpu->current_tb = NULL;
 638                 /* reset soft MMU for next block (it can currently
 639                    only be set by a memory fault) */
 640             } /* for(;;) */
 641         } else {
 642             /* Reload env after longjmp - the compiler may have smashed all
 643              * local variables as longjmp is marked 'noreturn'. */
 644             env = cpu_single_env;
 645         }
 646     } /* for(;;) */
 647
 648
 649 #if defined(TARGET_I386)
 650     /* restore flags in standard format */
 651     env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
 652         | (DF & DF_MASK);
 653 #elif defined(TARGET_ARM)
 654     /* XXX: Save/restore host fpu exception state?.  */
 655 #elif defined(TARGET_UNICORE32)
 656 #elif defined(TARGET_SPARC)
 657 #elif defined(TARGET_PPC)
 658 #elif defined(TARGET_LM32)
 659 #elif defined(TARGET_M68K)
 660     cpu_m68k_flush_flags(env, env->cc_op);
 661     env->cc_op = CC_OP_FLAGS;
 662     env->sr = (env->sr & 0xffe0)
 663               | env->cc_dest | (env->cc_x << 4);
 664 #elif defined(TARGET_MICROBLAZE)
 665 #elif defined(TARGET_MIPS)
 666 #elif defined(TARGET_OPENRISC)
 667 #elif defined(TARGET_SH4)
 668 #elif defined(TARGET_ALPHA)
 669 #elif defined(TARGET_CRIS)
 670 #elif defined(TARGET_S390X)
 671 #elif defined(TARGET_XTENSA)
 672     /* XXXXX */
 673 #else
 674 #error unsupported target CPU
 675 #endif
 676
 677     /* fail safe : never use cpu_single_env outside cpu_exec() */
 678     cpu_single_env = NULL;
 679     return ret;
 680 }