cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #ifdef TARGET_I386
  22 #include "exec-i386.h"
  23 #endif
  24 #ifdef TARGET_ARM
  25 #include "exec-arm.h"
  26 #endif
  27
  28 #include "disas.h"
  29
  30 //#define DEBUG_EXEC
  31 //#define DEBUG_SIGNAL
  32
  33 #if defined(TARGET_ARM)
  34 /* XXX: unify with i386 target */
  35 void cpu_loop_exit(void)
  36 {
  37     longjmp(env->jmp_env, 1);
  38 }
  39 #endif
  40
  41 /* main execution loop */
  42
  43 int cpu_exec(CPUState *env1)
  44 {
  45     int saved_T0, saved_T1, saved_T2;
  46     CPUState *saved_env;
  47 #ifdef reg_EAX
  48     int saved_EAX;
  49 #endif
  50 #ifdef reg_ECX
  51     int saved_ECX;
  52 #endif
  53 #ifdef reg_EDX
  54     int saved_EDX;
  55 #endif
  56 #ifdef reg_EBX
  57     int saved_EBX;
  58 #endif
  59 #ifdef reg_ESP
  60     int saved_ESP;
  61 #endif
  62 #ifdef reg_EBP
  63     int saved_EBP;
  64 #endif
  65 #ifdef reg_ESI
  66     int saved_ESI;
  67 #endif
  68 #ifdef reg_EDI
  69     int saved_EDI;
  70 #endif
  71 #ifdef __sparc__
  72     int saved_i7, tmp_T0;
  73 #endif
  74     int code_gen_size, ret;
  75     void (*gen_func)(void);
  76     TranslationBlock *tb, **ptb;
  77     uint8_t *tc_ptr, *cs_base, *pc;
  78     unsigned int flags;
  79
  80     /* first we save global registers */
  81     saved_T0 = T0;
  82     saved_T1 = T1;
  83     saved_T2 = T2;
  84     saved_env = env;
  85     env = env1;
  86 #ifdef __sparc__
  87     /* we also save i7 because longjmp may not restore it */
  88     asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
  89 #endif
  90
  91 #if defined(TARGET_I386)
  92 #ifdef reg_EAX
  93     saved_EAX = EAX;
  94     EAX = env->regs[R_EAX];
  95 #endif
  96 #ifdef reg_ECX
  97     saved_ECX = ECX;
  98     ECX = env->regs[R_ECX];
  99 #endif
 100 #ifdef reg_EDX
 101     saved_EDX = EDX;
 102     EDX = env->regs[R_EDX];
 103 #endif
 104 #ifdef reg_EBX
 105     saved_EBX = EBX;
 106     EBX = env->regs[R_EBX];
 107 #endif
 108 #ifdef reg_ESP
 109     saved_ESP = ESP;
 110     ESP = env->regs[R_ESP];
 111 #endif
 112 #ifdef reg_EBP
 113     saved_EBP = EBP;
 114     EBP = env->regs[R_EBP];
 115 #endif
 116 #ifdef reg_ESI
 117     saved_ESI = ESI;
 118     ESI = env->regs[R_ESI];
 119 #endif
 120 #ifdef reg_EDI
 121     saved_EDI = EDI;
 122     EDI = env->regs[R_EDI];
 123 #endif
 124
 125     /* put eflags in CPU temporary format */
 126     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 127     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 128     CC_OP = CC_OP_EFLAGS;
 129     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 130 #elif defined(TARGET_ARM)
 131     {
 132         unsigned int psr;
 133         psr = env->cpsr;
 134         env->CF = (psr >> 29) & 1;
 135         env->NZF = (psr & 0xc0000000) ^ 0x40000000;
 136         env->VF = (psr << 3) & 0x80000000;
 137         env->cpsr = psr & ~0xf0000000;
 138     }
 139 #else
 140 #error unsupported target CPU
 141 #endif
 142     env->interrupt_request = 0;
 143
 144     /* prepare setjmp context for exception handling */
 145     if (setjmp(env->jmp_env) == 0) {
 146         T0 = 0; /* force lookup of first TB */
 147         for(;;) {
 148 #ifdef __sparc__
 149           /* g1 can be modified by some libc? functions */
 150             tmp_T0 = T0;
 151 #endif
 152             if (env->interrupt_request) {
 153                 env->exception_index = EXCP_INTERRUPT;
 154                 cpu_loop_exit();
 155             }
 156 #ifdef DEBUG_EXEC
 157             if (loglevel) {
 158 #if defined(TARGET_I386)
 159                 /* restore flags in standard format */
 160                 env->regs[R_EAX] = EAX;
 161                 env->regs[R_EBX] = EBX;
 162                 env->regs[R_ECX] = ECX;
 163                 env->regs[R_EDX] = EDX;
 164                 env->regs[R_ESI] = ESI;
 165                 env->regs[R_EDI] = EDI;
 166                 env->regs[R_EBP] = EBP;
 167                 env->regs[R_ESP] = ESP;
 168                 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 169                 cpu_x86_dump_state(env, logfile, 0);
 170                 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 171 #elif defined(TARGET_ARM)
 172                 cpu_arm_dump_state(env, logfile, 0);
 173 #else
 174 #error unsupported target CPU
 175 #endif
 176             }
 177 #endif
 178             /* we compute the CPU state. We assume it will not
 179                change during the whole generated block. */
 180 #if defined(TARGET_I386)
 181             flags = env->segs[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
 182             flags |= env->segs[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
 183             flags |= (((unsigned long)env->segs[R_DS].base |
 184                        (unsigned long)env->segs[R_ES].base |
 185                        (unsigned long)env->segs[R_SS].base) != 0) <<
 186                 GEN_FLAG_ADDSEG_SHIFT;
 187             if (!(env->eflags & VM_MASK)) {
 188                 flags |= (env->segs[R_CS].selector & 3) << GEN_FLAG_CPL_SHIFT;
 189             } else {
 190                 /* NOTE: a dummy CPL is kept */
 191                 flags |= (1 << GEN_FLAG_VM_SHIFT);
 192                 flags |= (3 << GEN_FLAG_CPL_SHIFT);
 193             }
 194             flags |= (env->eflags & (IOPL_MASK | TF_MASK));
 195             cs_base = env->segs[R_CS].base;
 196             pc = cs_base + env->eip;
 197 #elif defined(TARGET_ARM)
 198             flags = 0;
 199             cs_base = 0;
 200             pc = (uint8_t *)env->regs[15];
 201 #else
 202 #error unsupported CPU
 203 #endif
 204             tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
 205                          flags);
 206             if (!tb) {
 207                 spin_lock(&tb_lock);
 208                 /* if no translated code available, then translate it now */
 209                 tb = tb_alloc((unsigned long)pc);
 210                 if (!tb) {
 211                     /* flush must be done */
 212                     tb_flush();
 213                     /* cannot fail at this point */
 214                     tb = tb_alloc((unsigned long)pc);
 215                     /* don't forget to invalidate previous TB info */
 216                     ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
 217                     T0 = 0;
 218                 }
 219                 tc_ptr = code_gen_ptr;
 220                 tb->tc_ptr = tc_ptr;
 221                 tb->cs_base = (unsigned long)cs_base;
 222                 tb->flags = flags;
 223                 ret = cpu_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
 224 #if defined(TARGET_I386)
 225                 /* XXX: suppress that, this is incorrect */
 226                 /* if invalid instruction, signal it */
 227                 if (ret != 0) {
 228                     /* NOTE: the tb is allocated but not linked, so we
 229                        can leave it */
 230                     spin_unlock(&tb_lock);
 231                     raise_exception(EXCP06_ILLOP);
 232                 }
 233 #endif
 234                 *ptb = tb;
 235                 tb->hash_next = NULL;
 236                 tb_link(tb);
 237                 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
 238                 spin_unlock(&tb_lock);
 239             }
 240 #ifdef DEBUG_EXEC
 241             if (loglevel) {
 242                 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
 243                         (long)tb->tc_ptr, (long)tb->pc,
 244                         lookup_symbol((void *)tb->pc));
 245             }
 246 #endif
 247 #ifdef __sparc__
 248             T0 = tmp_T0;
 249 #endif
 250             /* see if we can patch the calling TB. XXX: remove TF test */
 251             if (T0 != 0
 252 #if defined(TARGET_I386)
 253                 && !(env->eflags & TF_MASK)
 254 #endif
 255                 ) {
 256                 spin_lock(&tb_lock);
 257                 tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
 258                 spin_unlock(&tb_lock);
 259             }
 260             tc_ptr = tb->tc_ptr;
 261
 262             /* execute the generated code */
 263             gen_func = (void *)tc_ptr;
 264 #if defined(__sparc__)
 265             __asm__ __volatile__("call  %0\n\t"
 266                                  "mov   %%o7,%%i0"
 267                                  : /* no outputs */
 268                                  : "r" (gen_func)
 269                                  : "i0", "i1", "i2", "i3", "i4", "i5");
 270 #elif defined(__arm__)
 271             asm volatile ("mov pc, %0\n\t"
 272                           ".global exec_loop\n\t"
 273                           "exec_loop:\n\t"
 274                           : /* no outputs */
 275                           : "r" (gen_func)
 276                           : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
 277 #else
 278             gen_func();
 279 #endif
 280         }
 281     }
 282     ret = env->exception_index;
 283
 284 #if defined(TARGET_I386)
 285     /* restore flags in standard format */
 286     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 287
 288     /* restore global registers */
 289 #ifdef reg_EAX
 290     EAX = saved_EAX;
 291 #endif
 292 #ifdef reg_ECX
 293     ECX = saved_ECX;
 294 #endif
 295 #ifdef reg_EDX
 296     EDX = saved_EDX;
 297 #endif
 298 #ifdef reg_EBX
 299     EBX = saved_EBX;
 300 #endif
 301 #ifdef reg_ESP
 302     ESP = saved_ESP;
 303 #endif
 304 #ifdef reg_EBP
 305     EBP = saved_EBP;
 306 #endif
 307 #ifdef reg_ESI
 308     ESI = saved_ESI;
 309 #endif
 310 #ifdef reg_EDI
 311     EDI = saved_EDI;
 312 #endif
 313 #elif defined(TARGET_ARM)
 314     {
 315         int ZF;
 316         ZF = (env->NZF == 0);
 317         env->cpsr = env->cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
 318             (env->CF << 29) | ((env->VF & 0x80000000) >> 3);
 319     }
 320 #else
 321 #error unsupported target CPU
 322 #endif
 323 #ifdef __sparc__
 324     asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
 325 #endif
 326     T0 = saved_T0;
 327     T1 = saved_T1;
 328     T2 = saved_T2;
 329     env = saved_env;
 330     return ret;
 331 }
 332
 333 void cpu_interrupt(CPUState *s)
 334 {
 335     s->interrupt_request = 1;
 336 }
 337
 338
 339 #if defined(TARGET_I386)
 340
 341 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
 342 {
 343     CPUX86State *saved_env;
 344
 345     saved_env = env;
 346     env = s;
 347     if (env->eflags & VM_MASK) {
 348         SegmentCache *sc;
 349         selector &= 0xffff;
 350         sc = &env->segs[seg_reg];
 351         /* NOTE: in VM86 mode, limit and seg_32bit are never reloaded,
 352            so we must load them here */
 353         sc->base = (void *)(selector << 4);
 354         sc->limit = 0xffff;
 355         sc->seg_32bit = 0;
 356         sc->selector = selector;
 357     } else {
 358         load_seg(seg_reg, selector, 0);
 359     }
 360     env = saved_env;
 361 }
 362
 363 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
 364 {
 365     CPUX86State *saved_env;
 366
 367     saved_env = env;
 368     env = s;
 369
 370     helper_fsave(ptr, data32);
 371
 372     env = saved_env;
 373 }
 374
 375 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
 376 {
 377     CPUX86State *saved_env;
 378
 379     saved_env = env;
 380     env = s;
 381
 382     helper_frstor(ptr, data32);
 383
 384     env = saved_env;
 385 }
 386
 387 #endif /* TARGET_I386 */
 388
 389 #undef EAX
 390 #undef ECX
 391 #undef EDX
 392 #undef EBX
 393 #undef ESP
 394 #undef EBP
 395 #undef ESI
 396 #undef EDI
 397 #undef EIP
 398 #include <signal.h>
 399 #include <sys/ucontext.h>
 400
 401 /* 'pc' is the host PC at which the exception was raised. 'address' is
 402    the effective address of the memory exception. 'is_write' is 1 if a
 403    write caused the exception and otherwise 0'. 'old_set' is the
 404    signal set which should be restored */
 405 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 406                                     int is_write, sigset_t *old_set)
 407 {
 408     TranslationBlock *tb;
 409     int ret;
 410     uint32_t found_pc;
 411
 412 #if defined(DEBUG_SIGNAL)
 413     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
 414            pc, address, is_write, *(unsigned long *)old_set);
 415 #endif
 416     /* XXX: locking issue */
 417     if (is_write && page_unprotect(address)) {
 418         return 1;
 419     }
 420     tb = tb_find_pc(pc);
 421     if (tb) {
 422         /* the PC is inside the translated code. It means that we have
 423            a virtual CPU fault */
 424         ret = cpu_search_pc(tb, &found_pc, pc);
 425         if (ret < 0)
 426             return 0;
 427 #if defined(TARGET_I386)
 428         env->eip = found_pc - tb->cs_base;
 429         env->cr[2] = address;
 430         /* we restore the process signal mask as the sigreturn should
 431            do it (XXX: use sigsetjmp) */
 432         sigprocmask(SIG_SETMASK, old_set, NULL);
 433         raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1));
 434 #elif defined(TARGET_ARM)
 435         env->regs[15] = found_pc;
 436         /* XXX: do more */
 437 #else
 438 #error unsupported target CPU
 439 #endif
 440         /* never comes here */
 441         return 1;
 442     } else {
 443         return 0;
 444     }
 445 }
 446
 447 #if defined(__i386__)
 448
 449 int cpu_signal_handler(int host_signum, struct siginfo *info,
 450                        void *puc)
 451 {
 452     struct ucontext *uc = puc;
 453     unsigned long pc;
 454
 455 #ifndef REG_EIP
 456 /* for glibc 2.1 */
 457 #define REG_EIP    EIP
 458 #define REG_ERR    ERR
 459 #define REG_TRAPNO TRAPNO
 460 #endif
 461     pc = uc->uc_mcontext.gregs[REG_EIP];
 462     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 463                              uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
 464                              (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
 465                              &uc->uc_sigmask);
 466 }
 467
 468 #elif defined(__powerpc)
 469
 470 int cpu_signal_handler(int host_signum, struct siginfo *info,
 471                        void *puc)
 472 {
 473     struct ucontext *uc = puc;
 474     struct pt_regs *regs = uc->uc_mcontext.regs;
 475     unsigned long pc;
 476     int is_write;
 477
 478     pc = regs->nip;
 479     is_write = 0;
 480 #if 0
 481     /* ppc 4xx case */
 482     if (regs->dsisr & 0x00800000)
 483         is_write = 1;
 484 #else
 485     if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
 486         is_write = 1;
 487 #endif
 488     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 489                              is_write, &uc->uc_sigmask);
 490 }
 491
 492 #elif defined(__alpha__)
 493
 494 int cpu_signal_handler(int host_signum, struct siginfo *info,
 495                            void *puc)
 496 {
 497     struct ucontext *uc = puc;
 498     uint32_t *pc = uc->uc_mcontext.sc_pc;
 499     uint32_t insn = *pc;
 500     int is_write = 0;
 501
 502     /* XXX: need kernel patch to get write flag faster */
 503     switch (insn >> 26) {
 504     case 0x0d: // stw
 505     case 0x0e: // stb
 506     case 0x0f: // stq_u
 507     case 0x24: // stf
 508     case 0x25: // stg
 509     case 0x26: // sts
 510     case 0x27: // stt
 511     case 0x2c: // stl
 512     case 0x2d: // stq
 513     case 0x2e: // stl_c
 514     case 0x2f: // stq_c
 515         is_write = 1;
 516     }
 517
 518     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 519                              is_write, &uc->uc_sigmask);
 520 }
 521 #elif defined(__sparc__)
 522
 523 int cpu_signal_handler(int host_signum, struct siginfo *info,
 524                        void *puc)
 525 {
 526     uint32_t *regs = (uint32_t *)(info + 1);
 527     void *sigmask = (regs + 20);
 528     unsigned long pc;
 529     int is_write;
 530     uint32_t insn;
 531
 532     /* XXX: is there a standard glibc define ? */
 533     pc = regs[1];
 534     /* XXX: need kernel patch to get write flag faster */
 535     is_write = 0;
 536     insn = *(uint32_t *)pc;
 537     if ((insn >> 30) == 3) {
 538       switch((insn >> 19) & 0x3f) {
 539       case 0x05: // stb
 540       case 0x06: // sth
 541       case 0x04: // st
 542       case 0x07: // std
 543       case 0x24: // stf
 544       case 0x27: // stdf
 545       case 0x25: // stfsr
 546         is_write = 1;
 547         break;
 548       }
 549     }
 550     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 551                              is_write, sigmask);
 552 }
 553
 554 #elif defined(__arm__)
 555
 556 int cpu_signal_handler(int host_signum, struct siginfo *info,
 557                        void *puc)
 558 {
 559     struct ucontext *uc = puc;
 560     unsigned long pc;
 561     int is_write;
 562
 563     pc = uc->uc_mcontext.gregs[R15];
 564     /* XXX: compute is_write */
 565     is_write = 0;
 566     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 567                              is_write,
 568                              &uc->uc_sigmask);
 569 }
 570
 571 #else
 572
 573 #error CPU specific signal handler needed
 574
 575 #endif