cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #include "exec.h"
  22 #include "disas.h"
  23
  24 int tb_invalidated_flag;
  25
  26 //#define DEBUG_EXEC
  27 //#define DEBUG_SIGNAL
  28
  29 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
  30 /* XXX: unify with i386 target */
  31 void cpu_loop_exit(void)
  32 {
  33     longjmp(env->jmp_env, 1);
  34 }
  35 #endif
  36
  37 /* main execution loop */
  38
  39 int cpu_exec(CPUState *env1)
  40 {
  41     int saved_T0, saved_T1, saved_T2;
  42     CPUState *saved_env;
  43 #ifdef reg_EAX
  44     int saved_EAX;
  45 #endif
  46 #ifdef reg_ECX
  47     int saved_ECX;
  48 #endif
  49 #ifdef reg_EDX
  50     int saved_EDX;
  51 #endif
  52 #ifdef reg_EBX
  53     int saved_EBX;
  54 #endif
  55 #ifdef reg_ESP
  56     int saved_ESP;
  57 #endif
  58 #ifdef reg_EBP
  59     int saved_EBP;
  60 #endif
  61 #ifdef reg_ESI
  62     int saved_ESI;
  63 #endif
  64 #ifdef reg_EDI
  65     int saved_EDI;
  66 #endif
  67 #ifdef __sparc__
  68     int saved_i7, tmp_T0;
  69 #endif
  70     int code_gen_size, ret, interrupt_request;
  71     void (*gen_func)(void);
  72     TranslationBlock *tb, **ptb;
  73     uint8_t *tc_ptr, *cs_base, *pc;
  74     unsigned int flags;
  75
  76     /* first we save global registers */
  77     saved_T0 = T0;
  78     saved_T1 = T1;
  79     saved_T2 = T2;
  80     saved_env = env;
  81     env = env1;
  82 #ifdef __sparc__
  83     /* we also save i7 because longjmp may not restore it */
  84     asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
  85 #endif
  86
  87 #if defined(TARGET_I386)
  88 #ifdef reg_EAX
  89     saved_EAX = EAX;
  90     EAX = env->regs[R_EAX];
  91 #endif
  92 #ifdef reg_ECX
  93     saved_ECX = ECX;
  94     ECX = env->regs[R_ECX];
  95 #endif
  96 #ifdef reg_EDX
  97     saved_EDX = EDX;
  98     EDX = env->regs[R_EDX];
  99 #endif
 100 #ifdef reg_EBX
 101     saved_EBX = EBX;
 102     EBX = env->regs[R_EBX];
 103 #endif
 104 #ifdef reg_ESP
 105     saved_ESP = ESP;
 106     ESP = env->regs[R_ESP];
 107 #endif
 108 #ifdef reg_EBP
 109     saved_EBP = EBP;
 110     EBP = env->regs[R_EBP];
 111 #endif
 112 #ifdef reg_ESI
 113     saved_ESI = ESI;
 114     ESI = env->regs[R_ESI];
 115 #endif
 116 #ifdef reg_EDI
 117     saved_EDI = EDI;
 118     EDI = env->regs[R_EDI];
 119 #endif
 120
 121     /* put eflags in CPU temporary format */
 122     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 123     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 124     CC_OP = CC_OP_EFLAGS;
 125     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 126 #elif defined(TARGET_ARM)
 127     {
 128         unsigned int psr;
 129         psr = env->cpsr;
 130         env->CF = (psr >> 29) & 1;
 131         env->NZF = (psr & 0xc0000000) ^ 0x40000000;
 132         env->VF = (psr << 3) & 0x80000000;
 133         env->cpsr = psr & ~0xf0000000;
 134     }
 135 #elif defined(TARGET_SPARC)
 136 #elif defined(TARGET_PPC)
 137 #else
 138 #error unsupported target CPU
 139 #endif
 140     env->exception_index = -1;
 141
 142     /* prepare setjmp context for exception handling */
 143     for(;;) {
 144         if (setjmp(env->jmp_env) == 0) {
 145             /* if an exception is pending, we execute it here */
 146             if (env->exception_index >= 0) {
 147                 if (env->exception_index >= EXCP_INTERRUPT) {
 148                     /* exit request from the cpu execution loop */
 149                     ret = env->exception_index;
 150                     break;
 151                 } else if (env->user_mode_only) {
 152                     /* if user mode only, we simulate a fake exception
 153                        which will be hanlded outside the cpu execution
 154                        loop */
 155 #if defined(TARGET_I386)
 156                     do_interrupt_user(env->exception_index,
 157                                       env->exception_is_int,
 158                                       env->error_code,
 159                                       env->exception_next_eip);
 160 #endif
 161                     ret = env->exception_index;
 162                     break;
 163                 } else {
 164 #if defined(TARGET_I386)
 165                     /* simulate a real cpu exception. On i386, it can
 166                        trigger new exceptions, but we do not handle
 167                        double or triple faults yet. */
 168                     do_interrupt(env->exception_index,
 169                                  env->exception_is_int,
 170                                  env->error_code,
 171                                  env->exception_next_eip, 0);
 172 #elif defined(TARGET_PPC)
 173                     do_interrupt(env);
 174 #endif
 175                 }
 176                 env->exception_index = -1;
 177             }
 178             T0 = 0; /* force lookup of first TB */
 179             for(;;) {
 180 #ifdef __sparc__
 181                 /* g1 can be modified by some libc? functions */
 182                 tmp_T0 = T0;
 183 #endif
 184                 interrupt_request = env->interrupt_request;
 185                 if (__builtin_expect(interrupt_request, 0)) {
 186 #if defined(TARGET_I386)
 187                     /* if hardware interrupt pending, we execute it */
 188                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 189                         (env->eflags & IF_MASK) &&
 190                         !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
 191                         int intno;
 192                         intno = cpu_x86_get_pic_interrupt(env);
 193                         if (loglevel) {
 194                             fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
 195                         }
 196                         do_interrupt(intno, 0, 0, 0, 1);
 197                         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 198                         /* ensure that no TB jump will be modified as
 199                            the program flow was changed */
 200 #ifdef __sparc__
 201                         tmp_T0 = 0;
 202 #else
 203                         T0 = 0;
 204 #endif
 205                     }
 206 #elif defined(TARGET_PPC)
 207                     if ((interrupt_request & CPU_INTERRUPT_HARD)) {
 208                         do_queue_exception(EXCP_EXTERNAL);
 209                         if (check_exception_state(env))
 210                             do_interrupt(env);
 211                         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 212                     }
 213 #endif
 214                     if (interrupt_request & CPU_INTERRUPT_EXIT) {
 215                         env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
 216                         env->exception_index = EXCP_INTERRUPT;
 217                         cpu_loop_exit();
 218                     }
 219                 }
 220 #ifdef DEBUG_EXEC
 221                 if (loglevel) {
 222 #if defined(TARGET_I386)
 223                     /* restore flags in standard format */
 224                     env->regs[R_EAX] = EAX;
 225                     env->regs[R_EBX] = EBX;
 226                     env->regs[R_ECX] = ECX;
 227                     env->regs[R_EDX] = EDX;
 228                     env->regs[R_ESI] = ESI;
 229                     env->regs[R_EDI] = EDI;
 230                     env->regs[R_EBP] = EBP;
 231                     env->regs[R_ESP] = ESP;
 232                     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 233                     cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
 234                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 235 #elif defined(TARGET_ARM)
 236                     env->cpsr = compute_cpsr();
 237                     cpu_arm_dump_state(env, logfile, 0);
 238                     env->cpsr &= ~0xf0000000;
 239 #elif defined(TARGET_SPARC)
 240                     cpu_sparc_dump_state (env, logfile, 0);
 241 #elif defined(TARGET_PPC)
 242                     cpu_ppc_dump_state(env, logfile, 0);
 243 #else
 244 #error unsupported target CPU
 245 #endif
 246                 }
 247 #endif
 248                 /* we record a subset of the CPU state. It will
 249                    always be the same before a given translated block
 250                    is executed. */
 251 #if defined(TARGET_I386)
 252                 flags = env->hflags;
 253                 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
 254                 cs_base = env->segs[R_CS].base;
 255                 pc = cs_base + env->eip;
 256 #elif defined(TARGET_ARM)
 257                 flags = 0;
 258                 cs_base = 0;
 259                 pc = (uint8_t *)env->regs[15];
 260 #elif defined(TARGET_SPARC)
 261                 flags = 0;
 262                 cs_base = (uint8_t *)env->npc;
 263                 pc = (uint8_t *) env->pc;
 264 #elif defined(TARGET_PPC)
 265                 flags = 0;
 266                 cs_base = 0;
 267                 pc = (uint8_t *)env->nip;
 268 #else
 269 #error unsupported CPU
 270 #endif
 271                 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
 272                              flags);
 273                 if (!tb) {
 274                     TranslationBlock **ptb1;
 275                     unsigned int h;
 276                     target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
 277
 278
 279                     spin_lock(&tb_lock);
 280
 281                     tb_invalidated_flag = 0;
 282
 283                     /* find translated block using physical mappings */
 284                     phys_pc = get_phys_addr_code(env, (unsigned long)pc);
 285                     phys_page1 = phys_pc & TARGET_PAGE_MASK;
 286                     phys_page2 = -1;
 287                     h = tb_phys_hash_func(phys_pc);
 288                     ptb1 = &tb_phys_hash[h];
 289                     for(;;) {
 290                         tb = *ptb1;
 291                         if (!tb)
 292                             goto not_found;
 293                         if (tb->pc == (unsigned long)pc &&
 294                             tb->page_addr[0] == phys_page1 &&
 295                             tb->cs_base == (unsigned long)cs_base &&
 296                             tb->flags == flags) {
 297                             /* check next page if needed */
 298                             virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK;
 299                             if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) {
 300                                 phys_page2 = get_phys_addr_code(env, virt_page2);
 301                                 if (tb->page_addr[1] == phys_page2)
 302                                     goto found;
 303                             } else {
 304                                 goto found;
 305                             }
 306                         }
 307                         ptb1 = &tb->phys_hash_next;
 308                     }
 309                 not_found:
 310                     /* if no translated code available, then translate it now */
 311                     tb = tb_alloc((unsigned long)pc);
 312                     if (!tb) {
 313                         /* flush must be done */
 314                         tb_flush(env);
 315                         /* cannot fail at this point */
 316                         tb = tb_alloc((unsigned long)pc);
 317                         /* don't forget to invalidate previous TB info */
 318                         ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
 319                         T0 = 0;
 320                     }
 321                     tc_ptr = code_gen_ptr;
 322                     tb->tc_ptr = tc_ptr;
 323                     tb->cs_base = (unsigned long)cs_base;
 324                     tb->flags = flags;
 325                     cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
 326                     code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
 327
 328                     /* check next page if needed */
 329                     virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK;
 330                     phys_page2 = -1;
 331                     if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) {
 332                         phys_page2 = get_phys_addr_code(env, virt_page2);
 333                     }
 334                     tb_link_phys(tb, phys_pc, phys_page2);
 335
 336                 found:
 337                     if (tb_invalidated_flag) {
 338                         /* as some TB could have been invalidated because
 339                            of memory exceptions while generating the code, we
 340                            must recompute the hash index here */
 341                         ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
 342                         while (*ptb != NULL)
 343                             ptb = &(*ptb)->hash_next;
 344                         T0 = 0;
 345                     }
 346                     /* we add the TB in the virtual pc hash table */
 347                     *ptb = tb;
 348                     tb->hash_next = NULL;
 349                     tb_link(tb);
 350                     spin_unlock(&tb_lock);
 351                 }
 352 #ifdef DEBUG_EXEC
 353                 if (loglevel) {
 354                     fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
 355                             (long)tb->tc_ptr, (long)tb->pc,
 356                             lookup_symbol((void *)tb->pc));
 357                 }
 358 #endif
 359 #ifdef __sparc__
 360                 T0 = tmp_T0;
 361 #endif
 362                 /* see if we can patch the calling TB. */
 363                 if (T0 != 0) {
 364                     spin_lock(&tb_lock);
 365                     tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
 366                     spin_unlock(&tb_lock);
 367                 }
 368                 tc_ptr = tb->tc_ptr;
 369                 env->current_tb = tb;
 370                 /* execute the generated code */
 371                 gen_func = (void *)tc_ptr;
 372 #if defined(__sparc__)
 373                 __asm__ __volatile__("call      %0\n\t"
 374                                      "mov       %%o7,%%i0"
 375                                      : /* no outputs */
 376                                      : "r" (gen_func)
 377                                      : "i0", "i1", "i2", "i3", "i4", "i5");
 378 #elif defined(__arm__)
 379                 asm volatile ("mov pc, %0\n\t"
 380                               ".global exec_loop\n\t"
 381                               "exec_loop:\n\t"
 382                               : /* no outputs */
 383                               : "r" (gen_func)
 384                               : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
 385 #else
 386                 gen_func();
 387 #endif
 388                 env->current_tb = NULL;
 389                 /* reset soft MMU for next block (it can currently
 390                    only be set by a memory fault) */
 391 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
 392                 if (env->hflags & HF_SOFTMMU_MASK) {
 393                     env->hflags &= ~HF_SOFTMMU_MASK;
 394                     /* do not allow linking to another block */
 395                     T0 = 0;
 396                 }
 397 #endif
 398             }
 399         } else {
 400         }
 401     } /* for(;;) */
 402
 403
 404 #if defined(TARGET_I386)
 405     /* restore flags in standard format */
 406     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 407
 408     /* restore global registers */
 409 #ifdef reg_EAX
 410     EAX = saved_EAX;
 411 #endif
 412 #ifdef reg_ECX
 413     ECX = saved_ECX;
 414 #endif
 415 #ifdef reg_EDX
 416     EDX = saved_EDX;
 417 #endif
 418 #ifdef reg_EBX
 419     EBX = saved_EBX;
 420 #endif
 421 #ifdef reg_ESP
 422     ESP = saved_ESP;
 423 #endif
 424 #ifdef reg_EBP
 425     EBP = saved_EBP;
 426 #endif
 427 #ifdef reg_ESI
 428     ESI = saved_ESI;
 429 #endif
 430 #ifdef reg_EDI
 431     EDI = saved_EDI;
 432 #endif
 433 #elif defined(TARGET_ARM)
 434     env->cpsr = compute_cpsr();
 435 #elif defined(TARGET_SPARC)
 436 #elif defined(TARGET_PPC)
 437 #else
 438 #error unsupported target CPU
 439 #endif
 440 #ifdef __sparc__
 441     asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
 442 #endif
 443     T0 = saved_T0;
 444     T1 = saved_T1;
 445     T2 = saved_T2;
 446     env = saved_env;
 447     return ret;
 448 }
 449
 450 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
 451
 452 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
 453 {
 454     CPUX86State *saved_env;
 455
 456     saved_env = env;
 457     env = s;
 458     if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 459         selector &= 0xffff;
 460         cpu_x86_load_seg_cache(env, seg_reg, selector,
 461                                (uint8_t *)(selector << 4), 0xffff, 0);
 462     } else {
 463         load_seg(seg_reg, selector);
 464     }
 465     env = saved_env;
 466 }
 467
 468 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
 469 {
 470     CPUX86State *saved_env;
 471
 472     saved_env = env;
 473     env = s;
 474
 475     helper_fsave(ptr, data32);
 476
 477     env = saved_env;
 478 }
 479
 480 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
 481 {
 482     CPUX86State *saved_env;
 483
 484     saved_env = env;
 485     env = s;
 486
 487     helper_frstor(ptr, data32);
 488
 489     env = saved_env;
 490 }
 491
 492 #endif /* TARGET_I386 */
 493
 494 #undef EAX
 495 #undef ECX
 496 #undef EDX
 497 #undef EBX
 498 #undef ESP
 499 #undef EBP
 500 #undef ESI
 501 #undef EDI
 502 #undef EIP
 503 #include <signal.h>
 504 #include <sys/ucontext.h>
 505
 506 #if defined(TARGET_I386)
 507
 508 /* 'pc' is the host PC at which the exception was raised. 'address' is
 509    the effective address of the memory exception. 'is_write' is 1 if a
 510    write caused the exception and otherwise 0'. 'old_set' is the
 511    signal set which should be restored */
 512 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 513                                     int is_write, sigset_t *old_set)
 514 {
 515     TranslationBlock *tb;
 516     int ret;
 517
 518     if (cpu_single_env)
 519         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 520 #if defined(DEBUG_SIGNAL)
 521     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 522            pc, address, is_write, *(unsigned long *)old_set);
 523 #endif
 524     /* XXX: locking issue */
 525     if (is_write && page_unprotect(address)) {
 526         return 1;
 527     }
 528     /* see if it is an MMU fault */
 529     ret = cpu_x86_handle_mmu_fault(env, address, is_write,
 530                                    ((env->hflags & HF_CPL_MASK) == 3), 0);
 531     if (ret < 0)
 532         return 0; /* not an MMU fault */
 533     if (ret == 0)
 534         return 1; /* the MMU fault was handled without causing real CPU fault */
 535     /* now we have a real cpu fault */
 536     tb = tb_find_pc(pc);
 537     if (tb) {
 538         /* the PC is inside the translated code. It means that we have
 539            a virtual CPU fault */
 540         cpu_restore_state(tb, env, pc);
 541     }
 542     if (ret == 1) {
 543 #if 0
 544         printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
 545                env->eip, env->cr[2], env->error_code);
 546 #endif
 547         /* we restore the process signal mask as the sigreturn should
 548            do it (XXX: use sigsetjmp) */
 549         sigprocmask(SIG_SETMASK, old_set, NULL);
 550         raise_exception_err(EXCP0E_PAGE, env->error_code);
 551     } else {
 552         /* activate soft MMU for this block */
 553         env->hflags |= HF_SOFTMMU_MASK;
 554         sigprocmask(SIG_SETMASK, old_set, NULL);
 555         cpu_loop_exit();
 556     }
 557     /* never comes here */
 558     return 1;
 559 }
 560
 561 #elif defined(TARGET_ARM)
 562 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 563                                     int is_write, sigset_t *old_set)
 564 {
 565     /* XXX: do more */
 566     return 0;
 567 }
 568 #elif defined(TARGET_SPARC)
 569 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 570                                     int is_write, sigset_t *old_set)
 571 {
 572     /* XXX: locking issue */
 573     if (is_write && page_unprotect(address)) {
 574         return 1;
 575     }
 576     return 0;
 577 }
 578 #elif defined (TARGET_PPC)
 579 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 580                                     int is_write, sigset_t *old_set)
 581 {
 582     TranslationBlock *tb;
 583     int ret;
 584
 585 #if 1
 586     if (cpu_single_env)
 587         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 588 #endif
 589 #if defined(DEBUG_SIGNAL)
 590     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 591            pc, address, is_write, *(unsigned long *)old_set);
 592 #endif
 593     /* XXX: locking issue */
 594     if (is_write && page_unprotect(address)) {
 595         return 1;
 596     }
 597
 598     /* see if it is an MMU fault */
 599     ret = cpu_ppc_handle_mmu_fault(env, address, is_write | ACCESS_INT, msr_pr, 0);
 600     if (ret < 0)
 601         return 0; /* not an MMU fault */
 602     if (ret == 0)
 603         return 1; /* the MMU fault was handled without causing real CPU fault */
 604
 605     /* now we have a real cpu fault */
 606     tb = tb_find_pc(pc);
 607     if (tb) {
 608         /* the PC is inside the translated code. It means that we have
 609            a virtual CPU fault */
 610         cpu_restore_state(tb, env, pc);
 611     }
 612     if (ret == 1) {
 613 #if 0
 614         printf("PF exception: NIP=0x%08x error=0x%x %p\n",
 615                env->nip, env->error_code, tb);
 616 #endif
 617     /* we restore the process signal mask as the sigreturn should
 618        do it (XXX: use sigsetjmp) */
 619     sigprocmask(SIG_SETMASK, old_set, NULL);
 620         do_queue_exception_err(env->exception_index, env->error_code);
 621     } else {
 622         /* activate soft MMU for this block */
 623         sigprocmask(SIG_SETMASK, old_set, NULL);
 624         cpu_loop_exit();
 625     }
 626     /* never comes here */
 627     return 1;
 628 }
 629 #else
 630 #error unsupported target CPU
 631 #endif
 632
 633 #if defined(__i386__)
 634
 635 int cpu_signal_handler(int host_signum, struct siginfo *info,
 636                        void *puc)
 637 {
 638     struct ucontext *uc = puc;
 639     unsigned long pc;
 640
 641 #ifndef REG_EIP
 642 /* for glibc 2.1 */
 643 #define REG_EIP    EIP
 644 #define REG_ERR    ERR
 645 #define REG_TRAPNO TRAPNO
 646 #endif
 647     pc = uc->uc_mcontext.gregs[REG_EIP];
 648     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 649                              uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
 650                              (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
 651                              &uc->uc_sigmask);
 652 }
 653
 654 #elif defined(__powerpc)
 655
 656 int cpu_signal_handler(int host_signum, struct siginfo *info,
 657                        void *puc)
 658 {
 659     struct ucontext *uc = puc;
 660     struct pt_regs *regs = uc->uc_mcontext.regs;
 661     unsigned long pc;
 662     int is_write;
 663
 664     pc = regs->nip;
 665     is_write = 0;
 666 #if 0
 667     /* ppc 4xx case */
 668     if (regs->dsisr & 0x00800000)
 669         is_write = 1;
 670 #else
 671     if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
 672         is_write = 1;
 673 #endif
 674     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 675                              is_write, &uc->uc_sigmask);
 676 }
 677
 678 #elif defined(__alpha__)
 679
 680 int cpu_signal_handler(int host_signum, struct siginfo *info,
 681                            void *puc)
 682 {
 683     struct ucontext *uc = puc;
 684     uint32_t *pc = uc->uc_mcontext.sc_pc;
 685     uint32_t insn = *pc;
 686     int is_write = 0;
 687
 688     /* XXX: need kernel patch to get write flag faster */
 689     switch (insn >> 26) {
 690     case 0x0d: // stw
 691     case 0x0e: // stb
 692     case 0x0f: // stq_u
 693     case 0x24: // stf
 694     case 0x25: // stg
 695     case 0x26: // sts
 696     case 0x27: // stt
 697     case 0x2c: // stl
 698     case 0x2d: // stq
 699     case 0x2e: // stl_c
 700     case 0x2f: // stq_c
 701         is_write = 1;
 702     }
 703
 704     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 705                              is_write, &uc->uc_sigmask);
 706 }
 707 #elif defined(__sparc__)
 708
 709 int cpu_signal_handler(int host_signum, struct siginfo *info,
 710                        void *puc)
 711 {
 712     uint32_t *regs = (uint32_t *)(info + 1);
 713     void *sigmask = (regs + 20);
 714     unsigned long pc;
 715     int is_write;
 716     uint32_t insn;
 717
 718     /* XXX: is there a standard glibc define ? */
 719     pc = regs[1];
 720     /* XXX: need kernel patch to get write flag faster */
 721     is_write = 0;
 722     insn = *(uint32_t *)pc;
 723     if ((insn >> 30) == 3) {
 724       switch((insn >> 19) & 0x3f) {
 725       case 0x05: // stb
 726       case 0x06: // sth
 727       case 0x04: // st
 728       case 0x07: // std
 729       case 0x24: // stf
 730       case 0x27: // stdf
 731       case 0x25: // stfsr
 732         is_write = 1;
 733         break;
 734       }
 735     }
 736     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 737                              is_write, sigmask);
 738 }
 739
 740 #elif defined(__arm__)
 741
 742 int cpu_signal_handler(int host_signum, struct siginfo *info,
 743                        void *puc)
 744 {
 745     struct ucontext *uc = puc;
 746     unsigned long pc;
 747     int is_write;
 748
 749     pc = uc->uc_mcontext.gregs[R15];
 750     /* XXX: compute is_write */
 751     is_write = 0;
 752     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 753                              is_write,
 754                              &uc->uc_sigmask);
 755 }
 756
 757 #elif defined(__mc68000)
 758
 759 int cpu_signal_handler(int host_signum, struct siginfo *info,
 760                        void *puc)
 761 {
 762     struct ucontext *uc = puc;
 763     unsigned long pc;
 764     int is_write;
 765
 766     pc = uc->uc_mcontext.gregs[16];
 767     /* XXX: compute is_write */
 768     is_write = 0;
 769     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 770                              is_write,
 771                              &uc->uc_sigmask);
 772 }
 773
 774 #else
 775
 776 #error host CPU specific signal handler needed
 777
 778 #endif