cpu.c

   1 /*
   2  * Target-specific parts of the CPU object
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22
  23 #include "exec/target_page.h"
  24 #include "hw/qdev-core.h"
  25 #include "hw/qdev-properties.h"
  26 #include "qemu/error-report.h"
  27 #include "migration/vmstate.h"
  28 #ifdef CONFIG_USER_ONLY
  29 #include "qemu.h"
  30 #else
  31 #include "hw/core/sysemu-cpu-ops.h"
  32 #include "exec/address-spaces.h"
  33 #endif
  34 #include "sysemu/cpus.h"
  35 #include "sysemu/tcg.h"
  36 #include "exec/replay-core.h"
  37 #include "exec/cpu-common.h"
  38 #include "exec/exec-all.h"
  39 #include "exec/tb-flush.h"
  40 #include "exec/translate-all.h"
  41 #include "exec/log.h"
  42 #include "hw/core/accel-cpu.h"
  43 #include "trace/trace-root.h"
  44 #include "qemu/accel.h"
  45
  46 uintptr_t qemu_host_page_size;
  47 intptr_t qemu_host_page_mask;
  48
  49 #ifndef CONFIG_USER_ONLY
  50 static int cpu_common_post_load(void *opaque, int version_id)
  51 {
  52     CPUState *cpu = opaque;
  53
  54     /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
  55        version_id is increased. */
  56     cpu->interrupt_request &= ~0x01;
  57     tlb_flush(cpu);
  58
  59     /* loadvm has just updated the content of RAM, bypassing the
  60      * usual mechanisms that ensure we flush TBs for writes to
  61      * memory we've translated code from. So we must flush all TBs,
  62      * which will now be stale.
  63      */
  64     tb_flush(cpu);
  65
  66     return 0;
  67 }
  68
  69 static int cpu_common_pre_load(void *opaque)
  70 {
  71     CPUState *cpu = opaque;
  72
  73     cpu->exception_index = -1;
  74
  75     return 0;
  76 }
  77
  78 static bool cpu_common_exception_index_needed(void *opaque)
  79 {
  80     CPUState *cpu = opaque;
  81
  82     return tcg_enabled() && cpu->exception_index != -1;
  83 }
  84
  85 static const VMStateDescription vmstate_cpu_common_exception_index = {
  86     .name = "cpu_common/exception_index",
  87     .version_id = 1,
  88     .minimum_version_id = 1,
  89     .needed = cpu_common_exception_index_needed,
  90     .fields = (VMStateField[]) {
  91         VMSTATE_INT32(exception_index, CPUState),
  92         VMSTATE_END_OF_LIST()
  93     }
  94 };
  95
  96 static bool cpu_common_crash_occurred_needed(void *opaque)
  97 {
  98     CPUState *cpu = opaque;
  99
 100     return cpu->crash_occurred;
 101 }
 102
 103 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
 104     .name = "cpu_common/crash_occurred",
 105     .version_id = 1,
 106     .minimum_version_id = 1,
 107     .needed = cpu_common_crash_occurred_needed,
 108     .fields = (VMStateField[]) {
 109         VMSTATE_BOOL(crash_occurred, CPUState),
 110         VMSTATE_END_OF_LIST()
 111     }
 112 };
 113
 114 const VMStateDescription vmstate_cpu_common = {
 115     .name = "cpu_common",
 116     .version_id = 1,
 117     .minimum_version_id = 1,
 118     .pre_load = cpu_common_pre_load,
 119     .post_load = cpu_common_post_load,
 120     .fields = (VMStateField[]) {
 121         VMSTATE_UINT32(halted, CPUState),
 122         VMSTATE_UINT32(interrupt_request, CPUState),
 123         VMSTATE_END_OF_LIST()
 124     },
 125     .subsections = (const VMStateDescription*[]) {
 126         &vmstate_cpu_common_exception_index,
 127         &vmstate_cpu_common_crash_occurred,
 128         NULL
 129     }
 130 };
 131 #endif
 132
 133 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
 134 {
 135     /* cache the cpu class for the hotpath */
 136     cpu->cc = CPU_GET_CLASS(cpu);
 137
 138     if (!accel_cpu_realizefn(cpu, errp)) {
 139         return;
 140     }
 141
 142     /* NB: errp parameter is unused currently */
 143     if (tcg_enabled()) {
 144         tcg_exec_realizefn(cpu, errp);
 145     }
 146
 147     /* Wait until cpu initialization complete before exposing cpu. */
 148     cpu_list_add(cpu);
 149
 150     /* Plugin initialization must wait until cpu_index assigned. */
 151     if (tcg_enabled()) {
 152         qemu_plugin_vcpu_init_hook(cpu);
 153     }
 154
 155 #ifdef CONFIG_USER_ONLY
 156     assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
 157            qdev_get_vmsd(DEVICE(cpu))->unmigratable);
 158 #else
 159     if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
 160         vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
 161     }
 162     if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
 163         vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
 164     }
 165 #endif /* CONFIG_USER_ONLY */
 166 }
 167
 168 void cpu_exec_unrealizefn(CPUState *cpu)
 169 {
 170 #ifndef CONFIG_USER_ONLY
 171     CPUClass *cc = CPU_GET_CLASS(cpu);
 172
 173     if (cc->sysemu_ops->legacy_vmsd != NULL) {
 174         vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
 175     }
 176     if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
 177         vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
 178     }
 179 #endif
 180
 181     /* Call the plugin hook before clearing cpu->cpu_index in cpu_list_remove */
 182     if (tcg_enabled()) {
 183         qemu_plugin_vcpu_exit_hook(cpu);
 184     }
 185
 186     cpu_list_remove(cpu);
 187     /*
 188      * Now that the vCPU has been removed from the RCU list, we can call
 189      * tcg_exec_unrealizefn, which may free fields using call_rcu.
 190      */
 191     if (tcg_enabled()) {
 192         tcg_exec_unrealizefn(cpu);
 193     }
 194 }
 195
 196 /*
 197  * This can't go in hw/core/cpu.c because that file is compiled only
 198  * once for both user-mode and system builds.
 199  */
 200 static Property cpu_common_props[] = {
 201 #ifdef CONFIG_USER_ONLY
 202     /*
 203      * Create a property for the user-only object, so users can
 204      * adjust prctl(PR_SET_UNALIGN) from the command-line.
 205      * Has no effect if the target does not support the feature.
 206      */
 207     DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
 208                      prctl_unalign_sigbus, false),
 209 #else
 210     /*
 211      * Create a memory property for softmmu CPU object, so users can
 212      * wire up its memory.  The default if no link is set up is to use
 213      * the system address space.
 214      */
 215     DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
 216                      MemoryRegion *),
 217 #endif
 218     DEFINE_PROP_END_OF_LIST(),
 219 };
 220
 221 static bool cpu_get_start_powered_off(Object *obj, Error **errp)
 222 {
 223     CPUState *cpu = CPU(obj);
 224     return cpu->start_powered_off;
 225 }
 226
 227 static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
 228 {
 229     CPUState *cpu = CPU(obj);
 230     cpu->start_powered_off = value;
 231 }
 232
 233 void cpu_class_init_props(DeviceClass *dc)
 234 {
 235     ObjectClass *oc = OBJECT_CLASS(dc);
 236
 237     device_class_set_props(dc, cpu_common_props);
 238     /*
 239      * We can't use DEFINE_PROP_BOOL in the Property array for this
 240      * property, because we want this to be settable after realize.
 241      */
 242     object_class_property_add_bool(oc, "start-powered-off",
 243                                    cpu_get_start_powered_off,
 244                                    cpu_set_start_powered_off);
 245 }
 246
 247 void cpu_exec_initfn(CPUState *cpu)
 248 {
 249     cpu->as = NULL;
 250     cpu->num_ases = 0;
 251
 252 #ifndef CONFIG_USER_ONLY
 253     cpu->thread_id = qemu_get_thread_id();
 254     cpu->memory = get_system_memory();
 255     object_ref(OBJECT(cpu->memory));
 256 #endif
 257 }
 258
 259 const char *parse_cpu_option(const char *cpu_option)
 260 {
 261     ObjectClass *oc;
 262     CPUClass *cc;
 263     gchar **model_pieces;
 264     const char *cpu_type;
 265
 266     model_pieces = g_strsplit(cpu_option, ",", 2);
 267     if (!model_pieces[0]) {
 268         error_report("-cpu option cannot be empty");
 269         exit(1);
 270     }
 271
 272     oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
 273     if (oc == NULL) {
 274         error_report("unable to find CPU model '%s'", model_pieces[0]);
 275         g_strfreev(model_pieces);
 276         exit(EXIT_FAILURE);
 277     }
 278
 279     cpu_type = object_class_get_name(oc);
 280     cc = CPU_CLASS(oc);
 281     cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
 282     g_strfreev(model_pieces);
 283     return cpu_type;
 284 }
 285
 286 void list_cpus(const char *optarg)
 287 {
 288     /* XXX: implement xxx_cpu_list for targets that still miss it */
 289 #if defined(cpu_list)
 290     cpu_list();
 291 #endif
 292 }
 293
 294 #if defined(CONFIG_USER_ONLY)
 295 void tb_invalidate_phys_addr(target_ulong addr)
 296 {
 297     mmap_lock();
 298     tb_invalidate_phys_page(addr);
 299     mmap_unlock();
 300 }
 301 #else
 302 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
 303 {
 304     ram_addr_t ram_addr;
 305     MemoryRegion *mr;
 306     hwaddr l = 1;
 307
 308     if (!tcg_enabled()) {
 309         return;
 310     }
 311
 312     RCU_READ_LOCK_GUARD();
 313     mr = address_space_translate(as, addr, &addr, &l, false, attrs);
 314     if (!(memory_region_is_ram(mr)
 315           || memory_region_is_romd(mr))) {
 316         return;
 317     }
 318     ram_addr = memory_region_get_ram_addr(mr) + addr;
 319     tb_invalidate_phys_page(ram_addr);
 320 }
 321 #endif
 322
 323 /* enable or disable single step mode. EXCP_DEBUG is returned by the
 324    CPU loop after each instruction */
 325 void cpu_single_step(CPUState *cpu, int enabled)
 326 {
 327     if (cpu->singlestep_enabled != enabled) {
 328         cpu->singlestep_enabled = enabled;
 329
 330 #if !defined(CONFIG_USER_ONLY)
 331         const AccelOpsClass *ops = cpus_get_accel();
 332         if (ops->update_guest_debug) {
 333             ops->update_guest_debug(cpu);
 334         }
 335 #endif
 336
 337         trace_breakpoint_singlestep(cpu->cpu_index, enabled);
 338     }
 339 }
 340
 341 void cpu_abort(CPUState *cpu, const char *fmt, ...)
 342 {
 343     va_list ap;
 344     va_list ap2;
 345
 346     va_start(ap, fmt);
 347     va_copy(ap2, ap);
 348     fprintf(stderr, "qemu: fatal: ");
 349     vfprintf(stderr, fmt, ap);
 350     fprintf(stderr, "\n");
 351     cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
 352     if (qemu_log_separate()) {
 353         FILE *logfile = qemu_log_trylock();
 354         if (logfile) {
 355             fprintf(logfile, "qemu: fatal: ");
 356             vfprintf(logfile, fmt, ap2);
 357             fprintf(logfile, "\n");
 358             cpu_dump_state(cpu, logfile, CPU_DUMP_FPU | CPU_DUMP_CCOP);
 359             qemu_log_unlock(logfile);
 360         }
 361     }
 362     va_end(ap2);
 363     va_end(ap);
 364     replay_finish();
 365 #if defined(CONFIG_USER_ONLY)
 366     {
 367         struct sigaction act;
 368         sigfillset(&act.sa_mask);
 369         act.sa_handler = SIG_DFL;
 370         act.sa_flags = 0;
 371         sigaction(SIGABRT, &act, NULL);
 372     }
 373 #endif
 374     abort();
 375 }
 376
 377 /* physical memory access (slow version, mainly for debug) */
 378 #if defined(CONFIG_USER_ONLY)
 379 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
 380                         void *ptr, size_t len, bool is_write)
 381 {
 382     int flags;
 383     vaddr l, page;
 384     void * p;
 385     uint8_t *buf = ptr;
 386
 387     while (len > 0) {
 388         page = addr & TARGET_PAGE_MASK;
 389         l = (page + TARGET_PAGE_SIZE) - addr;
 390         if (l > len)
 391             l = len;
 392         flags = page_get_flags(page);
 393         if (!(flags & PAGE_VALID))
 394             return -1;
 395         if (is_write) {
 396             if (!(flags & PAGE_WRITE))
 397                 return -1;
 398             /* XXX: this code should not depend on lock_user */
 399             if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
 400                 return -1;
 401             memcpy(p, buf, l);
 402             unlock_user(p, addr, l);
 403         } else {
 404             if (!(flags & PAGE_READ))
 405                 return -1;
 406             /* XXX: this code should not depend on lock_user */
 407             if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
 408                 return -1;
 409             memcpy(buf, p, l);
 410             unlock_user(p, addr, 0);
 411         }
 412         len -= l;
 413         buf += l;
 414         addr += l;
 415     }
 416     return 0;
 417 }
 418 #endif
 419
 420 bool target_words_bigendian(void)
 421 {
 422 #if TARGET_BIG_ENDIAN
 423     return true;
 424 #else
 425     return false;
 426 #endif
 427 }
 428
 429 void page_size_init(void)
 430 {
 431     /* NOTE: we can always suppose that qemu_host_page_size >=
 432        TARGET_PAGE_SIZE */
 433     if (qemu_host_page_size == 0) {
 434         qemu_host_page_size = qemu_real_host_page_size();
 435     }
 436     if (qemu_host_page_size < TARGET_PAGE_SIZE) {
 437         qemu_host_page_size = TARGET_PAGE_SIZE;
 438     }
 439     qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
 440 }