2 * QEMU RISC-V Disassembler
4 * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com>
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "disas/dis-asm.h"
22 #include "target/riscv/cpu_cfg.h"
23 #include "disas/riscv.h"
26 /* 0 is reserved for rv_op_illegal. */
110 rv_op_amoswap_w
= 84,
117 rv_op_amominu_w
= 91,
118 rv_op_amomaxu_w
= 92,
121 rv_op_amoswap_d
= 95,
126 rv_op_amomin_d
= 100,
127 rv_op_amomax_d
= 101,
128 rv_op_amominu_d
= 102,
129 rv_op_amomaxu_d
= 103,
132 rv_op_amoswap_q
= 106,
133 rv_op_amoadd_q
= 107,
134 rv_op_amoxor_q
= 108,
136 rv_op_amoand_q
= 110,
137 rv_op_amomin_q
= 111,
138 rv_op_amomax_q
= 112,
139 rv_op_amominu_q
= 113,
140 rv_op_amomaxu_q
= 114,
148 rv_op_sfence_vm
= 122,
149 rv_op_sfence_vma
= 123,
161 rv_op_fnmsub_s
= 135,
162 rv_op_fnmadd_s
= 136,
168 rv_op_fsgnjn_s
= 142,
169 rv_op_fsgnjx_s
= 143,
176 rv_op_fcvt_w_s
= 150,
177 rv_op_fcvt_wu_s
= 151,
178 rv_op_fcvt_s_w
= 152,
179 rv_op_fcvt_s_wu
= 153,
181 rv_op_fclass_s
= 155,
183 rv_op_fcvt_l_s
= 157,
184 rv_op_fcvt_lu_s
= 158,
185 rv_op_fcvt_s_l
= 159,
186 rv_op_fcvt_s_lu
= 160,
191 rv_op_fnmsub_d
= 165,
192 rv_op_fnmadd_d
= 166,
198 rv_op_fsgnjn_d
= 172,
199 rv_op_fsgnjx_d
= 173,
202 rv_op_fcvt_s_d
= 176,
203 rv_op_fcvt_d_s
= 177,
208 rv_op_fcvt_w_d
= 182,
209 rv_op_fcvt_wu_d
= 183,
210 rv_op_fcvt_d_w
= 184,
211 rv_op_fcvt_d_wu
= 185,
212 rv_op_fclass_d
= 186,
213 rv_op_fcvt_l_d
= 187,
214 rv_op_fcvt_lu_d
= 188,
216 rv_op_fcvt_d_l
= 190,
217 rv_op_fcvt_d_lu
= 191,
223 rv_op_fnmsub_q
= 197,
224 rv_op_fnmadd_q
= 198,
230 rv_op_fsgnjn_q
= 204,
231 rv_op_fsgnjx_q
= 205,
234 rv_op_fcvt_s_q
= 208,
235 rv_op_fcvt_q_s
= 209,
236 rv_op_fcvt_d_q
= 210,
237 rv_op_fcvt_q_d
= 211,
242 rv_op_fcvt_w_q
= 216,
243 rv_op_fcvt_wu_q
= 217,
244 rv_op_fcvt_q_w
= 218,
245 rv_op_fcvt_q_wu
= 219,
246 rv_op_fclass_q
= 220,
247 rv_op_fcvt_l_q
= 221,
248 rv_op_fcvt_lu_q
= 222,
249 rv_op_fcvt_q_l
= 223,
250 rv_op_fcvt_q_lu
= 224,
253 rv_op_c_addi4spn
= 227,
264 rv_op_c_addi16sp
= 238,
284 rv_op_c_ebreak
= 258,
333 rv_op_rdinstret
= 307,
334 rv_op_rdcycleh
= 308,
336 rv_op_rdinstreth
= 310,
344 rv_op_fsflagsi
= 318,
363 rv_op_sh1add_uw
= 337,
364 rv_op_sh2add_uw
= 338,
365 rv_op_sh3add_uw
= 339,
388 rv_op_aes32esmi
= 362,
389 rv_op_aes32esi
= 363,
390 rv_op_aes32dsmi
= 364,
391 rv_op_aes32dsi
= 365,
392 rv_op_aes64ks1i
= 366,
393 rv_op_aes64ks2
= 367,
395 rv_op_aes64esm
= 369,
397 rv_op_aes64dsm
= 371,
399 rv_op_sha256sig0
= 373,
400 rv_op_sha256sig1
= 374,
401 rv_op_sha256sum0
= 375,
402 rv_op_sha256sum1
= 376,
403 rv_op_sha512sig0
= 377,
404 rv_op_sha512sig1
= 378,
405 rv_op_sha512sum0
= 379,
406 rv_op_sha512sum1
= 380,
407 rv_op_sha512sum0r
= 381,
408 rv_op_sha512sum1r
= 382,
409 rv_op_sha512sig0l
= 383,
410 rv_op_sha512sig0h
= 384,
411 rv_op_sha512sig1l
= 385,
412 rv_op_sha512sig1h
= 386,
436 rv_op_vlse16_v
= 410,
437 rv_op_vlse32_v
= 411,
438 rv_op_vlse64_v
= 412,
440 rv_op_vsse16_v
= 414,
441 rv_op_vsse32_v
= 415,
442 rv_op_vsse64_v
= 416,
443 rv_op_vluxei8_v
= 417,
444 rv_op_vluxei16_v
= 418,
445 rv_op_vluxei32_v
= 419,
446 rv_op_vluxei64_v
= 420,
447 rv_op_vloxei8_v
= 421,
448 rv_op_vloxei16_v
= 422,
449 rv_op_vloxei32_v
= 423,
450 rv_op_vloxei64_v
= 424,
451 rv_op_vsuxei8_v
= 425,
452 rv_op_vsuxei16_v
= 426,
453 rv_op_vsuxei32_v
= 427,
454 rv_op_vsuxei64_v
= 428,
455 rv_op_vsoxei8_v
= 429,
456 rv_op_vsoxei16_v
= 430,
457 rv_op_vsoxei32_v
= 431,
458 rv_op_vsoxei64_v
= 432,
459 rv_op_vle8ff_v
= 433,
460 rv_op_vle16ff_v
= 434,
461 rv_op_vle32ff_v
= 435,
462 rv_op_vle64ff_v
= 436,
463 rv_op_vl1re8_v
= 437,
464 rv_op_vl1re16_v
= 438,
465 rv_op_vl1re32_v
= 439,
466 rv_op_vl1re64_v
= 440,
467 rv_op_vl2re8_v
= 441,
468 rv_op_vl2re16_v
= 442,
469 rv_op_vl2re32_v
= 443,
470 rv_op_vl2re64_v
= 444,
471 rv_op_vl4re8_v
= 445,
472 rv_op_vl4re16_v
= 446,
473 rv_op_vl4re32_v
= 447,
474 rv_op_vl4re64_v
= 448,
475 rv_op_vl8re8_v
= 449,
476 rv_op_vl8re16_v
= 450,
477 rv_op_vl8re32_v
= 451,
478 rv_op_vl8re64_v
= 452,
488 rv_op_vrsub_vx
= 462,
489 rv_op_vrsub_vi
= 463,
490 rv_op_vwaddu_vv
= 464,
491 rv_op_vwaddu_vx
= 465,
492 rv_op_vwadd_vv
= 466,
493 rv_op_vwadd_vx
= 467,
494 rv_op_vwsubu_vv
= 468,
495 rv_op_vwsubu_vx
= 469,
496 rv_op_vwsub_vv
= 470,
497 rv_op_vwsub_vx
= 471,
498 rv_op_vwaddu_wv
= 472,
499 rv_op_vwaddu_wx
= 473,
500 rv_op_vwadd_wv
= 474,
501 rv_op_vwadd_wx
= 475,
502 rv_op_vwsubu_wv
= 476,
503 rv_op_vwsubu_wx
= 477,
504 rv_op_vwsub_wv
= 478,
505 rv_op_vwsub_wx
= 479,
506 rv_op_vadc_vvm
= 480,
507 rv_op_vadc_vxm
= 481,
508 rv_op_vadc_vim
= 482,
509 rv_op_vmadc_vvm
= 483,
510 rv_op_vmadc_vxm
= 484,
511 rv_op_vmadc_vim
= 485,
512 rv_op_vsbc_vvm
= 486,
513 rv_op_vsbc_vxm
= 487,
514 rv_op_vmsbc_vvm
= 488,
515 rv_op_vmsbc_vxm
= 489,
534 rv_op_vnsrl_wv
= 508,
535 rv_op_vnsrl_wx
= 509,
536 rv_op_vnsrl_wi
= 510,
537 rv_op_vnsra_wv
= 511,
538 rv_op_vnsra_wx
= 512,
539 rv_op_vnsra_wi
= 513,
540 rv_op_vmseq_vv
= 514,
541 rv_op_vmseq_vx
= 515,
542 rv_op_vmseq_vi
= 516,
543 rv_op_vmsne_vv
= 517,
544 rv_op_vmsne_vx
= 518,
545 rv_op_vmsne_vi
= 519,
546 rv_op_vmsltu_vv
= 520,
547 rv_op_vmsltu_vx
= 521,
548 rv_op_vmslt_vv
= 522,
549 rv_op_vmslt_vx
= 523,
550 rv_op_vmsleu_vv
= 524,
551 rv_op_vmsleu_vx
= 525,
552 rv_op_vmsleu_vi
= 526,
553 rv_op_vmsle_vv
= 527,
554 rv_op_vmsle_vx
= 528,
555 rv_op_vmsle_vi
= 529,
556 rv_op_vmsgtu_vx
= 530,
557 rv_op_vmsgtu_vi
= 531,
558 rv_op_vmsgt_vx
= 532,
559 rv_op_vmsgt_vi
= 533,
560 rv_op_vminu_vv
= 534,
561 rv_op_vminu_vx
= 535,
564 rv_op_vmaxu_vv
= 538,
565 rv_op_vmaxu_vx
= 539,
570 rv_op_vmulh_vv
= 544,
571 rv_op_vmulh_vx
= 545,
572 rv_op_vmulhu_vv
= 546,
573 rv_op_vmulhu_vx
= 547,
574 rv_op_vmulhsu_vv
= 548,
575 rv_op_vmulhsu_vx
= 549,
576 rv_op_vdivu_vv
= 550,
577 rv_op_vdivu_vx
= 551,
580 rv_op_vremu_vv
= 554,
581 rv_op_vremu_vx
= 555,
584 rv_op_vwmulu_vv
= 558,
585 rv_op_vwmulu_vx
= 559,
586 rv_op_vwmulsu_vv
= 560,
587 rv_op_vwmulsu_vx
= 561,
588 rv_op_vwmul_vv
= 562,
589 rv_op_vwmul_vx
= 563,
590 rv_op_vmacc_vv
= 564,
591 rv_op_vmacc_vx
= 565,
592 rv_op_vnmsac_vv
= 566,
593 rv_op_vnmsac_vx
= 567,
594 rv_op_vmadd_vv
= 568,
595 rv_op_vmadd_vx
= 569,
596 rv_op_vnmsub_vv
= 570,
597 rv_op_vnmsub_vx
= 571,
598 rv_op_vwmaccu_vv
= 572,
599 rv_op_vwmaccu_vx
= 573,
600 rv_op_vwmacc_vv
= 574,
601 rv_op_vwmacc_vx
= 575,
602 rv_op_vwmaccsu_vv
= 576,
603 rv_op_vwmaccsu_vx
= 577,
604 rv_op_vwmaccus_vx
= 578,
608 rv_op_vmerge_vvm
= 582,
609 rv_op_vmerge_vxm
= 583,
610 rv_op_vmerge_vim
= 584,
611 rv_op_vsaddu_vv
= 585,
612 rv_op_vsaddu_vx
= 586,
613 rv_op_vsaddu_vi
= 587,
614 rv_op_vsadd_vv
= 588,
615 rv_op_vsadd_vx
= 589,
616 rv_op_vsadd_vi
= 590,
617 rv_op_vssubu_vv
= 591,
618 rv_op_vssubu_vx
= 592,
619 rv_op_vssub_vv
= 593,
620 rv_op_vssub_vx
= 594,
621 rv_op_vaadd_vv
= 595,
622 rv_op_vaadd_vx
= 596,
623 rv_op_vaaddu_vv
= 597,
624 rv_op_vaaddu_vx
= 598,
625 rv_op_vasub_vv
= 599,
626 rv_op_vasub_vx
= 600,
627 rv_op_vasubu_vv
= 601,
628 rv_op_vasubu_vx
= 602,
629 rv_op_vsmul_vv
= 603,
630 rv_op_vsmul_vx
= 604,
631 rv_op_vssrl_vv
= 605,
632 rv_op_vssrl_vx
= 606,
633 rv_op_vssrl_vi
= 607,
634 rv_op_vssra_vv
= 608,
635 rv_op_vssra_vx
= 609,
636 rv_op_vssra_vi
= 610,
637 rv_op_vnclipu_wv
= 611,
638 rv_op_vnclipu_wx
= 612,
639 rv_op_vnclipu_wi
= 613,
640 rv_op_vnclip_wv
= 614,
641 rv_op_vnclip_wx
= 615,
642 rv_op_vnclip_wi
= 616,
643 rv_op_vfadd_vv
= 617,
644 rv_op_vfadd_vf
= 618,
645 rv_op_vfsub_vv
= 619,
646 rv_op_vfsub_vf
= 620,
647 rv_op_vfrsub_vf
= 621,
648 rv_op_vfwadd_vv
= 622,
649 rv_op_vfwadd_vf
= 623,
650 rv_op_vfwadd_wv
= 624,
651 rv_op_vfwadd_wf
= 625,
652 rv_op_vfwsub_vv
= 626,
653 rv_op_vfwsub_vf
= 627,
654 rv_op_vfwsub_wv
= 628,
655 rv_op_vfwsub_wf
= 629,
656 rv_op_vfmul_vv
= 630,
657 rv_op_vfmul_vf
= 631,
658 rv_op_vfdiv_vv
= 632,
659 rv_op_vfdiv_vf
= 633,
660 rv_op_vfrdiv_vf
= 634,
661 rv_op_vfwmul_vv
= 635,
662 rv_op_vfwmul_vf
= 636,
663 rv_op_vfmacc_vv
= 637,
664 rv_op_vfmacc_vf
= 638,
665 rv_op_vfnmacc_vv
= 639,
666 rv_op_vfnmacc_vf
= 640,
667 rv_op_vfmsac_vv
= 641,
668 rv_op_vfmsac_vf
= 642,
669 rv_op_vfnmsac_vv
= 643,
670 rv_op_vfnmsac_vf
= 644,
671 rv_op_vfmadd_vv
= 645,
672 rv_op_vfmadd_vf
= 646,
673 rv_op_vfnmadd_vv
= 647,
674 rv_op_vfnmadd_vf
= 648,
675 rv_op_vfmsub_vv
= 649,
676 rv_op_vfmsub_vf
= 650,
677 rv_op_vfnmsub_vv
= 651,
678 rv_op_vfnmsub_vf
= 652,
679 rv_op_vfwmacc_vv
= 653,
680 rv_op_vfwmacc_vf
= 654,
681 rv_op_vfwnmacc_vv
= 655,
682 rv_op_vfwnmacc_vf
= 656,
683 rv_op_vfwmsac_vv
= 657,
684 rv_op_vfwmsac_vf
= 658,
685 rv_op_vfwnmsac_vv
= 659,
686 rv_op_vfwnmsac_vf
= 660,
687 rv_op_vfsqrt_v
= 661,
688 rv_op_vfrsqrt7_v
= 662,
689 rv_op_vfrec7_v
= 663,
690 rv_op_vfmin_vv
= 664,
691 rv_op_vfmin_vf
= 665,
692 rv_op_vfmax_vv
= 666,
693 rv_op_vfmax_vf
= 667,
694 rv_op_vfsgnj_vv
= 668,
695 rv_op_vfsgnj_vf
= 669,
696 rv_op_vfsgnjn_vv
= 670,
697 rv_op_vfsgnjn_vf
= 671,
698 rv_op_vfsgnjx_vv
= 672,
699 rv_op_vfsgnjx_vf
= 673,
700 rv_op_vfslide1up_vf
= 674,
701 rv_op_vfslide1down_vf
= 675,
702 rv_op_vmfeq_vv
= 676,
703 rv_op_vmfeq_vf
= 677,
704 rv_op_vmfne_vv
= 678,
705 rv_op_vmfne_vf
= 679,
706 rv_op_vmflt_vv
= 680,
707 rv_op_vmflt_vf
= 681,
708 rv_op_vmfle_vv
= 682,
709 rv_op_vmfle_vf
= 683,
710 rv_op_vmfgt_vf
= 684,
711 rv_op_vmfge_vf
= 685,
712 rv_op_vfclass_v
= 686,
713 rv_op_vfmerge_vfm
= 687,
714 rv_op_vfmv_v_f
= 688,
715 rv_op_vfcvt_xu_f_v
= 689,
716 rv_op_vfcvt_x_f_v
= 690,
717 rv_op_vfcvt_f_xu_v
= 691,
718 rv_op_vfcvt_f_x_v
= 692,
719 rv_op_vfcvt_rtz_xu_f_v
= 693,
720 rv_op_vfcvt_rtz_x_f_v
= 694,
721 rv_op_vfwcvt_xu_f_v
= 695,
722 rv_op_vfwcvt_x_f_v
= 696,
723 rv_op_vfwcvt_f_xu_v
= 697,
724 rv_op_vfwcvt_f_x_v
= 698,
725 rv_op_vfwcvt_f_f_v
= 699,
726 rv_op_vfwcvt_rtz_xu_f_v
= 700,
727 rv_op_vfwcvt_rtz_x_f_v
= 701,
728 rv_op_vfncvt_xu_f_w
= 702,
729 rv_op_vfncvt_x_f_w
= 703,
730 rv_op_vfncvt_f_xu_w
= 704,
731 rv_op_vfncvt_f_x_w
= 705,
732 rv_op_vfncvt_f_f_w
= 706,
733 rv_op_vfncvt_rod_f_f_w
= 707,
734 rv_op_vfncvt_rtz_xu_f_w
= 708,
735 rv_op_vfncvt_rtz_x_f_w
= 709,
736 rv_op_vredsum_vs
= 710,
737 rv_op_vredand_vs
= 711,
738 rv_op_vredor_vs
= 712,
739 rv_op_vredxor_vs
= 713,
740 rv_op_vredminu_vs
= 714,
741 rv_op_vredmin_vs
= 715,
742 rv_op_vredmaxu_vs
= 716,
743 rv_op_vredmax_vs
= 717,
744 rv_op_vwredsumu_vs
= 718,
745 rv_op_vwredsum_vs
= 719,
746 rv_op_vfredusum_vs
= 720,
747 rv_op_vfredosum_vs
= 721,
748 rv_op_vfredmin_vs
= 722,
749 rv_op_vfredmax_vs
= 723,
750 rv_op_vfwredusum_vs
= 724,
751 rv_op_vfwredosum_vs
= 725,
752 rv_op_vmand_mm
= 726,
753 rv_op_vmnand_mm
= 727,
754 rv_op_vmandn_mm
= 728,
755 rv_op_vmxor_mm
= 729,
757 rv_op_vmnor_mm
= 731,
758 rv_op_vmorn_mm
= 732,
759 rv_op_vmxnor_mm
= 733,
761 rv_op_vfirst_m
= 735,
769 rv_op_vfmv_f_s
= 743,
770 rv_op_vfmv_s_f
= 744,
771 rv_op_vslideup_vx
= 745,
772 rv_op_vslideup_vi
= 746,
773 rv_op_vslide1up_vx
= 747,
774 rv_op_vslidedown_vx
= 748,
775 rv_op_vslidedown_vi
= 749,
776 rv_op_vslide1down_vx
= 750,
777 rv_op_vrgather_vv
= 751,
778 rv_op_vrgatherei16_vv
= 752,
779 rv_op_vrgather_vx
= 753,
780 rv_op_vrgather_vi
= 754,
781 rv_op_vcompress_vm
= 755,
786 rv_op_vzext_vf2
= 760,
787 rv_op_vzext_vf4
= 761,
788 rv_op_vzext_vf8
= 762,
789 rv_op_vsext_vf2
= 763,
790 rv_op_vsext_vf4
= 764,
791 rv_op_vsext_vf8
= 765,
793 rv_op_vsetivli
= 767,
795 rv_op_c_zext_b
= 769,
796 rv_op_c_sext_b
= 770,
797 rv_op_c_zext_h
= 771,
798 rv_op_c_sext_h
= 772,
799 rv_op_c_zext_w
= 773,
809 rv_op_cm_popret
= 783,
810 rv_op_cm_popretz
= 784,
811 rv_op_cm_mva01s
= 785,
812 rv_op_cm_mvsa01
= 786,
815 rv_op_czero_eqz
= 789,
816 rv_op_czero_nez
= 790,
821 static const char rv_ireg_name_sym
[32][5] = {
822 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
823 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
824 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
825 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
828 static const char rv_freg_name_sym
[32][5] = {
829 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
830 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
831 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
832 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11",
835 static const char rv_vreg_name_sym
[32][4] = {
836 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
837 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
838 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
839 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
842 /* pseudo-instruction constraints */
844 static const rvc_constraint rvcc_jal
[] = { rvc_rd_eq_ra
, rvc_end
};
845 static const rvc_constraint rvcc_jalr
[] = { rvc_rd_eq_ra
, rvc_imm_eq_zero
,
847 static const rvc_constraint rvcc_nop
[] = { rvc_rd_eq_x0
, rvc_rs1_eq_x0
,
848 rvc_imm_eq_zero
, rvc_end
};
849 static const rvc_constraint rvcc_mv
[] = { rvc_imm_eq_zero
, rvc_end
};
850 static const rvc_constraint rvcc_not
[] = { rvc_imm_eq_n1
, rvc_end
};
851 static const rvc_constraint rvcc_neg
[] = { rvc_rs1_eq_x0
, rvc_end
};
852 static const rvc_constraint rvcc_negw
[] = { rvc_rs1_eq_x0
, rvc_end
};
853 static const rvc_constraint rvcc_sext_w
[] = { rvc_imm_eq_zero
, rvc_end
};
854 static const rvc_constraint rvcc_seqz
[] = { rvc_imm_eq_p1
, rvc_end
};
855 static const rvc_constraint rvcc_snez
[] = { rvc_rs1_eq_x0
, rvc_end
};
856 static const rvc_constraint rvcc_sltz
[] = { rvc_rs2_eq_x0
, rvc_end
};
857 static const rvc_constraint rvcc_sgtz
[] = { rvc_rs1_eq_x0
, rvc_end
};
858 static const rvc_constraint rvcc_fmv_s
[] = { rvc_rs2_eq_rs1
, rvc_end
};
859 static const rvc_constraint rvcc_fabs_s
[] = { rvc_rs2_eq_rs1
, rvc_end
};
860 static const rvc_constraint rvcc_fneg_s
[] = { rvc_rs2_eq_rs1
, rvc_end
};
861 static const rvc_constraint rvcc_fmv_d
[] = { rvc_rs2_eq_rs1
, rvc_end
};
862 static const rvc_constraint rvcc_fabs_d
[] = { rvc_rs2_eq_rs1
, rvc_end
};
863 static const rvc_constraint rvcc_fneg_d
[] = { rvc_rs2_eq_rs1
, rvc_end
};
864 static const rvc_constraint rvcc_fmv_q
[] = { rvc_rs2_eq_rs1
, rvc_end
};
865 static const rvc_constraint rvcc_fabs_q
[] = { rvc_rs2_eq_rs1
, rvc_end
};
866 static const rvc_constraint rvcc_fneg_q
[] = { rvc_rs2_eq_rs1
, rvc_end
};
867 static const rvc_constraint rvcc_beqz
[] = { rvc_rs2_eq_x0
, rvc_end
};
868 static const rvc_constraint rvcc_bnez
[] = { rvc_rs2_eq_x0
, rvc_end
};
869 static const rvc_constraint rvcc_blez
[] = { rvc_rs1_eq_x0
, rvc_end
};
870 static const rvc_constraint rvcc_bgez
[] = { rvc_rs2_eq_x0
, rvc_end
};
871 static const rvc_constraint rvcc_bltz
[] = { rvc_rs2_eq_x0
, rvc_end
};
872 static const rvc_constraint rvcc_bgtz
[] = { rvc_rs1_eq_x0
, rvc_end
};
873 static const rvc_constraint rvcc_ble
[] = { rvc_end
};
874 static const rvc_constraint rvcc_bleu
[] = { rvc_end
};
875 static const rvc_constraint rvcc_bgt
[] = { rvc_end
};
876 static const rvc_constraint rvcc_bgtu
[] = { rvc_end
};
877 static const rvc_constraint rvcc_j
[] = { rvc_rd_eq_x0
, rvc_end
};
878 static const rvc_constraint rvcc_ret
[] = { rvc_rd_eq_x0
, rvc_rs1_eq_ra
,
880 static const rvc_constraint rvcc_jr
[] = { rvc_rd_eq_x0
, rvc_imm_eq_zero
,
882 static const rvc_constraint rvcc_rdcycle
[] = { rvc_rs1_eq_x0
, rvc_csr_eq_0xc00
,
884 static const rvc_constraint rvcc_rdtime
[] = { rvc_rs1_eq_x0
, rvc_csr_eq_0xc01
,
886 static const rvc_constraint rvcc_rdinstret
[] = { rvc_rs1_eq_x0
,
887 rvc_csr_eq_0xc02
, rvc_end
};
888 static const rvc_constraint rvcc_rdcycleh
[] = { rvc_rs1_eq_x0
,
889 rvc_csr_eq_0xc80
, rvc_end
};
890 static const rvc_constraint rvcc_rdtimeh
[] = { rvc_rs1_eq_x0
, rvc_csr_eq_0xc81
,
892 static const rvc_constraint rvcc_rdinstreth
[] = { rvc_rs1_eq_x0
,
893 rvc_csr_eq_0xc82
, rvc_end
};
894 static const rvc_constraint rvcc_frcsr
[] = { rvc_rs1_eq_x0
, rvc_csr_eq_0x003
,
896 static const rvc_constraint rvcc_frrm
[] = { rvc_rs1_eq_x0
, rvc_csr_eq_0x002
,
898 static const rvc_constraint rvcc_frflags
[] = { rvc_rs1_eq_x0
, rvc_csr_eq_0x001
,
900 static const rvc_constraint rvcc_fscsr
[] = { rvc_csr_eq_0x003
, rvc_end
};
901 static const rvc_constraint rvcc_fsrm
[] = { rvc_csr_eq_0x002
, rvc_end
};
902 static const rvc_constraint rvcc_fsflags
[] = { rvc_csr_eq_0x001
, rvc_end
};
903 static const rvc_constraint rvcc_fsrmi
[] = { rvc_csr_eq_0x002
, rvc_end
};
904 static const rvc_constraint rvcc_fsflagsi
[] = { rvc_csr_eq_0x001
, rvc_end
};
906 /* pseudo-instruction metadata */
908 static const rv_comp_data rvcp_jal
[] = {
910 { rv_op_jal
, rvcc_jal
},
911 { rv_op_illegal
, NULL
}
914 static const rv_comp_data rvcp_jalr
[] = {
915 { rv_op_ret
, rvcc_ret
},
916 { rv_op_jr
, rvcc_jr
},
917 { rv_op_jalr
, rvcc_jalr
},
918 { rv_op_illegal
, NULL
}
921 static const rv_comp_data rvcp_beq
[] = {
922 { rv_op_beqz
, rvcc_beqz
},
923 { rv_op_illegal
, NULL
}
926 static const rv_comp_data rvcp_bne
[] = {
927 { rv_op_bnez
, rvcc_bnez
},
928 { rv_op_illegal
, NULL
}
931 static const rv_comp_data rvcp_blt
[] = {
932 { rv_op_bltz
, rvcc_bltz
},
933 { rv_op_bgtz
, rvcc_bgtz
},
934 { rv_op_bgt
, rvcc_bgt
},
935 { rv_op_illegal
, NULL
}
938 static const rv_comp_data rvcp_bge
[] = {
939 { rv_op_blez
, rvcc_blez
},
940 { rv_op_bgez
, rvcc_bgez
},
941 { rv_op_ble
, rvcc_ble
},
942 { rv_op_illegal
, NULL
}
945 static const rv_comp_data rvcp_bltu
[] = {
946 { rv_op_bgtu
, rvcc_bgtu
},
947 { rv_op_illegal
, NULL
}
950 static const rv_comp_data rvcp_bgeu
[] = {
951 { rv_op_bleu
, rvcc_bleu
},
952 { rv_op_illegal
, NULL
}
955 static const rv_comp_data rvcp_addi
[] = {
956 { rv_op_nop
, rvcc_nop
},
957 { rv_op_mv
, rvcc_mv
},
958 { rv_op_illegal
, NULL
}
961 static const rv_comp_data rvcp_sltiu
[] = {
962 { rv_op_seqz
, rvcc_seqz
},
963 { rv_op_illegal
, NULL
}
966 static const rv_comp_data rvcp_xori
[] = {
967 { rv_op_not
, rvcc_not
},
968 { rv_op_illegal
, NULL
}
971 static const rv_comp_data rvcp_sub
[] = {
972 { rv_op_neg
, rvcc_neg
},
973 { rv_op_illegal
, NULL
}
976 static const rv_comp_data rvcp_slt
[] = {
977 { rv_op_sltz
, rvcc_sltz
},
978 { rv_op_sgtz
, rvcc_sgtz
},
979 { rv_op_illegal
, NULL
}
982 static const rv_comp_data rvcp_sltu
[] = {
983 { rv_op_snez
, rvcc_snez
},
984 { rv_op_illegal
, NULL
}
987 static const rv_comp_data rvcp_addiw
[] = {
988 { rv_op_sext_w
, rvcc_sext_w
},
989 { rv_op_illegal
, NULL
}
992 static const rv_comp_data rvcp_subw
[] = {
993 { rv_op_negw
, rvcc_negw
},
994 { rv_op_illegal
, NULL
}
997 static const rv_comp_data rvcp_csrrw
[] = {
998 { rv_op_fscsr
, rvcc_fscsr
},
999 { rv_op_fsrm
, rvcc_fsrm
},
1000 { rv_op_fsflags
, rvcc_fsflags
},
1001 { rv_op_illegal
, NULL
}
1005 static const rv_comp_data rvcp_csrrs
[] = {
1006 { rv_op_rdcycle
, rvcc_rdcycle
},
1007 { rv_op_rdtime
, rvcc_rdtime
},
1008 { rv_op_rdinstret
, rvcc_rdinstret
},
1009 { rv_op_rdcycleh
, rvcc_rdcycleh
},
1010 { rv_op_rdtimeh
, rvcc_rdtimeh
},
1011 { rv_op_rdinstreth
, rvcc_rdinstreth
},
1012 { rv_op_frcsr
, rvcc_frcsr
},
1013 { rv_op_frrm
, rvcc_frrm
},
1014 { rv_op_frflags
, rvcc_frflags
},
1015 { rv_op_illegal
, NULL
}
1018 static const rv_comp_data rvcp_csrrwi
[] = {
1019 { rv_op_fsrmi
, rvcc_fsrmi
},
1020 { rv_op_fsflagsi
, rvcc_fsflagsi
},
1021 { rv_op_illegal
, NULL
}
1024 static const rv_comp_data rvcp_fsgnj_s
[] = {
1025 { rv_op_fmv_s
, rvcc_fmv_s
},
1026 { rv_op_illegal
, NULL
}
1029 static const rv_comp_data rvcp_fsgnjn_s
[] = {
1030 { rv_op_fneg_s
, rvcc_fneg_s
},
1031 { rv_op_illegal
, NULL
}
1034 static const rv_comp_data rvcp_fsgnjx_s
[] = {
1035 { rv_op_fabs_s
, rvcc_fabs_s
},
1036 { rv_op_illegal
, NULL
}
1039 static const rv_comp_data rvcp_fsgnj_d
[] = {
1040 { rv_op_fmv_d
, rvcc_fmv_d
},
1041 { rv_op_illegal
, NULL
}
1044 static const rv_comp_data rvcp_fsgnjn_d
[] = {
1045 { rv_op_fneg_d
, rvcc_fneg_d
},
1046 { rv_op_illegal
, NULL
}
1049 static const rv_comp_data rvcp_fsgnjx_d
[] = {
1050 { rv_op_fabs_d
, rvcc_fabs_d
},
1051 { rv_op_illegal
, NULL
}
1054 static const rv_comp_data rvcp_fsgnj_q
[] = {
1055 { rv_op_fmv_q
, rvcc_fmv_q
},
1056 { rv_op_illegal
, NULL
}
1059 static const rv_comp_data rvcp_fsgnjn_q
[] = {
1060 { rv_op_fneg_q
, rvcc_fneg_q
},
1061 { rv_op_illegal
, NULL
}
1064 static const rv_comp_data rvcp_fsgnjx_q
[] = {
1065 { rv_op_fabs_q
, rvcc_fabs_q
},
1066 { rv_op_illegal
, NULL
}
1069 /* instruction metadata */
1071 const rv_opcode_data opcode_data
[] = {
1072 { "illegal", rv_codec_illegal
, rv_fmt_none
, NULL
, 0, 0, 0 },
1073 { "lui", rv_codec_u
, rv_fmt_rd_imm
, NULL
, 0, 0, 0 },
1074 { "auipc", rv_codec_u
, rv_fmt_rd_offset
, NULL
, 0, 0, 0 },
1075 { "jal", rv_codec_uj
, rv_fmt_rd_offset
, rvcp_jal
, 0, 0, 0 },
1076 { "jalr", rv_codec_i
, rv_fmt_rd_rs1_offset
, rvcp_jalr
, 0, 0, 0 },
1077 { "beq", rv_codec_sb
, rv_fmt_rs1_rs2_offset
, rvcp_beq
, 0, 0, 0 },
1078 { "bne", rv_codec_sb
, rv_fmt_rs1_rs2_offset
, rvcp_bne
, 0, 0, 0 },
1079 { "blt", rv_codec_sb
, rv_fmt_rs1_rs2_offset
, rvcp_blt
, 0, 0, 0 },
1080 { "bge", rv_codec_sb
, rv_fmt_rs1_rs2_offset
, rvcp_bge
, 0, 0, 0 },
1081 { "bltu", rv_codec_sb
, rv_fmt_rs1_rs2_offset
, rvcp_bltu
, 0, 0, 0 },
1082 { "bgeu", rv_codec_sb
, rv_fmt_rs1_rs2_offset
, rvcp_bgeu
, 0, 0, 0 },
1083 { "lb", rv_codec_i
, rv_fmt_rd_offset_rs1
, NULL
, 0, 0, 0 },
1084 { "lh", rv_codec_i
, rv_fmt_rd_offset_rs1
, NULL
, 0, 0, 0 },
1085 { "lw", rv_codec_i
, rv_fmt_rd_offset_rs1
, NULL
, 0, 0, 0 },
1086 { "lbu", rv_codec_i
, rv_fmt_rd_offset_rs1
, NULL
, 0, 0, 0 },
1087 { "lhu", rv_codec_i
, rv_fmt_rd_offset_rs1
, NULL
, 0, 0, 0 },
1088 { "sb", rv_codec_s
, rv_fmt_rs2_offset_rs1
, NULL
, 0, 0, 0 },
1089 { "sh", rv_codec_s
, rv_fmt_rs2_offset_rs1
, NULL
, 0, 0, 0 },
1090 { "sw", rv_codec_s
, rv_fmt_rs2_offset_rs1
, NULL
, 0, 0, 0 },
1091 { "addi", rv_codec_i
, rv_fmt_rd_rs1_imm
, rvcp_addi
, 0, 0, 0 },
1092 { "slti", rv_codec_i
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1093 { "sltiu", rv_codec_i
, rv_fmt_rd_rs1_imm
, rvcp_sltiu
, 0, 0, 0 },
1094 { "xori", rv_codec_i
, rv_fmt_rd_rs1_imm
, rvcp_xori
, 0, 0, 0 },
1095 { "ori", rv_codec_i
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1096 { "andi", rv_codec_i
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1097 { "slli", rv_codec_i_sh7
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1098 { "srli", rv_codec_i_sh7
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1099 { "srai", rv_codec_i_sh7
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1100 { "add", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1101 { "sub", rv_codec_r
, rv_fmt_rd_rs1_rs2
, rvcp_sub
, 0, 0, 0 },
1102 { "sll", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1103 { "slt", rv_codec_r
, rv_fmt_rd_rs1_rs2
, rvcp_slt
, 0, 0, 0 },
1104 { "sltu", rv_codec_r
, rv_fmt_rd_rs1_rs2
, rvcp_sltu
, 0, 0, 0 },
1105 { "xor", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1106 { "srl", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1107 { "sra", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1108 { "or", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1109 { "and", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1110 { "fence", rv_codec_r_f
, rv_fmt_pred_succ
, NULL
, 0, 0, 0 },
1111 { "fence.i", rv_codec_none
, rv_fmt_none
, NULL
, 0, 0, 0 },
1112 { "lwu", rv_codec_i
, rv_fmt_rd_offset_rs1
, NULL
, 0, 0, 0 },
1113 { "ld", rv_codec_i
, rv_fmt_rd_offset_rs1
, NULL
, 0, 0, 0 },
1114 { "sd", rv_codec_s
, rv_fmt_rs2_offset_rs1
, NULL
, 0, 0, 0 },
1115 { "addiw", rv_codec_i
, rv_fmt_rd_rs1_imm
, rvcp_addiw
, 0, 0, 0 },
1116 { "slliw", rv_codec_i_sh5
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1117 { "srliw", rv_codec_i_sh5
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1118 { "sraiw", rv_codec_i_sh5
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1119 { "addw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1120 { "subw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, rvcp_subw
, 0, 0, 0 },
1121 { "sllw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1122 { "srlw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1123 { "sraw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1124 { "ldu", rv_codec_i
, rv_fmt_rd_offset_rs1
, NULL
, 0, 0, 0 },
1125 { "lq", rv_codec_i
, rv_fmt_rd_offset_rs1
, NULL
, 0, 0, 0 },
1126 { "sq", rv_codec_s
, rv_fmt_rs2_offset_rs1
, NULL
, 0, 0, 0 },
1127 { "addid", rv_codec_i
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1128 { "sllid", rv_codec_i_sh6
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1129 { "srlid", rv_codec_i_sh6
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1130 { "sraid", rv_codec_i_sh6
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1131 { "addd", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1132 { "subd", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1133 { "slld", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1134 { "srld", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1135 { "srad", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1136 { "mul", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1137 { "mulh", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1138 { "mulhsu", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1139 { "mulhu", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1140 { "div", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1141 { "divu", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1142 { "rem", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1143 { "remu", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1144 { "mulw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1145 { "divw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1146 { "divuw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1147 { "remw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1148 { "remuw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1149 { "muld", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1150 { "divd", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1151 { "divud", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1152 { "remd", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1153 { "remud", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1154 { "lr.w", rv_codec_r_l
, rv_fmt_aqrl_rd_rs1
, NULL
, 0, 0, 0 },
1155 { "sc.w", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1156 { "amoswap.w", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1157 { "amoadd.w", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1158 { "amoxor.w", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1159 { "amoor.w", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1160 { "amoand.w", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1161 { "amomin.w", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1162 { "amomax.w", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1163 { "amominu.w", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1164 { "amomaxu.w", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1165 { "lr.d", rv_codec_r_l
, rv_fmt_aqrl_rd_rs1
, NULL
, 0, 0, 0 },
1166 { "sc.d", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1167 { "amoswap.d", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1168 { "amoadd.d", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1169 { "amoxor.d", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1170 { "amoor.d", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1171 { "amoand.d", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1172 { "amomin.d", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1173 { "amomax.d", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1174 { "amominu.d", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1175 { "amomaxu.d", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1176 { "lr.q", rv_codec_r_l
, rv_fmt_aqrl_rd_rs1
, NULL
, 0, 0, 0 },
1177 { "sc.q", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1178 { "amoswap.q", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1179 { "amoadd.q", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1180 { "amoxor.q", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1181 { "amoor.q", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1182 { "amoand.q", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1183 { "amomin.q", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1184 { "amomax.q", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1185 { "amominu.q", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1186 { "amomaxu.q", rv_codec_r_a
, rv_fmt_aqrl_rd_rs2_rs1
, NULL
, 0, 0, 0 },
1187 { "ecall", rv_codec_none
, rv_fmt_none
, NULL
, 0, 0, 0 },
1188 { "ebreak", rv_codec_none
, rv_fmt_none
, NULL
, 0, 0, 0 },
1189 { "uret", rv_codec_none
, rv_fmt_none
, NULL
, 0, 0, 0 },
1190 { "sret", rv_codec_none
, rv_fmt_none
, NULL
, 0, 0, 0 },
1191 { "hret", rv_codec_none
, rv_fmt_none
, NULL
, 0, 0, 0 },
1192 { "mret", rv_codec_none
, rv_fmt_none
, NULL
, 0, 0, 0 },
1193 { "dret", rv_codec_none
, rv_fmt_none
, NULL
, 0, 0, 0 },
1194 { "sfence.vm", rv_codec_r
, rv_fmt_rs1
, NULL
, 0, 0, 0 },
1195 { "sfence.vma", rv_codec_r
, rv_fmt_rs1_rs2
, NULL
, 0, 0, 0 },
1196 { "wfi", rv_codec_none
, rv_fmt_none
, NULL
, 0, 0, 0 },
1197 { "csrrw", rv_codec_i_csr
, rv_fmt_rd_csr_rs1
, rvcp_csrrw
, 0, 0, 0 },
1198 { "csrrs", rv_codec_i_csr
, rv_fmt_rd_csr_rs1
, rvcp_csrrs
, 0, 0, 0 },
1199 { "csrrc", rv_codec_i_csr
, rv_fmt_rd_csr_rs1
, NULL
, 0, 0, 0 },
1200 { "csrrwi", rv_codec_i_csr
, rv_fmt_rd_csr_zimm
, rvcp_csrrwi
, 0, 0, 0 },
1201 { "csrrsi", rv_codec_i_csr
, rv_fmt_rd_csr_zimm
, NULL
, 0, 0, 0 },
1202 { "csrrci", rv_codec_i_csr
, rv_fmt_rd_csr_zimm
, NULL
, 0, 0, 0 },
1203 { "flw", rv_codec_i
, rv_fmt_frd_offset_rs1
, NULL
, 0, 0, 0 },
1204 { "fsw", rv_codec_s
, rv_fmt_frs2_offset_rs1
, NULL
, 0, 0, 0 },
1205 { "fmadd.s", rv_codec_r4_m
, rv_fmt_rm_frd_frs1_frs2_frs3
, NULL
, 0, 0, 0 },
1206 { "fmsub.s", rv_codec_r4_m
, rv_fmt_rm_frd_frs1_frs2_frs3
, NULL
, 0, 0, 0 },
1207 { "fnmsub.s", rv_codec_r4_m
, rv_fmt_rm_frd_frs1_frs2_frs3
, NULL
, 0, 0, 0 },
1208 { "fnmadd.s", rv_codec_r4_m
, rv_fmt_rm_frd_frs1_frs2_frs3
, NULL
, 0, 0, 0 },
1209 { "fadd.s", rv_codec_r_m
, rv_fmt_rm_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1210 { "fsub.s", rv_codec_r_m
, rv_fmt_rm_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1211 { "fmul.s", rv_codec_r_m
, rv_fmt_rm_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1212 { "fdiv.s", rv_codec_r_m
, rv_fmt_rm_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1213 { "fsgnj.s", rv_codec_r
, rv_fmt_frd_frs1_frs2
, rvcp_fsgnj_s
, 0, 0, 0 },
1214 { "fsgnjn.s", rv_codec_r
, rv_fmt_frd_frs1_frs2
, rvcp_fsgnjn_s
, 0, 0, 0 },
1215 { "fsgnjx.s", rv_codec_r
, rv_fmt_frd_frs1_frs2
, rvcp_fsgnjx_s
, 0, 0, 0 },
1216 { "fmin.s", rv_codec_r
, rv_fmt_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1217 { "fmax.s", rv_codec_r
, rv_fmt_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1218 { "fsqrt.s", rv_codec_r_m
, rv_fmt_rm_frd_frs1
, NULL
, 0, 0, 0 },
1219 { "fle.s", rv_codec_r
, rv_fmt_rd_frs1_frs2
, NULL
, 0, 0, 0 },
1220 { "flt.s", rv_codec_r
, rv_fmt_rd_frs1_frs2
, NULL
, 0, 0, 0 },
1221 { "feq.s", rv_codec_r
, rv_fmt_rd_frs1_frs2
, NULL
, 0, 0, 0 },
1222 { "fcvt.w.s", rv_codec_r_m
, rv_fmt_rm_rd_frs1
, NULL
, 0, 0, 0 },
1223 { "fcvt.wu.s", rv_codec_r_m
, rv_fmt_rm_rd_frs1
, NULL
, 0, 0, 0 },
1224 { "fcvt.s.w", rv_codec_r_m
, rv_fmt_rm_frd_rs1
, NULL
, 0, 0, 0 },
1225 { "fcvt.s.wu", rv_codec_r_m
, rv_fmt_rm_frd_rs1
, NULL
, 0, 0, 0 },
1226 { "fmv.x.s", rv_codec_r
, rv_fmt_rd_frs1
, NULL
, 0, 0, 0 },
1227 { "fclass.s", rv_codec_r
, rv_fmt_rd_frs1
, NULL
, 0, 0, 0 },
1228 { "fmv.s.x", rv_codec_r
, rv_fmt_frd_rs1
, NULL
, 0, 0, 0 },
1229 { "fcvt.l.s", rv_codec_r_m
, rv_fmt_rm_rd_frs1
, NULL
, 0, 0, 0 },
1230 { "fcvt.lu.s", rv_codec_r_m
, rv_fmt_rm_rd_frs1
, NULL
, 0, 0, 0 },
1231 { "fcvt.s.l", rv_codec_r_m
, rv_fmt_rm_frd_rs1
, NULL
, 0, 0, 0 },
1232 { "fcvt.s.lu", rv_codec_r_m
, rv_fmt_rm_frd_rs1
, NULL
, 0, 0, 0 },
1233 { "fld", rv_codec_i
, rv_fmt_frd_offset_rs1
, NULL
, 0, 0, 0 },
1234 { "fsd", rv_codec_s
, rv_fmt_frs2_offset_rs1
, NULL
, 0, 0, 0 },
1235 { "fmadd.d", rv_codec_r4_m
, rv_fmt_rm_frd_frs1_frs2_frs3
, NULL
, 0, 0, 0 },
1236 { "fmsub.d", rv_codec_r4_m
, rv_fmt_rm_frd_frs1_frs2_frs3
, NULL
, 0, 0, 0 },
1237 { "fnmsub.d", rv_codec_r4_m
, rv_fmt_rm_frd_frs1_frs2_frs3
, NULL
, 0, 0, 0 },
1238 { "fnmadd.d", rv_codec_r4_m
, rv_fmt_rm_frd_frs1_frs2_frs3
, NULL
, 0, 0, 0 },
1239 { "fadd.d", rv_codec_r_m
, rv_fmt_rm_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1240 { "fsub.d", rv_codec_r_m
, rv_fmt_rm_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1241 { "fmul.d", rv_codec_r_m
, rv_fmt_rm_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1242 { "fdiv.d", rv_codec_r_m
, rv_fmt_rm_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1243 { "fsgnj.d", rv_codec_r
, rv_fmt_frd_frs1_frs2
, rvcp_fsgnj_d
, 0, 0, 0 },
1244 { "fsgnjn.d", rv_codec_r
, rv_fmt_frd_frs1_frs2
, rvcp_fsgnjn_d
, 0, 0, 0 },
1245 { "fsgnjx.d", rv_codec_r
, rv_fmt_frd_frs1_frs2
, rvcp_fsgnjx_d
, 0, 0, 0 },
1246 { "fmin.d", rv_codec_r
, rv_fmt_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1247 { "fmax.d", rv_codec_r
, rv_fmt_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1248 { "fcvt.s.d", rv_codec_r_m
, rv_fmt_rm_frd_frs1
, NULL
, 0, 0, 0 },
1249 { "fcvt.d.s", rv_codec_r_m
, rv_fmt_rm_frd_frs1
, NULL
, 0, 0, 0 },
1250 { "fsqrt.d", rv_codec_r_m
, rv_fmt_rm_frd_frs1
, NULL
, 0, 0, 0 },
1251 { "fle.d", rv_codec_r
, rv_fmt_rd_frs1_frs2
, NULL
, 0, 0, 0 },
1252 { "flt.d", rv_codec_r
, rv_fmt_rd_frs1_frs2
, NULL
, 0, 0, 0 },
1253 { "feq.d", rv_codec_r
, rv_fmt_rd_frs1_frs2
, NULL
, 0, 0, 0 },
1254 { "fcvt.w.d", rv_codec_r_m
, rv_fmt_rm_rd_frs1
, NULL
, 0, 0, 0 },
1255 { "fcvt.wu.d", rv_codec_r_m
, rv_fmt_rm_rd_frs1
, NULL
, 0, 0, 0 },
1256 { "fcvt.d.w", rv_codec_r_m
, rv_fmt_rm_frd_rs1
, NULL
, 0, 0, 0 },
1257 { "fcvt.d.wu", rv_codec_r_m
, rv_fmt_rm_frd_rs1
, NULL
, 0, 0, 0 },
1258 { "fclass.d", rv_codec_r
, rv_fmt_rd_frs1
, NULL
, 0, 0, 0 },
1259 { "fcvt.l.d", rv_codec_r_m
, rv_fmt_rm_rd_frs1
, NULL
, 0, 0, 0 },
1260 { "fcvt.lu.d", rv_codec_r_m
, rv_fmt_rm_rd_frs1
, NULL
, 0, 0, 0 },
1261 { "fmv.x.d", rv_codec_r
, rv_fmt_rd_frs1
, NULL
, 0, 0, 0 },
1262 { "fcvt.d.l", rv_codec_r_m
, rv_fmt_rm_frd_rs1
, NULL
, 0, 0, 0 },
1263 { "fcvt.d.lu", rv_codec_r_m
, rv_fmt_rm_frd_rs1
, NULL
, 0, 0, 0 },
1264 { "fmv.d.x", rv_codec_r
, rv_fmt_frd_rs1
, NULL
, 0, 0, 0 },
1265 { "flq", rv_codec_i
, rv_fmt_frd_offset_rs1
, NULL
, 0, 0, 0 },
1266 { "fsq", rv_codec_s
, rv_fmt_frs2_offset_rs1
, NULL
, 0, 0, 0 },
1267 { "fmadd.q", rv_codec_r4_m
, rv_fmt_rm_frd_frs1_frs2_frs3
, NULL
, 0, 0, 0 },
1268 { "fmsub.q", rv_codec_r4_m
, rv_fmt_rm_frd_frs1_frs2_frs3
, NULL
, 0, 0, 0 },
1269 { "fnmsub.q", rv_codec_r4_m
, rv_fmt_rm_frd_frs1_frs2_frs3
, NULL
, 0, 0, 0 },
1270 { "fnmadd.q", rv_codec_r4_m
, rv_fmt_rm_frd_frs1_frs2_frs3
, NULL
, 0, 0, 0 },
1271 { "fadd.q", rv_codec_r_m
, rv_fmt_rm_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1272 { "fsub.q", rv_codec_r_m
, rv_fmt_rm_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1273 { "fmul.q", rv_codec_r_m
, rv_fmt_rm_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1274 { "fdiv.q", rv_codec_r_m
, rv_fmt_rm_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1275 { "fsgnj.q", rv_codec_r
, rv_fmt_frd_frs1_frs2
, rvcp_fsgnj_q
, 0, 0, 0 },
1276 { "fsgnjn.q", rv_codec_r
, rv_fmt_frd_frs1_frs2
, rvcp_fsgnjn_q
, 0, 0, 0 },
1277 { "fsgnjx.q", rv_codec_r
, rv_fmt_frd_frs1_frs2
, rvcp_fsgnjx_q
, 0, 0, 0 },
1278 { "fmin.q", rv_codec_r
, rv_fmt_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1279 { "fmax.q", rv_codec_r
, rv_fmt_frd_frs1_frs2
, NULL
, 0, 0, 0 },
1280 { "fcvt.s.q", rv_codec_r_m
, rv_fmt_rm_frd_frs1
, NULL
, 0, 0, 0 },
1281 { "fcvt.q.s", rv_codec_r_m
, rv_fmt_rm_frd_frs1
, NULL
, 0, 0, 0 },
1282 { "fcvt.d.q", rv_codec_r_m
, rv_fmt_rm_frd_frs1
, NULL
, 0, 0, 0 },
1283 { "fcvt.q.d", rv_codec_r_m
, rv_fmt_rm_frd_frs1
, NULL
, 0, 0, 0 },
1284 { "fsqrt.q", rv_codec_r_m
, rv_fmt_rm_frd_frs1
, NULL
, 0, 0, 0 },
1285 { "fle.q", rv_codec_r
, rv_fmt_rd_frs1_frs2
, NULL
, 0, 0, 0 },
1286 { "flt.q", rv_codec_r
, rv_fmt_rd_frs1_frs2
, NULL
, 0, 0, 0 },
1287 { "feq.q", rv_codec_r
, rv_fmt_rd_frs1_frs2
, NULL
, 0, 0, 0 },
1288 { "fcvt.w.q", rv_codec_r_m
, rv_fmt_rm_rd_frs1
, NULL
, 0, 0, 0 },
1289 { "fcvt.wu.q", rv_codec_r_m
, rv_fmt_rm_rd_frs1
, NULL
, 0, 0, 0 },
1290 { "fcvt.q.w", rv_codec_r_m
, rv_fmt_rm_frd_rs1
, NULL
, 0, 0, 0 },
1291 { "fcvt.q.wu", rv_codec_r_m
, rv_fmt_rm_frd_rs1
, NULL
, 0, 0, 0 },
1292 { "fclass.q", rv_codec_r
, rv_fmt_rd_frs1
, NULL
, 0, 0, 0 },
1293 { "fcvt.l.q", rv_codec_r_m
, rv_fmt_rm_rd_frs1
, NULL
, 0, 0, 0 },
1294 { "fcvt.lu.q", rv_codec_r_m
, rv_fmt_rm_rd_frs1
, NULL
, 0, 0, 0 },
1295 { "fcvt.q.l", rv_codec_r_m
, rv_fmt_rm_frd_rs1
, NULL
, 0, 0, 0 },
1296 { "fcvt.q.lu", rv_codec_r_m
, rv_fmt_rm_frd_rs1
, NULL
, 0, 0, 0 },
1297 { "fmv.x.q", rv_codec_r
, rv_fmt_rd_frs1
, NULL
, 0, 0, 0 },
1298 { "fmv.q.x", rv_codec_r
, rv_fmt_frd_rs1
, NULL
, 0, 0, 0 },
1299 { "c.addi4spn", rv_codec_ciw_4spn
, rv_fmt_rd_rs1_imm
, NULL
, rv_op_addi
,
1300 rv_op_addi
, rv_op_addi
, rvcd_imm_nz
},
1301 { "c.fld", rv_codec_cl_ld
, rv_fmt_frd_offset_rs1
, NULL
, rv_op_fld
,
1303 { "c.lw", rv_codec_cl_lw
, rv_fmt_rd_offset_rs1
, NULL
, rv_op_lw
, rv_op_lw
,
1305 { "c.flw", rv_codec_cl_lw
, rv_fmt_frd_offset_rs1
, NULL
, rv_op_flw
, 0, 0 },
1306 { "c.fsd", rv_codec_cs_sd
, rv_fmt_frs2_offset_rs1
, NULL
, rv_op_fsd
,
1308 { "c.sw", rv_codec_cs_sw
, rv_fmt_rs2_offset_rs1
, NULL
, rv_op_sw
, rv_op_sw
,
1310 { "c.fsw", rv_codec_cs_sw
, rv_fmt_frs2_offset_rs1
, NULL
, rv_op_fsw
, 0, 0 },
1311 { "c.nop", rv_codec_ci_none
, rv_fmt_none
, NULL
, rv_op_addi
, rv_op_addi
,
1313 { "c.addi", rv_codec_ci
, rv_fmt_rd_rs1_imm
, NULL
, rv_op_addi
, rv_op_addi
,
1314 rv_op_addi
, rvcd_imm_nz
},
1315 { "c.jal", rv_codec_cj_jal
, rv_fmt_rd_offset
, NULL
, rv_op_jal
, 0, 0 },
1316 { "c.li", rv_codec_ci_li
, rv_fmt_rd_rs1_imm
, NULL
, rv_op_addi
, rv_op_addi
,
1318 { "c.addi16sp", rv_codec_ci_16sp
, rv_fmt_rd_rs1_imm
, NULL
, rv_op_addi
,
1319 rv_op_addi
, rv_op_addi
, rvcd_imm_nz
},
1320 { "c.lui", rv_codec_ci_lui
, rv_fmt_rd_imm
, NULL
, rv_op_lui
, rv_op_lui
,
1321 rv_op_lui
, rvcd_imm_nz
},
1322 { "c.srli", rv_codec_cb_sh6
, rv_fmt_rd_rs1_imm
, NULL
, rv_op_srli
,
1323 rv_op_srli
, rv_op_srli
, rvcd_imm_nz
},
1324 { "c.srai", rv_codec_cb_sh6
, rv_fmt_rd_rs1_imm
, NULL
, rv_op_srai
,
1325 rv_op_srai
, rv_op_srai
, rvcd_imm_nz
},
1326 { "c.andi", rv_codec_cb_imm
, rv_fmt_rd_rs1_imm
, NULL
, rv_op_andi
,
1327 rv_op_andi
, rv_op_andi
},
1328 { "c.sub", rv_codec_cs
, rv_fmt_rd_rs1_rs2
, NULL
, rv_op_sub
, rv_op_sub
,
1330 { "c.xor", rv_codec_cs
, rv_fmt_rd_rs1_rs2
, NULL
, rv_op_xor
, rv_op_xor
,
1332 { "c.or", rv_codec_cs
, rv_fmt_rd_rs1_rs2
, NULL
, rv_op_or
, rv_op_or
,
1334 { "c.and", rv_codec_cs
, rv_fmt_rd_rs1_rs2
, NULL
, rv_op_and
, rv_op_and
,
1336 { "c.subw", rv_codec_cs
, rv_fmt_rd_rs1_rs2
, NULL
, rv_op_subw
, rv_op_subw
,
1338 { "c.addw", rv_codec_cs
, rv_fmt_rd_rs1_rs2
, NULL
, rv_op_addw
, rv_op_addw
,
1340 { "c.j", rv_codec_cj
, rv_fmt_rd_offset
, NULL
, rv_op_jal
, rv_op_jal
,
1342 { "c.beqz", rv_codec_cb
, rv_fmt_rs1_rs2_offset
, NULL
, rv_op_beq
, rv_op_beq
,
1344 { "c.bnez", rv_codec_cb
, rv_fmt_rs1_rs2_offset
, NULL
, rv_op_bne
, rv_op_bne
,
1346 { "c.slli", rv_codec_ci_sh6
, rv_fmt_rd_rs1_imm
, NULL
, rv_op_slli
,
1347 rv_op_slli
, rv_op_slli
, rvcd_imm_nz
},
1348 { "c.fldsp", rv_codec_ci_ldsp
, rv_fmt_frd_offset_rs1
, NULL
, rv_op_fld
,
1349 rv_op_fld
, rv_op_fld
},
1350 { "c.lwsp", rv_codec_ci_lwsp
, rv_fmt_rd_offset_rs1
, NULL
, rv_op_lw
,
1351 rv_op_lw
, rv_op_lw
},
1352 { "c.flwsp", rv_codec_ci_lwsp
, rv_fmt_frd_offset_rs1
, NULL
, rv_op_flw
, 0,
1354 { "c.jr", rv_codec_cr_jr
, rv_fmt_rd_rs1_offset
, NULL
, rv_op_jalr
,
1355 rv_op_jalr
, rv_op_jalr
},
1356 { "c.mv", rv_codec_cr_mv
, rv_fmt_rd_rs1_rs2
, NULL
, rv_op_addi
, rv_op_addi
,
1358 { "c.ebreak", rv_codec_ci_none
, rv_fmt_none
, NULL
, rv_op_ebreak
,
1359 rv_op_ebreak
, rv_op_ebreak
},
1360 { "c.jalr", rv_codec_cr_jalr
, rv_fmt_rd_rs1_offset
, NULL
, rv_op_jalr
,
1361 rv_op_jalr
, rv_op_jalr
},
1362 { "c.add", rv_codec_cr
, rv_fmt_rd_rs1_rs2
, NULL
, rv_op_add
, rv_op_add
,
1364 { "c.fsdsp", rv_codec_css_sdsp
, rv_fmt_frs2_offset_rs1
, NULL
, rv_op_fsd
,
1365 rv_op_fsd
, rv_op_fsd
},
1366 { "c.swsp", rv_codec_css_swsp
, rv_fmt_rs2_offset_rs1
, NULL
, rv_op_sw
,
1367 rv_op_sw
, rv_op_sw
},
1368 { "c.fswsp", rv_codec_css_swsp
, rv_fmt_frs2_offset_rs1
, NULL
, rv_op_fsw
, 0,
1370 { "c.ld", rv_codec_cl_ld
, rv_fmt_rd_offset_rs1
, NULL
, 0, rv_op_ld
,
1372 { "c.sd", rv_codec_cs_sd
, rv_fmt_rs2_offset_rs1
, NULL
, 0, rv_op_sd
,
1374 { "c.addiw", rv_codec_ci
, rv_fmt_rd_rs1_imm
, NULL
, 0, rv_op_addiw
,
1376 { "c.ldsp", rv_codec_ci_ldsp
, rv_fmt_rd_offset_rs1
, NULL
, 0, rv_op_ld
,
1378 { "c.sdsp", rv_codec_css_sdsp
, rv_fmt_rs2_offset_rs1
, NULL
, 0, rv_op_sd
,
1380 { "c.lq", rv_codec_cl_lq
, rv_fmt_rd_offset_rs1
, NULL
, 0, 0, rv_op_lq
},
1381 { "c.sq", rv_codec_cs_sq
, rv_fmt_rs2_offset_rs1
, NULL
, 0, 0, rv_op_sq
},
1382 { "c.lqsp", rv_codec_ci_lqsp
, rv_fmt_rd_offset_rs1
, NULL
, 0, 0, rv_op_lq
},
1383 { "c.sqsp", rv_codec_css_sqsp
, rv_fmt_rs2_offset_rs1
, NULL
, 0, 0,
1385 { "nop", rv_codec_i
, rv_fmt_none
, NULL
, 0, 0, 0 },
1386 { "mv", rv_codec_i
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1387 { "not", rv_codec_i
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1388 { "neg", rv_codec_r
, rv_fmt_rd_rs2
, NULL
, 0, 0, 0 },
1389 { "negw", rv_codec_r
, rv_fmt_rd_rs2
, NULL
, 0, 0, 0 },
1390 { "sext.w", rv_codec_i
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1391 { "seqz", rv_codec_i
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1392 { "snez", rv_codec_r
, rv_fmt_rd_rs2
, NULL
, 0, 0, 0 },
1393 { "sltz", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1394 { "sgtz", rv_codec_r
, rv_fmt_rd_rs2
, NULL
, 0, 0, 0 },
1395 { "fmv.s", rv_codec_r
, rv_fmt_frd_frs1
, NULL
, 0, 0, 0 },
1396 { "fabs.s", rv_codec_r
, rv_fmt_frd_frs1
, NULL
, 0, 0, 0 },
1397 { "fneg.s", rv_codec_r
, rv_fmt_frd_frs1
, NULL
, 0, 0, 0 },
1398 { "fmv.d", rv_codec_r
, rv_fmt_frd_frs1
, NULL
, 0, 0, 0 },
1399 { "fabs.d", rv_codec_r
, rv_fmt_frd_frs1
, NULL
, 0, 0, 0 },
1400 { "fneg.d", rv_codec_r
, rv_fmt_frd_frs1
, NULL
, 0, 0, 0 },
1401 { "fmv.q", rv_codec_r
, rv_fmt_frd_frs1
, NULL
, 0, 0, 0 },
1402 { "fabs.q", rv_codec_r
, rv_fmt_frd_frs1
, NULL
, 0, 0, 0 },
1403 { "fneg.q", rv_codec_r
, rv_fmt_frd_frs1
, NULL
, 0, 0, 0 },
1404 { "beqz", rv_codec_sb
, rv_fmt_rs1_offset
, NULL
, 0, 0, 0 },
1405 { "bnez", rv_codec_sb
, rv_fmt_rs1_offset
, NULL
, 0, 0, 0 },
1406 { "blez", rv_codec_sb
, rv_fmt_rs2_offset
, NULL
, 0, 0, 0 },
1407 { "bgez", rv_codec_sb
, rv_fmt_rs1_offset
, NULL
, 0, 0, 0 },
1408 { "bltz", rv_codec_sb
, rv_fmt_rs1_offset
, NULL
, 0, 0, 0 },
1409 { "bgtz", rv_codec_sb
, rv_fmt_rs2_offset
, NULL
, 0, 0, 0 },
1410 { "ble", rv_codec_sb
, rv_fmt_rs2_rs1_offset
, NULL
, 0, 0, 0 },
1411 { "bleu", rv_codec_sb
, rv_fmt_rs2_rs1_offset
, NULL
, 0, 0, 0 },
1412 { "bgt", rv_codec_sb
, rv_fmt_rs2_rs1_offset
, NULL
, 0, 0, 0 },
1413 { "bgtu", rv_codec_sb
, rv_fmt_rs2_rs1_offset
, NULL
, 0, 0, 0 },
1414 { "j", rv_codec_uj
, rv_fmt_offset
, NULL
, 0, 0, 0 },
1415 { "ret", rv_codec_i
, rv_fmt_none
, NULL
, 0, 0, 0 },
1416 { "jr", rv_codec_i
, rv_fmt_rs1
, NULL
, 0, 0, 0 },
1417 { "rdcycle", rv_codec_i_csr
, rv_fmt_rd
, NULL
, 0, 0, 0 },
1418 { "rdtime", rv_codec_i_csr
, rv_fmt_rd
, NULL
, 0, 0, 0 },
1419 { "rdinstret", rv_codec_i_csr
, rv_fmt_rd
, NULL
, 0, 0, 0 },
1420 { "rdcycleh", rv_codec_i_csr
, rv_fmt_rd
, NULL
, 0, 0, 0 },
1421 { "rdtimeh", rv_codec_i_csr
, rv_fmt_rd
, NULL
, 0, 0, 0 },
1422 { "rdinstreth", rv_codec_i_csr
, rv_fmt_rd
, NULL
, 0, 0, 0 },
1423 { "frcsr", rv_codec_i_csr
, rv_fmt_rd
, NULL
, 0, 0, 0 },
1424 { "frrm", rv_codec_i_csr
, rv_fmt_rd
, NULL
, 0, 0, 0 },
1425 { "frflags", rv_codec_i_csr
, rv_fmt_rd
, NULL
, 0, 0, 0 },
1426 { "fscsr", rv_codec_i_csr
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1427 { "fsrm", rv_codec_i_csr
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1428 { "fsflags", rv_codec_i_csr
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1429 { "fsrmi", rv_codec_i_csr
, rv_fmt_rd_zimm
, NULL
, 0, 0, 0 },
1430 { "fsflagsi", rv_codec_i_csr
, rv_fmt_rd_zimm
, NULL
, 0, 0, 0 },
1431 { "bseti", rv_codec_i_sh7
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1432 { "bclri", rv_codec_i_sh7
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1433 { "binvi", rv_codec_i_sh7
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1434 { "bexti", rv_codec_i_sh7
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1435 { "rori", rv_codec_i_sh7
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1436 { "clz", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1437 { "ctz", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1438 { "cpop", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1439 { "sext.h", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1440 { "sext.b", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1441 { "xnor", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1442 { "orn", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1443 { "andn", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1444 { "rol", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1445 { "ror", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1446 { "sh1add", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1447 { "sh2add", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1448 { "sh3add", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1449 { "sh1add.uw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1450 { "sh2add.uw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1451 { "sh3add.uw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1452 { "clmul", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1453 { "clmulr", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1454 { "clmulh", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1455 { "min", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1456 { "minu", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1457 { "max", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1458 { "maxu", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1459 { "clzw", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1460 { "ctzw", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1461 { "cpopw", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1462 { "slli.uw", rv_codec_i_sh6
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1463 { "add.uw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1464 { "rolw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1465 { "rorw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1466 { "rev8", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1467 { "zext.h", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1468 { "roriw", rv_codec_i_sh5
, rv_fmt_rd_rs1_imm
, NULL
, 0, 0, 0 },
1469 { "orc.b", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1470 { "bset", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1471 { "bclr", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1472 { "binv", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1473 { "bext", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1474 { "aes32esmi", rv_codec_k_bs
, rv_fmt_rs1_rs2_bs
, NULL
, 0, 0, 0 },
1475 { "aes32esi", rv_codec_k_bs
, rv_fmt_rs1_rs2_bs
, NULL
, 0, 0, 0 },
1476 { "aes32dsmi", rv_codec_k_bs
, rv_fmt_rs1_rs2_bs
, NULL
, 0, 0, 0 },
1477 { "aes32dsi", rv_codec_k_bs
, rv_fmt_rs1_rs2_bs
, NULL
, 0, 0, 0 },
1478 { "aes64ks1i", rv_codec_k_rnum
, rv_fmt_rd_rs1_rnum
, NULL
, 0, 0, 0 },
1479 { "aes64ks2", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1480 { "aes64im", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0 },
1481 { "aes64esm", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1482 { "aes64es", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1483 { "aes64dsm", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1484 { "aes64ds", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1485 { "sha256sig0", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0 },
1486 { "sha256sig1", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0 },
1487 { "sha256sum0", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0 },
1488 { "sha256sum1", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0 },
1489 { "sha512sig0", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1490 { "sha512sig1", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1491 { "sha512sum0", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1492 { "sha512sum1", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1493 { "sha512sum0r", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1494 { "sha512sum1r", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1495 { "sha512sig0l", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1496 { "sha512sig0h", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1497 { "sha512sig1l", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1498 { "sha512sig1h", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1499 { "sm3p0", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0 },
1500 { "sm3p1", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0 },
1501 { "sm4ed", rv_codec_k_bs
, rv_fmt_rs1_rs2_bs
, NULL
, 0, 0, 0 },
1502 { "sm4ks", rv_codec_k_bs
, rv_fmt_rs1_rs2_bs
, NULL
, 0, 0, 0 },
1503 { "brev8", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1504 { "pack", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1505 { "packh", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1506 { "packw", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1507 { "unzip", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1508 { "zip", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1509 { "xperm4", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1510 { "xperm8", rv_codec_r
, rv_fmt_rd_rs1
, NULL
, 0, 0, 0 },
1511 { "vle8.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1512 { "vle16.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1513 { "vle32.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1514 { "vle64.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1515 { "vse8.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1516 { "vse16.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1517 { "vse32.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1518 { "vse64.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1519 { "vlm.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1520 { "vsm.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1521 { "vlse8.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_rs2_vm
, NULL
, 0, 0, 0 },
1522 { "vlse16.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_rs2_vm
, NULL
, 0, 0, 0 },
1523 { "vlse32.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_rs2_vm
, NULL
, 0, 0, 0 },
1524 { "vlse64.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_rs2_vm
, NULL
, 0, 0, 0 },
1525 { "vsse8.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_rs2_vm
, NULL
, 0, 0, 0 },
1526 { "vsse16.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_rs2_vm
, NULL
, 0, 0, 0 },
1527 { "vsse32.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_rs2_vm
, NULL
, 0, 0, 0 },
1528 { "vsse64.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_rs2_vm
, NULL
, 0, 0, 0 },
1529 { "vluxei8.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1530 { "vluxei16.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1531 { "vluxei32.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1532 { "vluxei64.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1533 { "vloxei8.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1534 { "vloxei16.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1535 { "vloxei32.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1536 { "vloxei64.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1537 { "vsuxei8.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1538 { "vsuxei16.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1539 { "vsuxei32.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1540 { "vsuxei64.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1541 { "vsoxei8.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1542 { "vsoxei16.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1543 { "vsoxei32.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1544 { "vsoxei64.v", rv_codec_v_r
, rv_fmt_ldst_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1545 { "vle8ff.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1546 { "vle16ff.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1547 { "vle32ff.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1548 { "vle64ff.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1549 { "vl1re8.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1550 { "vl1re16.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1551 { "vl1re32.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1552 { "vl1re64.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1553 { "vl2re8.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1554 { "vl2re16.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1555 { "vl2re32.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1556 { "vl2re64.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1557 { "vl4re8.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1558 { "vl4re16.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1559 { "vl4re32.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1560 { "vl4re64.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1561 { "vl8re8.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1562 { "vl8re16.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1563 { "vl8re32.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1564 { "vl8re64.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1565 { "vs1r.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1566 { "vs2r.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1567 { "vs4r.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1568 { "vs8r.v", rv_codec_v_ldst
, rv_fmt_ldst_vd_rs1_vm
, NULL
, 0, 0, 0 },
1569 { "vadd.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1570 { "vadd.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1571 { "vadd.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1572 { "vsub.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1573 { "vsub.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1574 { "vrsub.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1575 { "vrsub.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1576 { "vwaddu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1577 { "vwaddu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1578 { "vwadd.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1579 { "vwadd.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1580 { "vwsubu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1581 { "vwsubu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1582 { "vwsub.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1583 { "vwsub.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1584 { "vwaddu.wv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1585 { "vwaddu.wx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1586 { "vwadd.wv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1587 { "vwadd.wx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1588 { "vwsubu.wv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1589 { "vwsubu.wx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1590 { "vwsub.wv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1591 { "vwsub.wx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1592 { "vadc.vvm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vl
, NULL
, 0, 0, 0 },
1593 { "vadc.vxm", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vl
, NULL
, 0, 0, 0 },
1594 { "vadc.vim", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vl
, NULL
, 0, 0, 0 },
1595 { "vmadc.vvm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vl
, NULL
, 0, 0, 0 },
1596 { "vmadc.vxm", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vl
, NULL
, 0, 0, 0 },
1597 { "vmadc.vim", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vl
, NULL
, 0, 0, 0 },
1598 { "vsbc.vvm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vl
, NULL
, 0, 0, 0 },
1599 { "vsbc.vxm", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vl
, NULL
, 0, 0, 0 },
1600 { "vmsbc.vvm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vl
, NULL
, 0, 0, 0 },
1601 { "vmsbc.vxm", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vl
, NULL
, 0, 0, 0 },
1602 { "vand.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1603 { "vand.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1604 { "vand.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1605 { "vor.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1606 { "vor.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1607 { "vor.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1608 { "vxor.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1609 { "vxor.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1610 { "vxor.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1611 { "vsll.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1612 { "vsll.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1613 { "vsll.vi", rv_codec_v_i
, rv_fmt_vd_vs2_uimm_vm
, NULL
, 0, 0, 0 },
1614 { "vsrl.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1615 { "vsrl.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1616 { "vsrl.vi", rv_codec_v_i
, rv_fmt_vd_vs2_uimm_vm
, NULL
, 0, 0, 0 },
1617 { "vsra.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1618 { "vsra.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1619 { "vsra.vi", rv_codec_v_i
, rv_fmt_vd_vs2_uimm_vm
, NULL
, 0, 0, 0 },
1620 { "vnsrl.wv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1621 { "vnsrl.wx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1622 { "vnsrl.wi", rv_codec_v_i
, rv_fmt_vd_vs2_uimm_vm
, NULL
, 0, 0, 0 },
1623 { "vnsra.wv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1624 { "vnsra.wx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1625 { "vnsra.wi", rv_codec_v_i
, rv_fmt_vd_vs2_uimm_vm
, NULL
, 0, 0, 0 },
1626 { "vmseq.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1627 { "vmseq.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1628 { "vmseq.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1629 { "vmsne.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1630 { "vmsne.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1631 { "vmsne.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1632 { "vmsltu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1633 { "vmsltu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1634 { "vmslt.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1635 { "vmslt.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1636 { "vmsleu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1637 { "vmsleu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1638 { "vmsleu.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1639 { "vmsle.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1640 { "vmsle.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1641 { "vmsle.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1642 { "vmsgtu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1643 { "vmsgtu.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1644 { "vmsgt.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1645 { "vmsgt.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1646 { "vminu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1647 { "vminu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1648 { "vmin.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1649 { "vmin.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1650 { "vmaxu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1651 { "vmaxu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1652 { "vmax.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1653 { "vmax.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1654 { "vmul.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1655 { "vmul.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1656 { "vmulh.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1657 { "vmulh.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1658 { "vmulhu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1659 { "vmulhu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1660 { "vmulhsu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1661 { "vmulhsu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1662 { "vdivu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1663 { "vdivu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1664 { "vdiv.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1665 { "vdiv.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1666 { "vremu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1667 { "vremu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1668 { "vrem.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1669 { "vrem.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1670 { "vwmulu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1671 { "vwmulu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1672 { "vwmulsu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1673 { "vwmulsu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1674 { "vwmul.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1675 { "vwmul.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1676 { "vmacc.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1677 { "vmacc.vx", rv_codec_v_r
, rv_fmt_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1678 { "vnmsac.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1679 { "vnmsac.vx", rv_codec_v_r
, rv_fmt_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1680 { "vmadd.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1681 { "vmadd.vx", rv_codec_v_r
, rv_fmt_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1682 { "vnmsub.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1683 { "vnmsub.vx", rv_codec_v_r
, rv_fmt_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1684 { "vwmaccu.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1685 { "vwmaccu.vx", rv_codec_v_r
, rv_fmt_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1686 { "vwmacc.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1687 { "vwmacc.vx", rv_codec_v_r
, rv_fmt_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1688 { "vwmaccsu.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1689 { "vwmaccsu.vx", rv_codec_v_r
, rv_fmt_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1690 { "vwmaccus.vx", rv_codec_v_r
, rv_fmt_vd_rs1_vs2_vm
, NULL
, 0, 0, 0 },
1691 { "vmv.v.v", rv_codec_v_r
, rv_fmt_vd_vs1
, NULL
, 0, 0, 0 },
1692 { "vmv.v.x", rv_codec_v_r
, rv_fmt_vd_rs1
, NULL
, 0, 0, 0 },
1693 { "vmv.v.i", rv_codec_v_i
, rv_fmt_vd_imm
, NULL
, 0, 0, 0 },
1694 { "vmerge.vvm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vl
, NULL
, 0, 0, 0 },
1695 { "vmerge.vxm", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vl
, NULL
, 0, 0, 0 },
1696 { "vmerge.vim", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vl
, NULL
, 0, 0, 0 },
1697 { "vsaddu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1698 { "vsaddu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1699 { "vsaddu.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1700 { "vsadd.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1701 { "vsadd.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1702 { "vsadd.vi", rv_codec_v_i
, rv_fmt_vd_vs2_imm_vm
, NULL
, 0, 0, 0 },
1703 { "vssubu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1704 { "vssubu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1705 { "vssub.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1706 { "vssub.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1707 { "vaadd.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1708 { "vaadd.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1709 { "vaaddu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1710 { "vaaddu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1711 { "vasub.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1712 { "vasub.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1713 { "vasubu.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1714 { "vasubu.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1715 { "vsmul.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1716 { "vsmul.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1717 { "vssrl.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1718 { "vssrl.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1719 { "vssrl.vi", rv_codec_v_i
, rv_fmt_vd_vs2_uimm_vm
, NULL
, 0, 0, 0 },
1720 { "vssra.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1721 { "vssra.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1722 { "vssra.vi", rv_codec_v_i
, rv_fmt_vd_vs2_uimm_vm
, NULL
, 0, 0, 0 },
1723 { "vnclipu.wv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1724 { "vnclipu.wx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1725 { "vnclipu.wi", rv_codec_v_i
, rv_fmt_vd_vs2_uimm_vm
, NULL
, 0, 0, 0 },
1726 { "vnclip.wv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1727 { "vnclip.wx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1728 { "vnclip.wi", rv_codec_v_i
, rv_fmt_vd_vs2_uimm_vm
, NULL
, 0, 0, 0 },
1729 { "vfadd.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1730 { "vfadd.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1731 { "vfsub.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1732 { "vfsub.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1733 { "vfrsub.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1734 { "vfwadd.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1735 { "vfwadd.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1736 { "vfwadd.wv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1737 { "vfwadd.wf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1738 { "vfwsub.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1739 { "vfwsub.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1740 { "vfwsub.wv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1741 { "vfwsub.wf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1742 { "vfmul.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1743 { "vfmul.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1744 { "vfdiv.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1745 { "vfdiv.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1746 { "vfrdiv.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1747 { "vfwmul.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1748 { "vfwmul.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1749 { "vfmacc.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1750 { "vfmacc.vf", rv_codec_v_r
, rv_fmt_vd_fs1_vs2_vm
, NULL
, 0, 0, 0 },
1751 { "vfnmacc.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1752 { "vfnmacc.vf", rv_codec_v_r
, rv_fmt_vd_fs1_vs2_vm
, NULL
, 0, 0, 0 },
1753 { "vfmsac.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1754 { "vfmsac.vf", rv_codec_v_r
, rv_fmt_vd_fs1_vs2_vm
, NULL
, 0, 0, 0 },
1755 { "vfnmsac.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1756 { "vfnmsac.vf", rv_codec_v_r
, rv_fmt_vd_fs1_vs2_vm
, NULL
, 0, 0, 0 },
1757 { "vfmadd.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1758 { "vfmadd.vf", rv_codec_v_r
, rv_fmt_vd_fs1_vs2_vm
, NULL
, 0, 0, 0 },
1759 { "vfnmadd.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1760 { "vfnmadd.vf", rv_codec_v_r
, rv_fmt_vd_fs1_vs2_vm
, NULL
, 0, 0, 0 },
1761 { "vfmsub.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1762 { "vfmsub.vf", rv_codec_v_r
, rv_fmt_vd_fs1_vs2_vm
, NULL
, 0, 0, 0 },
1763 { "vfnmsub.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1764 { "vfnmsub.vf", rv_codec_v_r
, rv_fmt_vd_fs1_vs2_vm
, NULL
, 0, 0, 0 },
1765 { "vfwmacc.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1766 { "vfwmacc.vf", rv_codec_v_r
, rv_fmt_vd_fs1_vs2_vm
, NULL
, 0, 0, 0 },
1767 { "vfwnmacc.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1768 { "vfwnmacc.vf", rv_codec_v_r
, rv_fmt_vd_fs1_vs2_vm
, NULL
, 0, 0, 0 },
1769 { "vfwmsac.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1770 { "vfwmsac.vf", rv_codec_v_r
, rv_fmt_vd_fs1_vs2_vm
, NULL
, 0, 0, 0 },
1771 { "vfwnmsac.vv", rv_codec_v_r
, rv_fmt_vd_vs1_vs2_vm
, NULL
, 0, 0, 0 },
1772 { "vfwnmsac.vf", rv_codec_v_r
, rv_fmt_vd_fs1_vs2_vm
, NULL
, 0, 0, 0 },
1773 { "vfsqrt.v", rv_codec_v_r
, rv_fmt_vd_vs2
, NULL
, 0, 0, 0 },
1774 { "vfrsqrt7.v", rv_codec_v_r
, rv_fmt_vd_vs2
, NULL
, 0, 0, 0 },
1775 { "vfrec7.v", rv_codec_v_r
, rv_fmt_vd_vs2
, NULL
, 0, 0, 0 },
1776 { "vfmin.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1777 { "vfmin.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1778 { "vfmax.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1779 { "vfmax.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1780 { "vfsgnj.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1781 { "vfsgnj.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1782 { "vfsgnjn.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1783 { "vfsgnjn.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1784 { "vfsgnjx.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1785 { "vfsgnjx.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1786 { "vfslide1up.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1787 { "vfslide1down.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1788 { "vmfeq.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1789 { "vmfeq.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1790 { "vmfne.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1791 { "vmfne.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1792 { "vmflt.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1793 { "vmflt.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1794 { "vmfle.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1795 { "vmfle.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1796 { "vmfgt.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1797 { "vmfge.vf", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vm
, NULL
, 0, 0, 0 },
1798 { "vfclass.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1799 { "vfmerge.vfm", rv_codec_v_r
, rv_fmt_vd_vs2_fs1_vl
, NULL
, 0, 0, 0 },
1800 { "vfmv.v.f", rv_codec_v_r
, rv_fmt_vd_fs1
, NULL
, 0, 0, 0 },
1801 { "vfcvt.xu.f.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1802 { "vfcvt.x.f.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1803 { "vfcvt.f.xu.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1804 { "vfcvt.f.x.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1805 { "vfcvt.rtz.xu.f.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1806 { "vfcvt.rtz.x.f.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1807 { "vfwcvt.xu.f.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1808 { "vfwcvt.x.f.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1809 { "vfwcvt.f.xu.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1810 { "vfwcvt.f.x.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1811 { "vfwcvt.f.f.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1812 { "vfwcvt.rtz.xu.f.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1813 { "vfwcvt.rtz.x.f.v", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1814 { "vfncvt.xu.f.w", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1815 { "vfncvt.x.f.w", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1816 { "vfncvt.f.xu.w", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1817 { "vfncvt.f.x.w", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1818 { "vfncvt.f.f.w", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1819 { "vfncvt.rod.f.f.w", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1820 { "vfncvt.rtz.xu.f.w", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1821 { "vfncvt.rtz.x.f.w", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1822 { "vredsum.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1823 { "vredand.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1824 { "vredor.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1825 { "vredxor.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1826 { "vredminu.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1827 { "vredmin.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1828 { "vredmaxu.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1829 { "vredmax.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1830 { "vwredsumu.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1831 { "vwredsum.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1832 { "vfredusum.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1833 { "vfredosum.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1834 { "vfredmin.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1835 { "vfredmax.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1836 { "vfwredusum.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1837 { "vfwredosum.vs", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1838 { "vmand.mm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1839 { "vmnand.mm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1840 { "vmandn.mm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1841 { "vmxor.mm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1842 { "vmor.mm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1843 { "vmnor.mm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1844 { "vmorn.mm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1845 { "vmxnor.mm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1846 { "vcpop.m", rv_codec_v_r
, rv_fmt_rd_vs2_vm
, NULL
, 0, 0, 0 },
1847 { "vfirst.m", rv_codec_v_r
, rv_fmt_rd_vs2_vm
, NULL
, 0, 0, 0 },
1848 { "vmsbf.m", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1849 { "vmsif.m", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1850 { "vmsof.m", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1851 { "viota.m", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1852 { "vid.v", rv_codec_v_r
, rv_fmt_vd_vm
, NULL
, 0, 0, 0 },
1853 { "vmv.x.s", rv_codec_v_r
, rv_fmt_rd_vs2
, NULL
, 0, 0, 0 },
1854 { "vmv.s.x", rv_codec_v_r
, rv_fmt_vd_rs1
, NULL
, 0, 0, 0 },
1855 { "vfmv.f.s", rv_codec_v_r
, rv_fmt_fd_vs2
, NULL
, 0, 0, 0 },
1856 { "vfmv.s.f", rv_codec_v_r
, rv_fmt_vd_fs1
, NULL
, 0, 0, 0 },
1857 { "vslideup.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1858 { "vslideup.vi", rv_codec_v_i
, rv_fmt_vd_vs2_uimm_vm
, NULL
, 0, 0, 0 },
1859 { "vslide1up.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1860 { "vslidedown.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1861 { "vslidedown.vi", rv_codec_v_i
, rv_fmt_vd_vs2_uimm_vm
, NULL
, 0, 0, 0 },
1862 { "vslide1down.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1863 { "vrgather.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1864 { "vrgatherei16.vv", rv_codec_v_r
, rv_fmt_vd_vs2_vs1_vm
, NULL
, 0, 0, 0 },
1865 { "vrgather.vx", rv_codec_v_r
, rv_fmt_vd_vs2_rs1_vm
, NULL
, 0, 0, 0 },
1866 { "vrgather.vi", rv_codec_v_i
, rv_fmt_vd_vs2_uimm_vm
, NULL
, 0, 0, 0 },
1867 { "vcompress.vm", rv_codec_v_r
, rv_fmt_vd_vs2_vs1
, NULL
, 0, 0, 0 },
1868 { "vmv1r.v", rv_codec_v_r
, rv_fmt_vd_vs2
, NULL
, 0, 0, 0 },
1869 { "vmv2r.v", rv_codec_v_r
, rv_fmt_vd_vs2
, NULL
, 0, 0, 0 },
1870 { "vmv4r.v", rv_codec_v_r
, rv_fmt_vd_vs2
, NULL
, 0, 0, 0 },
1871 { "vmv8r.v", rv_codec_v_r
, rv_fmt_vd_vs2
, NULL
, 0, 0, 0 },
1872 { "vzext.vf2", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1873 { "vzext.vf4", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1874 { "vzext.vf8", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1875 { "vsext.vf2", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1876 { "vsext.vf4", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1877 { "vsext.vf8", rv_codec_v_r
, rv_fmt_vd_vs2_vm
, NULL
, 0, 0, 0 },
1878 { "vsetvli", rv_codec_vsetvli
, rv_fmt_vsetvli
, NULL
, 0, 0, 0 },
1879 { "vsetivli", rv_codec_vsetivli
, rv_fmt_vsetivli
, NULL
, 0, 0, 0 },
1880 { "vsetvl", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1881 { "c.zext.b", rv_codec_zcb_ext
, rv_fmt_rd
, NULL
, 0 },
1882 { "c.sext.b", rv_codec_zcb_ext
, rv_fmt_rd
, NULL
, 0 },
1883 { "c.zext.h", rv_codec_zcb_ext
, rv_fmt_rd
, NULL
, 0 },
1884 { "c.sext.h", rv_codec_zcb_ext
, rv_fmt_rd
, NULL
, 0 },
1885 { "c.zext.w", rv_codec_zcb_ext
, rv_fmt_rd
, NULL
, 0 },
1886 { "c.not", rv_codec_zcb_ext
, rv_fmt_rd
, NULL
, 0 },
1887 { "c.mul", rv_codec_zcb_mul
, rv_fmt_rd_rs2
, NULL
, 0, 0 },
1888 { "c.lbu", rv_codec_zcb_lb
, rv_fmt_rs1_rs2_zce_ldst
, NULL
, 0, 0, 0 },
1889 { "c.lhu", rv_codec_zcb_lh
, rv_fmt_rs1_rs2_zce_ldst
, NULL
, 0, 0, 0 },
1890 { "c.lh", rv_codec_zcb_lh
, rv_fmt_rs1_rs2_zce_ldst
, NULL
, 0, 0, 0 },
1891 { "c.sb", rv_codec_zcb_lb
, rv_fmt_rs1_rs2_zce_ldst
, NULL
, 0, 0, 0 },
1892 { "c.sh", rv_codec_zcb_lh
, rv_fmt_rs1_rs2_zce_ldst
, NULL
, 0, 0, 0 },
1893 { "cm.push", rv_codec_zcmp_cm_pushpop
, rv_fmt_push_rlist
, NULL
, 0, 0 },
1894 { "cm.pop", rv_codec_zcmp_cm_pushpop
, rv_fmt_pop_rlist
, NULL
, 0, 0 },
1895 { "cm.popret", rv_codec_zcmp_cm_pushpop
, rv_fmt_pop_rlist
, NULL
, 0, 0, 0 },
1896 { "cm.popretz", rv_codec_zcmp_cm_pushpop
, rv_fmt_pop_rlist
, NULL
, 0, 0 },
1897 { "cm.mva01s", rv_codec_zcmp_cm_mv
, rv_fmt_rd_rs2
, NULL
, 0, 0, 0 },
1898 { "cm.mvsa01", rv_codec_zcmp_cm_mv
, rv_fmt_rd_rs2
, NULL
, 0, 0, 0 },
1899 { "cm.jt", rv_codec_zcmt_jt
, rv_fmt_zcmt_index
, NULL
, 0 },
1900 { "cm.jalt", rv_codec_zcmt_jt
, rv_fmt_zcmt_index
, NULL
, 0 },
1901 { "czero.eqz", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1902 { "czero.nez", rv_codec_r
, rv_fmt_rd_rs1_rs2
, NULL
, 0, 0, 0 },
1907 static const char *csr_name(int csrno
)
1910 case 0x0000: return "ustatus";
1911 case 0x0001: return "fflags";
1912 case 0x0002: return "frm";
1913 case 0x0003: return "fcsr";
1914 case 0x0004: return "uie";
1915 case 0x0005: return "utvec";
1916 case 0x0008: return "vstart";
1917 case 0x0009: return "vxsat";
1918 case 0x000a: return "vxrm";
1919 case 0x000f: return "vcsr";
1920 case 0x0015: return "seed";
1921 case 0x0017: return "jvt";
1922 case 0x0040: return "uscratch";
1923 case 0x0041: return "uepc";
1924 case 0x0042: return "ucause";
1925 case 0x0043: return "utval";
1926 case 0x0044: return "uip";
1927 case 0x0100: return "sstatus";
1928 case 0x0104: return "sie";
1929 case 0x0105: return "stvec";
1930 case 0x0106: return "scounteren";
1931 case 0x0140: return "sscratch";
1932 case 0x0141: return "sepc";
1933 case 0x0142: return "scause";
1934 case 0x0143: return "stval";
1935 case 0x0144: return "sip";
1936 case 0x0180: return "satp";
1937 case 0x0200: return "hstatus";
1938 case 0x0202: return "hedeleg";
1939 case 0x0203: return "hideleg";
1940 case 0x0204: return "hie";
1941 case 0x0205: return "htvec";
1942 case 0x0240: return "hscratch";
1943 case 0x0241: return "hepc";
1944 case 0x0242: return "hcause";
1945 case 0x0243: return "hbadaddr";
1946 case 0x0244: return "hip";
1947 case 0x0300: return "mstatus";
1948 case 0x0301: return "misa";
1949 case 0x0302: return "medeleg";
1950 case 0x0303: return "mideleg";
1951 case 0x0304: return "mie";
1952 case 0x0305: return "mtvec";
1953 case 0x0306: return "mcounteren";
1954 case 0x0320: return "mucounteren";
1955 case 0x0321: return "mscounteren";
1956 case 0x0322: return "mhcounteren";
1957 case 0x0323: return "mhpmevent3";
1958 case 0x0324: return "mhpmevent4";
1959 case 0x0325: return "mhpmevent5";
1960 case 0x0326: return "mhpmevent6";
1961 case 0x0327: return "mhpmevent7";
1962 case 0x0328: return "mhpmevent8";
1963 case 0x0329: return "mhpmevent9";
1964 case 0x032a: return "mhpmevent10";
1965 case 0x032b: return "mhpmevent11";
1966 case 0x032c: return "mhpmevent12";
1967 case 0x032d: return "mhpmevent13";
1968 case 0x032e: return "mhpmevent14";
1969 case 0x032f: return "mhpmevent15";
1970 case 0x0330: return "mhpmevent16";
1971 case 0x0331: return "mhpmevent17";
1972 case 0x0332: return "mhpmevent18";
1973 case 0x0333: return "mhpmevent19";
1974 case 0x0334: return "mhpmevent20";
1975 case 0x0335: return "mhpmevent21";
1976 case 0x0336: return "mhpmevent22";
1977 case 0x0337: return "mhpmevent23";
1978 case 0x0338: return "mhpmevent24";
1979 case 0x0339: return "mhpmevent25";
1980 case 0x033a: return "mhpmevent26";
1981 case 0x033b: return "mhpmevent27";
1982 case 0x033c: return "mhpmevent28";
1983 case 0x033d: return "mhpmevent29";
1984 case 0x033e: return "mhpmevent30";
1985 case 0x033f: return "mhpmevent31";
1986 case 0x0340: return "mscratch";
1987 case 0x0341: return "mepc";
1988 case 0x0342: return "mcause";
1989 case 0x0343: return "mtval";
1990 case 0x0344: return "mip";
1991 case 0x0380: return "mbase";
1992 case 0x0381: return "mbound";
1993 case 0x0382: return "mibase";
1994 case 0x0383: return "mibound";
1995 case 0x0384: return "mdbase";
1996 case 0x0385: return "mdbound";
1997 case 0x03a0: return "pmpcfg3";
1998 case 0x03b0: return "pmpaddr0";
1999 case 0x03b1: return "pmpaddr1";
2000 case 0x03b2: return "pmpaddr2";
2001 case 0x03b3: return "pmpaddr3";
2002 case 0x03b4: return "pmpaddr4";
2003 case 0x03b5: return "pmpaddr5";
2004 case 0x03b6: return "pmpaddr6";
2005 case 0x03b7: return "pmpaddr7";
2006 case 0x03b8: return "pmpaddr8";
2007 case 0x03b9: return "pmpaddr9";
2008 case 0x03ba: return "pmpaddr10";
2009 case 0x03bb: return "pmpaddr11";
2010 case 0x03bc: return "pmpaddr12";
2011 case 0x03bd: return "pmpaddr14";
2012 case 0x03be: return "pmpaddr13";
2013 case 0x03bf: return "pmpaddr15";
2014 case 0x0780: return "mtohost";
2015 case 0x0781: return "mfromhost";
2016 case 0x0782: return "mreset";
2017 case 0x0783: return "mipi";
2018 case 0x0784: return "miobase";
2019 case 0x07a0: return "tselect";
2020 case 0x07a1: return "tdata1";
2021 case 0x07a2: return "tdata2";
2022 case 0x07a3: return "tdata3";
2023 case 0x07b0: return "dcsr";
2024 case 0x07b1: return "dpc";
2025 case 0x07b2: return "dscratch";
2026 case 0x0b00: return "mcycle";
2027 case 0x0b01: return "mtime";
2028 case 0x0b02: return "minstret";
2029 case 0x0b03: return "mhpmcounter3";
2030 case 0x0b04: return "mhpmcounter4";
2031 case 0x0b05: return "mhpmcounter5";
2032 case 0x0b06: return "mhpmcounter6";
2033 case 0x0b07: return "mhpmcounter7";
2034 case 0x0b08: return "mhpmcounter8";
2035 case 0x0b09: return "mhpmcounter9";
2036 case 0x0b0a: return "mhpmcounter10";
2037 case 0x0b0b: return "mhpmcounter11";
2038 case 0x0b0c: return "mhpmcounter12";
2039 case 0x0b0d: return "mhpmcounter13";
2040 case 0x0b0e: return "mhpmcounter14";
2041 case 0x0b0f: return "mhpmcounter15";
2042 case 0x0b10: return "mhpmcounter16";
2043 case 0x0b11: return "mhpmcounter17";
2044 case 0x0b12: return "mhpmcounter18";
2045 case 0x0b13: return "mhpmcounter19";
2046 case 0x0b14: return "mhpmcounter20";
2047 case 0x0b15: return "mhpmcounter21";
2048 case 0x0b16: return "mhpmcounter22";
2049 case 0x0b17: return "mhpmcounter23";
2050 case 0x0b18: return "mhpmcounter24";
2051 case 0x0b19: return "mhpmcounter25";
2052 case 0x0b1a: return "mhpmcounter26";
2053 case 0x0b1b: return "mhpmcounter27";
2054 case 0x0b1c: return "mhpmcounter28";
2055 case 0x0b1d: return "mhpmcounter29";
2056 case 0x0b1e: return "mhpmcounter30";
2057 case 0x0b1f: return "mhpmcounter31";
2058 case 0x0b80: return "mcycleh";
2059 case 0x0b81: return "mtimeh";
2060 case 0x0b82: return "minstreth";
2061 case 0x0b83: return "mhpmcounter3h";
2062 case 0x0b84: return "mhpmcounter4h";
2063 case 0x0b85: return "mhpmcounter5h";
2064 case 0x0b86: return "mhpmcounter6h";
2065 case 0x0b87: return "mhpmcounter7h";
2066 case 0x0b88: return "mhpmcounter8h";
2067 case 0x0b89: return "mhpmcounter9h";
2068 case 0x0b8a: return "mhpmcounter10h";
2069 case 0x0b8b: return "mhpmcounter11h";
2070 case 0x0b8c: return "mhpmcounter12h";
2071 case 0x0b8d: return "mhpmcounter13h";
2072 case 0x0b8e: return "mhpmcounter14h";
2073 case 0x0b8f: return "mhpmcounter15h";
2074 case 0x0b90: return "mhpmcounter16h";
2075 case 0x0b91: return "mhpmcounter17h";
2076 case 0x0b92: return "mhpmcounter18h";
2077 case 0x0b93: return "mhpmcounter19h";
2078 case 0x0b94: return "mhpmcounter20h";
2079 case 0x0b95: return "mhpmcounter21h";
2080 case 0x0b96: return "mhpmcounter22h";
2081 case 0x0b97: return "mhpmcounter23h";
2082 case 0x0b98: return "mhpmcounter24h";
2083 case 0x0b99: return "mhpmcounter25h";
2084 case 0x0b9a: return "mhpmcounter26h";
2085 case 0x0b9b: return "mhpmcounter27h";
2086 case 0x0b9c: return "mhpmcounter28h";
2087 case 0x0b9d: return "mhpmcounter29h";
2088 case 0x0b9e: return "mhpmcounter30h";
2089 case 0x0b9f: return "mhpmcounter31h";
2090 case 0x0c00: return "cycle";
2091 case 0x0c01: return "time";
2092 case 0x0c02: return "instret";
2093 case 0x0c20: return "vl";
2094 case 0x0c21: return "vtype";
2095 case 0x0c22: return "vlenb";
2096 case 0x0c80: return "cycleh";
2097 case 0x0c81: return "timeh";
2098 case 0x0c82: return "instreth";
2099 case 0x0d00: return "scycle";
2100 case 0x0d01: return "stime";
2101 case 0x0d02: return "sinstret";
2102 case 0x0d80: return "scycleh";
2103 case 0x0d81: return "stimeh";
2104 case 0x0d82: return "sinstreth";
2105 case 0x0e00: return "hcycle";
2106 case 0x0e01: return "htime";
2107 case 0x0e02: return "hinstret";
2108 case 0x0e80: return "hcycleh";
2109 case 0x0e81: return "htimeh";
2110 case 0x0e82: return "hinstreth";
2111 case 0x0f11: return "mvendorid";
2112 case 0x0f12: return "marchid";
2113 case 0x0f13: return "mimpid";
2114 case 0x0f14: return "mhartid";
2115 default: return NULL
;
2121 static void decode_inst_opcode(rv_decode
*dec
, rv_isa isa
)
2123 rv_inst inst
= dec
->inst
;
2124 rv_opcode op
= rv_op_illegal
;
2125 switch ((inst
>> 0) & 0b11) {
2127 switch ((inst
>> 13) & 0b111) {
2128 case 0: op
= rv_op_c_addi4spn
; break;
2136 case 2: op
= rv_op_c_lw
; break;
2145 switch ((inst
>> 10) & 0b111) {
2146 case 0: op
= rv_op_c_lbu
; break;
2148 if (((inst
>> 6) & 1) == 0) {
2154 case 2: op
= rv_op_c_sb
; break;
2156 if (((inst
>> 6) & 1) == 0) {
2169 case 6: op
= rv_op_c_sw
; break;
2180 switch ((inst
>> 13) & 0b111) {
2182 switch ((inst
>> 2) & 0b11111111111) {
2183 case 0: op
= rv_op_c_nop
; break;
2184 default: op
= rv_op_c_addi
; break;
2194 case 2: op
= rv_op_c_li
; break;
2196 switch ((inst
>> 7) & 0b11111) {
2197 case 2: op
= rv_op_c_addi16sp
; break;
2198 default: op
= rv_op_c_lui
; break;
2202 switch ((inst
>> 10) & 0b11) {
2209 case 2: op
= rv_op_c_andi
; break;
2211 switch (((inst
>> 10) & 0b100) | ((inst
>> 5) & 0b011)) {
2212 case 0: op
= rv_op_c_sub
; break;
2213 case 1: op
= rv_op_c_xor
; break;
2214 case 2: op
= rv_op_c_or
; break;
2215 case 3: op
= rv_op_c_and
; break;
2216 case 4: op
= rv_op_c_subw
; break;
2217 case 5: op
= rv_op_c_addw
; break;
2218 case 6: op
= rv_op_c_mul
; break;
2220 switch ((inst
>> 2) & 0b111) {
2221 case 0: op
= rv_op_c_zext_b
; break;
2222 case 1: op
= rv_op_c_sext_b
; break;
2223 case 2: op
= rv_op_c_zext_h
; break;
2224 case 3: op
= rv_op_c_sext_h
; break;
2225 case 4: op
= rv_op_c_zext_w
; break;
2226 case 5: op
= rv_op_c_not
; break;
2233 case 5: op
= rv_op_c_j
; break;
2234 case 6: op
= rv_op_c_beqz
; break;
2235 case 7: op
= rv_op_c_bnez
; break;
2239 switch ((inst
>> 13) & 0b111) {
2250 case 2: op
= rv_op_c_lwsp
; break;
2259 switch ((inst
>> 12) & 0b1) {
2261 switch ((inst
>> 2) & 0b11111) {
2262 case 0: op
= rv_op_c_jr
; break;
2263 default: op
= rv_op_c_mv
; break;
2267 switch ((inst
>> 2) & 0b11111) {
2269 switch ((inst
>> 7) & 0b11111) {
2270 case 0: op
= rv_op_c_ebreak
; break;
2271 default: op
= rv_op_c_jalr
; break;
2274 default: op
= rv_op_c_add
; break;
2284 if (dec
->cfg
->ext_zcmp
&& ((inst
>> 12) & 0b01)) {
2285 switch ((inst
>> 8) & 0b01111) {
2287 if (((inst
>> 4) & 0b01111) >= 4) {
2292 if (((inst
>> 4) & 0b01111) >= 4) {
2297 if (((inst
>> 4) & 0b01111) >= 4) {
2298 op
= rv_op_cm_popretz
;
2302 if (((inst
>> 4) & 0b01111) >= 4) {
2303 op
= rv_op_cm_popret
;
2308 switch ((inst
>> 10) & 0b011) {
2310 if (!dec
->cfg
->ext_zcmt
) {
2313 if (((inst
>> 2) & 0xFF) >= 32) {
2320 if (!dec
->cfg
->ext_zcmp
) {
2323 switch ((inst
>> 5) & 0b011) {
2324 case 1: op
= rv_op_cm_mvsa01
; break;
2325 case 3: op
= rv_op_cm_mva01s
; break;
2332 case 6: op
= rv_op_c_swsp
; break;
2343 switch ((inst
>> 2) & 0b11111) {
2345 switch ((inst
>> 12) & 0b111) {
2346 case 0: op
= rv_op_lb
; break;
2347 case 1: op
= rv_op_lh
; break;
2348 case 2: op
= rv_op_lw
; break;
2349 case 3: op
= rv_op_ld
; break;
2350 case 4: op
= rv_op_lbu
; break;
2351 case 5: op
= rv_op_lhu
; break;
2352 case 6: op
= rv_op_lwu
; break;
2353 case 7: op
= rv_op_ldu
; break;
2357 switch ((inst
>> 12) & 0b111) {
2359 switch ((inst
>> 20) & 0b111111111111) {
2360 case 40: op
= rv_op_vl1re8_v
; break;
2361 case 552: op
= rv_op_vl2re8_v
; break;
2362 case 1576: op
= rv_op_vl4re8_v
; break;
2363 case 3624: op
= rv_op_vl8re8_v
; break;
2365 switch ((inst
>> 26) & 0b111) {
2367 switch ((inst
>> 20) & 0b11111) {
2368 case 0: op
= rv_op_vle8_v
; break;
2369 case 11: op
= rv_op_vlm_v
; break;
2370 case 16: op
= rv_op_vle8ff_v
; break;
2373 case 1: op
= rv_op_vluxei8_v
; break;
2374 case 2: op
= rv_op_vlse8_v
; break;
2375 case 3: op
= rv_op_vloxei8_v
; break;
2378 case 2: op
= rv_op_flw
; break;
2379 case 3: op
= rv_op_fld
; break;
2380 case 4: op
= rv_op_flq
; break;
2382 switch ((inst
>> 20) & 0b111111111111) {
2383 case 40: op
= rv_op_vl1re16_v
; break;
2384 case 552: op
= rv_op_vl2re16_v
; break;
2385 case 1576: op
= rv_op_vl4re16_v
; break;
2386 case 3624: op
= rv_op_vl8re16_v
; break;
2388 switch ((inst
>> 26) & 0b111) {
2390 switch ((inst
>> 20) & 0b11111) {
2391 case 0: op
= rv_op_vle16_v
; break;
2392 case 16: op
= rv_op_vle16ff_v
; break;
2395 case 1: op
= rv_op_vluxei16_v
; break;
2396 case 2: op
= rv_op_vlse16_v
; break;
2397 case 3: op
= rv_op_vloxei16_v
; break;
2401 switch ((inst
>> 20) & 0b111111111111) {
2402 case 40: op
= rv_op_vl1re32_v
; break;
2403 case 552: op
= rv_op_vl2re32_v
; break;
2404 case 1576: op
= rv_op_vl4re32_v
; break;
2405 case 3624: op
= rv_op_vl8re32_v
; break;
2407 switch ((inst
>> 26) & 0b111) {
2409 switch ((inst
>> 20) & 0b11111) {
2410 case 0: op
= rv_op_vle32_v
; break;
2411 case 16: op
= rv_op_vle32ff_v
; break;
2414 case 1: op
= rv_op_vluxei32_v
; break;
2415 case 2: op
= rv_op_vlse32_v
; break;
2416 case 3: op
= rv_op_vloxei32_v
; break;
2420 switch ((inst
>> 20) & 0b111111111111) {
2421 case 40: op
= rv_op_vl1re64_v
; break;
2422 case 552: op
= rv_op_vl2re64_v
; break;
2423 case 1576: op
= rv_op_vl4re64_v
; break;
2424 case 3624: op
= rv_op_vl8re64_v
; break;
2426 switch ((inst
>> 26) & 0b111) {
2428 switch ((inst
>> 20) & 0b11111) {
2429 case 0: op
= rv_op_vle64_v
; break;
2430 case 16: op
= rv_op_vle64ff_v
; break;
2433 case 1: op
= rv_op_vluxei64_v
; break;
2434 case 2: op
= rv_op_vlse64_v
; break;
2435 case 3: op
= rv_op_vloxei64_v
; break;
2441 switch ((inst
>> 12) & 0b111) {
2442 case 0: op
= rv_op_fence
; break;
2443 case 1: op
= rv_op_fence_i
; break;
2444 case 2: op
= rv_op_lq
; break;
2448 switch ((inst
>> 12) & 0b111) {
2449 case 0: op
= rv_op_addi
; break;
2451 switch ((inst
>> 27) & 0b11111) {
2452 case 0b00000: op
= rv_op_slli
; break;
2454 switch ((inst
>> 20) & 0b1111111) {
2455 case 0b0001111: op
= rv_op_zip
; break;
2459 switch ((inst
>> 20) & 0b1111111) {
2460 case 0b0000000: op
= rv_op_sha256sum0
; break;
2461 case 0b0000001: op
= rv_op_sha256sum1
; break;
2462 case 0b0000010: op
= rv_op_sha256sig0
; break;
2463 case 0b0000011: op
= rv_op_sha256sig1
; break;
2464 case 0b0000100: op
= rv_op_sha512sum0
; break;
2465 case 0b0000101: op
= rv_op_sha512sum1
; break;
2466 case 0b0000110: op
= rv_op_sha512sig0
; break;
2467 case 0b0000111: op
= rv_op_sha512sig1
; break;
2468 case 0b0001000: op
= rv_op_sm3p0
; break;
2469 case 0b0001001: op
= rv_op_sm3p1
; break;
2472 case 0b00101: op
= rv_op_bseti
; break;
2474 switch ((inst
>> 20) & 0b1111111) {
2475 case 0b0000000: op
= rv_op_aes64im
; break;
2477 if (((inst
>> 24) & 0b0111) == 0b001) {
2478 op
= rv_op_aes64ks1i
;
2483 case 0b01001: op
= rv_op_bclri
; break;
2484 case 0b01101: op
= rv_op_binvi
; break;
2486 switch ((inst
>> 20) & 0b1111111) {
2487 case 0b0000000: op
= rv_op_clz
; break;
2488 case 0b0000001: op
= rv_op_ctz
; break;
2489 case 0b0000010: op
= rv_op_cpop
; break;
2491 case 0b0000100: op
= rv_op_sext_b
; break;
2492 case 0b0000101: op
= rv_op_sext_h
; break;
2497 case 2: op
= rv_op_slti
; break;
2498 case 3: op
= rv_op_sltiu
; break;
2499 case 4: op
= rv_op_xori
; break;
2501 switch ((inst
>> 27) & 0b11111) {
2502 case 0b00000: op
= rv_op_srli
; break;
2504 switch ((inst
>> 20) & 0b1111111) {
2505 case 0b0001111: op
= rv_op_unzip
; break;
2508 case 0b00101: op
= rv_op_orc_b
; break;
2509 case 0b01000: op
= rv_op_srai
; break;
2510 case 0b01001: op
= rv_op_bexti
; break;
2511 case 0b01100: op
= rv_op_rori
; break;
2513 switch ((inst
>> 20) & 0b1111111) {
2514 case 0b0011000: op
= rv_op_rev8
; break;
2515 case 0b0111000: op
= rv_op_rev8
; break;
2516 case 0b0000111: op
= rv_op_brev8
; break;
2521 case 6: op
= rv_op_ori
; break;
2522 case 7: op
= rv_op_andi
; break;
2525 case 5: op
= rv_op_auipc
; break;
2527 switch ((inst
>> 12) & 0b111) {
2528 case 0: op
= rv_op_addiw
; break;
2530 switch ((inst
>> 26) & 0b111111) {
2531 case 0: op
= rv_op_slliw
; break;
2532 case 2: op
= rv_op_slli_uw
; break;
2534 switch ((inst
>> 20) & 0b11111) {
2535 case 0b00000: op
= rv_op_clzw
; break;
2536 case 0b00001: op
= rv_op_ctzw
; break;
2537 case 0b00010: op
= rv_op_cpopw
; break;
2543 switch ((inst
>> 25) & 0b1111111) {
2544 case 0: op
= rv_op_srliw
; break;
2545 case 32: op
= rv_op_sraiw
; break;
2546 case 48: op
= rv_op_roriw
; break;
2552 switch ((inst
>> 12) & 0b111) {
2553 case 0: op
= rv_op_sb
; break;
2554 case 1: op
= rv_op_sh
; break;
2555 case 2: op
= rv_op_sw
; break;
2556 case 3: op
= rv_op_sd
; break;
2557 case 4: op
= rv_op_sq
; break;
2561 switch ((inst
>> 12) & 0b111) {
2563 switch ((inst
>> 20) & 0b111111111111) {
2564 case 40: op
= rv_op_vs1r_v
; break;
2565 case 552: op
= rv_op_vs2r_v
; break;
2566 case 1576: op
= rv_op_vs4r_v
; break;
2567 case 3624: op
= rv_op_vs8r_v
; break;
2569 switch ((inst
>> 26) & 0b111) {
2571 switch ((inst
>> 20) & 0b11111) {
2572 case 0: op
= rv_op_vse8_v
; break;
2573 case 11: op
= rv_op_vsm_v
; break;
2576 case 1: op
= rv_op_vsuxei8_v
; break;
2577 case 2: op
= rv_op_vsse8_v
; break;
2578 case 3: op
= rv_op_vsoxei8_v
; break;
2581 case 2: op
= rv_op_fsw
; break;
2582 case 3: op
= rv_op_fsd
; break;
2583 case 4: op
= rv_op_fsq
; break;
2585 switch ((inst
>> 26) & 0b111) {
2587 switch ((inst
>> 20) & 0b11111) {
2588 case 0: op
= rv_op_vse16_v
; break;
2591 case 1: op
= rv_op_vsuxei16_v
; break;
2592 case 2: op
= rv_op_vsse16_v
; break;
2593 case 3: op
= rv_op_vsoxei16_v
; break;
2597 switch ((inst
>> 26) & 0b111) {
2599 switch ((inst
>> 20) & 0b11111) {
2600 case 0: op
= rv_op_vse32_v
; break;
2603 case 1: op
= rv_op_vsuxei32_v
; break;
2604 case 2: op
= rv_op_vsse32_v
; break;
2605 case 3: op
= rv_op_vsoxei32_v
; break;
2609 switch ((inst
>> 26) & 0b111) {
2611 switch ((inst
>> 20) & 0b11111) {
2612 case 0: op
= rv_op_vse64_v
; break;
2615 case 1: op
= rv_op_vsuxei64_v
; break;
2616 case 2: op
= rv_op_vsse64_v
; break;
2617 case 3: op
= rv_op_vsoxei64_v
; break;
2623 switch (((inst
>> 24) & 0b11111000) |
2624 ((inst
>> 12) & 0b00000111)) {
2625 case 2: op
= rv_op_amoadd_w
; break;
2626 case 3: op
= rv_op_amoadd_d
; break;
2627 case 4: op
= rv_op_amoadd_q
; break;
2628 case 10: op
= rv_op_amoswap_w
; break;
2629 case 11: op
= rv_op_amoswap_d
; break;
2630 case 12: op
= rv_op_amoswap_q
; break;
2632 switch ((inst
>> 20) & 0b11111) {
2633 case 0: op
= rv_op_lr_w
; break;
2637 switch ((inst
>> 20) & 0b11111) {
2638 case 0: op
= rv_op_lr_d
; break;
2642 switch ((inst
>> 20) & 0b11111) {
2643 case 0: op
= rv_op_lr_q
; break;
2646 case 26: op
= rv_op_sc_w
; break;
2647 case 27: op
= rv_op_sc_d
; break;
2648 case 28: op
= rv_op_sc_q
; break;
2649 case 34: op
= rv_op_amoxor_w
; break;
2650 case 35: op
= rv_op_amoxor_d
; break;
2651 case 36: op
= rv_op_amoxor_q
; break;
2652 case 66: op
= rv_op_amoor_w
; break;
2653 case 67: op
= rv_op_amoor_d
; break;
2654 case 68: op
= rv_op_amoor_q
; break;
2655 case 98: op
= rv_op_amoand_w
; break;
2656 case 99: op
= rv_op_amoand_d
; break;
2657 case 100: op
= rv_op_amoand_q
; break;
2658 case 130: op
= rv_op_amomin_w
; break;
2659 case 131: op
= rv_op_amomin_d
; break;
2660 case 132: op
= rv_op_amomin_q
; break;
2661 case 162: op
= rv_op_amomax_w
; break;
2662 case 163: op
= rv_op_amomax_d
; break;
2663 case 164: op
= rv_op_amomax_q
; break;
2664 case 194: op
= rv_op_amominu_w
; break;
2665 case 195: op
= rv_op_amominu_d
; break;
2666 case 196: op
= rv_op_amominu_q
; break;
2667 case 226: op
= rv_op_amomaxu_w
; break;
2668 case 227: op
= rv_op_amomaxu_d
; break;
2669 case 228: op
= rv_op_amomaxu_q
; break;
2673 switch (((inst
>> 22) & 0b1111111000) |
2674 ((inst
>> 12) & 0b0000000111)) {
2675 case 0: op
= rv_op_add
; break;
2676 case 1: op
= rv_op_sll
; break;
2677 case 2: op
= rv_op_slt
; break;
2678 case 3: op
= rv_op_sltu
; break;
2679 case 4: op
= rv_op_xor
; break;
2680 case 5: op
= rv_op_srl
; break;
2681 case 6: op
= rv_op_or
; break;
2682 case 7: op
= rv_op_and
; break;
2683 case 8: op
= rv_op_mul
; break;
2684 case 9: op
= rv_op_mulh
; break;
2685 case 10: op
= rv_op_mulhsu
; break;
2686 case 11: op
= rv_op_mulhu
; break;
2687 case 12: op
= rv_op_div
; break;
2688 case 13: op
= rv_op_divu
; break;
2689 case 14: op
= rv_op_rem
; break;
2690 case 15: op
= rv_op_remu
; break;
2692 switch ((inst
>> 20) & 0b11111) {
2693 case 0: op
= rv_op_zext_h
; break;
2694 default: op
= rv_op_pack
; break;
2697 case 39: op
= rv_op_packh
; break;
2699 case 41: op
= rv_op_clmul
; break;
2700 case 42: op
= rv_op_clmulr
; break;
2701 case 43: op
= rv_op_clmulh
; break;
2702 case 44: op
= rv_op_min
; break;
2703 case 45: op
= rv_op_minu
; break;
2704 case 46: op
= rv_op_max
; break;
2705 case 47: op
= rv_op_maxu
; break;
2706 case 075: op
= rv_op_czero_eqz
; break;
2707 case 077: op
= rv_op_czero_nez
; break;
2708 case 130: op
= rv_op_sh1add
; break;
2709 case 132: op
= rv_op_sh2add
; break;
2710 case 134: op
= rv_op_sh3add
; break;
2711 case 161: op
= rv_op_bset
; break;
2712 case 162: op
= rv_op_xperm4
; break;
2713 case 164: op
= rv_op_xperm8
; break;
2714 case 200: op
= rv_op_aes64es
; break;
2715 case 216: op
= rv_op_aes64esm
; break;
2716 case 232: op
= rv_op_aes64ds
; break;
2717 case 248: op
= rv_op_aes64dsm
; break;
2718 case 256: op
= rv_op_sub
; break;
2719 case 260: op
= rv_op_xnor
; break;
2720 case 261: op
= rv_op_sra
; break;
2721 case 262: op
= rv_op_orn
; break;
2722 case 263: op
= rv_op_andn
; break;
2723 case 289: op
= rv_op_bclr
; break;
2724 case 293: op
= rv_op_bext
; break;
2725 case 320: op
= rv_op_sha512sum0r
; break;
2726 case 328: op
= rv_op_sha512sum1r
; break;
2727 case 336: op
= rv_op_sha512sig0l
; break;
2728 case 344: op
= rv_op_sha512sig1l
; break;
2729 case 368: op
= rv_op_sha512sig0h
; break;
2730 case 376: op
= rv_op_sha512sig1h
; break;
2731 case 385: op
= rv_op_rol
; break;
2732 case 389: op
= rv_op_ror
; break;
2733 case 417: op
= rv_op_binv
; break;
2734 case 504: op
= rv_op_aes64ks2
; break;
2736 switch ((inst
>> 25) & 0b0011111) {
2737 case 17: op
= rv_op_aes32esi
; break;
2738 case 19: op
= rv_op_aes32esmi
; break;
2739 case 21: op
= rv_op_aes32dsi
; break;
2740 case 23: op
= rv_op_aes32dsmi
; break;
2741 case 24: op
= rv_op_sm4ed
; break;
2742 case 26: op
= rv_op_sm4ks
; break;
2745 case 13: op
= rv_op_lui
; break;
2747 switch (((inst
>> 22) & 0b1111111000) |
2748 ((inst
>> 12) & 0b0000000111)) {
2749 case 0: op
= rv_op_addw
; break;
2750 case 1: op
= rv_op_sllw
; break;
2751 case 5: op
= rv_op_srlw
; break;
2752 case 8: op
= rv_op_mulw
; break;
2753 case 12: op
= rv_op_divw
; break;
2754 case 13: op
= rv_op_divuw
; break;
2755 case 14: op
= rv_op_remw
; break;
2756 case 15: op
= rv_op_remuw
; break;
2757 case 32: op
= rv_op_add_uw
; break;
2759 switch ((inst
>> 20) & 0b11111) {
2760 case 0: op
= rv_op_zext_h
; break;
2761 default: op
= rv_op_packw
; break;
2764 case 130: op
= rv_op_sh1add_uw
; break;
2765 case 132: op
= rv_op_sh2add_uw
; break;
2766 case 134: op
= rv_op_sh3add_uw
; break;
2767 case 256: op
= rv_op_subw
; break;
2768 case 261: op
= rv_op_sraw
; break;
2769 case 385: op
= rv_op_rolw
; break;
2770 case 389: op
= rv_op_rorw
; break;
2774 switch ((inst
>> 25) & 0b11) {
2775 case 0: op
= rv_op_fmadd_s
; break;
2776 case 1: op
= rv_op_fmadd_d
; break;
2777 case 3: op
= rv_op_fmadd_q
; break;
2781 switch ((inst
>> 25) & 0b11) {
2782 case 0: op
= rv_op_fmsub_s
; break;
2783 case 1: op
= rv_op_fmsub_d
; break;
2784 case 3: op
= rv_op_fmsub_q
; break;
2788 switch ((inst
>> 25) & 0b11) {
2789 case 0: op
= rv_op_fnmsub_s
; break;
2790 case 1: op
= rv_op_fnmsub_d
; break;
2791 case 3: op
= rv_op_fnmsub_q
; break;
2795 switch ((inst
>> 25) & 0b11) {
2796 case 0: op
= rv_op_fnmadd_s
; break;
2797 case 1: op
= rv_op_fnmadd_d
; break;
2798 case 3: op
= rv_op_fnmadd_q
; break;
2802 switch ((inst
>> 25) & 0b1111111) {
2803 case 0: op
= rv_op_fadd_s
; break;
2804 case 1: op
= rv_op_fadd_d
; break;
2805 case 3: op
= rv_op_fadd_q
; break;
2806 case 4: op
= rv_op_fsub_s
; break;
2807 case 5: op
= rv_op_fsub_d
; break;
2808 case 7: op
= rv_op_fsub_q
; break;
2809 case 8: op
= rv_op_fmul_s
; break;
2810 case 9: op
= rv_op_fmul_d
; break;
2811 case 11: op
= rv_op_fmul_q
; break;
2812 case 12: op
= rv_op_fdiv_s
; break;
2813 case 13: op
= rv_op_fdiv_d
; break;
2814 case 15: op
= rv_op_fdiv_q
; break;
2816 switch ((inst
>> 12) & 0b111) {
2817 case 0: op
= rv_op_fsgnj_s
; break;
2818 case 1: op
= rv_op_fsgnjn_s
; break;
2819 case 2: op
= rv_op_fsgnjx_s
; break;
2823 switch ((inst
>> 12) & 0b111) {
2824 case 0: op
= rv_op_fsgnj_d
; break;
2825 case 1: op
= rv_op_fsgnjn_d
; break;
2826 case 2: op
= rv_op_fsgnjx_d
; break;
2830 switch ((inst
>> 12) & 0b111) {
2831 case 0: op
= rv_op_fsgnj_q
; break;
2832 case 1: op
= rv_op_fsgnjn_q
; break;
2833 case 2: op
= rv_op_fsgnjx_q
; break;
2837 switch ((inst
>> 12) & 0b111) {
2838 case 0: op
= rv_op_fmin_s
; break;
2839 case 1: op
= rv_op_fmax_s
; break;
2843 switch ((inst
>> 12) & 0b111) {
2844 case 0: op
= rv_op_fmin_d
; break;
2845 case 1: op
= rv_op_fmax_d
; break;
2849 switch ((inst
>> 12) & 0b111) {
2850 case 0: op
= rv_op_fmin_q
; break;
2851 case 1: op
= rv_op_fmax_q
; break;
2855 switch ((inst
>> 20) & 0b11111) {
2856 case 1: op
= rv_op_fcvt_s_d
; break;
2857 case 3: op
= rv_op_fcvt_s_q
; break;
2861 switch ((inst
>> 20) & 0b11111) {
2862 case 0: op
= rv_op_fcvt_d_s
; break;
2863 case 3: op
= rv_op_fcvt_d_q
; break;
2867 switch ((inst
>> 20) & 0b11111) {
2868 case 0: op
= rv_op_fcvt_q_s
; break;
2869 case 1: op
= rv_op_fcvt_q_d
; break;
2873 switch ((inst
>> 20) & 0b11111) {
2874 case 0: op
= rv_op_fsqrt_s
; break;
2878 switch ((inst
>> 20) & 0b11111) {
2879 case 0: op
= rv_op_fsqrt_d
; break;
2883 switch ((inst
>> 20) & 0b11111) {
2884 case 0: op
= rv_op_fsqrt_q
; break;
2888 switch ((inst
>> 12) & 0b111) {
2889 case 0: op
= rv_op_fle_s
; break;
2890 case 1: op
= rv_op_flt_s
; break;
2891 case 2: op
= rv_op_feq_s
; break;
2895 switch ((inst
>> 12) & 0b111) {
2896 case 0: op
= rv_op_fle_d
; break;
2897 case 1: op
= rv_op_flt_d
; break;
2898 case 2: op
= rv_op_feq_d
; break;
2902 switch ((inst
>> 12) & 0b111) {
2903 case 0: op
= rv_op_fle_q
; break;
2904 case 1: op
= rv_op_flt_q
; break;
2905 case 2: op
= rv_op_feq_q
; break;
2909 switch ((inst
>> 20) & 0b11111) {
2910 case 0: op
= rv_op_fcvt_w_s
; break;
2911 case 1: op
= rv_op_fcvt_wu_s
; break;
2912 case 2: op
= rv_op_fcvt_l_s
; break;
2913 case 3: op
= rv_op_fcvt_lu_s
; break;
2917 switch ((inst
>> 20) & 0b11111) {
2918 case 0: op
= rv_op_fcvt_w_d
; break;
2919 case 1: op
= rv_op_fcvt_wu_d
; break;
2920 case 2: op
= rv_op_fcvt_l_d
; break;
2921 case 3: op
= rv_op_fcvt_lu_d
; break;
2925 switch ((inst
>> 20) & 0b11111) {
2926 case 0: op
= rv_op_fcvt_w_q
; break;
2927 case 1: op
= rv_op_fcvt_wu_q
; break;
2928 case 2: op
= rv_op_fcvt_l_q
; break;
2929 case 3: op
= rv_op_fcvt_lu_q
; break;
2933 switch ((inst
>> 20) & 0b11111) {
2934 case 0: op
= rv_op_fcvt_s_w
; break;
2935 case 1: op
= rv_op_fcvt_s_wu
; break;
2936 case 2: op
= rv_op_fcvt_s_l
; break;
2937 case 3: op
= rv_op_fcvt_s_lu
; break;
2941 switch ((inst
>> 20) & 0b11111) {
2942 case 0: op
= rv_op_fcvt_d_w
; break;
2943 case 1: op
= rv_op_fcvt_d_wu
; break;
2944 case 2: op
= rv_op_fcvt_d_l
; break;
2945 case 3: op
= rv_op_fcvt_d_lu
; break;
2949 switch ((inst
>> 20) & 0b11111) {
2950 case 0: op
= rv_op_fcvt_q_w
; break;
2951 case 1: op
= rv_op_fcvt_q_wu
; break;
2952 case 2: op
= rv_op_fcvt_q_l
; break;
2953 case 3: op
= rv_op_fcvt_q_lu
; break;
2957 switch (((inst
>> 17) & 0b11111000) |
2958 ((inst
>> 12) & 0b00000111)) {
2959 case 0: op
= rv_op_fmv_x_s
; break;
2960 case 1: op
= rv_op_fclass_s
; break;
2964 switch (((inst
>> 17) & 0b11111000) |
2965 ((inst
>> 12) & 0b00000111)) {
2966 case 0: op
= rv_op_fmv_x_d
; break;
2967 case 1: op
= rv_op_fclass_d
; break;
2971 switch (((inst
>> 17) & 0b11111000) |
2972 ((inst
>> 12) & 0b00000111)) {
2973 case 0: op
= rv_op_fmv_x_q
; break;
2974 case 1: op
= rv_op_fclass_q
; break;
2978 switch (((inst
>> 17) & 0b11111000) |
2979 ((inst
>> 12) & 0b00000111)) {
2980 case 0: op
= rv_op_fmv_s_x
; break;
2984 switch (((inst
>> 17) & 0b11111000) |
2985 ((inst
>> 12) & 0b00000111)) {
2986 case 0: op
= rv_op_fmv_d_x
; break;
2990 switch (((inst
>> 17) & 0b11111000) |
2991 ((inst
>> 12) & 0b00000111)) {
2992 case 0: op
= rv_op_fmv_q_x
; break;
2998 switch ((inst
>> 12) & 0b111) {
3000 switch ((inst
>> 26) & 0b111111) {
3001 case 0: op
= rv_op_vadd_vv
; break;
3002 case 2: op
= rv_op_vsub_vv
; break;
3003 case 4: op
= rv_op_vminu_vv
; break;
3004 case 5: op
= rv_op_vmin_vv
; break;
3005 case 6: op
= rv_op_vmaxu_vv
; break;
3006 case 7: op
= rv_op_vmax_vv
; break;
3007 case 9: op
= rv_op_vand_vv
; break;
3008 case 10: op
= rv_op_vor_vv
; break;
3009 case 11: op
= rv_op_vxor_vv
; break;
3010 case 12: op
= rv_op_vrgather_vv
; break;
3011 case 14: op
= rv_op_vrgatherei16_vv
; break;
3013 if (((inst
>> 25) & 1) == 0) {
3014 op
= rv_op_vadc_vvm
;
3017 case 17: op
= rv_op_vmadc_vvm
; break;
3019 if (((inst
>> 25) & 1) == 0) {
3020 op
= rv_op_vsbc_vvm
;
3023 case 19: op
= rv_op_vmsbc_vvm
; break;
3025 if (((inst
>> 20) & 0b111111) == 32)
3027 else if (((inst
>> 25) & 1) == 0)
3028 op
= rv_op_vmerge_vvm
;
3030 case 24: op
= rv_op_vmseq_vv
; break;
3031 case 25: op
= rv_op_vmsne_vv
; break;
3032 case 26: op
= rv_op_vmsltu_vv
; break;
3033 case 27: op
= rv_op_vmslt_vv
; break;
3034 case 28: op
= rv_op_vmsleu_vv
; break;
3035 case 29: op
= rv_op_vmsle_vv
; break;
3036 case 32: op
= rv_op_vsaddu_vv
; break;
3037 case 33: op
= rv_op_vsadd_vv
; break;
3038 case 34: op
= rv_op_vssubu_vv
; break;
3039 case 35: op
= rv_op_vssub_vv
; break;
3040 case 37: op
= rv_op_vsll_vv
; break;
3041 case 39: op
= rv_op_vsmul_vv
; break;
3042 case 40: op
= rv_op_vsrl_vv
; break;
3043 case 41: op
= rv_op_vsra_vv
; break;
3044 case 42: op
= rv_op_vssrl_vv
; break;
3045 case 43: op
= rv_op_vssra_vv
; break;
3046 case 44: op
= rv_op_vnsrl_wv
; break;
3047 case 45: op
= rv_op_vnsra_wv
; break;
3048 case 46: op
= rv_op_vnclipu_wv
; break;
3049 case 47: op
= rv_op_vnclip_wv
; break;
3050 case 48: op
= rv_op_vwredsumu_vs
; break;
3051 case 49: op
= rv_op_vwredsum_vs
; break;
3055 switch ((inst
>> 26) & 0b111111) {
3056 case 0: op
= rv_op_vfadd_vv
; break;
3057 case 1: op
= rv_op_vfredusum_vs
; break;
3058 case 2: op
= rv_op_vfsub_vv
; break;
3059 case 3: op
= rv_op_vfredosum_vs
; break;
3060 case 4: op
= rv_op_vfmin_vv
; break;
3061 case 5: op
= rv_op_vfredmin_vs
; break;
3062 case 6: op
= rv_op_vfmax_vv
; break;
3063 case 7: op
= rv_op_vfredmax_vs
; break;
3064 case 8: op
= rv_op_vfsgnj_vv
; break;
3065 case 9: op
= rv_op_vfsgnjn_vv
; break;
3066 case 10: op
= rv_op_vfsgnjx_vv
; break;
3068 switch ((inst
>> 15) & 0b11111) {
3069 case 0: if ((inst
>> 25) & 1) op
= rv_op_vfmv_f_s
; break;
3073 switch ((inst
>> 15) & 0b11111) {
3074 case 0: op
= rv_op_vfcvt_xu_f_v
; break;
3075 case 1: op
= rv_op_vfcvt_x_f_v
; break;
3076 case 2: op
= rv_op_vfcvt_f_xu_v
; break;
3077 case 3: op
= rv_op_vfcvt_f_x_v
; break;
3078 case 6: op
= rv_op_vfcvt_rtz_xu_f_v
; break;
3079 case 7: op
= rv_op_vfcvt_rtz_x_f_v
; break;
3080 case 8: op
= rv_op_vfwcvt_xu_f_v
; break;
3081 case 9: op
= rv_op_vfwcvt_x_f_v
; break;
3082 case 10: op
= rv_op_vfwcvt_f_xu_v
; break;
3083 case 11: op
= rv_op_vfwcvt_f_x_v
; break;
3084 case 12: op
= rv_op_vfwcvt_f_f_v
; break;
3085 case 14: op
= rv_op_vfwcvt_rtz_xu_f_v
; break;
3086 case 15: op
= rv_op_vfwcvt_rtz_x_f_v
; break;
3087 case 16: op
= rv_op_vfncvt_xu_f_w
; break;
3088 case 17: op
= rv_op_vfncvt_x_f_w
; break;
3089 case 18: op
= rv_op_vfncvt_f_xu_w
; break;
3090 case 19: op
= rv_op_vfncvt_f_x_w
; break;
3091 case 20: op
= rv_op_vfncvt_f_f_w
; break;
3092 case 21: op
= rv_op_vfncvt_rod_f_f_w
; break;
3093 case 22: op
= rv_op_vfncvt_rtz_xu_f_w
; break;
3094 case 23: op
= rv_op_vfncvt_rtz_x_f_w
; break;
3098 switch ((inst
>> 15) & 0b11111) {
3099 case 0: op
= rv_op_vfsqrt_v
; break;
3100 case 4: op
= rv_op_vfrsqrt7_v
; break;
3101 case 5: op
= rv_op_vfrec7_v
; break;
3102 case 16: op
= rv_op_vfclass_v
; break;
3105 case 24: op
= rv_op_vmfeq_vv
; break;
3106 case 25: op
= rv_op_vmfle_vv
; break;
3107 case 27: op
= rv_op_vmflt_vv
; break;
3108 case 28: op
= rv_op_vmfne_vv
; break;
3109 case 32: op
= rv_op_vfdiv_vv
; break;
3110 case 36: op
= rv_op_vfmul_vv
; break;
3111 case 40: op
= rv_op_vfmadd_vv
; break;
3112 case 41: op
= rv_op_vfnmadd_vv
; break;
3113 case 42: op
= rv_op_vfmsub_vv
; break;
3114 case 43: op
= rv_op_vfnmsub_vv
; break;
3115 case 44: op
= rv_op_vfmacc_vv
; break;
3116 case 45: op
= rv_op_vfnmacc_vv
; break;
3117 case 46: op
= rv_op_vfmsac_vv
; break;
3118 case 47: op
= rv_op_vfnmsac_vv
; break;
3119 case 48: op
= rv_op_vfwadd_vv
; break;
3120 case 49: op
= rv_op_vfwredusum_vs
; break;
3121 case 50: op
= rv_op_vfwsub_vv
; break;
3122 case 51: op
= rv_op_vfwredosum_vs
; break;
3123 case 52: op
= rv_op_vfwadd_wv
; break;
3124 case 54: op
= rv_op_vfwsub_wv
; break;
3125 case 56: op
= rv_op_vfwmul_vv
; break;
3126 case 60: op
= rv_op_vfwmacc_vv
; break;
3127 case 61: op
= rv_op_vfwnmacc_vv
; break;
3128 case 62: op
= rv_op_vfwmsac_vv
; break;
3129 case 63: op
= rv_op_vfwnmsac_vv
; break;
3133 switch ((inst
>> 26) & 0b111111) {
3134 case 0: op
= rv_op_vredsum_vs
; break;
3135 case 1: op
= rv_op_vredand_vs
; break;
3136 case 2: op
= rv_op_vredor_vs
; break;
3137 case 3: op
= rv_op_vredxor_vs
; break;
3138 case 4: op
= rv_op_vredminu_vs
; break;
3139 case 5: op
= rv_op_vredmin_vs
; break;
3140 case 6: op
= rv_op_vredmaxu_vs
; break;
3141 case 7: op
= rv_op_vredmax_vs
; break;
3142 case 8: op
= rv_op_vaaddu_vv
; break;
3143 case 9: op
= rv_op_vaadd_vv
; break;
3144 case 10: op
= rv_op_vasubu_vv
; break;
3145 case 11: op
= rv_op_vasub_vv
; break;
3147 switch ((inst
>> 15) & 0b11111) {
3148 case 0: if ((inst
>> 25) & 1) op
= rv_op_vmv_x_s
; break;
3149 case 16: op
= rv_op_vcpop_m
; break;
3150 case 17: op
= rv_op_vfirst_m
; break;
3154 switch ((inst
>> 15) & 0b11111) {
3155 case 2: op
= rv_op_vzext_vf8
; break;
3156 case 3: op
= rv_op_vsext_vf8
; break;
3157 case 4: op
= rv_op_vzext_vf4
; break;
3158 case 5: op
= rv_op_vsext_vf4
; break;
3159 case 6: op
= rv_op_vzext_vf2
; break;
3160 case 7: op
= rv_op_vsext_vf2
; break;
3164 switch ((inst
>> 15) & 0b11111) {
3165 case 1: op
= rv_op_vmsbf_m
; break;
3166 case 2: op
= rv_op_vmsof_m
; break;
3167 case 3: op
= rv_op_vmsif_m
; break;
3168 case 16: op
= rv_op_viota_m
; break;
3170 if (((inst
>> 20) & 0b11111) == 0) {
3176 case 23: if ((inst
>> 25) & 1) op
= rv_op_vcompress_vm
; break;
3177 case 24: if ((inst
>> 25) & 1) op
= rv_op_vmandn_mm
; break;
3178 case 25: if ((inst
>> 25) & 1) op
= rv_op_vmand_mm
; break;
3179 case 26: if ((inst
>> 25) & 1) op
= rv_op_vmor_mm
; break;
3180 case 27: if ((inst
>> 25) & 1) op
= rv_op_vmxor_mm
; break;
3181 case 28: if ((inst
>> 25) & 1) op
= rv_op_vmorn_mm
; break;
3182 case 29: if ((inst
>> 25) & 1) op
= rv_op_vmnand_mm
; break;
3183 case 30: if ((inst
>> 25) & 1) op
= rv_op_vmnor_mm
; break;
3184 case 31: if ((inst
>> 25) & 1) op
= rv_op_vmxnor_mm
; break;
3185 case 32: op
= rv_op_vdivu_vv
; break;
3186 case 33: op
= rv_op_vdiv_vv
; break;
3187 case 34: op
= rv_op_vremu_vv
; break;
3188 case 35: op
= rv_op_vrem_vv
; break;
3189 case 36: op
= rv_op_vmulhu_vv
; break;
3190 case 37: op
= rv_op_vmul_vv
; break;
3191 case 38: op
= rv_op_vmulhsu_vv
; break;
3192 case 39: op
= rv_op_vmulh_vv
; break;
3193 case 41: op
= rv_op_vmadd_vv
; break;
3194 case 43: op
= rv_op_vnmsub_vv
; break;
3195 case 45: op
= rv_op_vmacc_vv
; break;
3196 case 47: op
= rv_op_vnmsac_vv
; break;
3197 case 48: op
= rv_op_vwaddu_vv
; break;
3198 case 49: op
= rv_op_vwadd_vv
; break;
3199 case 50: op
= rv_op_vwsubu_vv
; break;
3200 case 51: op
= rv_op_vwsub_vv
; break;
3201 case 52: op
= rv_op_vwaddu_wv
; break;
3202 case 53: op
= rv_op_vwadd_wv
; break;
3203 case 54: op
= rv_op_vwsubu_wv
; break;
3204 case 55: op
= rv_op_vwsub_wv
; break;
3205 case 56: op
= rv_op_vwmulu_vv
; break;
3206 case 58: op
= rv_op_vwmulsu_vv
; break;
3207 case 59: op
= rv_op_vwmul_vv
; break;
3208 case 60: op
= rv_op_vwmaccu_vv
; break;
3209 case 61: op
= rv_op_vwmacc_vv
; break;
3210 case 63: op
= rv_op_vwmaccsu_vv
; break;
3214 switch ((inst
>> 26) & 0b111111) {
3215 case 0: op
= rv_op_vadd_vi
; break;
3216 case 3: op
= rv_op_vrsub_vi
; break;
3217 case 9: op
= rv_op_vand_vi
; break;
3218 case 10: op
= rv_op_vor_vi
; break;
3219 case 11: op
= rv_op_vxor_vi
; break;
3220 case 12: op
= rv_op_vrgather_vi
; break;
3221 case 14: op
= rv_op_vslideup_vi
; break;
3222 case 15: op
= rv_op_vslidedown_vi
; break;
3224 if (((inst
>> 25) & 1) == 0) {
3225 op
= rv_op_vadc_vim
;
3228 case 17: op
= rv_op_vmadc_vim
; break;
3230 if (((inst
>> 20) & 0b111111) == 32)
3232 else if (((inst
>> 25) & 1) == 0)
3233 op
= rv_op_vmerge_vim
;
3235 case 24: op
= rv_op_vmseq_vi
; break;
3236 case 25: op
= rv_op_vmsne_vi
; break;
3237 case 28: op
= rv_op_vmsleu_vi
; break;
3238 case 29: op
= rv_op_vmsle_vi
; break;
3239 case 30: op
= rv_op_vmsgtu_vi
; break;
3240 case 31: op
= rv_op_vmsgt_vi
; break;
3241 case 32: op
= rv_op_vsaddu_vi
; break;
3242 case 33: op
= rv_op_vsadd_vi
; break;
3243 case 37: op
= rv_op_vsll_vi
; break;
3245 switch ((inst
>> 15) & 0b11111) {
3246 case 0: op
= rv_op_vmv1r_v
; break;
3247 case 1: op
= rv_op_vmv2r_v
; break;
3248 case 3: op
= rv_op_vmv4r_v
; break;
3249 case 7: op
= rv_op_vmv8r_v
; break;
3252 case 40: op
= rv_op_vsrl_vi
; break;
3253 case 41: op
= rv_op_vsra_vi
; break;
3254 case 42: op
= rv_op_vssrl_vi
; break;
3255 case 43: op
= rv_op_vssra_vi
; break;
3256 case 44: op
= rv_op_vnsrl_wi
; break;
3257 case 45: op
= rv_op_vnsra_wi
; break;
3258 case 46: op
= rv_op_vnclipu_wi
; break;
3259 case 47: op
= rv_op_vnclip_wi
; break;
3263 switch ((inst
>> 26) & 0b111111) {
3264 case 0: op
= rv_op_vadd_vx
; break;
3265 case 2: op
= rv_op_vsub_vx
; break;
3266 case 3: op
= rv_op_vrsub_vx
; break;
3267 case 4: op
= rv_op_vminu_vx
; break;
3268 case 5: op
= rv_op_vmin_vx
; break;
3269 case 6: op
= rv_op_vmaxu_vx
; break;
3270 case 7: op
= rv_op_vmax_vx
; break;
3271 case 9: op
= rv_op_vand_vx
; break;
3272 case 10: op
= rv_op_vor_vx
; break;
3273 case 11: op
= rv_op_vxor_vx
; break;
3274 case 12: op
= rv_op_vrgather_vx
; break;
3275 case 14: op
= rv_op_vslideup_vx
; break;
3276 case 15: op
= rv_op_vslidedown_vx
; break;
3278 if (((inst
>> 25) & 1) == 0) {
3279 op
= rv_op_vadc_vxm
;
3282 case 17: op
= rv_op_vmadc_vxm
; break;
3284 if (((inst
>> 25) & 1) == 0) {
3285 op
= rv_op_vsbc_vxm
;
3288 case 19: op
= rv_op_vmsbc_vxm
; break;
3290 if (((inst
>> 20) & 0b111111) == 32)
3292 else if (((inst
>> 25) & 1) == 0)
3293 op
= rv_op_vmerge_vxm
;
3295 case 24: op
= rv_op_vmseq_vx
; break;
3296 case 25: op
= rv_op_vmsne_vx
; break;
3297 case 26: op
= rv_op_vmsltu_vx
; break;
3298 case 27: op
= rv_op_vmslt_vx
; break;
3299 case 28: op
= rv_op_vmsleu_vx
; break;
3300 case 29: op
= rv_op_vmsle_vx
; break;
3301 case 30: op
= rv_op_vmsgtu_vx
; break;
3302 case 31: op
= rv_op_vmsgt_vx
; break;
3303 case 32: op
= rv_op_vsaddu_vx
; break;
3304 case 33: op
= rv_op_vsadd_vx
; break;
3305 case 34: op
= rv_op_vssubu_vx
; break;
3306 case 35: op
= rv_op_vssub_vx
; break;
3307 case 37: op
= rv_op_vsll_vx
; break;
3308 case 39: op
= rv_op_vsmul_vx
; break;
3309 case 40: op
= rv_op_vsrl_vx
; break;
3310 case 41: op
= rv_op_vsra_vx
; break;
3311 case 42: op
= rv_op_vssrl_vx
; break;
3312 case 43: op
= rv_op_vssra_vx
; break;
3313 case 44: op
= rv_op_vnsrl_wx
; break;
3314 case 45: op
= rv_op_vnsra_wx
; break;
3315 case 46: op
= rv_op_vnclipu_wx
; break;
3316 case 47: op
= rv_op_vnclip_wx
; break;
3320 switch ((inst
>> 26) & 0b111111) {
3321 case 0: op
= rv_op_vfadd_vf
; break;
3322 case 2: op
= rv_op_vfsub_vf
; break;
3323 case 4: op
= rv_op_vfmin_vf
; break;
3324 case 6: op
= rv_op_vfmax_vf
; break;
3325 case 8: op
= rv_op_vfsgnj_vf
; break;
3326 case 9: op
= rv_op_vfsgnjn_vf
; break;
3327 case 10: op
= rv_op_vfsgnjx_vf
; break;
3328 case 14: op
= rv_op_vfslide1up_vf
; break;
3329 case 15: op
= rv_op_vfslide1down_vf
; break;
3331 switch ((inst
>> 20) & 0b11111) {
3332 case 0: if ((inst
>> 25) & 1) op
= rv_op_vfmv_s_f
; break;
3336 if (((inst
>> 25) & 1) == 0)
3337 op
= rv_op_vfmerge_vfm
;
3338 else if (((inst
>> 20) & 0b111111) == 32)
3339 op
= rv_op_vfmv_v_f
;
3341 case 24: op
= rv_op_vmfeq_vf
; break;
3342 case 25: op
= rv_op_vmfle_vf
; break;
3343 case 27: op
= rv_op_vmflt_vf
; break;
3344 case 28: op
= rv_op_vmfne_vf
; break;
3345 case 29: op
= rv_op_vmfgt_vf
; break;
3346 case 31: op
= rv_op_vmfge_vf
; break;
3347 case 32: op
= rv_op_vfdiv_vf
; break;
3348 case 33: op
= rv_op_vfrdiv_vf
; break;
3349 case 36: op
= rv_op_vfmul_vf
; break;
3350 case 39: op
= rv_op_vfrsub_vf
; break;
3351 case 40: op
= rv_op_vfmadd_vf
; break;
3352 case 41: op
= rv_op_vfnmadd_vf
; break;
3353 case 42: op
= rv_op_vfmsub_vf
; break;
3354 case 43: op
= rv_op_vfnmsub_vf
; break;
3355 case 44: op
= rv_op_vfmacc_vf
; break;
3356 case 45: op
= rv_op_vfnmacc_vf
; break;
3357 case 46: op
= rv_op_vfmsac_vf
; break;
3358 case 47: op
= rv_op_vfnmsac_vf
; break;
3359 case 48: op
= rv_op_vfwadd_vf
; break;
3360 case 50: op
= rv_op_vfwsub_vf
; break;
3361 case 52: op
= rv_op_vfwadd_wf
; break;
3362 case 54: op
= rv_op_vfwsub_wf
; break;
3363 case 56: op
= rv_op_vfwmul_vf
; break;
3364 case 60: op
= rv_op_vfwmacc_vf
; break;
3365 case 61: op
= rv_op_vfwnmacc_vf
; break;
3366 case 62: op
= rv_op_vfwmsac_vf
; break;
3367 case 63: op
= rv_op_vfwnmsac_vf
; break;
3371 switch ((inst
>> 26) & 0b111111) {
3372 case 8: op
= rv_op_vaaddu_vx
; break;
3373 case 9: op
= rv_op_vaadd_vx
; break;
3374 case 10: op
= rv_op_vasubu_vx
; break;
3375 case 11: op
= rv_op_vasub_vx
; break;
3376 case 14: op
= rv_op_vslide1up_vx
; break;
3377 case 15: op
= rv_op_vslide1down_vx
; break;
3379 switch ((inst
>> 20) & 0b11111) {
3380 case 0: if ((inst
>> 25) & 1) op
= rv_op_vmv_s_x
; break;
3383 case 32: op
= rv_op_vdivu_vx
; break;
3384 case 33: op
= rv_op_vdiv_vx
; break;
3385 case 34: op
= rv_op_vremu_vx
; break;
3386 case 35: op
= rv_op_vrem_vx
; break;
3387 case 36: op
= rv_op_vmulhu_vx
; break;
3388 case 37: op
= rv_op_vmul_vx
; break;
3389 case 38: op
= rv_op_vmulhsu_vx
; break;
3390 case 39: op
= rv_op_vmulh_vx
; break;
3391 case 41: op
= rv_op_vmadd_vx
; break;
3392 case 43: op
= rv_op_vnmsub_vx
; break;
3393 case 45: op
= rv_op_vmacc_vx
; break;
3394 case 47: op
= rv_op_vnmsac_vx
; break;
3395 case 48: op
= rv_op_vwaddu_vx
; break;
3396 case 49: op
= rv_op_vwadd_vx
; break;
3397 case 50: op
= rv_op_vwsubu_vx
; break;
3398 case 51: op
= rv_op_vwsub_vx
; break;
3399 case 52: op
= rv_op_vwaddu_wx
; break;
3400 case 53: op
= rv_op_vwadd_wx
; break;
3401 case 54: op
= rv_op_vwsubu_wx
; break;
3402 case 55: op
= rv_op_vwsub_wx
; break;
3403 case 56: op
= rv_op_vwmulu_vx
; break;
3404 case 58: op
= rv_op_vwmulsu_vx
; break;
3405 case 59: op
= rv_op_vwmul_vx
; break;
3406 case 60: op
= rv_op_vwmaccu_vx
; break;
3407 case 61: op
= rv_op_vwmacc_vx
; break;
3408 case 62: op
= rv_op_vwmaccus_vx
; break;
3409 case 63: op
= rv_op_vwmaccsu_vx
; break;
3413 if (((inst
>> 31) & 1) == 0) {
3415 } else if ((inst
>> 30) & 1) {
3416 op
= rv_op_vsetivli
;
3417 } else if (((inst
>> 25) & 0b11111) == 0) {
3424 switch ((inst
>> 12) & 0b111) {
3425 case 0: op
= rv_op_addid
; break;
3427 switch ((inst
>> 26) & 0b111111) {
3428 case 0: op
= rv_op_sllid
; break;
3432 switch ((inst
>> 26) & 0b111111) {
3433 case 0: op
= rv_op_srlid
; break;
3434 case 16: op
= rv_op_sraid
; break;
3440 switch ((inst
>> 12) & 0b111) {
3441 case 0: op
= rv_op_beq
; break;
3442 case 1: op
= rv_op_bne
; break;
3443 case 4: op
= rv_op_blt
; break;
3444 case 5: op
= rv_op_bge
; break;
3445 case 6: op
= rv_op_bltu
; break;
3446 case 7: op
= rv_op_bgeu
; break;
3450 switch ((inst
>> 12) & 0b111) {
3451 case 0: op
= rv_op_jalr
; break;
3454 case 27: op
= rv_op_jal
; break;
3456 switch ((inst
>> 12) & 0b111) {
3458 switch (((inst
>> 20) & 0b111111100000) |
3459 ((inst
>> 7) & 0b000000011111)) {
3461 switch ((inst
>> 15) & 0b1111111111) {
3462 case 0: op
= rv_op_ecall
; break;
3463 case 32: op
= rv_op_ebreak
; break;
3464 case 64: op
= rv_op_uret
; break;
3468 switch ((inst
>> 20) & 0b11111) {
3470 switch ((inst
>> 15) & 0b11111) {
3471 case 0: op
= rv_op_sret
; break;
3474 case 4: op
= rv_op_sfence_vm
; break;
3476 switch ((inst
>> 15) & 0b11111) {
3477 case 0: op
= rv_op_wfi
; break;
3482 case 288: op
= rv_op_sfence_vma
; break;
3484 switch ((inst
>> 15) & 0b1111111111) {
3485 case 64: op
= rv_op_hret
; break;
3489 switch ((inst
>> 15) & 0b1111111111) {
3490 case 64: op
= rv_op_mret
; break;
3494 switch ((inst
>> 15) & 0b1111111111) {
3495 case 576: op
= rv_op_dret
; break;
3500 case 1: op
= rv_op_csrrw
; break;
3501 case 2: op
= rv_op_csrrs
; break;
3502 case 3: op
= rv_op_csrrc
; break;
3503 case 5: op
= rv_op_csrrwi
; break;
3504 case 6: op
= rv_op_csrrsi
; break;
3505 case 7: op
= rv_op_csrrci
; break;
3509 switch (((inst
>> 22) & 0b1111111000) |
3510 ((inst
>> 12) & 0b0000000111)) {
3511 case 0: op
= rv_op_addd
; break;
3512 case 1: op
= rv_op_slld
; break;
3513 case 5: op
= rv_op_srld
; break;
3514 case 8: op
= rv_op_muld
; break;
3515 case 12: op
= rv_op_divd
; break;
3516 case 13: op
= rv_op_divud
; break;
3517 case 14: op
= rv_op_remd
; break;
3518 case 15: op
= rv_op_remud
; break;
3519 case 256: op
= rv_op_subd
; break;
3520 case 261: op
= rv_op_srad
; break;
3529 /* operand extractors */
3531 static uint32_t operand_rd(rv_inst inst
)
3533 return (inst
<< 52) >> 59;
3536 static uint32_t operand_rs1(rv_inst inst
)
3538 return (inst
<< 44) >> 59;
3541 static uint32_t operand_rs2(rv_inst inst
)
3543 return (inst
<< 39) >> 59;
3546 static uint32_t operand_rs3(rv_inst inst
)
3548 return (inst
<< 32) >> 59;
3551 static uint32_t operand_aq(rv_inst inst
)
3553 return (inst
<< 37) >> 63;
3556 static uint32_t operand_rl(rv_inst inst
)
3558 return (inst
<< 38) >> 63;
3561 static uint32_t operand_pred(rv_inst inst
)
3563 return (inst
<< 36) >> 60;
3566 static uint32_t operand_succ(rv_inst inst
)
3568 return (inst
<< 40) >> 60;
3571 static uint32_t operand_rm(rv_inst inst
)
3573 return (inst
<< 49) >> 61;
3576 static uint32_t operand_shamt5(rv_inst inst
)
3578 return (inst
<< 39) >> 59;
3581 static uint32_t operand_shamt6(rv_inst inst
)
3583 return (inst
<< 38) >> 58;
3586 static uint32_t operand_shamt7(rv_inst inst
)
3588 return (inst
<< 37) >> 57;
3591 static uint32_t operand_crdq(rv_inst inst
)
3593 return (inst
<< 59) >> 61;
3596 static uint32_t operand_crs1q(rv_inst inst
)
3598 return (inst
<< 54) >> 61;
3601 static uint32_t operand_crs1rdq(rv_inst inst
)
3603 return (inst
<< 54) >> 61;
3606 static uint32_t operand_crs2q(rv_inst inst
)
3608 return (inst
<< 59) >> 61;
3611 static uint32_t calculate_xreg(uint32_t sreg
)
3613 return sreg
< 2 ? sreg
+ 8 : sreg
+ 16;
3616 static uint32_t operand_sreg1(rv_inst inst
)
3618 return calculate_xreg((inst
<< 54) >> 61);
3621 static uint32_t operand_sreg2(rv_inst inst
)
3623 return calculate_xreg((inst
<< 59) >> 61);
3626 static uint32_t operand_crd(rv_inst inst
)
3628 return (inst
<< 52) >> 59;
3631 static uint32_t operand_crs1(rv_inst inst
)
3633 return (inst
<< 52) >> 59;
3636 static uint32_t operand_crs1rd(rv_inst inst
)
3638 return (inst
<< 52) >> 59;
3641 static uint32_t operand_crs2(rv_inst inst
)
3643 return (inst
<< 57) >> 59;
3646 static uint32_t operand_cimmsh5(rv_inst inst
)
3648 return (inst
<< 57) >> 59;
3651 static uint32_t operand_csr12(rv_inst inst
)
3653 return (inst
<< 32) >> 52;
3656 static int32_t operand_imm12(rv_inst inst
)
3658 return ((int64_t)inst
<< 32) >> 52;
3661 static int32_t operand_imm20(rv_inst inst
)
3663 return (((int64_t)inst
<< 32) >> 44) << 12;
3666 static int32_t operand_jimm20(rv_inst inst
)
3668 return (((int64_t)inst
<< 32) >> 63) << 20 |
3669 ((inst
<< 33) >> 54) << 1 |
3670 ((inst
<< 43) >> 63) << 11 |
3671 ((inst
<< 44) >> 56) << 12;
3674 static int32_t operand_simm12(rv_inst inst
)
3676 return (((int64_t)inst
<< 32) >> 57) << 5 |
3680 static int32_t operand_sbimm12(rv_inst inst
)
3682 return (((int64_t)inst
<< 32) >> 63) << 12 |
3683 ((inst
<< 33) >> 58) << 5 |
3684 ((inst
<< 52) >> 60) << 1 |
3685 ((inst
<< 56) >> 63) << 11;
3688 static uint32_t operand_cimmshl6(rv_inst inst
, rv_isa isa
)
3690 int imm
= ((inst
<< 51) >> 63) << 5 |
3693 imm
= imm
? imm
: 64;
3698 static uint32_t operand_cimmshr6(rv_inst inst
, rv_isa isa
)
3700 int imm
= ((inst
<< 51) >> 63) << 5 |
3703 imm
= imm
| (imm
& 32) << 1;
3704 imm
= imm
? imm
: 64;
3709 static int32_t operand_cimmi(rv_inst inst
)
3711 return (((int64_t)inst
<< 51) >> 63) << 5 |
3715 static int32_t operand_cimmui(rv_inst inst
)
3717 return (((int64_t)inst
<< 51) >> 63) << 17 |
3718 ((inst
<< 57) >> 59) << 12;
3721 static uint32_t operand_cimmlwsp(rv_inst inst
)
3723 return ((inst
<< 51) >> 63) << 5 |
3724 ((inst
<< 57) >> 61) << 2 |
3725 ((inst
<< 60) >> 62) << 6;
3728 static uint32_t operand_cimmldsp(rv_inst inst
)
3730 return ((inst
<< 51) >> 63) << 5 |
3731 ((inst
<< 57) >> 62) << 3 |
3732 ((inst
<< 59) >> 61) << 6;
3735 static uint32_t operand_cimmlqsp(rv_inst inst
)
3737 return ((inst
<< 51) >> 63) << 5 |
3738 ((inst
<< 57) >> 63) << 4 |
3739 ((inst
<< 58) >> 60) << 6;
3742 static int32_t operand_cimm16sp(rv_inst inst
)
3744 return (((int64_t)inst
<< 51) >> 63) << 9 |
3745 ((inst
<< 57) >> 63) << 4 |
3746 ((inst
<< 58) >> 63) << 6 |
3747 ((inst
<< 59) >> 62) << 7 |
3748 ((inst
<< 61) >> 63) << 5;
3751 static int32_t operand_cimmj(rv_inst inst
)
3753 return (((int64_t)inst
<< 51) >> 63) << 11 |
3754 ((inst
<< 52) >> 63) << 4 |
3755 ((inst
<< 53) >> 62) << 8 |
3756 ((inst
<< 55) >> 63) << 10 |
3757 ((inst
<< 56) >> 63) << 6 |
3758 ((inst
<< 57) >> 63) << 7 |
3759 ((inst
<< 58) >> 61) << 1 |
3760 ((inst
<< 61) >> 63) << 5;
3763 static int32_t operand_cimmb(rv_inst inst
)
3765 return (((int64_t)inst
<< 51) >> 63) << 8 |
3766 ((inst
<< 52) >> 62) << 3 |
3767 ((inst
<< 57) >> 62) << 6 |
3768 ((inst
<< 59) >> 62) << 1 |
3769 ((inst
<< 61) >> 63) << 5;
3772 static uint32_t operand_cimmswsp(rv_inst inst
)
3774 return ((inst
<< 51) >> 60) << 2 |
3775 ((inst
<< 55) >> 62) << 6;
3778 static uint32_t operand_cimmsdsp(rv_inst inst
)
3780 return ((inst
<< 51) >> 61) << 3 |
3781 ((inst
<< 54) >> 61) << 6;
3784 static uint32_t operand_cimmsqsp(rv_inst inst
)
3786 return ((inst
<< 51) >> 62) << 4 |
3787 ((inst
<< 53) >> 60) << 6;
3790 static uint32_t operand_cimm4spn(rv_inst inst
)
3792 return ((inst
<< 51) >> 62) << 4 |
3793 ((inst
<< 53) >> 60) << 6 |
3794 ((inst
<< 57) >> 63) << 2 |
3795 ((inst
<< 58) >> 63) << 3;
3798 static uint32_t operand_cimmw(rv_inst inst
)
3800 return ((inst
<< 51) >> 61) << 3 |
3801 ((inst
<< 57) >> 63) << 2 |
3802 ((inst
<< 58) >> 63) << 6;
3805 static uint32_t operand_cimmd(rv_inst inst
)
3807 return ((inst
<< 51) >> 61) << 3 |
3808 ((inst
<< 57) >> 62) << 6;
3811 static uint32_t operand_cimmq(rv_inst inst
)
3813 return ((inst
<< 51) >> 62) << 4 |
3814 ((inst
<< 53) >> 63) << 8 |
3815 ((inst
<< 57) >> 62) << 6;
3818 static uint32_t operand_vimm(rv_inst inst
)
3820 return (int64_t)(inst
<< 44) >> 59;
3823 static uint32_t operand_vzimm11(rv_inst inst
)
3825 return (inst
<< 33) >> 53;
3828 static uint32_t operand_vzimm10(rv_inst inst
)
3830 return (inst
<< 34) >> 54;
3833 static uint32_t operand_bs(rv_inst inst
)
3835 return (inst
<< 32) >> 62;
3838 static uint32_t operand_rnum(rv_inst inst
)
3840 return (inst
<< 40) >> 60;
3843 static uint32_t operand_vm(rv_inst inst
)
3845 return (inst
<< 38) >> 63;
3848 static uint32_t operand_uimm_c_lb(rv_inst inst
)
3850 return (((inst
<< 58) >> 63) << 1) |
3851 ((inst
<< 57) >> 63);
3854 static uint32_t operand_uimm_c_lh(rv_inst inst
)
3856 return (((inst
<< 58) >> 63) << 1);
3859 static uint32_t operand_zcmp_spimm(rv_inst inst
)
3861 return ((inst
<< 60) >> 62) << 4;
3864 static uint32_t operand_zcmp_rlist(rv_inst inst
)
3866 return ((inst
<< 56) >> 60);
3869 static uint32_t calculate_stack_adj(rv_isa isa
, uint32_t rlist
, uint32_t spimm
)
3871 int xlen_bytes_log2
= isa
== rv64
? 3 : 2;
3872 int regs
= rlist
== 15 ? 13 : rlist
- 3;
3873 uint32_t stack_adj_base
= ROUND_UP(regs
<< xlen_bytes_log2
, 16);
3874 return stack_adj_base
+ spimm
;
3877 static uint32_t operand_zcmp_stack_adj(rv_inst inst
, rv_isa isa
)
3879 return calculate_stack_adj(isa
, operand_zcmp_rlist(inst
),
3880 operand_zcmp_spimm(inst
));
3883 static uint32_t operand_tbl_index(rv_inst inst
)
3885 return ((inst
<< 54) >> 56);
3888 /* decode operands */
3890 static void decode_inst_operands(rv_decode
*dec
, rv_isa isa
)
3892 rv_inst inst
= dec
->inst
;
3893 dec
->codec
= opcode_data
[dec
->op
].codec
;
3894 switch (dec
->codec
) {
3896 dec
->rd
= dec
->rs1
= dec
->rs2
= rv_ireg_zero
;
3900 dec
->rd
= operand_rd(inst
);
3901 dec
->rs1
= dec
->rs2
= rv_ireg_zero
;
3902 dec
->imm
= operand_imm20(inst
);
3905 dec
->rd
= operand_rd(inst
);
3906 dec
->rs1
= dec
->rs2
= rv_ireg_zero
;
3907 dec
->imm
= operand_jimm20(inst
);
3910 dec
->rd
= operand_rd(inst
);
3911 dec
->rs1
= operand_rs1(inst
);
3912 dec
->rs2
= rv_ireg_zero
;
3913 dec
->imm
= operand_imm12(inst
);
3915 case rv_codec_i_sh5
:
3916 dec
->rd
= operand_rd(inst
);
3917 dec
->rs1
= operand_rs1(inst
);
3918 dec
->rs2
= rv_ireg_zero
;
3919 dec
->imm
= operand_shamt5(inst
);
3921 case rv_codec_i_sh6
:
3922 dec
->rd
= operand_rd(inst
);
3923 dec
->rs1
= operand_rs1(inst
);
3924 dec
->rs2
= rv_ireg_zero
;
3925 dec
->imm
= operand_shamt6(inst
);
3927 case rv_codec_i_sh7
:
3928 dec
->rd
= operand_rd(inst
);
3929 dec
->rs1
= operand_rs1(inst
);
3930 dec
->rs2
= rv_ireg_zero
;
3931 dec
->imm
= operand_shamt7(inst
);
3933 case rv_codec_i_csr
:
3934 dec
->rd
= operand_rd(inst
);
3935 dec
->rs1
= operand_rs1(inst
);
3936 dec
->rs2
= rv_ireg_zero
;
3937 dec
->imm
= operand_csr12(inst
);
3940 dec
->rd
= rv_ireg_zero
;
3941 dec
->rs1
= operand_rs1(inst
);
3942 dec
->rs2
= operand_rs2(inst
);
3943 dec
->imm
= operand_simm12(inst
);
3946 dec
->rd
= rv_ireg_zero
;
3947 dec
->rs1
= operand_rs1(inst
);
3948 dec
->rs2
= operand_rs2(inst
);
3949 dec
->imm
= operand_sbimm12(inst
);
3952 dec
->rd
= operand_rd(inst
);
3953 dec
->rs1
= operand_rs1(inst
);
3954 dec
->rs2
= operand_rs2(inst
);
3958 dec
->rd
= operand_rd(inst
);
3959 dec
->rs1
= operand_rs1(inst
);
3960 dec
->rs2
= operand_rs2(inst
);
3962 dec
->rm
= operand_rm(inst
);
3965 dec
->rd
= operand_rd(inst
);
3966 dec
->rs1
= operand_rs1(inst
);
3967 dec
->rs2
= operand_rs2(inst
);
3968 dec
->rs3
= operand_rs3(inst
);
3970 dec
->rm
= operand_rm(inst
);
3973 dec
->rd
= operand_rd(inst
);
3974 dec
->rs1
= operand_rs1(inst
);
3975 dec
->rs2
= operand_rs2(inst
);
3977 dec
->aq
= operand_aq(inst
);
3978 dec
->rl
= operand_rl(inst
);
3981 dec
->rd
= operand_rd(inst
);
3982 dec
->rs1
= operand_rs1(inst
);
3983 dec
->rs2
= rv_ireg_zero
;
3985 dec
->aq
= operand_aq(inst
);
3986 dec
->rl
= operand_rl(inst
);
3989 dec
->rd
= dec
->rs1
= dec
->rs2
= rv_ireg_zero
;
3990 dec
->pred
= operand_pred(inst
);
3991 dec
->succ
= operand_succ(inst
);
3995 dec
->rd
= rv_ireg_zero
;
3996 dec
->rs1
= operand_crs1q(inst
) + 8;
3997 dec
->rs2
= rv_ireg_zero
;
3998 dec
->imm
= operand_cimmb(inst
);
4000 case rv_codec_cb_imm
:
4001 dec
->rd
= dec
->rs1
= operand_crs1rdq(inst
) + 8;
4002 dec
->rs2
= rv_ireg_zero
;
4003 dec
->imm
= operand_cimmi(inst
);
4005 case rv_codec_cb_sh5
:
4006 dec
->rd
= dec
->rs1
= operand_crs1rdq(inst
) + 8;
4007 dec
->rs2
= rv_ireg_zero
;
4008 dec
->imm
= operand_cimmsh5(inst
);
4010 case rv_codec_cb_sh6
:
4011 dec
->rd
= dec
->rs1
= operand_crs1rdq(inst
) + 8;
4012 dec
->rs2
= rv_ireg_zero
;
4013 dec
->imm
= operand_cimmshr6(inst
, isa
);
4016 dec
->rd
= dec
->rs1
= operand_crs1rd(inst
);
4017 dec
->rs2
= rv_ireg_zero
;
4018 dec
->imm
= operand_cimmi(inst
);
4020 case rv_codec_ci_sh5
:
4021 dec
->rd
= dec
->rs1
= operand_crs1rd(inst
);
4022 dec
->rs2
= rv_ireg_zero
;
4023 dec
->imm
= operand_cimmsh5(inst
);
4025 case rv_codec_ci_sh6
:
4026 dec
->rd
= dec
->rs1
= operand_crs1rd(inst
);
4027 dec
->rs2
= rv_ireg_zero
;
4028 dec
->imm
= operand_cimmshl6(inst
, isa
);
4030 case rv_codec_ci_16sp
:
4031 dec
->rd
= rv_ireg_sp
;
4032 dec
->rs1
= rv_ireg_sp
;
4033 dec
->rs2
= rv_ireg_zero
;
4034 dec
->imm
= operand_cimm16sp(inst
);
4036 case rv_codec_ci_lwsp
:
4037 dec
->rd
= operand_crd(inst
);
4038 dec
->rs1
= rv_ireg_sp
;
4039 dec
->rs2
= rv_ireg_zero
;
4040 dec
->imm
= operand_cimmlwsp(inst
);
4042 case rv_codec_ci_ldsp
:
4043 dec
->rd
= operand_crd(inst
);
4044 dec
->rs1
= rv_ireg_sp
;
4045 dec
->rs2
= rv_ireg_zero
;
4046 dec
->imm
= operand_cimmldsp(inst
);
4048 case rv_codec_ci_lqsp
:
4049 dec
->rd
= operand_crd(inst
);
4050 dec
->rs1
= rv_ireg_sp
;
4051 dec
->rs2
= rv_ireg_zero
;
4052 dec
->imm
= operand_cimmlqsp(inst
);
4054 case rv_codec_ci_li
:
4055 dec
->rd
= operand_crd(inst
);
4056 dec
->rs1
= rv_ireg_zero
;
4057 dec
->rs2
= rv_ireg_zero
;
4058 dec
->imm
= operand_cimmi(inst
);
4060 case rv_codec_ci_lui
:
4061 dec
->rd
= operand_crd(inst
);
4062 dec
->rs1
= rv_ireg_zero
;
4063 dec
->rs2
= rv_ireg_zero
;
4064 dec
->imm
= operand_cimmui(inst
);
4066 case rv_codec_ci_none
:
4067 dec
->rd
= dec
->rs1
= dec
->rs2
= rv_ireg_zero
;
4070 case rv_codec_ciw_4spn
:
4071 dec
->rd
= operand_crdq(inst
) + 8;
4072 dec
->rs1
= rv_ireg_sp
;
4073 dec
->rs2
= rv_ireg_zero
;
4074 dec
->imm
= operand_cimm4spn(inst
);
4077 dec
->rd
= dec
->rs1
= dec
->rs2
= rv_ireg_zero
;
4078 dec
->imm
= operand_cimmj(inst
);
4080 case rv_codec_cj_jal
:
4081 dec
->rd
= rv_ireg_ra
;
4082 dec
->rs1
= dec
->rs2
= rv_ireg_zero
;
4083 dec
->imm
= operand_cimmj(inst
);
4085 case rv_codec_cl_lw
:
4086 dec
->rd
= operand_crdq(inst
) + 8;
4087 dec
->rs1
= operand_crs1q(inst
) + 8;
4088 dec
->rs2
= rv_ireg_zero
;
4089 dec
->imm
= operand_cimmw(inst
);
4091 case rv_codec_cl_ld
:
4092 dec
->rd
= operand_crdq(inst
) + 8;
4093 dec
->rs1
= operand_crs1q(inst
) + 8;
4094 dec
->rs2
= rv_ireg_zero
;
4095 dec
->imm
= operand_cimmd(inst
);
4097 case rv_codec_cl_lq
:
4098 dec
->rd
= operand_crdq(inst
) + 8;
4099 dec
->rs1
= operand_crs1q(inst
) + 8;
4100 dec
->rs2
= rv_ireg_zero
;
4101 dec
->imm
= operand_cimmq(inst
);
4104 dec
->rd
= dec
->rs1
= operand_crs1rd(inst
);
4105 dec
->rs2
= operand_crs2(inst
);
4108 case rv_codec_cr_mv
:
4109 dec
->rd
= operand_crd(inst
);
4110 dec
->rs1
= operand_crs2(inst
);
4111 dec
->rs2
= rv_ireg_zero
;
4114 case rv_codec_cr_jalr
:
4115 dec
->rd
= rv_ireg_ra
;
4116 dec
->rs1
= operand_crs1(inst
);
4117 dec
->rs2
= rv_ireg_zero
;
4120 case rv_codec_cr_jr
:
4121 dec
->rd
= rv_ireg_zero
;
4122 dec
->rs1
= operand_crs1(inst
);
4123 dec
->rs2
= rv_ireg_zero
;
4127 dec
->rd
= dec
->rs1
= operand_crs1rdq(inst
) + 8;
4128 dec
->rs2
= operand_crs2q(inst
) + 8;
4131 case rv_codec_cs_sw
:
4132 dec
->rd
= rv_ireg_zero
;
4133 dec
->rs1
= operand_crs1q(inst
) + 8;
4134 dec
->rs2
= operand_crs2q(inst
) + 8;
4135 dec
->imm
= operand_cimmw(inst
);
4137 case rv_codec_cs_sd
:
4138 dec
->rd
= rv_ireg_zero
;
4139 dec
->rs1
= operand_crs1q(inst
) + 8;
4140 dec
->rs2
= operand_crs2q(inst
) + 8;
4141 dec
->imm
= operand_cimmd(inst
);
4143 case rv_codec_cs_sq
:
4144 dec
->rd
= rv_ireg_zero
;
4145 dec
->rs1
= operand_crs1q(inst
) + 8;
4146 dec
->rs2
= operand_crs2q(inst
) + 8;
4147 dec
->imm
= operand_cimmq(inst
);
4149 case rv_codec_css_swsp
:
4150 dec
->rd
= rv_ireg_zero
;
4151 dec
->rs1
= rv_ireg_sp
;
4152 dec
->rs2
= operand_crs2(inst
);
4153 dec
->imm
= operand_cimmswsp(inst
);
4155 case rv_codec_css_sdsp
:
4156 dec
->rd
= rv_ireg_zero
;
4157 dec
->rs1
= rv_ireg_sp
;
4158 dec
->rs2
= operand_crs2(inst
);
4159 dec
->imm
= operand_cimmsdsp(inst
);
4161 case rv_codec_css_sqsp
:
4162 dec
->rd
= rv_ireg_zero
;
4163 dec
->rs1
= rv_ireg_sp
;
4164 dec
->rs2
= operand_crs2(inst
);
4165 dec
->imm
= operand_cimmsqsp(inst
);
4168 dec
->rs1
= operand_rs1(inst
);
4169 dec
->rs2
= operand_rs2(inst
);
4170 dec
->bs
= operand_bs(inst
);
4172 case rv_codec_k_rnum
:
4173 dec
->rd
= operand_rd(inst
);
4174 dec
->rs1
= operand_rs1(inst
);
4175 dec
->rnum
= operand_rnum(inst
);
4178 dec
->rd
= operand_rd(inst
);
4179 dec
->rs1
= operand_rs1(inst
);
4180 dec
->rs2
= operand_rs2(inst
);
4181 dec
->vm
= operand_vm(inst
);
4183 case rv_codec_v_ldst
:
4184 dec
->rd
= operand_rd(inst
);
4185 dec
->rs1
= operand_rs1(inst
);
4186 dec
->vm
= operand_vm(inst
);
4189 dec
->rd
= operand_rd(inst
);
4190 dec
->rs2
= operand_rs2(inst
);
4191 dec
->imm
= operand_vimm(inst
);
4192 dec
->vm
= operand_vm(inst
);
4194 case rv_codec_vsetvli
:
4195 dec
->rd
= operand_rd(inst
);
4196 dec
->rs1
= operand_rs1(inst
);
4197 dec
->vzimm
= operand_vzimm11(inst
);
4199 case rv_codec_vsetivli
:
4200 dec
->rd
= operand_rd(inst
);
4201 dec
->imm
= operand_vimm(inst
);
4202 dec
->vzimm
= operand_vzimm10(inst
);
4204 case rv_codec_zcb_lb
:
4205 dec
->rs1
= operand_crs1q(inst
) + 8;
4206 dec
->rs2
= operand_crs2q(inst
) + 8;
4207 dec
->imm
= operand_uimm_c_lb(inst
);
4209 case rv_codec_zcb_lh
:
4210 dec
->rs1
= operand_crs1q(inst
) + 8;
4211 dec
->rs2
= operand_crs2q(inst
) + 8;
4212 dec
->imm
= operand_uimm_c_lh(inst
);
4214 case rv_codec_zcb_ext
:
4215 dec
->rd
= operand_crs1q(inst
) + 8;
4217 case rv_codec_zcb_mul
:
4218 dec
->rd
= operand_crs1rdq(inst
) + 8;
4219 dec
->rs2
= operand_crs2q(inst
) + 8;
4221 case rv_codec_zcmp_cm_pushpop
:
4222 dec
->imm
= operand_zcmp_stack_adj(inst
, isa
);
4223 dec
->rlist
= operand_zcmp_rlist(inst
);
4225 case rv_codec_zcmp_cm_mv
:
4226 dec
->rd
= operand_sreg1(inst
);
4227 dec
->rs2
= operand_sreg2(inst
);
4229 case rv_codec_zcmt_jt
:
4230 dec
->imm
= operand_tbl_index(inst
);
4235 /* check constraint */
4237 static bool check_constraints(rv_decode
*dec
, const rvc_constraint
*c
)
4239 int32_t imm
= dec
->imm
;
4240 uint8_t rd
= dec
->rd
, rs1
= dec
->rs1
, rs2
= dec
->rs2
;
4241 while (*c
!= rvc_end
) {
4263 case rvc_rs2_eq_rs1
:
4264 if (!(rs2
== rs1
)) {
4273 case rvc_imm_eq_zero
:
4288 case rvc_csr_eq_0x001
:
4289 if (!(imm
== 0x001)) {
4293 case rvc_csr_eq_0x002
:
4294 if (!(imm
== 0x002)) {
4298 case rvc_csr_eq_0x003
:
4299 if (!(imm
== 0x003)) {
4303 case rvc_csr_eq_0xc00
:
4304 if (!(imm
== 0xc00)) {
4308 case rvc_csr_eq_0xc01
:
4309 if (!(imm
== 0xc01)) {
4313 case rvc_csr_eq_0xc02
:
4314 if (!(imm
== 0xc02)) {
4318 case rvc_csr_eq_0xc80
:
4319 if (!(imm
== 0xc80)) {
4323 case rvc_csr_eq_0xc81
:
4324 if (!(imm
== 0xc81)) {
4328 case rvc_csr_eq_0xc82
:
4329 if (!(imm
== 0xc82)) {
4340 /* instruction length */
4342 static size_t inst_length(rv_inst inst
)
4344 /* NOTE: supports maximum instruction size of 64-bits */
4347 * instruction length coding
4349 * aa - 16 bit aa != 11
4350 * bbb11 - 32 bit bbb != 111
4355 return (inst
& 0b11) != 0b11 ? 2
4356 : (inst
& 0b11100) != 0b11100 ? 4
4357 : (inst
& 0b111111) == 0b011111 ? 6
4358 : (inst
& 0b1111111) == 0b0111111 ? 8
4362 /* format instruction */
4364 static void append(char *s1
, const char *s2
, size_t n
)
4366 size_t l1
= strlen(s1
);
4367 if (n
- l1
- 1 > 0) {
4368 strncat(s1
, s2
, n
- l1
);
4372 static void format_inst(char *buf
, size_t buflen
, size_t tab
, rv_decode
*dec
)
4377 fmt
= opcode_data
[dec
->op
].format
;
4381 append(buf
, opcode_data
[dec
->op
].name
, buflen
);
4384 append(buf
, "(", buflen
);
4387 append(buf
, ",", buflen
);
4390 append(buf
, ")", buflen
);
4393 append(buf
, "-", buflen
);
4396 snprintf(tmp
, sizeof(tmp
), "%d", dec
->bs
);
4397 append(buf
, tmp
, buflen
);
4400 snprintf(tmp
, sizeof(tmp
), "%d", dec
->rnum
);
4401 append(buf
, tmp
, buflen
);
4404 append(buf
, rv_ireg_name_sym
[dec
->rd
], buflen
);
4407 append(buf
, rv_ireg_name_sym
[dec
->rs1
], buflen
);
4410 append(buf
, rv_ireg_name_sym
[dec
->rs2
], buflen
);
4413 append(buf
, dec
->cfg
->ext_zfinx
? rv_ireg_name_sym
[dec
->rd
] :
4414 rv_freg_name_sym
[dec
->rd
],
4418 append(buf
, dec
->cfg
->ext_zfinx
? rv_ireg_name_sym
[dec
->rs1
] :
4419 rv_freg_name_sym
[dec
->rs1
],
4423 append(buf
, dec
->cfg
->ext_zfinx
? rv_ireg_name_sym
[dec
->rs2
] :
4424 rv_freg_name_sym
[dec
->rs2
],
4428 append(buf
, dec
->cfg
->ext_zfinx
? rv_ireg_name_sym
[dec
->rs3
] :
4429 rv_freg_name_sym
[dec
->rs3
],
4433 snprintf(tmp
, sizeof(tmp
), "%d", dec
->rs1
);
4434 append(buf
, tmp
, buflen
);
4437 snprintf(tmp
, sizeof(tmp
), "%d", dec
->imm
);
4438 append(buf
, tmp
, buflen
);
4441 snprintf(tmp
, sizeof(tmp
), "%u", ((uint32_t)dec
->imm
& 0b11111));
4442 append(buf
, tmp
, buflen
);
4445 snprintf(tmp
, sizeof(tmp
), "%d", dec
->imm
);
4446 append(buf
, tmp
, buflen
);
4447 while (strlen(buf
) < tab
* 2) {
4448 append(buf
, " ", buflen
);
4450 snprintf(tmp
, sizeof(tmp
), "# 0x%" PRIx64
,
4451 dec
->pc
+ dec
->imm
);
4452 append(buf
, tmp
, buflen
);
4455 const char *name
= csr_name(dec
->imm
& 0xfff);
4457 append(buf
, name
, buflen
);
4459 snprintf(tmp
, sizeof(tmp
), "0x%03x", dec
->imm
& 0xfff);
4460 append(buf
, tmp
, buflen
);
4467 append(buf
, "rne", buflen
);
4470 append(buf
, "rtz", buflen
);
4473 append(buf
, "rdn", buflen
);
4476 append(buf
, "rup", buflen
);
4479 append(buf
, "rmm", buflen
);
4482 append(buf
, "dyn", buflen
);
4485 append(buf
, "inv", buflen
);
4490 if (dec
->pred
& rv_fence_i
) {
4491 append(buf
, "i", buflen
);
4493 if (dec
->pred
& rv_fence_o
) {
4494 append(buf
, "o", buflen
);
4496 if (dec
->pred
& rv_fence_r
) {
4497 append(buf
, "r", buflen
);
4499 if (dec
->pred
& rv_fence_w
) {
4500 append(buf
, "w", buflen
);
4504 if (dec
->succ
& rv_fence_i
) {
4505 append(buf
, "i", buflen
);
4507 if (dec
->succ
& rv_fence_o
) {
4508 append(buf
, "o", buflen
);
4510 if (dec
->succ
& rv_fence_r
) {
4511 append(buf
, "r", buflen
);
4513 if (dec
->succ
& rv_fence_w
) {
4514 append(buf
, "w", buflen
);
4518 while (strlen(buf
) < tab
) {
4519 append(buf
, " ", buflen
);
4524 append(buf
, ".aq", buflen
);
4529 append(buf
, ".rl", buflen
);
4533 append(buf
, ",v0", buflen
);
4537 append(buf
, ",v0.t", buflen
);
4541 append(buf
, rv_vreg_name_sym
[dec
->rd
], buflen
);
4544 append(buf
, rv_vreg_name_sym
[dec
->rs1
], buflen
);
4547 append(buf
, rv_vreg_name_sym
[dec
->rs2
], buflen
);
4550 append(buf
, rv_vreg_name_sym
[dec
->rs3
], buflen
);
4553 char nbuf
[32] = {0};
4554 const int sew
= 1 << (((dec
->vzimm
>> 3) & 0b111) + 3);
4555 sprintf(nbuf
, "%d", sew
);
4556 const int lmul
= dec
->vzimm
& 0b11;
4557 const int flmul
= (dec
->vzimm
>> 2) & 1;
4558 const char *vta
= (dec
->vzimm
>> 6) & 1 ? "ta" : "tu";
4559 const char *vma
= (dec
->vzimm
>> 7) & 1 ? "ma" : "mu";
4560 append(buf
, "e", buflen
);
4561 append(buf
, nbuf
, buflen
);
4562 append(buf
, ",m", buflen
);
4566 sprintf(nbuf
, "f2");
4569 sprintf(nbuf
, "f4");
4572 sprintf(nbuf
, "f8");
4575 append(buf
, nbuf
, buflen
);
4577 sprintf(nbuf
, "%d", 1 << lmul
);
4578 append(buf
, nbuf
, buflen
);
4580 append(buf
, ",", buflen
);
4581 append(buf
, vta
, buflen
);
4582 append(buf
, ",", buflen
);
4583 append(buf
, vma
, buflen
);
4587 switch (dec
->rlist
) {
4589 snprintf(tmp
, sizeof(tmp
), "{ra}");
4592 snprintf(tmp
, sizeof(tmp
), "{ra, s0}");
4595 snprintf(tmp
, sizeof(tmp
), "{ra, s0-s11}");
4598 snprintf(tmp
, sizeof(tmp
), "{ra, s0-s%d}", dec
->rlist
- 5);
4601 append(buf
, tmp
, buflen
);
4611 /* lift instruction to pseudo-instruction */
4613 static void decode_inst_lift_pseudo(rv_decode
*dec
)
4615 const rv_comp_data
*comp_data
= opcode_data
[dec
->op
].pseudo
;
4619 while (comp_data
->constraints
) {
4620 if (check_constraints(dec
, comp_data
->constraints
)) {
4621 dec
->op
= comp_data
->op
;
4622 dec
->codec
= opcode_data
[dec
->op
].codec
;
4629 /* decompress instruction */
4631 static void decode_inst_decompress_rv32(rv_decode
*dec
)
4633 int decomp_op
= opcode_data
[dec
->op
].decomp_rv32
;
4634 if (decomp_op
!= rv_op_illegal
) {
4635 if ((opcode_data
[dec
->op
].decomp_data
& rvcd_imm_nz
)
4637 dec
->op
= rv_op_illegal
;
4639 dec
->op
= decomp_op
;
4640 dec
->codec
= opcode_data
[decomp_op
].codec
;
4645 static void decode_inst_decompress_rv64(rv_decode
*dec
)
4647 int decomp_op
= opcode_data
[dec
->op
].decomp_rv64
;
4648 if (decomp_op
!= rv_op_illegal
) {
4649 if ((opcode_data
[dec
->op
].decomp_data
& rvcd_imm_nz
)
4651 dec
->op
= rv_op_illegal
;
4653 dec
->op
= decomp_op
;
4654 dec
->codec
= opcode_data
[decomp_op
].codec
;
4659 static void decode_inst_decompress_rv128(rv_decode
*dec
)
4661 int decomp_op
= opcode_data
[dec
->op
].decomp_rv128
;
4662 if (decomp_op
!= rv_op_illegal
) {
4663 if ((opcode_data
[dec
->op
].decomp_data
& rvcd_imm_nz
)
4665 dec
->op
= rv_op_illegal
;
4667 dec
->op
= decomp_op
;
4668 dec
->codec
= opcode_data
[decomp_op
].codec
;
4673 static void decode_inst_decompress(rv_decode
*dec
, rv_isa isa
)
4677 decode_inst_decompress_rv32(dec
);
4680 decode_inst_decompress_rv64(dec
);
4683 decode_inst_decompress_rv128(dec
);
4688 /* disassemble instruction */
4691 disasm_inst(char *buf
, size_t buflen
, rv_isa isa
, uint64_t pc
, rv_inst inst
,
4692 RISCVCPUConfig
*cfg
)
4694 rv_decode dec
= { 0 };
4698 decode_inst_opcode(&dec
, isa
);
4699 decode_inst_operands(&dec
, isa
);
4700 decode_inst_decompress(&dec
, isa
);
4701 decode_inst_lift_pseudo(&dec
);
4702 format_inst(buf
, buflen
, 24, &dec
);
4705 #define INST_FMT_2 "%04" PRIx64 " "
4706 #define INST_FMT_4 "%08" PRIx64 " "
4707 #define INST_FMT_6 "%012" PRIx64 " "
4708 #define INST_FMT_8 "%016" PRIx64 " "
4711 print_insn_riscv(bfd_vma memaddr
, struct disassemble_info
*info
, rv_isa isa
)
4713 char buf
[128] = { 0 };
4720 /* Instructions are made of 2-byte packets in little-endian order */
4721 for (n
= 0; n
< len
; n
+= 2) {
4722 status
= (*info
->read_memory_func
)(memaddr
+ n
, packet
, 2, info
);
4724 /* Don't fail just because we fell off the end. */
4728 (*info
->memory_error_func
)(status
, memaddr
, info
);
4731 inst
|= ((rv_inst
) bfd_getl16(packet
)) << (8 * n
);
4733 len
= inst_length(inst
);
4739 (*info
->fprintf_func
)(info
->stream
, INST_FMT_2
, inst
);
4742 (*info
->fprintf_func
)(info
->stream
, INST_FMT_4
, inst
);
4745 (*info
->fprintf_func
)(info
->stream
, INST_FMT_6
, inst
);
4748 (*info
->fprintf_func
)(info
->stream
, INST_FMT_8
, inst
);
4752 disasm_inst(buf
, sizeof(buf
), isa
, memaddr
, inst
,
4753 (RISCVCPUConfig
*)info
->target_info
);
4754 (*info
->fprintf_func
)(info
->stream
, "%s", buf
);
4759 int print_insn_riscv32(bfd_vma memaddr
, struct disassemble_info
*info
)
4761 return print_insn_riscv(memaddr
, info
, rv32
);
4764 int print_insn_riscv64(bfd_vma memaddr
, struct disassemble_info
*info
)
4766 return print_insn_riscv(memaddr
, info
, rv64
);
4769 int print_insn_riscv128(bfd_vma memaddr
, struct disassemble_info
*info
)
4771 return print_insn_riscv(memaddr
, info
, rv128
);