disas/riscv.c

   1 /*
   2  * QEMU RISC-V Disassembler
   3  *
   4  * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com>
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/bitops.h"
  22 #include "disas/dis-asm.h"
  23 #include "target/riscv/cpu_cfg.h"
  24 #include "disas/riscv.h"
  25
  26 /* Vendor extensions */
  27 #include "disas/riscv-xthead.h"
  28 #include "disas/riscv-xventana.h"
  29
  30 typedef enum {
  31     /* 0 is reserved for rv_op_illegal. */
  32     rv_op_lui = 1,
  33     rv_op_auipc = 2,
  34     rv_op_jal = 3,
  35     rv_op_jalr = 4,
  36     rv_op_beq = 5,
  37     rv_op_bne = 6,
  38     rv_op_blt = 7,
  39     rv_op_bge = 8,
  40     rv_op_bltu = 9,
  41     rv_op_bgeu = 10,
  42     rv_op_lb = 11,
  43     rv_op_lh = 12,
  44     rv_op_lw = 13,
  45     rv_op_lbu = 14,
  46     rv_op_lhu = 15,
  47     rv_op_sb = 16,
  48     rv_op_sh = 17,
  49     rv_op_sw = 18,
  50     rv_op_addi = 19,
  51     rv_op_slti = 20,
  52     rv_op_sltiu = 21,
  53     rv_op_xori = 22,
  54     rv_op_ori = 23,
  55     rv_op_andi = 24,
  56     rv_op_slli = 25,
  57     rv_op_srli = 26,
  58     rv_op_srai = 27,
  59     rv_op_add = 28,
  60     rv_op_sub = 29,
  61     rv_op_sll = 30,
  62     rv_op_slt = 31,
  63     rv_op_sltu = 32,
  64     rv_op_xor = 33,
  65     rv_op_srl = 34,
  66     rv_op_sra = 35,
  67     rv_op_or = 36,
  68     rv_op_and = 37,
  69     rv_op_fence = 38,
  70     rv_op_fence_i = 39,
  71     rv_op_lwu = 40,
  72     rv_op_ld = 41,
  73     rv_op_sd = 42,
  74     rv_op_addiw = 43,
  75     rv_op_slliw = 44,
  76     rv_op_srliw = 45,
  77     rv_op_sraiw = 46,
  78     rv_op_addw = 47,
  79     rv_op_subw = 48,
  80     rv_op_sllw = 49,
  81     rv_op_srlw = 50,
  82     rv_op_sraw = 51,
  83     rv_op_ldu = 52,
  84     rv_op_lq = 53,
  85     rv_op_sq = 54,
  86     rv_op_addid = 55,
  87     rv_op_sllid = 56,
  88     rv_op_srlid = 57,
  89     rv_op_sraid = 58,
  90     rv_op_addd = 59,
  91     rv_op_subd = 60,
  92     rv_op_slld = 61,
  93     rv_op_srld = 62,
  94     rv_op_srad = 63,
  95     rv_op_mul = 64,
  96     rv_op_mulh = 65,
  97     rv_op_mulhsu = 66,
  98     rv_op_mulhu = 67,
  99     rv_op_div = 68,
 100     rv_op_divu = 69,
 101     rv_op_rem = 70,
 102     rv_op_remu = 71,
 103     rv_op_mulw = 72,
 104     rv_op_divw = 73,
 105     rv_op_divuw = 74,
 106     rv_op_remw = 75,
 107     rv_op_remuw = 76,
 108     rv_op_muld = 77,
 109     rv_op_divd = 78,
 110     rv_op_divud = 79,
 111     rv_op_remd = 80,
 112     rv_op_remud = 81,
 113     rv_op_lr_w = 82,
 114     rv_op_sc_w = 83,
 115     rv_op_amoswap_w = 84,
 116     rv_op_amoadd_w = 85,
 117     rv_op_amoxor_w = 86,
 118     rv_op_amoor_w = 87,
 119     rv_op_amoand_w = 88,
 120     rv_op_amomin_w = 89,
 121     rv_op_amomax_w = 90,
 122     rv_op_amominu_w = 91,
 123     rv_op_amomaxu_w = 92,
 124     rv_op_lr_d = 93,
 125     rv_op_sc_d = 94,
 126     rv_op_amoswap_d = 95,
 127     rv_op_amoadd_d = 96,
 128     rv_op_amoxor_d = 97,
 129     rv_op_amoor_d = 98,
 130     rv_op_amoand_d = 99,
 131     rv_op_amomin_d = 100,
 132     rv_op_amomax_d = 101,
 133     rv_op_amominu_d = 102,
 134     rv_op_amomaxu_d = 103,
 135     rv_op_lr_q = 104,
 136     rv_op_sc_q = 105,
 137     rv_op_amoswap_q = 106,
 138     rv_op_amoadd_q = 107,
 139     rv_op_amoxor_q = 108,
 140     rv_op_amoor_q = 109,
 141     rv_op_amoand_q = 110,
 142     rv_op_amomin_q = 111,
 143     rv_op_amomax_q = 112,
 144     rv_op_amominu_q = 113,
 145     rv_op_amomaxu_q = 114,
 146     rv_op_ecall = 115,
 147     rv_op_ebreak = 116,
 148     rv_op_uret = 117,
 149     rv_op_sret = 118,
 150     rv_op_hret = 119,
 151     rv_op_mret = 120,
 152     rv_op_dret = 121,
 153     rv_op_sfence_vm = 122,
 154     rv_op_sfence_vma = 123,
 155     rv_op_wfi = 124,
 156     rv_op_csrrw = 125,
 157     rv_op_csrrs = 126,
 158     rv_op_csrrc = 127,
 159     rv_op_csrrwi = 128,
 160     rv_op_csrrsi = 129,
 161     rv_op_csrrci = 130,
 162     rv_op_flw = 131,
 163     rv_op_fsw = 132,
 164     rv_op_fmadd_s = 133,
 165     rv_op_fmsub_s = 134,
 166     rv_op_fnmsub_s = 135,
 167     rv_op_fnmadd_s = 136,
 168     rv_op_fadd_s = 137,
 169     rv_op_fsub_s = 138,
 170     rv_op_fmul_s = 139,
 171     rv_op_fdiv_s = 140,
 172     rv_op_fsgnj_s = 141,
 173     rv_op_fsgnjn_s = 142,
 174     rv_op_fsgnjx_s = 143,
 175     rv_op_fmin_s = 144,
 176     rv_op_fmax_s = 145,
 177     rv_op_fsqrt_s = 146,
 178     rv_op_fle_s = 147,
 179     rv_op_flt_s = 148,
 180     rv_op_feq_s = 149,
 181     rv_op_fcvt_w_s = 150,
 182     rv_op_fcvt_wu_s = 151,
 183     rv_op_fcvt_s_w = 152,
 184     rv_op_fcvt_s_wu = 153,
 185     rv_op_fmv_x_s = 154,
 186     rv_op_fclass_s = 155,
 187     rv_op_fmv_s_x = 156,
 188     rv_op_fcvt_l_s = 157,
 189     rv_op_fcvt_lu_s = 158,
 190     rv_op_fcvt_s_l = 159,
 191     rv_op_fcvt_s_lu = 160,
 192     rv_op_fld = 161,
 193     rv_op_fsd = 162,
 194     rv_op_fmadd_d = 163,
 195     rv_op_fmsub_d = 164,
 196     rv_op_fnmsub_d = 165,
 197     rv_op_fnmadd_d = 166,
 198     rv_op_fadd_d = 167,
 199     rv_op_fsub_d = 168,
 200     rv_op_fmul_d = 169,
 201     rv_op_fdiv_d = 170,
 202     rv_op_fsgnj_d = 171,
 203     rv_op_fsgnjn_d = 172,
 204     rv_op_fsgnjx_d = 173,
 205     rv_op_fmin_d = 174,
 206     rv_op_fmax_d = 175,
 207     rv_op_fcvt_s_d = 176,
 208     rv_op_fcvt_d_s = 177,
 209     rv_op_fsqrt_d = 178,
 210     rv_op_fle_d = 179,
 211     rv_op_flt_d = 180,
 212     rv_op_feq_d = 181,
 213     rv_op_fcvt_w_d = 182,
 214     rv_op_fcvt_wu_d = 183,
 215     rv_op_fcvt_d_w = 184,
 216     rv_op_fcvt_d_wu = 185,
 217     rv_op_fclass_d = 186,
 218     rv_op_fcvt_l_d = 187,
 219     rv_op_fcvt_lu_d = 188,
 220     rv_op_fmv_x_d = 189,
 221     rv_op_fcvt_d_l = 190,
 222     rv_op_fcvt_d_lu = 191,
 223     rv_op_fmv_d_x = 192,
 224     rv_op_flq = 193,
 225     rv_op_fsq = 194,
 226     rv_op_fmadd_q = 195,
 227     rv_op_fmsub_q = 196,
 228     rv_op_fnmsub_q = 197,
 229     rv_op_fnmadd_q = 198,
 230     rv_op_fadd_q = 199,
 231     rv_op_fsub_q = 200,
 232     rv_op_fmul_q = 201,
 233     rv_op_fdiv_q = 202,
 234     rv_op_fsgnj_q = 203,
 235     rv_op_fsgnjn_q = 204,
 236     rv_op_fsgnjx_q = 205,
 237     rv_op_fmin_q = 206,
 238     rv_op_fmax_q = 207,
 239     rv_op_fcvt_s_q = 208,
 240     rv_op_fcvt_q_s = 209,
 241     rv_op_fcvt_d_q = 210,
 242     rv_op_fcvt_q_d = 211,
 243     rv_op_fsqrt_q = 212,
 244     rv_op_fle_q = 213,
 245     rv_op_flt_q = 214,
 246     rv_op_feq_q = 215,
 247     rv_op_fcvt_w_q = 216,
 248     rv_op_fcvt_wu_q = 217,
 249     rv_op_fcvt_q_w = 218,
 250     rv_op_fcvt_q_wu = 219,
 251     rv_op_fclass_q = 220,
 252     rv_op_fcvt_l_q = 221,
 253     rv_op_fcvt_lu_q = 222,
 254     rv_op_fcvt_q_l = 223,
 255     rv_op_fcvt_q_lu = 224,
 256     rv_op_fmv_x_q = 225,
 257     rv_op_fmv_q_x = 226,
 258     rv_op_c_addi4spn = 227,
 259     rv_op_c_fld = 228,
 260     rv_op_c_lw = 229,
 261     rv_op_c_flw = 230,
 262     rv_op_c_fsd = 231,
 263     rv_op_c_sw = 232,
 264     rv_op_c_fsw = 233,
 265     rv_op_c_nop = 234,
 266     rv_op_c_addi = 235,
 267     rv_op_c_jal = 236,
 268     rv_op_c_li = 237,
 269     rv_op_c_addi16sp = 238,
 270     rv_op_c_lui = 239,
 271     rv_op_c_srli = 240,
 272     rv_op_c_srai = 241,
 273     rv_op_c_andi = 242,
 274     rv_op_c_sub = 243,
 275     rv_op_c_xor = 244,
 276     rv_op_c_or = 245,
 277     rv_op_c_and = 246,
 278     rv_op_c_subw = 247,
 279     rv_op_c_addw = 248,
 280     rv_op_c_j = 249,
 281     rv_op_c_beqz = 250,
 282     rv_op_c_bnez = 251,
 283     rv_op_c_slli = 252,
 284     rv_op_c_fldsp = 253,
 285     rv_op_c_lwsp = 254,
 286     rv_op_c_flwsp = 255,
 287     rv_op_c_jr = 256,
 288     rv_op_c_mv = 257,
 289     rv_op_c_ebreak = 258,
 290     rv_op_c_jalr = 259,
 291     rv_op_c_add = 260,
 292     rv_op_c_fsdsp = 261,
 293     rv_op_c_swsp = 262,
 294     rv_op_c_fswsp = 263,
 295     rv_op_c_ld = 264,
 296     rv_op_c_sd = 265,
 297     rv_op_c_addiw = 266,
 298     rv_op_c_ldsp = 267,
 299     rv_op_c_sdsp = 268,
 300     rv_op_c_lq = 269,
 301     rv_op_c_sq = 270,
 302     rv_op_c_lqsp = 271,
 303     rv_op_c_sqsp = 272,
 304     rv_op_nop = 273,
 305     rv_op_mv = 274,
 306     rv_op_not = 275,
 307     rv_op_neg = 276,
 308     rv_op_negw = 277,
 309     rv_op_sext_w = 278,
 310     rv_op_seqz = 279,
 311     rv_op_snez = 280,
 312     rv_op_sltz = 281,
 313     rv_op_sgtz = 282,
 314     rv_op_fmv_s = 283,
 315     rv_op_fabs_s = 284,
 316     rv_op_fneg_s = 285,
 317     rv_op_fmv_d = 286,
 318     rv_op_fabs_d = 287,
 319     rv_op_fneg_d = 288,
 320     rv_op_fmv_q = 289,
 321     rv_op_fabs_q = 290,
 322     rv_op_fneg_q = 291,
 323     rv_op_beqz = 292,
 324     rv_op_bnez = 293,
 325     rv_op_blez = 294,
 326     rv_op_bgez = 295,
 327     rv_op_bltz = 296,
 328     rv_op_bgtz = 297,
 329     rv_op_ble = 298,
 330     rv_op_bleu = 299,
 331     rv_op_bgt = 300,
 332     rv_op_bgtu = 301,
 333     rv_op_j = 302,
 334     rv_op_ret = 303,
 335     rv_op_jr = 304,
 336     rv_op_rdcycle = 305,
 337     rv_op_rdtime = 306,
 338     rv_op_rdinstret = 307,
 339     rv_op_rdcycleh = 308,
 340     rv_op_rdtimeh = 309,
 341     rv_op_rdinstreth = 310,
 342     rv_op_frcsr = 311,
 343     rv_op_frrm = 312,
 344     rv_op_frflags = 313,
 345     rv_op_fscsr = 314,
 346     rv_op_fsrm = 315,
 347     rv_op_fsflags = 316,
 348     rv_op_fsrmi = 317,
 349     rv_op_fsflagsi = 318,
 350     rv_op_bseti = 319,
 351     rv_op_bclri = 320,
 352     rv_op_binvi = 321,
 353     rv_op_bexti = 322,
 354     rv_op_rori = 323,
 355     rv_op_clz = 324,
 356     rv_op_ctz = 325,
 357     rv_op_cpop = 326,
 358     rv_op_sext_h = 327,
 359     rv_op_sext_b = 328,
 360     rv_op_xnor = 329,
 361     rv_op_orn = 330,
 362     rv_op_andn = 331,
 363     rv_op_rol = 332,
 364     rv_op_ror = 333,
 365     rv_op_sh1add = 334,
 366     rv_op_sh2add = 335,
 367     rv_op_sh3add = 336,
 368     rv_op_sh1add_uw = 337,
 369     rv_op_sh2add_uw = 338,
 370     rv_op_sh3add_uw = 339,
 371     rv_op_clmul = 340,
 372     rv_op_clmulr = 341,
 373     rv_op_clmulh = 342,
 374     rv_op_min = 343,
 375     rv_op_minu = 344,
 376     rv_op_max = 345,
 377     rv_op_maxu = 346,
 378     rv_op_clzw = 347,
 379     rv_op_ctzw = 348,
 380     rv_op_cpopw = 349,
 381     rv_op_slli_uw = 350,
 382     rv_op_add_uw = 351,
 383     rv_op_rolw = 352,
 384     rv_op_rorw = 353,
 385     rv_op_rev8 = 354,
 386     rv_op_zext_h = 355,
 387     rv_op_roriw = 356,
 388     rv_op_orc_b = 357,
 389     rv_op_bset = 358,
 390     rv_op_bclr = 359,
 391     rv_op_binv = 360,
 392     rv_op_bext = 361,
 393     rv_op_aes32esmi = 362,
 394     rv_op_aes32esi = 363,
 395     rv_op_aes32dsmi = 364,
 396     rv_op_aes32dsi = 365,
 397     rv_op_aes64ks1i = 366,
 398     rv_op_aes64ks2 = 367,
 399     rv_op_aes64im = 368,
 400     rv_op_aes64esm = 369,
 401     rv_op_aes64es = 370,
 402     rv_op_aes64dsm = 371,
 403     rv_op_aes64ds = 372,
 404     rv_op_sha256sig0 = 373,
 405     rv_op_sha256sig1 = 374,
 406     rv_op_sha256sum0 = 375,
 407     rv_op_sha256sum1 = 376,
 408     rv_op_sha512sig0 = 377,
 409     rv_op_sha512sig1 = 378,
 410     rv_op_sha512sum0 = 379,
 411     rv_op_sha512sum1 = 380,
 412     rv_op_sha512sum0r = 381,
 413     rv_op_sha512sum1r = 382,
 414     rv_op_sha512sig0l = 383,
 415     rv_op_sha512sig0h = 384,
 416     rv_op_sha512sig1l = 385,
 417     rv_op_sha512sig1h = 386,
 418     rv_op_sm3p0 = 387,
 419     rv_op_sm3p1 = 388,
 420     rv_op_sm4ed = 389,
 421     rv_op_sm4ks = 390,
 422     rv_op_brev8 = 391,
 423     rv_op_pack = 392,
 424     rv_op_packh = 393,
 425     rv_op_packw = 394,
 426     rv_op_unzip = 395,
 427     rv_op_zip = 396,
 428     rv_op_xperm4 = 397,
 429     rv_op_xperm8 = 398,
 430     rv_op_vle8_v = 399,
 431     rv_op_vle16_v = 400,
 432     rv_op_vle32_v = 401,
 433     rv_op_vle64_v = 402,
 434     rv_op_vse8_v = 403,
 435     rv_op_vse16_v = 404,
 436     rv_op_vse32_v = 405,
 437     rv_op_vse64_v = 406,
 438     rv_op_vlm_v = 407,
 439     rv_op_vsm_v = 408,
 440     rv_op_vlse8_v = 409,
 441     rv_op_vlse16_v = 410,
 442     rv_op_vlse32_v = 411,
 443     rv_op_vlse64_v = 412,
 444     rv_op_vsse8_v = 413,
 445     rv_op_vsse16_v = 414,
 446     rv_op_vsse32_v = 415,
 447     rv_op_vsse64_v = 416,
 448     rv_op_vluxei8_v = 417,
 449     rv_op_vluxei16_v = 418,
 450     rv_op_vluxei32_v = 419,
 451     rv_op_vluxei64_v = 420,
 452     rv_op_vloxei8_v = 421,
 453     rv_op_vloxei16_v = 422,
 454     rv_op_vloxei32_v = 423,
 455     rv_op_vloxei64_v = 424,
 456     rv_op_vsuxei8_v = 425,
 457     rv_op_vsuxei16_v = 426,
 458     rv_op_vsuxei32_v = 427,
 459     rv_op_vsuxei64_v = 428,
 460     rv_op_vsoxei8_v = 429,
 461     rv_op_vsoxei16_v = 430,
 462     rv_op_vsoxei32_v = 431,
 463     rv_op_vsoxei64_v = 432,
 464     rv_op_vle8ff_v = 433,
 465     rv_op_vle16ff_v = 434,
 466     rv_op_vle32ff_v = 435,
 467     rv_op_vle64ff_v = 436,
 468     rv_op_vl1re8_v = 437,
 469     rv_op_vl1re16_v = 438,
 470     rv_op_vl1re32_v = 439,
 471     rv_op_vl1re64_v = 440,
 472     rv_op_vl2re8_v = 441,
 473     rv_op_vl2re16_v = 442,
 474     rv_op_vl2re32_v = 443,
 475     rv_op_vl2re64_v = 444,
 476     rv_op_vl4re8_v = 445,
 477     rv_op_vl4re16_v = 446,
 478     rv_op_vl4re32_v = 447,
 479     rv_op_vl4re64_v = 448,
 480     rv_op_vl8re8_v = 449,
 481     rv_op_vl8re16_v = 450,
 482     rv_op_vl8re32_v = 451,
 483     rv_op_vl8re64_v = 452,
 484     rv_op_vs1r_v = 453,
 485     rv_op_vs2r_v = 454,
 486     rv_op_vs4r_v = 455,
 487     rv_op_vs8r_v = 456,
 488     rv_op_vadd_vv = 457,
 489     rv_op_vadd_vx = 458,
 490     rv_op_vadd_vi = 459,
 491     rv_op_vsub_vv = 460,
 492     rv_op_vsub_vx = 461,
 493     rv_op_vrsub_vx = 462,
 494     rv_op_vrsub_vi = 463,
 495     rv_op_vwaddu_vv = 464,
 496     rv_op_vwaddu_vx = 465,
 497     rv_op_vwadd_vv = 466,
 498     rv_op_vwadd_vx = 467,
 499     rv_op_vwsubu_vv = 468,
 500     rv_op_vwsubu_vx = 469,
 501     rv_op_vwsub_vv = 470,
 502     rv_op_vwsub_vx = 471,
 503     rv_op_vwaddu_wv = 472,
 504     rv_op_vwaddu_wx = 473,
 505     rv_op_vwadd_wv = 474,
 506     rv_op_vwadd_wx = 475,
 507     rv_op_vwsubu_wv = 476,
 508     rv_op_vwsubu_wx = 477,
 509     rv_op_vwsub_wv = 478,
 510     rv_op_vwsub_wx = 479,
 511     rv_op_vadc_vvm = 480,
 512     rv_op_vadc_vxm = 481,
 513     rv_op_vadc_vim = 482,
 514     rv_op_vmadc_vvm = 483,
 515     rv_op_vmadc_vxm = 484,
 516     rv_op_vmadc_vim = 485,
 517     rv_op_vsbc_vvm = 486,
 518     rv_op_vsbc_vxm = 487,
 519     rv_op_vmsbc_vvm = 488,
 520     rv_op_vmsbc_vxm = 489,
 521     rv_op_vand_vv = 490,
 522     rv_op_vand_vx = 491,
 523     rv_op_vand_vi = 492,
 524     rv_op_vor_vv = 493,
 525     rv_op_vor_vx = 494,
 526     rv_op_vor_vi = 495,
 527     rv_op_vxor_vv = 496,
 528     rv_op_vxor_vx = 497,
 529     rv_op_vxor_vi = 498,
 530     rv_op_vsll_vv = 499,
 531     rv_op_vsll_vx = 500,
 532     rv_op_vsll_vi = 501,
 533     rv_op_vsrl_vv = 502,
 534     rv_op_vsrl_vx = 503,
 535     rv_op_vsrl_vi = 504,
 536     rv_op_vsra_vv = 505,
 537     rv_op_vsra_vx = 506,
 538     rv_op_vsra_vi = 507,
 539     rv_op_vnsrl_wv = 508,
 540     rv_op_vnsrl_wx = 509,
 541     rv_op_vnsrl_wi = 510,
 542     rv_op_vnsra_wv = 511,
 543     rv_op_vnsra_wx = 512,
 544     rv_op_vnsra_wi = 513,
 545     rv_op_vmseq_vv = 514,
 546     rv_op_vmseq_vx = 515,
 547     rv_op_vmseq_vi = 516,
 548     rv_op_vmsne_vv = 517,
 549     rv_op_vmsne_vx = 518,
 550     rv_op_vmsne_vi = 519,
 551     rv_op_vmsltu_vv = 520,
 552     rv_op_vmsltu_vx = 521,
 553     rv_op_vmslt_vv = 522,
 554     rv_op_vmslt_vx = 523,
 555     rv_op_vmsleu_vv = 524,
 556     rv_op_vmsleu_vx = 525,
 557     rv_op_vmsleu_vi = 526,
 558     rv_op_vmsle_vv = 527,
 559     rv_op_vmsle_vx = 528,
 560     rv_op_vmsle_vi = 529,
 561     rv_op_vmsgtu_vx = 530,
 562     rv_op_vmsgtu_vi = 531,
 563     rv_op_vmsgt_vx = 532,
 564     rv_op_vmsgt_vi = 533,
 565     rv_op_vminu_vv = 534,
 566     rv_op_vminu_vx = 535,
 567     rv_op_vmin_vv = 536,
 568     rv_op_vmin_vx = 537,
 569     rv_op_vmaxu_vv = 538,
 570     rv_op_vmaxu_vx = 539,
 571     rv_op_vmax_vv = 540,
 572     rv_op_vmax_vx = 541,
 573     rv_op_vmul_vv = 542,
 574     rv_op_vmul_vx = 543,
 575     rv_op_vmulh_vv = 544,
 576     rv_op_vmulh_vx = 545,
 577     rv_op_vmulhu_vv = 546,
 578     rv_op_vmulhu_vx = 547,
 579     rv_op_vmulhsu_vv = 548,
 580     rv_op_vmulhsu_vx = 549,
 581     rv_op_vdivu_vv = 550,
 582     rv_op_vdivu_vx = 551,
 583     rv_op_vdiv_vv = 552,
 584     rv_op_vdiv_vx = 553,
 585     rv_op_vremu_vv = 554,
 586     rv_op_vremu_vx = 555,
 587     rv_op_vrem_vv = 556,
 588     rv_op_vrem_vx = 557,
 589     rv_op_vwmulu_vv = 558,
 590     rv_op_vwmulu_vx = 559,
 591     rv_op_vwmulsu_vv = 560,
 592     rv_op_vwmulsu_vx = 561,
 593     rv_op_vwmul_vv = 562,
 594     rv_op_vwmul_vx = 563,
 595     rv_op_vmacc_vv = 564,
 596     rv_op_vmacc_vx = 565,
 597     rv_op_vnmsac_vv = 566,
 598     rv_op_vnmsac_vx = 567,
 599     rv_op_vmadd_vv = 568,
 600     rv_op_vmadd_vx = 569,
 601     rv_op_vnmsub_vv = 570,
 602     rv_op_vnmsub_vx = 571,
 603     rv_op_vwmaccu_vv = 572,
 604     rv_op_vwmaccu_vx = 573,
 605     rv_op_vwmacc_vv = 574,
 606     rv_op_vwmacc_vx = 575,
 607     rv_op_vwmaccsu_vv = 576,
 608     rv_op_vwmaccsu_vx = 577,
 609     rv_op_vwmaccus_vx = 578,
 610     rv_op_vmv_v_v = 579,
 611     rv_op_vmv_v_x = 580,
 612     rv_op_vmv_v_i = 581,
 613     rv_op_vmerge_vvm = 582,
 614     rv_op_vmerge_vxm = 583,
 615     rv_op_vmerge_vim = 584,
 616     rv_op_vsaddu_vv = 585,
 617     rv_op_vsaddu_vx = 586,
 618     rv_op_vsaddu_vi = 587,
 619     rv_op_vsadd_vv = 588,
 620     rv_op_vsadd_vx = 589,
 621     rv_op_vsadd_vi = 590,
 622     rv_op_vssubu_vv = 591,
 623     rv_op_vssubu_vx = 592,
 624     rv_op_vssub_vv = 593,
 625     rv_op_vssub_vx = 594,
 626     rv_op_vaadd_vv = 595,
 627     rv_op_vaadd_vx = 596,
 628     rv_op_vaaddu_vv = 597,
 629     rv_op_vaaddu_vx = 598,
 630     rv_op_vasub_vv = 599,
 631     rv_op_vasub_vx = 600,
 632     rv_op_vasubu_vv = 601,
 633     rv_op_vasubu_vx = 602,
 634     rv_op_vsmul_vv = 603,
 635     rv_op_vsmul_vx = 604,
 636     rv_op_vssrl_vv = 605,
 637     rv_op_vssrl_vx = 606,
 638     rv_op_vssrl_vi = 607,
 639     rv_op_vssra_vv = 608,
 640     rv_op_vssra_vx = 609,
 641     rv_op_vssra_vi = 610,
 642     rv_op_vnclipu_wv = 611,
 643     rv_op_vnclipu_wx = 612,
 644     rv_op_vnclipu_wi = 613,
 645     rv_op_vnclip_wv = 614,
 646     rv_op_vnclip_wx = 615,
 647     rv_op_vnclip_wi = 616,
 648     rv_op_vfadd_vv = 617,
 649     rv_op_vfadd_vf = 618,
 650     rv_op_vfsub_vv = 619,
 651     rv_op_vfsub_vf = 620,
 652     rv_op_vfrsub_vf = 621,
 653     rv_op_vfwadd_vv = 622,
 654     rv_op_vfwadd_vf = 623,
 655     rv_op_vfwadd_wv = 624,
 656     rv_op_vfwadd_wf = 625,
 657     rv_op_vfwsub_vv = 626,
 658     rv_op_vfwsub_vf = 627,
 659     rv_op_vfwsub_wv = 628,
 660     rv_op_vfwsub_wf = 629,
 661     rv_op_vfmul_vv = 630,
 662     rv_op_vfmul_vf = 631,
 663     rv_op_vfdiv_vv = 632,
 664     rv_op_vfdiv_vf = 633,
 665     rv_op_vfrdiv_vf = 634,
 666     rv_op_vfwmul_vv = 635,
 667     rv_op_vfwmul_vf = 636,
 668     rv_op_vfmacc_vv = 637,
 669     rv_op_vfmacc_vf = 638,
 670     rv_op_vfnmacc_vv = 639,
 671     rv_op_vfnmacc_vf = 640,
 672     rv_op_vfmsac_vv = 641,
 673     rv_op_vfmsac_vf = 642,
 674     rv_op_vfnmsac_vv = 643,
 675     rv_op_vfnmsac_vf = 644,
 676     rv_op_vfmadd_vv = 645,
 677     rv_op_vfmadd_vf = 646,
 678     rv_op_vfnmadd_vv = 647,
 679     rv_op_vfnmadd_vf = 648,
 680     rv_op_vfmsub_vv = 649,
 681     rv_op_vfmsub_vf = 650,
 682     rv_op_vfnmsub_vv = 651,
 683     rv_op_vfnmsub_vf = 652,
 684     rv_op_vfwmacc_vv = 653,
 685     rv_op_vfwmacc_vf = 654,
 686     rv_op_vfwnmacc_vv = 655,
 687     rv_op_vfwnmacc_vf = 656,
 688     rv_op_vfwmsac_vv = 657,
 689     rv_op_vfwmsac_vf = 658,
 690     rv_op_vfwnmsac_vv = 659,
 691     rv_op_vfwnmsac_vf = 660,
 692     rv_op_vfsqrt_v = 661,
 693     rv_op_vfrsqrt7_v = 662,
 694     rv_op_vfrec7_v = 663,
 695     rv_op_vfmin_vv = 664,
 696     rv_op_vfmin_vf = 665,
 697     rv_op_vfmax_vv = 666,
 698     rv_op_vfmax_vf = 667,
 699     rv_op_vfsgnj_vv = 668,
 700     rv_op_vfsgnj_vf = 669,
 701     rv_op_vfsgnjn_vv = 670,
 702     rv_op_vfsgnjn_vf = 671,
 703     rv_op_vfsgnjx_vv = 672,
 704     rv_op_vfsgnjx_vf = 673,
 705     rv_op_vfslide1up_vf = 674,
 706     rv_op_vfslide1down_vf = 675,
 707     rv_op_vmfeq_vv = 676,
 708     rv_op_vmfeq_vf = 677,
 709     rv_op_vmfne_vv = 678,
 710     rv_op_vmfne_vf = 679,
 711     rv_op_vmflt_vv = 680,
 712     rv_op_vmflt_vf = 681,
 713     rv_op_vmfle_vv = 682,
 714     rv_op_vmfle_vf = 683,
 715     rv_op_vmfgt_vf = 684,
 716     rv_op_vmfge_vf = 685,
 717     rv_op_vfclass_v = 686,
 718     rv_op_vfmerge_vfm = 687,
 719     rv_op_vfmv_v_f = 688,
 720     rv_op_vfcvt_xu_f_v = 689,
 721     rv_op_vfcvt_x_f_v = 690,
 722     rv_op_vfcvt_f_xu_v = 691,
 723     rv_op_vfcvt_f_x_v = 692,
 724     rv_op_vfcvt_rtz_xu_f_v = 693,
 725     rv_op_vfcvt_rtz_x_f_v = 694,
 726     rv_op_vfwcvt_xu_f_v = 695,
 727     rv_op_vfwcvt_x_f_v = 696,
 728     rv_op_vfwcvt_f_xu_v = 697,
 729     rv_op_vfwcvt_f_x_v = 698,
 730     rv_op_vfwcvt_f_f_v = 699,
 731     rv_op_vfwcvt_rtz_xu_f_v = 700,
 732     rv_op_vfwcvt_rtz_x_f_v = 701,
 733     rv_op_vfncvt_xu_f_w = 702,
 734     rv_op_vfncvt_x_f_w = 703,
 735     rv_op_vfncvt_f_xu_w = 704,
 736     rv_op_vfncvt_f_x_w = 705,
 737     rv_op_vfncvt_f_f_w = 706,
 738     rv_op_vfncvt_rod_f_f_w = 707,
 739     rv_op_vfncvt_rtz_xu_f_w = 708,
 740     rv_op_vfncvt_rtz_x_f_w = 709,
 741     rv_op_vredsum_vs = 710,
 742     rv_op_vredand_vs = 711,
 743     rv_op_vredor_vs = 712,
 744     rv_op_vredxor_vs = 713,
 745     rv_op_vredminu_vs = 714,
 746     rv_op_vredmin_vs = 715,
 747     rv_op_vredmaxu_vs = 716,
 748     rv_op_vredmax_vs = 717,
 749     rv_op_vwredsumu_vs = 718,
 750     rv_op_vwredsum_vs = 719,
 751     rv_op_vfredusum_vs = 720,
 752     rv_op_vfredosum_vs = 721,
 753     rv_op_vfredmin_vs = 722,
 754     rv_op_vfredmax_vs = 723,
 755     rv_op_vfwredusum_vs = 724,
 756     rv_op_vfwredosum_vs = 725,
 757     rv_op_vmand_mm = 726,
 758     rv_op_vmnand_mm = 727,
 759     rv_op_vmandn_mm = 728,
 760     rv_op_vmxor_mm = 729,
 761     rv_op_vmor_mm = 730,
 762     rv_op_vmnor_mm = 731,
 763     rv_op_vmorn_mm = 732,
 764     rv_op_vmxnor_mm = 733,
 765     rv_op_vcpop_m = 734,
 766     rv_op_vfirst_m = 735,
 767     rv_op_vmsbf_m = 736,
 768     rv_op_vmsif_m = 737,
 769     rv_op_vmsof_m = 738,
 770     rv_op_viota_m = 739,
 771     rv_op_vid_v = 740,
 772     rv_op_vmv_x_s = 741,
 773     rv_op_vmv_s_x = 742,
 774     rv_op_vfmv_f_s = 743,
 775     rv_op_vfmv_s_f = 744,
 776     rv_op_vslideup_vx = 745,
 777     rv_op_vslideup_vi = 746,
 778     rv_op_vslide1up_vx = 747,
 779     rv_op_vslidedown_vx = 748,
 780     rv_op_vslidedown_vi = 749,
 781     rv_op_vslide1down_vx = 750,
 782     rv_op_vrgather_vv = 751,
 783     rv_op_vrgatherei16_vv = 752,
 784     rv_op_vrgather_vx = 753,
 785     rv_op_vrgather_vi = 754,
 786     rv_op_vcompress_vm = 755,
 787     rv_op_vmv1r_v = 756,
 788     rv_op_vmv2r_v = 757,
 789     rv_op_vmv4r_v = 758,
 790     rv_op_vmv8r_v = 759,
 791     rv_op_vzext_vf2 = 760,
 792     rv_op_vzext_vf4 = 761,
 793     rv_op_vzext_vf8 = 762,
 794     rv_op_vsext_vf2 = 763,
 795     rv_op_vsext_vf4 = 764,
 796     rv_op_vsext_vf8 = 765,
 797     rv_op_vsetvli = 766,
 798     rv_op_vsetivli = 767,
 799     rv_op_vsetvl = 768,
 800     rv_op_c_zext_b = 769,
 801     rv_op_c_sext_b = 770,
 802     rv_op_c_zext_h = 771,
 803     rv_op_c_sext_h = 772,
 804     rv_op_c_zext_w = 773,
 805     rv_op_c_not = 774,
 806     rv_op_c_mul = 775,
 807     rv_op_c_lbu = 776,
 808     rv_op_c_lhu = 777,
 809     rv_op_c_lh = 778,
 810     rv_op_c_sb = 779,
 811     rv_op_c_sh = 780,
 812     rv_op_cm_push = 781,
 813     rv_op_cm_pop = 782,
 814     rv_op_cm_popret = 783,
 815     rv_op_cm_popretz = 784,
 816     rv_op_cm_mva01s = 785,
 817     rv_op_cm_mvsa01 = 786,
 818     rv_op_cm_jt = 787,
 819     rv_op_cm_jalt = 788,
 820     rv_op_czero_eqz = 789,
 821     rv_op_czero_nez = 790,
 822 } rv_op;
 823
 824 /* register names */
 825
 826 static const char rv_ireg_name_sym[32][5] = {
 827     "zero", "ra",   "sp",   "gp",   "tp",   "t0",   "t1",   "t2",
 828     "s0",   "s1",   "a0",   "a1",   "a2",   "a3",   "a4",   "a5",
 829     "a6",   "a7",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
 830     "s8",   "s9",   "s10",  "s11",  "t3",   "t4",   "t5",   "t6",
 831 };
 832
 833 static const char rv_freg_name_sym[32][5] = {
 834     "ft0",  "ft1",  "ft2",  "ft3",  "ft4",  "ft5",  "ft6",  "ft7",
 835     "fs0",  "fs1",  "fa0",  "fa1",  "fa2",  "fa3",  "fa4",  "fa5",
 836     "fa6",  "fa7",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7",
 837     "fs8",  "fs9",  "fs10", "fs11", "ft8",  "ft9",  "ft10", "ft11",
 838 };
 839
 840 static const char rv_vreg_name_sym[32][4] = {
 841     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
 842     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
 843     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
 844     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
 845 };
 846
 847 /* pseudo-instruction constraints */
 848
 849 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
 850 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero,
 851                                             rvc_end };
 852 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0,
 853                                            rvc_imm_eq_zero, rvc_end };
 854 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
 855 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
 856 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
 857 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
 858 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };
 859 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
 860 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
 861 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };
 862 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end };
 863 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end };
 864 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end };
 865 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end };
 866 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end };
 867 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end };
 868 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end };
 869 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end };
 870 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end };
 871 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end };
 872 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end };
 873 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end };
 874 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end };
 875 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end };
 876 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end };
 877 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end };
 878 static const rvc_constraint rvcc_ble[] = { rvc_end };
 879 static const rvc_constraint rvcc_bleu[] = { rvc_end };
 880 static const rvc_constraint rvcc_bgt[] = { rvc_end };
 881 static const rvc_constraint rvcc_bgtu[] = { rvc_end };
 882 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
 883 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
 884                                            rvc_end };
 885 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
 886                                           rvc_end };
 887 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00,
 888                                                rvc_end };
 889 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01,
 890                                               rvc_end };
 891 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
 892                                                  rvc_csr_eq_0xc02, rvc_end };
 893 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
 894                                                 rvc_csr_eq_0xc80, rvc_end };
 895 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81,
 896                                                rvc_end };
 897 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
 898                                                   rvc_csr_eq_0xc82, rvc_end };
 899 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003,
 900                                              rvc_end };
 901 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002,
 902                                             rvc_end };
 903 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001,
 904                                                rvc_end };
 905 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
 906 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
 907 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
 908 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };
 909 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };
 910
 911 /* pseudo-instruction metadata */
 912
 913 static const rv_comp_data rvcp_jal[] = {
 914     { rv_op_j, rvcc_j },
 915     { rv_op_jal, rvcc_jal },
 916     { rv_op_illegal, NULL }
 917 };
 918
 919 static const rv_comp_data rvcp_jalr[] = {
 920     { rv_op_ret, rvcc_ret },
 921     { rv_op_jr, rvcc_jr },
 922     { rv_op_jalr, rvcc_jalr },
 923     { rv_op_illegal, NULL }
 924 };
 925
 926 static const rv_comp_data rvcp_beq[] = {
 927     { rv_op_beqz, rvcc_beqz },
 928     { rv_op_illegal, NULL }
 929 };
 930
 931 static const rv_comp_data rvcp_bne[] = {
 932     { rv_op_bnez, rvcc_bnez },
 933     { rv_op_illegal, NULL }
 934 };
 935
 936 static const rv_comp_data rvcp_blt[] = {
 937     { rv_op_bltz, rvcc_bltz },
 938     { rv_op_bgtz, rvcc_bgtz },
 939     { rv_op_bgt, rvcc_bgt },
 940     { rv_op_illegal, NULL }
 941 };
 942
 943 static const rv_comp_data rvcp_bge[] = {
 944     { rv_op_blez, rvcc_blez },
 945     { rv_op_bgez, rvcc_bgez },
 946     { rv_op_ble, rvcc_ble },
 947     { rv_op_illegal, NULL }
 948 };
 949
 950 static const rv_comp_data rvcp_bltu[] = {
 951     { rv_op_bgtu, rvcc_bgtu },
 952     { rv_op_illegal, NULL }
 953 };
 954
 955 static const rv_comp_data rvcp_bgeu[] = {
 956     { rv_op_bleu, rvcc_bleu },
 957     { rv_op_illegal, NULL }
 958 };
 959
 960 static const rv_comp_data rvcp_addi[] = {
 961     { rv_op_nop, rvcc_nop },
 962     { rv_op_mv, rvcc_mv },
 963     { rv_op_illegal, NULL }
 964 };
 965
 966 static const rv_comp_data rvcp_sltiu[] = {
 967     { rv_op_seqz, rvcc_seqz },
 968     { rv_op_illegal, NULL }
 969 };
 970
 971 static const rv_comp_data rvcp_xori[] = {
 972     { rv_op_not, rvcc_not },
 973     { rv_op_illegal, NULL }
 974 };
 975
 976 static const rv_comp_data rvcp_sub[] = {
 977     { rv_op_neg, rvcc_neg },
 978     { rv_op_illegal, NULL }
 979 };
 980
 981 static const rv_comp_data rvcp_slt[] = {
 982     { rv_op_sltz, rvcc_sltz },
 983     { rv_op_sgtz, rvcc_sgtz },
 984     { rv_op_illegal, NULL }
 985 };
 986
 987 static const rv_comp_data rvcp_sltu[] = {
 988     { rv_op_snez, rvcc_snez },
 989     { rv_op_illegal, NULL }
 990 };
 991
 992 static const rv_comp_data rvcp_addiw[] = {
 993     { rv_op_sext_w, rvcc_sext_w },
 994     { rv_op_illegal, NULL }
 995 };
 996
 997 static const rv_comp_data rvcp_subw[] = {
 998     { rv_op_negw, rvcc_negw },
 999     { rv_op_illegal, NULL }
1000 };
1001
1002 static const rv_comp_data rvcp_csrrw[] = {
1003     { rv_op_fscsr, rvcc_fscsr },
1004     { rv_op_fsrm, rvcc_fsrm },
1005     { rv_op_fsflags, rvcc_fsflags },
1006     { rv_op_illegal, NULL }
1007 };
1008
1009
1010 static const rv_comp_data rvcp_csrrs[] = {
1011     { rv_op_rdcycle, rvcc_rdcycle },
1012     { rv_op_rdtime, rvcc_rdtime },
1013     { rv_op_rdinstret, rvcc_rdinstret },
1014     { rv_op_rdcycleh, rvcc_rdcycleh },
1015     { rv_op_rdtimeh, rvcc_rdtimeh },
1016     { rv_op_rdinstreth, rvcc_rdinstreth },
1017     { rv_op_frcsr, rvcc_frcsr },
1018     { rv_op_frrm, rvcc_frrm },
1019     { rv_op_frflags, rvcc_frflags },
1020     { rv_op_illegal, NULL }
1021 };
1022
1023 static const rv_comp_data rvcp_csrrwi[] = {
1024     { rv_op_fsrmi, rvcc_fsrmi },
1025     { rv_op_fsflagsi, rvcc_fsflagsi },
1026     { rv_op_illegal, NULL }
1027 };
1028
1029 static const rv_comp_data rvcp_fsgnj_s[] = {
1030     { rv_op_fmv_s, rvcc_fmv_s },
1031     { rv_op_illegal, NULL }
1032 };
1033
1034 static const rv_comp_data rvcp_fsgnjn_s[] = {
1035     { rv_op_fneg_s, rvcc_fneg_s },
1036     { rv_op_illegal, NULL }
1037 };
1038
1039 static const rv_comp_data rvcp_fsgnjx_s[] = {
1040     { rv_op_fabs_s, rvcc_fabs_s },
1041     { rv_op_illegal, NULL }
1042 };
1043
1044 static const rv_comp_data rvcp_fsgnj_d[] = {
1045     { rv_op_fmv_d, rvcc_fmv_d },
1046     { rv_op_illegal, NULL }
1047 };
1048
1049 static const rv_comp_data rvcp_fsgnjn_d[] = {
1050     { rv_op_fneg_d, rvcc_fneg_d },
1051     { rv_op_illegal, NULL }
1052 };
1053
1054 static const rv_comp_data rvcp_fsgnjx_d[] = {
1055     { rv_op_fabs_d, rvcc_fabs_d },
1056     { rv_op_illegal, NULL }
1057 };
1058
1059 static const rv_comp_data rvcp_fsgnj_q[] = {
1060     { rv_op_fmv_q, rvcc_fmv_q },
1061     { rv_op_illegal, NULL }
1062 };
1063
1064 static const rv_comp_data rvcp_fsgnjn_q[] = {
1065     { rv_op_fneg_q, rvcc_fneg_q },
1066     { rv_op_illegal, NULL }
1067 };
1068
1069 static const rv_comp_data rvcp_fsgnjx_q[] = {
1070     { rv_op_fabs_q, rvcc_fabs_q },
1071     { rv_op_illegal, NULL }
1072 };
1073
1074 /* instruction metadata */
1075
1076 const rv_opcode_data rvi_opcode_data[] = {
1077     { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
1078     { "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 },
1079     { "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 },
1080     { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 },
1081     { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 },
1082     { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 },
1083     { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 },
1084     { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 },
1085     { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 },
1086     { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 },
1087     { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 },
1088     { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1089     { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1090     { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1091     { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1092     { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1093     { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1094     { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1095     { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1096     { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 },
1097     { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1098     { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 },
1099     { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 },
1100     { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1101     { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1102     { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1103     { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1104     { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1105     { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1106     { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 },
1107     { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1108     { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 },
1109     { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 },
1110     { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1111     { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1112     { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1113     { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1114     { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1115     { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 },
1116     { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1117     { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1118     { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1119     { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1120     { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 },
1121     { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1122     { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1123     { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1124     { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1125     { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 },
1126     { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1127     { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1128     { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1129     { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1130     { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1131     { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1132     { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1133     { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1134     { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1135     { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1136     { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1137     { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1138     { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1139     { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1140     { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1141     { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1142     { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1143     { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1144     { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1145     { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1146     { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1147     { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1148     { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1149     { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1150     { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1151     { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1152     { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1153     { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1154     { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1155     { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1156     { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1157     { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1158     { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1159     { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1160     { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1161     { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1162     { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1163     { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1164     { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1165     { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1166     { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1167     { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1168     { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1169     { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1170     { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1171     { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1172     { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1173     { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1174     { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1175     { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1176     { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1177     { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1178     { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1179     { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1180     { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1181     { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1182     { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1183     { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1184     { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1185     { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1186     { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1187     { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1188     { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1189     { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1190     { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1191     { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1192     { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1193     { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1194     { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1195     { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1196     { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1197     { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1198     { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1199     { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
1200     { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
1201     { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1202     { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 },
1203     { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 },
1204     { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 },
1205     { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 },
1206     { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
1207     { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
1208     { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1209     { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1210     { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1211     { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1212     { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1213     { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1214     { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1215     { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1216     { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1217     { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1218     { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 },
1219     { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 },
1220     { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 },
1221     { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1222     { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1223     { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1224     { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1225     { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1226     { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1227     { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1228     { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1229     { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1230     { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1231     { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1232     { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1233     { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1234     { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1235     { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1236     { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1237     { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1238     { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1239     { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1240     { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1241     { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1242     { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1243     { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1244     { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1245     { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1246     { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1247     { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1248     { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 },
1249     { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 },
1250     { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 },
1251     { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1252     { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1253     { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1254     { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1255     { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1256     { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1257     { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1258     { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1259     { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1260     { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1261     { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1262     { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1263     { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1264     { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1265     { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1266     { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1267     { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1268     { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1269     { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1270     { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1271     { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1272     { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1273     { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1274     { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1275     { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1276     { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1277     { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1278     { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1279     { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1280     { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 },
1281     { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 },
1282     { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 },
1283     { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1284     { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1285     { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1286     { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1287     { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1288     { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1289     { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1290     { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1291     { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1292     { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1293     { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1294     { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1295     { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1296     { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1297     { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1298     { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1299     { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1300     { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1301     { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1302     { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1303     { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1304     { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1305       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1306     { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
1307       rv_op_fld, 0 },
1308     { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw,
1309       rv_op_lw },
1310     { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
1311     { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
1312       rv_op_fsd, 0 },
1313     { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw,
1314       rv_op_sw },
1315     { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
1316     { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi,
1317       rv_op_addi },
1318     { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
1319       rv_op_addi, rvcd_imm_nz },
1320     { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
1321     { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
1322       rv_op_addi },
1323     { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1324       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1325     { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui,
1326       rv_op_lui, rvcd_imm_nz },
1327     { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli,
1328       rv_op_srli, rv_op_srli, rvcd_imm_nz },
1329     { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai,
1330       rv_op_srai, rv_op_srai, rvcd_imm_nz },
1331     { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
1332       rv_op_andi, rv_op_andi },
1333     { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub,
1334       rv_op_sub },
1335     { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor,
1336       rv_op_xor },
1337     { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or,
1338       rv_op_or },
1339     { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and,
1340       rv_op_and },
1341     { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw,
1342       rv_op_subw },
1343     { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw,
1344       rv_op_addw },
1345     { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal,
1346       rv_op_jal },
1347     { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq,
1348       rv_op_beq },
1349     { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne,
1350       rv_op_bne },
1351     { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
1352       rv_op_slli, rv_op_slli, rvcd_imm_nz },
1353     { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
1354       rv_op_fld, rv_op_fld },
1355     { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
1356       rv_op_lw, rv_op_lw },
1357     { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0,
1358       0 },
1359     { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
1360       rv_op_jalr, rv_op_jalr },
1361     { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi,
1362       rv_op_addi },
1363     { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak,
1364       rv_op_ebreak, rv_op_ebreak },
1365     { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
1366       rv_op_jalr, rv_op_jalr },
1367     { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add,
1368       rv_op_add },
1369     { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
1370       rv_op_fsd, rv_op_fsd },
1371     { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
1372       rv_op_sw, rv_op_sw },
1373     { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0,
1374       0 },
1375     { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
1376       rv_op_ld },
1377     { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
1378       rv_op_sd },
1379     { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw,
1380       rv_op_addiw },
1381     { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
1382       rv_op_ld },
1383     { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
1384       rv_op_sd },
1385     { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
1386     { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
1387     { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
1388     { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
1389       rv_op_sq },
1390     { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
1391     { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1392     { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1393     { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1394     { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1395     { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1396     { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1397     { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1398     { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1399     { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1400     { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1401     { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1402     { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1403     { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1404     { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1405     { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1406     { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1407     { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1408     { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1409     { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1410     { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1411     { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
1412     { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1413     { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1414     { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
1415     { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1416     { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1417     { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1418     { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1419     { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 },
1420     { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
1421     { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 },
1422     { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1423     { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1424     { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1425     { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1426     { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1427     { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1428     { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1429     { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1430     { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1431     { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1432     { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1433     { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1434     { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
1435     { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
1436     { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1437     { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1438     { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1439     { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1440     { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1441     { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1442     { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1443     { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1444     { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1445     { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1446     { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1447     { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1448     { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1449     { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1450     { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1451     { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1452     { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1453     { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1454     { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1455     { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1456     { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1457     { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1458     { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1459     { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1460     { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1461     { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1462     { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1463     { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1464     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1465     { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1466     { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1467     { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1468     { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1469     { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1470     { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1471     { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1472     { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1473     { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1474     { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1475     { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1476     { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1477     { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1478     { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1479     { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1480     { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1481     { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1482     { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1483     { "aes64ks1i", rv_codec_k_rnum,  rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
1484     { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1485     { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1486     { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1487     { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1488     { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1489     { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1490     { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1491     { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1492     { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1493     { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1494     { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1495     { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1496     { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1497     { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1498     { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1499     { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1500     { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1501     { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1502     { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1503     { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1504     { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1505     { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1506     { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1507     { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1508     { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1509     { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1510     { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1511     { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1512     { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1513     { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1514     { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1515     { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1516     { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1517     { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1518     { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1519     { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1520     { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1521     { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1522     { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1523     { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1524     { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1525     { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1526     { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1527     { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1528     { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1529     { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1530     { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1531     { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1532     { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1533     { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1534     { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1535     { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1536     { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1537     { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1538     { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1539     { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1540     { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1541     { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1542     { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1543     { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1544     { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1545     { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1546     { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1547     { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1548     { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1549     { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1550     { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1551     { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1552     { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1553     { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1554     { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1555     { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1556     { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1557     { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1558     { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1559     { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1560     { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1561     { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1562     { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1563     { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1564     { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1565     { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1566     { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1567     { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1568     { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1569     { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1570     { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1571     { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1572     { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1573     { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1574     { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1575     { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1576     { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1577     { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1578     { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1579     { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1580     { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1581     { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1582     { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1583     { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1584     { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1585     { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1586     { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1587     { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1588     { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1589     { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1590     { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1591     { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1592     { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1593     { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1594     { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1595     { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1596     { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1597     { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1598     { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1599     { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
1600     { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1601     { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1602     { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
1603     { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1604     { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1605     { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1606     { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1607     { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1608     { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1609     { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1610     { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1611     { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1612     { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1613     { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1614     { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1615     { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1616     { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1617     { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1618     { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1619     { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1620     { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1621     { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1622     { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1623     { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1624     { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1625     { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1626     { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1627     { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1628     { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1629     { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1630     { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1631     { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1632     { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1633     { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1634     { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1635     { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1636     { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1637     { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1638     { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1639     { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1640     { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1641     { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1642     { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1643     { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1644     { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1645     { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1646     { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1647     { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1648     { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1649     { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1650     { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1651     { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1652     { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1653     { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1654     { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1655     { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1656     { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1657     { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1658     { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1659     { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1660     { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1661     { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1662     { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1663     { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1664     { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1665     { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1666     { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1667     { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1668     { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1669     { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1670     { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1671     { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1672     { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1673     { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1674     { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1675     { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1676     { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1677     { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1678     { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1679     { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1680     { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1681     { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1682     { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1683     { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1684     { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1685     { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1686     { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1687     { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1688     { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1689     { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1690     { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1691     { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1692     { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1693     { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1694     { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1695     { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1696     { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 },
1697     { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
1698     { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 },
1699     { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1700     { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1701     { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
1702     { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1703     { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1704     { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1705     { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1706     { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1707     { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1708     { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1709     { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1710     { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1711     { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1712     { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1713     { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1714     { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1715     { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1716     { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1717     { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1718     { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1719     { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1720     { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1721     { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1722     { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1723     { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1724     { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1725     { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1726     { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1727     { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1728     { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1729     { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1730     { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1731     { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1732     { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1733     { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1734     { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1735     { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1736     { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1737     { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1738     { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1739     { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1740     { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1741     { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1742     { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1743     { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1744     { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1745     { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1746     { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1747     { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1748     { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1749     { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1750     { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1751     { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1752     { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1753     { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1754     { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1755     { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1756     { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1757     { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1758     { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1759     { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1760     { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1761     { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1762     { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1763     { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1764     { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1765     { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1766     { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1767     { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1768     { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1769     { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1770     { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1771     { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1772     { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1773     { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1774     { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1775     { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1776     { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1777     { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1778     { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1779     { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1780     { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1781     { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1782     { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1783     { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1784     { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1785     { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1786     { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1787     { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1788     { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1789     { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1790     { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1791     { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1792     { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1793     { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1794     { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1795     { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1796     { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1797     { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1798     { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1799     { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1800     { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1801     { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1802     { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1803     { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1804     { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 },
1805     { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
1806     { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1807     { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1808     { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1809     { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1810     { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1811     { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1812     { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1813     { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1814     { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1815     { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1816     { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1817     { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1818     { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1819     { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1820     { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1821     { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1822     { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1823     { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1824     { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1825     { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1826     { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1827     { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1828     { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1829     { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1830     { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1831     { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1832     { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1833     { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1834     { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1835     { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1836     { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1837     { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1838     { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1839     { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1840     { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1841     { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1842     { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1843     { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1844     { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1845     { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1846     { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1847     { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1848     { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1849     { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1850     { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1851     { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
1852     { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
1853     { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1854     { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1855     { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1856     { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1857     { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 },
1858     { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 },
1859     { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
1860     { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 },
1861     { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
1862     { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1863     { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1864     { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1865     { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1866     { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1867     { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1868     { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1869     { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1870     { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1871     { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1872     { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
1873     { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1874     { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1875     { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1876     { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1877     { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1878     { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1879     { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1880     { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1881     { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1882     { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1883     { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 },
1884     { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 },
1885     { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1886     { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
1887     { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
1888     { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
1889     { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
1890     { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
1891     { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
1892     { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 },
1893     { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
1894     { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
1895     { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
1896     { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
1897     { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
1898     { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 },
1899     { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
1900     { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 },
1901     { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
1902     { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1903     { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1904     { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
1905     { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
1906     { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1907     { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1908 };
1909
1910 /* CSR names */
1911
1912 static const char *csr_name(int csrno)
1913 {
1914     switch (csrno) {
1915     case 0x0000: return "ustatus";
1916     case 0x0001: return "fflags";
1917     case 0x0002: return "frm";
1918     case 0x0003: return "fcsr";
1919     case 0x0004: return "uie";
1920     case 0x0005: return "utvec";
1921     case 0x0008: return "vstart";
1922     case 0x0009: return "vxsat";
1923     case 0x000a: return "vxrm";
1924     case 0x000f: return "vcsr";
1925     case 0x0015: return "seed";
1926     case 0x0017: return "jvt";
1927     case 0x0040: return "uscratch";
1928     case 0x0041: return "uepc";
1929     case 0x0042: return "ucause";
1930     case 0x0043: return "utval";
1931     case 0x0044: return "uip";
1932     case 0x0100: return "sstatus";
1933     case 0x0104: return "sie";
1934     case 0x0105: return "stvec";
1935     case 0x0106: return "scounteren";
1936     case 0x0140: return "sscratch";
1937     case 0x0141: return "sepc";
1938     case 0x0142: return "scause";
1939     case 0x0143: return "stval";
1940     case 0x0144: return "sip";
1941     case 0x0180: return "satp";
1942     case 0x0200: return "hstatus";
1943     case 0x0202: return "hedeleg";
1944     case 0x0203: return "hideleg";
1945     case 0x0204: return "hie";
1946     case 0x0205: return "htvec";
1947     case 0x0240: return "hscratch";
1948     case 0x0241: return "hepc";
1949     case 0x0242: return "hcause";
1950     case 0x0243: return "hbadaddr";
1951     case 0x0244: return "hip";
1952     case 0x0300: return "mstatus";
1953     case 0x0301: return "misa";
1954     case 0x0302: return "medeleg";
1955     case 0x0303: return "mideleg";
1956     case 0x0304: return "mie";
1957     case 0x0305: return "mtvec";
1958     case 0x0306: return "mcounteren";
1959     case 0x0320: return "mucounteren";
1960     case 0x0321: return "mscounteren";
1961     case 0x0322: return "mhcounteren";
1962     case 0x0323: return "mhpmevent3";
1963     case 0x0324: return "mhpmevent4";
1964     case 0x0325: return "mhpmevent5";
1965     case 0x0326: return "mhpmevent6";
1966     case 0x0327: return "mhpmevent7";
1967     case 0x0328: return "mhpmevent8";
1968     case 0x0329: return "mhpmevent9";
1969     case 0x032a: return "mhpmevent10";
1970     case 0x032b: return "mhpmevent11";
1971     case 0x032c: return "mhpmevent12";
1972     case 0x032d: return "mhpmevent13";
1973     case 0x032e: return "mhpmevent14";
1974     case 0x032f: return "mhpmevent15";
1975     case 0x0330: return "mhpmevent16";
1976     case 0x0331: return "mhpmevent17";
1977     case 0x0332: return "mhpmevent18";
1978     case 0x0333: return "mhpmevent19";
1979     case 0x0334: return "mhpmevent20";
1980     case 0x0335: return "mhpmevent21";
1981     case 0x0336: return "mhpmevent22";
1982     case 0x0337: return "mhpmevent23";
1983     case 0x0338: return "mhpmevent24";
1984     case 0x0339: return "mhpmevent25";
1985     case 0x033a: return "mhpmevent26";
1986     case 0x033b: return "mhpmevent27";
1987     case 0x033c: return "mhpmevent28";
1988     case 0x033d: return "mhpmevent29";
1989     case 0x033e: return "mhpmevent30";
1990     case 0x033f: return "mhpmevent31";
1991     case 0x0340: return "mscratch";
1992     case 0x0341: return "mepc";
1993     case 0x0342: return "mcause";
1994     case 0x0343: return "mtval";
1995     case 0x0344: return "mip";
1996     case 0x0380: return "mbase";
1997     case 0x0381: return "mbound";
1998     case 0x0382: return "mibase";
1999     case 0x0383: return "mibound";
2000     case 0x0384: return "mdbase";
2001     case 0x0385: return "mdbound";
2002     case 0x03a0: return "pmpcfg3";
2003     case 0x03b0: return "pmpaddr0";
2004     case 0x03b1: return "pmpaddr1";
2005     case 0x03b2: return "pmpaddr2";
2006     case 0x03b3: return "pmpaddr3";
2007     case 0x03b4: return "pmpaddr4";
2008     case 0x03b5: return "pmpaddr5";
2009     case 0x03b6: return "pmpaddr6";
2010     case 0x03b7: return "pmpaddr7";
2011     case 0x03b8: return "pmpaddr8";
2012     case 0x03b9: return "pmpaddr9";
2013     case 0x03ba: return "pmpaddr10";
2014     case 0x03bb: return "pmpaddr11";
2015     case 0x03bc: return "pmpaddr12";
2016     case 0x03bd: return "pmpaddr14";
2017     case 0x03be: return "pmpaddr13";
2018     case 0x03bf: return "pmpaddr15";
2019     case 0x0780: return "mtohost";
2020     case 0x0781: return "mfromhost";
2021     case 0x0782: return "mreset";
2022     case 0x0783: return "mipi";
2023     case 0x0784: return "miobase";
2024     case 0x07a0: return "tselect";
2025     case 0x07a1: return "tdata1";
2026     case 0x07a2: return "tdata2";
2027     case 0x07a3: return "tdata3";
2028     case 0x07b0: return "dcsr";
2029     case 0x07b1: return "dpc";
2030     case 0x07b2: return "dscratch";
2031     case 0x0b00: return "mcycle";
2032     case 0x0b01: return "mtime";
2033     case 0x0b02: return "minstret";
2034     case 0x0b03: return "mhpmcounter3";
2035     case 0x0b04: return "mhpmcounter4";
2036     case 0x0b05: return "mhpmcounter5";
2037     case 0x0b06: return "mhpmcounter6";
2038     case 0x0b07: return "mhpmcounter7";
2039     case 0x0b08: return "mhpmcounter8";
2040     case 0x0b09: return "mhpmcounter9";
2041     case 0x0b0a: return "mhpmcounter10";
2042     case 0x0b0b: return "mhpmcounter11";
2043     case 0x0b0c: return "mhpmcounter12";
2044     case 0x0b0d: return "mhpmcounter13";
2045     case 0x0b0e: return "mhpmcounter14";
2046     case 0x0b0f: return "mhpmcounter15";
2047     case 0x0b10: return "mhpmcounter16";
2048     case 0x0b11: return "mhpmcounter17";
2049     case 0x0b12: return "mhpmcounter18";
2050     case 0x0b13: return "mhpmcounter19";
2051     case 0x0b14: return "mhpmcounter20";
2052     case 0x0b15: return "mhpmcounter21";
2053     case 0x0b16: return "mhpmcounter22";
2054     case 0x0b17: return "mhpmcounter23";
2055     case 0x0b18: return "mhpmcounter24";
2056     case 0x0b19: return "mhpmcounter25";
2057     case 0x0b1a: return "mhpmcounter26";
2058     case 0x0b1b: return "mhpmcounter27";
2059     case 0x0b1c: return "mhpmcounter28";
2060     case 0x0b1d: return "mhpmcounter29";
2061     case 0x0b1e: return "mhpmcounter30";
2062     case 0x0b1f: return "mhpmcounter31";
2063     case 0x0b80: return "mcycleh";
2064     case 0x0b81: return "mtimeh";
2065     case 0x0b82: return "minstreth";
2066     case 0x0b83: return "mhpmcounter3h";
2067     case 0x0b84: return "mhpmcounter4h";
2068     case 0x0b85: return "mhpmcounter5h";
2069     case 0x0b86: return "mhpmcounter6h";
2070     case 0x0b87: return "mhpmcounter7h";
2071     case 0x0b88: return "mhpmcounter8h";
2072     case 0x0b89: return "mhpmcounter9h";
2073     case 0x0b8a: return "mhpmcounter10h";
2074     case 0x0b8b: return "mhpmcounter11h";
2075     case 0x0b8c: return "mhpmcounter12h";
2076     case 0x0b8d: return "mhpmcounter13h";
2077     case 0x0b8e: return "mhpmcounter14h";
2078     case 0x0b8f: return "mhpmcounter15h";
2079     case 0x0b90: return "mhpmcounter16h";
2080     case 0x0b91: return "mhpmcounter17h";
2081     case 0x0b92: return "mhpmcounter18h";
2082     case 0x0b93: return "mhpmcounter19h";
2083     case 0x0b94: return "mhpmcounter20h";
2084     case 0x0b95: return "mhpmcounter21h";
2085     case 0x0b96: return "mhpmcounter22h";
2086     case 0x0b97: return "mhpmcounter23h";
2087     case 0x0b98: return "mhpmcounter24h";
2088     case 0x0b99: return "mhpmcounter25h";
2089     case 0x0b9a: return "mhpmcounter26h";
2090     case 0x0b9b: return "mhpmcounter27h";
2091     case 0x0b9c: return "mhpmcounter28h";
2092     case 0x0b9d: return "mhpmcounter29h";
2093     case 0x0b9e: return "mhpmcounter30h";
2094     case 0x0b9f: return "mhpmcounter31h";
2095     case 0x0c00: return "cycle";
2096     case 0x0c01: return "time";
2097     case 0x0c02: return "instret";
2098     case 0x0c20: return "vl";
2099     case 0x0c21: return "vtype";
2100     case 0x0c22: return "vlenb";
2101     case 0x0c80: return "cycleh";
2102     case 0x0c81: return "timeh";
2103     case 0x0c82: return "instreth";
2104     case 0x0d00: return "scycle";
2105     case 0x0d01: return "stime";
2106     case 0x0d02: return "sinstret";
2107     case 0x0d80: return "scycleh";
2108     case 0x0d81: return "stimeh";
2109     case 0x0d82: return "sinstreth";
2110     case 0x0e00: return "hcycle";
2111     case 0x0e01: return "htime";
2112     case 0x0e02: return "hinstret";
2113     case 0x0e80: return "hcycleh";
2114     case 0x0e81: return "htimeh";
2115     case 0x0e82: return "hinstreth";
2116     case 0x0f11: return "mvendorid";
2117     case 0x0f12: return "marchid";
2118     case 0x0f13: return "mimpid";
2119     case 0x0f14: return "mhartid";
2120     default: return NULL;
2121     }
2122 }
2123
2124 /* decode opcode */
2125
2126 static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
2127 {
2128     rv_inst inst = dec->inst;
2129     rv_opcode op = rv_op_illegal;
2130     switch ((inst >> 0) & 0b11) {
2131     case 0:
2132         switch ((inst >> 13) & 0b111) {
2133         case 0: op = rv_op_c_addi4spn; break;
2134         case 1:
2135             if (isa == rv128) {
2136                 op = rv_op_c_lq;
2137             } else {
2138                 op = rv_op_c_fld;
2139             }
2140             break;
2141         case 2: op = rv_op_c_lw; break;
2142         case 3:
2143             if (isa == rv32) {
2144                 op = rv_op_c_flw;
2145             } else {
2146                 op = rv_op_c_ld;
2147             }
2148             break;
2149         case 4:
2150             switch ((inst >> 10) & 0b111) {
2151             case 0: op = rv_op_c_lbu; break;
2152             case 1:
2153                 if (((inst >> 6) & 1) == 0) {
2154                     op = rv_op_c_lhu;
2155                 } else {
2156                     op = rv_op_c_lh;
2157                 }
2158                 break;
2159             case 2: op = rv_op_c_sb; break;
2160             case 3:
2161                 if (((inst >> 6) & 1) == 0) {
2162                     op = rv_op_c_sh;
2163                 }
2164                 break;
2165             }
2166             break;
2167         case 5:
2168             if (isa == rv128) {
2169                 op = rv_op_c_sq;
2170             } else {
2171                 op = rv_op_c_fsd;
2172             }
2173             break;
2174         case 6: op = rv_op_c_sw; break;
2175         case 7:
2176             if (isa == rv32) {
2177                 op = rv_op_c_fsw;
2178             } else {
2179                 op = rv_op_c_sd;
2180             }
2181             break;
2182         }
2183         break;
2184     case 1:
2185         switch ((inst >> 13) & 0b111) {
2186         case 0:
2187             switch ((inst >> 2) & 0b11111111111) {
2188             case 0: op = rv_op_c_nop; break;
2189             default: op = rv_op_c_addi; break;
2190             }
2191             break;
2192         case 1:
2193             if (isa == rv32) {
2194                 op = rv_op_c_jal;
2195             } else {
2196                 op = rv_op_c_addiw;
2197             }
2198             break;
2199         case 2: op = rv_op_c_li; break;
2200         case 3:
2201             switch ((inst >> 7) & 0b11111) {
2202             case 2: op = rv_op_c_addi16sp; break;
2203             default: op = rv_op_c_lui; break;
2204             }
2205             break;
2206         case 4:
2207             switch ((inst >> 10) & 0b11) {
2208             case 0:
2209                 op = rv_op_c_srli;
2210                 break;
2211             case 1:
2212                 op = rv_op_c_srai;
2213                 break;
2214             case 2: op = rv_op_c_andi; break;
2215             case 3:
2216                 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) {
2217                 case 0: op = rv_op_c_sub; break;
2218                 case 1: op = rv_op_c_xor; break;
2219                 case 2: op = rv_op_c_or; break;
2220                 case 3: op = rv_op_c_and; break;
2221                 case 4: op = rv_op_c_subw; break;
2222                 case 5: op = rv_op_c_addw; break;
2223                 case 6: op = rv_op_c_mul; break;
2224                 case 7:
2225                     switch ((inst >> 2) & 0b111) {
2226                     case 0: op = rv_op_c_zext_b; break;
2227                     case 1: op = rv_op_c_sext_b; break;
2228                     case 2: op = rv_op_c_zext_h; break;
2229                     case 3: op = rv_op_c_sext_h; break;
2230                     case 4: op = rv_op_c_zext_w; break;
2231                     case 5: op = rv_op_c_not; break;
2232                     }
2233                     break;
2234                 }
2235                 break;
2236             }
2237             break;
2238         case 5: op = rv_op_c_j; break;
2239         case 6: op = rv_op_c_beqz; break;
2240         case 7: op = rv_op_c_bnez; break;
2241         }
2242         break;
2243     case 2:
2244         switch ((inst >> 13) & 0b111) {
2245         case 0:
2246             op = rv_op_c_slli;
2247             break;
2248         case 1:
2249             if (isa == rv128) {
2250                 op = rv_op_c_lqsp;
2251             } else {
2252                 op = rv_op_c_fldsp;
2253             }
2254             break;
2255         case 2: op = rv_op_c_lwsp; break;
2256         case 3:
2257             if (isa == rv32) {
2258                 op = rv_op_c_flwsp;
2259             } else {
2260                 op = rv_op_c_ldsp;
2261             }
2262             break;
2263         case 4:
2264             switch ((inst >> 12) & 0b1) {
2265             case 0:
2266                 switch ((inst >> 2) & 0b11111) {
2267                 case 0: op = rv_op_c_jr; break;
2268                 default: op = rv_op_c_mv; break;
2269                 }
2270                 break;
2271             case 1:
2272                 switch ((inst >> 2) & 0b11111) {
2273                 case 0:
2274                     switch ((inst >> 7) & 0b11111) {
2275                     case 0: op = rv_op_c_ebreak; break;
2276                     default: op = rv_op_c_jalr; break;
2277                     }
2278                     break;
2279                 default: op = rv_op_c_add; break;
2280                 }
2281                 break;
2282             }
2283             break;
2284         case 5:
2285             if (isa == rv128) {
2286                 op = rv_op_c_sqsp;
2287             } else {
2288                 op = rv_op_c_fsdsp;
2289                 if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
2290                     switch ((inst >> 8) & 0b01111) {
2291                     case 8:
2292                         if (((inst >> 4) & 0b01111) >= 4) {
2293                             op = rv_op_cm_push;
2294                         }
2295                         break;
2296                     case 10:
2297                         if (((inst >> 4) & 0b01111) >= 4) {
2298                             op = rv_op_cm_pop;
2299                         }
2300                         break;
2301                     case 12:
2302                         if (((inst >> 4) & 0b01111) >= 4) {
2303                             op = rv_op_cm_popretz;
2304                         }
2305                         break;
2306                     case 14:
2307                         if (((inst >> 4) & 0b01111) >= 4) {
2308                             op = rv_op_cm_popret;
2309                         }
2310                         break;
2311                     }
2312                 } else {
2313                     switch ((inst >> 10) & 0b011) {
2314                     case 0:
2315                         if (!dec->cfg->ext_zcmt) {
2316                             break;
2317                         }
2318                         if (((inst >> 2) & 0xFF) >= 32) {
2319                             op = rv_op_cm_jalt;
2320                         } else {
2321                             op = rv_op_cm_jt;
2322                         }
2323                         break;
2324                     case 3:
2325                         if (!dec->cfg->ext_zcmp) {
2326                             break;
2327                         }
2328                         switch ((inst >> 5) & 0b011) {
2329                         case 1: op = rv_op_cm_mvsa01; break;
2330                         case 3: op = rv_op_cm_mva01s; break;
2331                         }
2332                         break;
2333                     }
2334                 }
2335             }
2336             break;
2337         case 6: op = rv_op_c_swsp; break;
2338         case 7:
2339             if (isa == rv32) {
2340                 op = rv_op_c_fswsp;
2341             } else {
2342                 op = rv_op_c_sdsp;
2343             }
2344             break;
2345         }
2346         break;
2347     case 3:
2348         switch ((inst >> 2) & 0b11111) {
2349         case 0:
2350             switch ((inst >> 12) & 0b111) {
2351             case 0: op = rv_op_lb; break;
2352             case 1: op = rv_op_lh; break;
2353             case 2: op = rv_op_lw; break;
2354             case 3: op = rv_op_ld; break;
2355             case 4: op = rv_op_lbu; break;
2356             case 5: op = rv_op_lhu; break;
2357             case 6: op = rv_op_lwu; break;
2358             case 7: op = rv_op_ldu; break;
2359             }
2360             break;
2361         case 1:
2362             switch ((inst >> 12) & 0b111) {
2363             case 0:
2364                 switch ((inst >> 20) & 0b111111111111) {
2365                 case 40: op = rv_op_vl1re8_v; break;
2366                 case 552: op = rv_op_vl2re8_v; break;
2367                 case 1576: op = rv_op_vl4re8_v; break;
2368                 case 3624: op = rv_op_vl8re8_v; break;
2369                 }
2370                 switch ((inst >> 26) & 0b111) {
2371                 case 0:
2372                     switch ((inst >> 20) & 0b11111) {
2373                     case 0: op = rv_op_vle8_v; break;
2374                     case 11: op = rv_op_vlm_v; break;
2375                     case 16: op = rv_op_vle8ff_v; break;
2376                     }
2377                     break;
2378                 case 1: op = rv_op_vluxei8_v; break;
2379                 case 2: op = rv_op_vlse8_v; break;
2380                 case 3: op = rv_op_vloxei8_v; break;
2381                 }
2382                 break;
2383             case 2: op = rv_op_flw; break;
2384             case 3: op = rv_op_fld; break;
2385             case 4: op = rv_op_flq; break;
2386             case 5:
2387                 switch ((inst >> 20) & 0b111111111111) {
2388                 case 40: op = rv_op_vl1re16_v; break;
2389                 case 552: op = rv_op_vl2re16_v; break;
2390                 case 1576: op = rv_op_vl4re16_v; break;
2391                 case 3624: op = rv_op_vl8re16_v; break;
2392                 }
2393                 switch ((inst >> 26) & 0b111) {
2394                 case 0:
2395                     switch ((inst >> 20) & 0b11111) {
2396                     case 0: op = rv_op_vle16_v; break;
2397                     case 16: op = rv_op_vle16ff_v; break;
2398                     }
2399                     break;
2400                 case 1: op = rv_op_vluxei16_v; break;
2401                 case 2: op = rv_op_vlse16_v; break;
2402                 case 3: op = rv_op_vloxei16_v; break;
2403                 }
2404                 break;
2405             case 6:
2406                 switch ((inst >> 20) & 0b111111111111) {
2407                 case 40: op = rv_op_vl1re32_v; break;
2408                 case 552: op = rv_op_vl2re32_v; break;
2409                 case 1576: op = rv_op_vl4re32_v; break;
2410                 case 3624: op = rv_op_vl8re32_v; break;
2411                 }
2412                 switch ((inst >> 26) & 0b111) {
2413                 case 0:
2414                     switch ((inst >> 20) & 0b11111) {
2415                     case 0: op = rv_op_vle32_v; break;
2416                     case 16: op = rv_op_vle32ff_v; break;
2417                     }
2418                     break;
2419                 case 1: op = rv_op_vluxei32_v; break;
2420                 case 2: op = rv_op_vlse32_v; break;
2421                 case 3: op = rv_op_vloxei32_v; break;
2422                 }
2423                 break;
2424             case 7:
2425                 switch ((inst >> 20) & 0b111111111111) {
2426                 case 40: op = rv_op_vl1re64_v; break;
2427                 case 552: op = rv_op_vl2re64_v; break;
2428                 case 1576: op = rv_op_vl4re64_v; break;
2429                 case 3624: op = rv_op_vl8re64_v; break;
2430                 }
2431                 switch ((inst >> 26) & 0b111) {
2432                 case 0:
2433                     switch ((inst >> 20) & 0b11111) {
2434                     case 0: op = rv_op_vle64_v; break;
2435                     case 16: op = rv_op_vle64ff_v; break;
2436                     }
2437                     break;
2438                 case 1: op = rv_op_vluxei64_v; break;
2439                 case 2: op = rv_op_vlse64_v; break;
2440                 case 3: op = rv_op_vloxei64_v; break;
2441                 }
2442                 break;
2443             }
2444             break;
2445         case 3:
2446             switch ((inst >> 12) & 0b111) {
2447             case 0: op = rv_op_fence; break;
2448             case 1: op = rv_op_fence_i; break;
2449             case 2: op = rv_op_lq; break;
2450             }
2451             break;
2452         case 4:
2453             switch ((inst >> 12) & 0b111) {
2454             case 0: op = rv_op_addi; break;
2455             case 1:
2456                 switch ((inst >> 27) & 0b11111) {
2457                 case 0b00000: op = rv_op_slli; break;
2458                 case 0b00001:
2459                     switch ((inst >> 20) & 0b1111111) {
2460                     case 0b0001111: op = rv_op_zip; break;
2461                     }
2462                     break;
2463                 case 0b00010:
2464                     switch ((inst >> 20) & 0b1111111) {
2465                     case 0b0000000: op = rv_op_sha256sum0; break;
2466                     case 0b0000001: op = rv_op_sha256sum1; break;
2467                     case 0b0000010: op = rv_op_sha256sig0; break;
2468                     case 0b0000011: op = rv_op_sha256sig1; break;
2469                     case 0b0000100: op = rv_op_sha512sum0; break;
2470                     case 0b0000101: op = rv_op_sha512sum1; break;
2471                     case 0b0000110: op = rv_op_sha512sig0; break;
2472                     case 0b0000111: op = rv_op_sha512sig1; break;
2473                     case 0b0001000: op = rv_op_sm3p0; break;
2474                     case 0b0001001: op = rv_op_sm3p1; break;
2475                     }
2476                     break;
2477                 case 0b00101: op = rv_op_bseti; break;
2478                 case 0b00110:
2479                     switch ((inst >> 20) & 0b1111111) {
2480                     case 0b0000000: op = rv_op_aes64im; break;
2481                     default:
2482                         if (((inst >> 24) & 0b0111) == 0b001) {
2483                             op = rv_op_aes64ks1i;
2484                         }
2485                         break;
2486                      }
2487                      break;
2488                 case 0b01001: op = rv_op_bclri; break;
2489                 case 0b01101: op = rv_op_binvi; break;
2490                 case 0b01100:
2491                     switch ((inst >> 20) & 0b1111111) {
2492                     case 0b0000000: op = rv_op_clz; break;
2493                     case 0b0000001: op = rv_op_ctz; break;
2494                     case 0b0000010: op = rv_op_cpop; break;
2495                       /* 0b0000011 */
2496                     case 0b0000100: op = rv_op_sext_b; break;
2497                     case 0b0000101: op = rv_op_sext_h; break;
2498                     }
2499                     break;
2500                 }
2501                 break;
2502             case 2: op = rv_op_slti; break;
2503             case 3: op = rv_op_sltiu; break;
2504             case 4: op = rv_op_xori; break;
2505             case 5:
2506                 switch ((inst >> 27) & 0b11111) {
2507                 case 0b00000: op = rv_op_srli; break;
2508                 case 0b00001:
2509                     switch ((inst >> 20) & 0b1111111) {
2510                     case 0b0001111: op = rv_op_unzip; break;
2511                     }
2512                     break;
2513                 case 0b00101: op = rv_op_orc_b; break;
2514                 case 0b01000: op = rv_op_srai; break;
2515                 case 0b01001: op = rv_op_bexti; break;
2516                 case 0b01100: op = rv_op_rori; break;
2517                 case 0b01101:
2518                     switch ((inst >> 20) & 0b1111111) {
2519                     case 0b0011000: op = rv_op_rev8; break;
2520                     case 0b0111000: op = rv_op_rev8; break;
2521                     case 0b0000111: op = rv_op_brev8; break;
2522                     }
2523                     break;
2524                 }
2525                 break;
2526             case 6: op = rv_op_ori; break;
2527             case 7: op = rv_op_andi; break;
2528             }
2529             break;
2530         case 5: op = rv_op_auipc; break;
2531         case 6:
2532             switch ((inst >> 12) & 0b111) {
2533             case 0: op = rv_op_addiw; break;
2534             case 1:
2535                 switch ((inst >> 26) & 0b111111) {
2536                 case 0: op = rv_op_slliw; break;
2537                 case 2: op = rv_op_slli_uw; break;
2538                 case 24:
2539                     switch ((inst >> 20) & 0b11111) {
2540                     case 0b00000: op = rv_op_clzw; break;
2541                     case 0b00001: op = rv_op_ctzw; break;
2542                     case 0b00010: op = rv_op_cpopw; break;
2543                     }
2544                     break;
2545                 }
2546                 break;
2547             case 5:
2548                 switch ((inst >> 25) & 0b1111111) {
2549                 case 0: op = rv_op_srliw; break;
2550                 case 32: op = rv_op_sraiw; break;
2551                 case 48: op = rv_op_roriw; break;
2552                 }
2553                 break;
2554             }
2555             break;
2556         case 8:
2557             switch ((inst >> 12) & 0b111) {
2558             case 0: op = rv_op_sb; break;
2559             case 1: op = rv_op_sh; break;
2560             case 2: op = rv_op_sw; break;
2561             case 3: op = rv_op_sd; break;
2562             case 4: op = rv_op_sq; break;
2563             }
2564             break;
2565         case 9:
2566             switch ((inst >> 12) & 0b111) {
2567             case 0:
2568                 switch ((inst >> 20) & 0b111111111111) {
2569                 case 40: op = rv_op_vs1r_v; break;
2570                 case 552: op = rv_op_vs2r_v; break;
2571                 case 1576: op = rv_op_vs4r_v; break;
2572                 case 3624: op = rv_op_vs8r_v; break;
2573                 }
2574                 switch ((inst >> 26) & 0b111) {
2575                 case 0:
2576                     switch ((inst >> 20) & 0b11111) {
2577                     case 0: op = rv_op_vse8_v; break;
2578                     case 11: op = rv_op_vsm_v; break;
2579                     }
2580                     break;
2581                 case 1: op = rv_op_vsuxei8_v; break;
2582                 case 2: op = rv_op_vsse8_v; break;
2583                 case 3: op = rv_op_vsoxei8_v; break;
2584                 }
2585                 break;
2586             case 2: op = rv_op_fsw; break;
2587             case 3: op = rv_op_fsd; break;
2588             case 4: op = rv_op_fsq; break;
2589             case 5:
2590                 switch ((inst >> 26) & 0b111) {
2591                 case 0:
2592                     switch ((inst >> 20) & 0b11111) {
2593                     case 0: op = rv_op_vse16_v; break;
2594                     }
2595                     break;
2596                 case 1: op = rv_op_vsuxei16_v; break;
2597                 case 2: op = rv_op_vsse16_v; break;
2598                 case 3: op = rv_op_vsoxei16_v; break;
2599                 }
2600                 break;
2601             case 6:
2602                 switch ((inst >> 26) & 0b111) {
2603                 case 0:
2604                     switch ((inst >> 20) & 0b11111) {
2605                     case 0: op = rv_op_vse32_v; break;
2606                     }
2607                     break;
2608                 case 1: op = rv_op_vsuxei32_v; break;
2609                 case 2: op = rv_op_vsse32_v; break;
2610                 case 3: op = rv_op_vsoxei32_v; break;
2611                 }
2612                 break;
2613             case 7:
2614                 switch ((inst >> 26) & 0b111) {
2615                 case 0:
2616                     switch ((inst >> 20) & 0b11111) {
2617                     case 0: op = rv_op_vse64_v; break;
2618                     }
2619                     break;
2620                 case 1: op = rv_op_vsuxei64_v; break;
2621                 case 2: op = rv_op_vsse64_v; break;
2622                 case 3: op = rv_op_vsoxei64_v; break;
2623                 }
2624                 break;
2625             }
2626             break;
2627         case 11:
2628             switch (((inst >> 24) & 0b11111000) |
2629                     ((inst >> 12) & 0b00000111)) {
2630             case 2: op = rv_op_amoadd_w; break;
2631             case 3: op = rv_op_amoadd_d; break;
2632             case 4: op = rv_op_amoadd_q; break;
2633             case 10: op = rv_op_amoswap_w; break;
2634             case 11: op = rv_op_amoswap_d; break;
2635             case 12: op = rv_op_amoswap_q; break;
2636             case 18:
2637                 switch ((inst >> 20) & 0b11111) {
2638                 case 0: op = rv_op_lr_w; break;
2639                 }
2640                 break;
2641             case 19:
2642                 switch ((inst >> 20) & 0b11111) {
2643                 case 0: op = rv_op_lr_d; break;
2644                 }
2645                 break;
2646             case 20:
2647                 switch ((inst >> 20) & 0b11111) {
2648                 case 0: op = rv_op_lr_q; break;
2649                 }
2650                 break;
2651             case 26: op = rv_op_sc_w; break;
2652             case 27: op = rv_op_sc_d; break;
2653             case 28: op = rv_op_sc_q; break;
2654             case 34: op = rv_op_amoxor_w; break;
2655             case 35: op = rv_op_amoxor_d; break;
2656             case 36: op = rv_op_amoxor_q; break;
2657             case 66: op = rv_op_amoor_w; break;
2658             case 67: op = rv_op_amoor_d; break;
2659             case 68: op = rv_op_amoor_q; break;
2660             case 98: op = rv_op_amoand_w; break;
2661             case 99: op = rv_op_amoand_d; break;
2662             case 100: op = rv_op_amoand_q; break;
2663             case 130: op = rv_op_amomin_w; break;
2664             case 131: op = rv_op_amomin_d; break;
2665             case 132: op = rv_op_amomin_q; break;
2666             case 162: op = rv_op_amomax_w; break;
2667             case 163: op = rv_op_amomax_d; break;
2668             case 164: op = rv_op_amomax_q; break;
2669             case 194: op = rv_op_amominu_w; break;
2670             case 195: op = rv_op_amominu_d; break;
2671             case 196: op = rv_op_amominu_q; break;
2672             case 226: op = rv_op_amomaxu_w; break;
2673             case 227: op = rv_op_amomaxu_d; break;
2674             case 228: op = rv_op_amomaxu_q; break;
2675             }
2676             break;
2677         case 12:
2678             switch (((inst >> 22) & 0b1111111000) |
2679                     ((inst >> 12) & 0b0000000111)) {
2680             case 0: op = rv_op_add; break;
2681             case 1: op = rv_op_sll; break;
2682             case 2: op = rv_op_slt; break;
2683             case 3: op = rv_op_sltu; break;
2684             case 4: op = rv_op_xor; break;
2685             case 5: op = rv_op_srl; break;
2686             case 6: op = rv_op_or; break;
2687             case 7: op = rv_op_and; break;
2688             case 8: op = rv_op_mul; break;
2689             case 9: op = rv_op_mulh; break;
2690             case 10: op = rv_op_mulhsu; break;
2691             case 11: op = rv_op_mulhu; break;
2692             case 12: op = rv_op_div; break;
2693             case 13: op = rv_op_divu; break;
2694             case 14: op = rv_op_rem; break;
2695             case 15: op = rv_op_remu; break;
2696             case 36:
2697                 switch ((inst >> 20) & 0b11111) {
2698                 case 0: op = rv_op_zext_h; break;
2699                 default: op = rv_op_pack; break;
2700                 }
2701                 break;
2702             case 39: op = rv_op_packh; break;
2703
2704             case 41: op = rv_op_clmul; break;
2705             case 42: op = rv_op_clmulr; break;
2706             case 43: op = rv_op_clmulh; break;
2707             case 44: op = rv_op_min; break;
2708             case 45: op = rv_op_minu; break;
2709             case 46: op = rv_op_max; break;
2710             case 47: op = rv_op_maxu; break;
2711             case 075: op = rv_op_czero_eqz; break;
2712             case 077: op = rv_op_czero_nez; break;
2713             case 130: op = rv_op_sh1add; break;
2714             case 132: op = rv_op_sh2add; break;
2715             case 134: op = rv_op_sh3add; break;
2716             case 161: op = rv_op_bset; break;
2717             case 162: op = rv_op_xperm4; break;
2718             case 164: op = rv_op_xperm8; break;
2719             case 200: op = rv_op_aes64es; break;
2720             case 216: op = rv_op_aes64esm; break;
2721             case 232: op = rv_op_aes64ds; break;
2722             case 248: op = rv_op_aes64dsm; break;
2723             case 256: op = rv_op_sub; break;
2724             case 260: op = rv_op_xnor; break;
2725             case 261: op = rv_op_sra; break;
2726             case 262: op = rv_op_orn; break;
2727             case 263: op = rv_op_andn; break;
2728             case 289: op = rv_op_bclr; break;
2729             case 293: op = rv_op_bext; break;
2730             case 320: op = rv_op_sha512sum0r; break;
2731             case 328: op = rv_op_sha512sum1r; break;
2732             case 336: op = rv_op_sha512sig0l; break;
2733             case 344: op = rv_op_sha512sig1l; break;
2734             case 368: op = rv_op_sha512sig0h; break;
2735             case 376: op = rv_op_sha512sig1h; break;
2736             case 385: op = rv_op_rol; break;
2737             case 389: op = rv_op_ror; break;
2738             case 417: op = rv_op_binv; break;
2739             case 504: op = rv_op_aes64ks2; break;
2740             }
2741             switch ((inst >> 25) & 0b0011111) {
2742             case 17: op = rv_op_aes32esi; break;
2743             case 19: op = rv_op_aes32esmi; break;
2744             case 21: op = rv_op_aes32dsi; break;
2745             case 23: op = rv_op_aes32dsmi; break;
2746             case 24: op = rv_op_sm4ed; break;
2747             case 26: op = rv_op_sm4ks; break;
2748             }
2749             break;
2750         case 13: op = rv_op_lui; break;
2751         case 14:
2752             switch (((inst >> 22) & 0b1111111000) |
2753                     ((inst >> 12) & 0b0000000111)) {
2754             case 0: op = rv_op_addw; break;
2755             case 1: op = rv_op_sllw; break;
2756             case 5: op = rv_op_srlw; break;
2757             case 8: op = rv_op_mulw; break;
2758             case 12: op = rv_op_divw; break;
2759             case 13: op = rv_op_divuw; break;
2760             case 14: op = rv_op_remw; break;
2761             case 15: op = rv_op_remuw; break;
2762             case 32: op = rv_op_add_uw; break;
2763             case 36:
2764                 switch ((inst >> 20) & 0b11111) {
2765                 case 0: op = rv_op_zext_h; break;
2766                 default: op = rv_op_packw; break;
2767                 }
2768                 break;
2769             case 130: op = rv_op_sh1add_uw; break;
2770             case 132: op = rv_op_sh2add_uw; break;
2771             case 134: op = rv_op_sh3add_uw; break;
2772             case 256: op = rv_op_subw; break;
2773             case 261: op = rv_op_sraw; break;
2774             case 385: op = rv_op_rolw; break;
2775             case 389: op = rv_op_rorw; break;
2776             }
2777             break;
2778         case 16:
2779             switch ((inst >> 25) & 0b11) {
2780             case 0: op = rv_op_fmadd_s; break;
2781             case 1: op = rv_op_fmadd_d; break;
2782             case 3: op = rv_op_fmadd_q; break;
2783             }
2784             break;
2785         case 17:
2786             switch ((inst >> 25) & 0b11) {
2787             case 0: op = rv_op_fmsub_s; break;
2788             case 1: op = rv_op_fmsub_d; break;
2789             case 3: op = rv_op_fmsub_q; break;
2790             }
2791             break;
2792         case 18:
2793             switch ((inst >> 25) & 0b11) {
2794             case 0: op = rv_op_fnmsub_s; break;
2795             case 1: op = rv_op_fnmsub_d; break;
2796             case 3: op = rv_op_fnmsub_q; break;
2797             }
2798             break;
2799         case 19:
2800             switch ((inst >> 25) & 0b11) {
2801             case 0: op = rv_op_fnmadd_s; break;
2802             case 1: op = rv_op_fnmadd_d; break;
2803             case 3: op = rv_op_fnmadd_q; break;
2804             }
2805             break;
2806         case 20:
2807             switch ((inst >> 25) & 0b1111111) {
2808             case 0: op = rv_op_fadd_s; break;
2809             case 1: op = rv_op_fadd_d; break;
2810             case 3: op = rv_op_fadd_q; break;
2811             case 4: op = rv_op_fsub_s; break;
2812             case 5: op = rv_op_fsub_d; break;
2813             case 7: op = rv_op_fsub_q; break;
2814             case 8: op = rv_op_fmul_s; break;
2815             case 9: op = rv_op_fmul_d; break;
2816             case 11: op = rv_op_fmul_q; break;
2817             case 12: op = rv_op_fdiv_s; break;
2818             case 13: op = rv_op_fdiv_d; break;
2819             case 15: op = rv_op_fdiv_q; break;
2820             case 16:
2821                 switch ((inst >> 12) & 0b111) {
2822                 case 0: op = rv_op_fsgnj_s; break;
2823                 case 1: op = rv_op_fsgnjn_s; break;
2824                 case 2: op = rv_op_fsgnjx_s; break;
2825                 }
2826                 break;
2827             case 17:
2828                 switch ((inst >> 12) & 0b111) {
2829                 case 0: op = rv_op_fsgnj_d; break;
2830                 case 1: op = rv_op_fsgnjn_d; break;
2831                 case 2: op = rv_op_fsgnjx_d; break;
2832                 }
2833                 break;
2834             case 19:
2835                 switch ((inst >> 12) & 0b111) {
2836                 case 0: op = rv_op_fsgnj_q; break;
2837                 case 1: op = rv_op_fsgnjn_q; break;
2838                 case 2: op = rv_op_fsgnjx_q; break;
2839                 }
2840                 break;
2841             case 20:
2842                 switch ((inst >> 12) & 0b111) {
2843                 case 0: op = rv_op_fmin_s; break;
2844                 case 1: op = rv_op_fmax_s; break;
2845                 }
2846                 break;
2847             case 21:
2848                 switch ((inst >> 12) & 0b111) {
2849                 case 0: op = rv_op_fmin_d; break;
2850                 case 1: op = rv_op_fmax_d; break;
2851                 }
2852                 break;
2853             case 23:
2854                 switch ((inst >> 12) & 0b111) {
2855                 case 0: op = rv_op_fmin_q; break;
2856                 case 1: op = rv_op_fmax_q; break;
2857                 }
2858                 break;
2859             case 32:
2860                 switch ((inst >> 20) & 0b11111) {
2861                 case 1: op = rv_op_fcvt_s_d; break;
2862                 case 3: op = rv_op_fcvt_s_q; break;
2863                 }
2864                 break;
2865             case 33:
2866                 switch ((inst >> 20) & 0b11111) {
2867                 case 0: op = rv_op_fcvt_d_s; break;
2868                 case 3: op = rv_op_fcvt_d_q; break;
2869                 }
2870                 break;
2871             case 35:
2872                 switch ((inst >> 20) & 0b11111) {
2873                 case 0: op = rv_op_fcvt_q_s; break;
2874                 case 1: op = rv_op_fcvt_q_d; break;
2875                 }
2876                 break;
2877             case 44:
2878                 switch ((inst >> 20) & 0b11111) {
2879                 case 0: op = rv_op_fsqrt_s; break;
2880                 }
2881                 break;
2882             case 45:
2883                 switch ((inst >> 20) & 0b11111) {
2884                 case 0: op = rv_op_fsqrt_d; break;
2885                 }
2886                 break;
2887             case 47:
2888                 switch ((inst >> 20) & 0b11111) {
2889                 case 0: op = rv_op_fsqrt_q; break;
2890                 }
2891                 break;
2892             case 80:
2893                 switch ((inst >> 12) & 0b111) {
2894                 case 0: op = rv_op_fle_s; break;
2895                 case 1: op = rv_op_flt_s; break;
2896                 case 2: op = rv_op_feq_s; break;
2897                 }
2898                 break;
2899             case 81:
2900                 switch ((inst >> 12) & 0b111) {
2901                 case 0: op = rv_op_fle_d; break;
2902                 case 1: op = rv_op_flt_d; break;
2903                 case 2: op = rv_op_feq_d; break;
2904                 }
2905                 break;
2906             case 83:
2907                 switch ((inst >> 12) & 0b111) {
2908                 case 0: op = rv_op_fle_q; break;
2909                 case 1: op = rv_op_flt_q; break;
2910                 case 2: op = rv_op_feq_q; break;
2911                 }
2912                 break;
2913             case 96:
2914                 switch ((inst >> 20) & 0b11111) {
2915                 case 0: op = rv_op_fcvt_w_s; break;
2916                 case 1: op = rv_op_fcvt_wu_s; break;
2917                 case 2: op = rv_op_fcvt_l_s; break;
2918                 case 3: op = rv_op_fcvt_lu_s; break;
2919                 }
2920                 break;
2921             case 97:
2922                 switch ((inst >> 20) & 0b11111) {
2923                 case 0: op = rv_op_fcvt_w_d; break;
2924                 case 1: op = rv_op_fcvt_wu_d; break;
2925                 case 2: op = rv_op_fcvt_l_d; break;
2926                 case 3: op = rv_op_fcvt_lu_d; break;
2927                 }
2928                 break;
2929             case 99:
2930                 switch ((inst >> 20) & 0b11111) {
2931                 case 0: op = rv_op_fcvt_w_q; break;
2932                 case 1: op = rv_op_fcvt_wu_q; break;
2933                 case 2: op = rv_op_fcvt_l_q; break;
2934                 case 3: op = rv_op_fcvt_lu_q; break;
2935                 }
2936                 break;
2937             case 104:
2938                 switch ((inst >> 20) & 0b11111) {
2939                 case 0: op = rv_op_fcvt_s_w; break;
2940                 case 1: op = rv_op_fcvt_s_wu; break;
2941                 case 2: op = rv_op_fcvt_s_l; break;
2942                 case 3: op = rv_op_fcvt_s_lu; break;
2943                 }
2944                 break;
2945             case 105:
2946                 switch ((inst >> 20) & 0b11111) {
2947                 case 0: op = rv_op_fcvt_d_w; break;
2948                 case 1: op = rv_op_fcvt_d_wu; break;
2949                 case 2: op = rv_op_fcvt_d_l; break;
2950                 case 3: op = rv_op_fcvt_d_lu; break;
2951                 }
2952                 break;
2953             case 107:
2954                 switch ((inst >> 20) & 0b11111) {
2955                 case 0: op = rv_op_fcvt_q_w; break;
2956                 case 1: op = rv_op_fcvt_q_wu; break;
2957                 case 2: op = rv_op_fcvt_q_l; break;
2958                 case 3: op = rv_op_fcvt_q_lu; break;
2959                 }
2960                 break;
2961             case 112:
2962                 switch (((inst >> 17) & 0b11111000) |
2963                         ((inst >> 12) & 0b00000111)) {
2964                 case 0: op = rv_op_fmv_x_s; break;
2965                 case 1: op = rv_op_fclass_s; break;
2966                 }
2967                 break;
2968             case 113:
2969                 switch (((inst >> 17) & 0b11111000) |
2970                         ((inst >> 12) & 0b00000111)) {
2971                 case 0: op = rv_op_fmv_x_d; break;
2972                 case 1: op = rv_op_fclass_d; break;
2973                 }
2974                 break;
2975             case 115:
2976                 switch (((inst >> 17) & 0b11111000) |
2977                         ((inst >> 12) & 0b00000111)) {
2978                 case 0: op = rv_op_fmv_x_q; break;
2979                 case 1: op = rv_op_fclass_q; break;
2980                 }
2981                 break;
2982             case 120:
2983                 switch (((inst >> 17) & 0b11111000) |
2984                         ((inst >> 12) & 0b00000111)) {
2985                 case 0: op = rv_op_fmv_s_x; break;
2986                 }
2987                 break;
2988             case 121:
2989                 switch (((inst >> 17) & 0b11111000) |
2990                         ((inst >> 12) & 0b00000111)) {
2991                 case 0: op = rv_op_fmv_d_x; break;
2992                 }
2993                 break;
2994             case 123:
2995                 switch (((inst >> 17) & 0b11111000) |
2996                         ((inst >> 12) & 0b00000111)) {
2997                 case 0: op = rv_op_fmv_q_x; break;
2998                 }
2999                 break;
3000             }
3001             break;
3002         case 21:
3003             switch ((inst >> 12) & 0b111) {
3004             case 0:
3005                 switch ((inst >> 26) & 0b111111) {
3006                 case 0: op = rv_op_vadd_vv; break;
3007                 case 2: op = rv_op_vsub_vv; break;
3008                 case 4: op = rv_op_vminu_vv; break;
3009                 case 5: op = rv_op_vmin_vv; break;
3010                 case 6: op = rv_op_vmaxu_vv; break;
3011                 case 7: op = rv_op_vmax_vv; break;
3012                 case 9: op = rv_op_vand_vv; break;
3013                 case 10: op = rv_op_vor_vv; break;
3014                 case 11: op = rv_op_vxor_vv; break;
3015                 case 12: op = rv_op_vrgather_vv; break;
3016                 case 14: op = rv_op_vrgatherei16_vv; break;
3017                 case 16:
3018                     if (((inst >> 25) & 1) == 0) {
3019                         op = rv_op_vadc_vvm;
3020                     }
3021                     break;
3022                 case 17: op = rv_op_vmadc_vvm; break;
3023                 case 18:
3024                     if (((inst >> 25) & 1) == 0) {
3025                         op = rv_op_vsbc_vvm;
3026                     }
3027                     break;
3028                 case 19: op = rv_op_vmsbc_vvm; break;
3029                 case 23:
3030                     if (((inst >> 20) & 0b111111) == 32)
3031                         op = rv_op_vmv_v_v;
3032                     else if (((inst >> 25) & 1) == 0)
3033                         op = rv_op_vmerge_vvm;
3034                     break;
3035                 case 24: op = rv_op_vmseq_vv; break;
3036                 case 25: op = rv_op_vmsne_vv; break;
3037                 case 26: op = rv_op_vmsltu_vv; break;
3038                 case 27: op = rv_op_vmslt_vv; break;
3039                 case 28: op = rv_op_vmsleu_vv; break;
3040                 case 29: op = rv_op_vmsle_vv; break;
3041                 case 32: op = rv_op_vsaddu_vv; break;
3042                 case 33: op = rv_op_vsadd_vv; break;
3043                 case 34: op = rv_op_vssubu_vv; break;
3044                 case 35: op = rv_op_vssub_vv; break;
3045                 case 37: op = rv_op_vsll_vv; break;
3046                 case 39: op = rv_op_vsmul_vv; break;
3047                 case 40: op = rv_op_vsrl_vv; break;
3048                 case 41: op = rv_op_vsra_vv; break;
3049                 case 42: op = rv_op_vssrl_vv; break;
3050                 case 43: op = rv_op_vssra_vv; break;
3051                 case 44: op = rv_op_vnsrl_wv; break;
3052                 case 45: op = rv_op_vnsra_wv; break;
3053                 case 46: op = rv_op_vnclipu_wv; break;
3054                 case 47: op = rv_op_vnclip_wv; break;
3055                 case 48: op = rv_op_vwredsumu_vs; break;
3056                 case 49: op = rv_op_vwredsum_vs; break;
3057                 }
3058                 break;
3059             case 1:
3060                 switch ((inst >> 26) & 0b111111) {
3061                 case 0: op = rv_op_vfadd_vv; break;
3062                 case 1: op = rv_op_vfredusum_vs; break;
3063                 case 2: op = rv_op_vfsub_vv; break;
3064                 case 3: op = rv_op_vfredosum_vs; break;
3065                 case 4: op = rv_op_vfmin_vv; break;
3066                 case 5: op = rv_op_vfredmin_vs; break;
3067                 case 6: op = rv_op_vfmax_vv; break;
3068                 case 7: op = rv_op_vfredmax_vs; break;
3069                 case 8: op = rv_op_vfsgnj_vv; break;
3070                 case 9: op = rv_op_vfsgnjn_vv; break;
3071                 case 10: op = rv_op_vfsgnjx_vv; break;
3072                 case 16:
3073                     switch ((inst >> 15) & 0b11111) {
3074                     case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break;
3075                     }
3076                     break;
3077                 case 18:
3078                     switch ((inst >> 15) & 0b11111) {
3079                     case 0: op = rv_op_vfcvt_xu_f_v; break;
3080                     case 1: op = rv_op_vfcvt_x_f_v; break;
3081                     case 2: op = rv_op_vfcvt_f_xu_v; break;
3082                     case 3: op = rv_op_vfcvt_f_x_v; break;
3083                     case 6: op = rv_op_vfcvt_rtz_xu_f_v; break;
3084                     case 7: op = rv_op_vfcvt_rtz_x_f_v; break;
3085                     case 8: op = rv_op_vfwcvt_xu_f_v; break;
3086                     case 9: op = rv_op_vfwcvt_x_f_v; break;
3087                     case 10: op = rv_op_vfwcvt_f_xu_v; break;
3088                     case 11: op = rv_op_vfwcvt_f_x_v; break;
3089                     case 12: op = rv_op_vfwcvt_f_f_v; break;
3090                     case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
3091                     case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
3092                     case 16: op = rv_op_vfncvt_xu_f_w; break;
3093                     case 17: op = rv_op_vfncvt_x_f_w; break;
3094                     case 18: op = rv_op_vfncvt_f_xu_w; break;
3095                     case 19: op = rv_op_vfncvt_f_x_w; break;
3096                     case 20: op = rv_op_vfncvt_f_f_w; break;
3097                     case 21: op = rv_op_vfncvt_rod_f_f_w; break;
3098                     case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
3099                     case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
3100                     }
3101                     break;
3102                 case 19:
3103                     switch ((inst >> 15) & 0b11111) {
3104                     case 0: op = rv_op_vfsqrt_v; break;
3105                     case 4: op = rv_op_vfrsqrt7_v; break;
3106                     case 5: op = rv_op_vfrec7_v; break;
3107                     case 16: op = rv_op_vfclass_v; break;
3108                     }
3109                     break;
3110                 case 24: op = rv_op_vmfeq_vv; break;
3111                 case 25: op = rv_op_vmfle_vv; break;
3112                 case 27: op = rv_op_vmflt_vv; break;
3113                 case 28: op = rv_op_vmfne_vv; break;
3114                 case 32: op = rv_op_vfdiv_vv; break;
3115                 case 36: op = rv_op_vfmul_vv; break;
3116                 case 40: op = rv_op_vfmadd_vv; break;
3117                 case 41: op = rv_op_vfnmadd_vv; break;
3118                 case 42: op = rv_op_vfmsub_vv; break;
3119                 case 43: op = rv_op_vfnmsub_vv; break;
3120                 case 44: op = rv_op_vfmacc_vv; break;
3121                 case 45: op = rv_op_vfnmacc_vv; break;
3122                 case 46: op = rv_op_vfmsac_vv; break;
3123                 case 47: op = rv_op_vfnmsac_vv; break;
3124                 case 48: op = rv_op_vfwadd_vv; break;
3125                 case 49: op = rv_op_vfwredusum_vs; break;
3126                 case 50: op = rv_op_vfwsub_vv; break;
3127                 case 51: op = rv_op_vfwredosum_vs; break;
3128                 case 52: op = rv_op_vfwadd_wv; break;
3129                 case 54: op = rv_op_vfwsub_wv; break;
3130                 case 56: op = rv_op_vfwmul_vv; break;
3131                 case 60: op = rv_op_vfwmacc_vv; break;
3132                 case 61: op = rv_op_vfwnmacc_vv; break;
3133                 case 62: op = rv_op_vfwmsac_vv; break;
3134                 case 63: op = rv_op_vfwnmsac_vv; break;
3135                 }
3136                 break;
3137             case 2:
3138                 switch ((inst >> 26) & 0b111111) {
3139                 case 0: op = rv_op_vredsum_vs; break;
3140                 case 1: op = rv_op_vredand_vs; break;
3141                 case 2: op = rv_op_vredor_vs; break;
3142                 case 3: op = rv_op_vredxor_vs; break;
3143                 case 4: op = rv_op_vredminu_vs; break;
3144                 case 5: op = rv_op_vredmin_vs; break;
3145                 case 6: op = rv_op_vredmaxu_vs; break;
3146                 case 7: op = rv_op_vredmax_vs; break;
3147                 case 8: op = rv_op_vaaddu_vv; break;
3148                 case 9: op = rv_op_vaadd_vv; break;
3149                 case 10: op = rv_op_vasubu_vv; break;
3150                 case 11: op = rv_op_vasub_vv; break;
3151                 case 16:
3152                     switch ((inst >> 15) & 0b11111) {
3153                     case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
3154                     case 16: op = rv_op_vcpop_m; break;
3155                     case 17: op = rv_op_vfirst_m; break;
3156                     }
3157                     break;
3158                 case 18:
3159                     switch ((inst >> 15) & 0b11111) {
3160                     case 2: op = rv_op_vzext_vf8; break;
3161                     case 3: op = rv_op_vsext_vf8; break;
3162                     case 4: op = rv_op_vzext_vf4; break;
3163                     case 5: op = rv_op_vsext_vf4; break;
3164                     case 6: op = rv_op_vzext_vf2; break;
3165                     case 7: op = rv_op_vsext_vf2; break;
3166                     }
3167                     break;
3168                 case 20:
3169                     switch ((inst >> 15) & 0b11111) {
3170                     case 1: op = rv_op_vmsbf_m;  break;
3171                     case 2: op = rv_op_vmsof_m; break;
3172                     case 3: op = rv_op_vmsif_m; break;
3173                     case 16: op = rv_op_viota_m; break;
3174                     case 17:
3175                         if (((inst >> 20) & 0b11111) == 0) {
3176                             op = rv_op_vid_v;
3177                         }
3178                         break;
3179                     }
3180                     break;
3181                 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
3182                 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break;
3183                 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break;
3184                 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break;
3185                 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break;
3186                 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break;
3187                 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break;
3188                 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break;
3189                 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break;
3190                 case 32: op = rv_op_vdivu_vv; break;
3191                 case 33: op = rv_op_vdiv_vv; break;
3192                 case 34: op = rv_op_vremu_vv; break;
3193                 case 35: op = rv_op_vrem_vv; break;
3194                 case 36: op = rv_op_vmulhu_vv; break;
3195                 case 37: op = rv_op_vmul_vv; break;
3196                 case 38: op = rv_op_vmulhsu_vv; break;
3197                 case 39: op = rv_op_vmulh_vv; break;
3198                 case 41: op = rv_op_vmadd_vv; break;
3199                 case 43: op = rv_op_vnmsub_vv; break;
3200                 case 45: op = rv_op_vmacc_vv; break;
3201                 case 47: op = rv_op_vnmsac_vv; break;
3202                 case 48: op = rv_op_vwaddu_vv; break;
3203                 case 49: op = rv_op_vwadd_vv; break;
3204                 case 50: op = rv_op_vwsubu_vv; break;
3205                 case 51: op = rv_op_vwsub_vv; break;
3206                 case 52: op = rv_op_vwaddu_wv; break;
3207                 case 53: op = rv_op_vwadd_wv; break;
3208                 case 54: op = rv_op_vwsubu_wv; break;
3209                 case 55: op = rv_op_vwsub_wv; break;
3210                 case 56: op = rv_op_vwmulu_vv; break;
3211                 case 58: op = rv_op_vwmulsu_vv; break;
3212                 case 59: op = rv_op_vwmul_vv; break;
3213                 case 60: op = rv_op_vwmaccu_vv; break;
3214                 case 61: op = rv_op_vwmacc_vv; break;
3215                 case 63: op = rv_op_vwmaccsu_vv; break;
3216                 }
3217                 break;
3218             case 3:
3219                 switch ((inst >> 26) & 0b111111) {
3220                 case 0: op = rv_op_vadd_vi; break;
3221                 case 3: op = rv_op_vrsub_vi; break;
3222                 case 9: op = rv_op_vand_vi; break;
3223                 case 10: op = rv_op_vor_vi; break;
3224                 case 11: op = rv_op_vxor_vi; break;
3225                 case 12: op = rv_op_vrgather_vi; break;
3226                 case 14: op = rv_op_vslideup_vi; break;
3227                 case 15: op = rv_op_vslidedown_vi; break;
3228                 case 16:
3229                     if (((inst >> 25) & 1) == 0) {
3230                         op = rv_op_vadc_vim;
3231                     }
3232                     break;
3233                 case 17: op = rv_op_vmadc_vim; break;
3234                 case 23:
3235                     if (((inst >> 20) & 0b111111) == 32)
3236                         op = rv_op_vmv_v_i;
3237                     else if (((inst >> 25) & 1) == 0)
3238                         op = rv_op_vmerge_vim;
3239                     break;
3240                 case 24: op = rv_op_vmseq_vi; break;
3241                 case 25: op = rv_op_vmsne_vi; break;
3242                 case 28: op = rv_op_vmsleu_vi; break;
3243                 case 29: op = rv_op_vmsle_vi; break;
3244                 case 30: op = rv_op_vmsgtu_vi; break;
3245                 case 31: op = rv_op_vmsgt_vi; break;
3246                 case 32: op = rv_op_vsaddu_vi; break;
3247                 case 33: op = rv_op_vsadd_vi; break;
3248                 case 37: op = rv_op_vsll_vi; break;
3249                 case 39:
3250                     switch ((inst >> 15) & 0b11111) {
3251                     case 0: op = rv_op_vmv1r_v; break;
3252                     case 1: op = rv_op_vmv2r_v; break;
3253                     case 3: op = rv_op_vmv4r_v; break;
3254                     case 7: op = rv_op_vmv8r_v; break;
3255                     }
3256                     break;
3257                 case 40: op = rv_op_vsrl_vi; break;
3258                 case 41: op = rv_op_vsra_vi; break;
3259                 case 42: op = rv_op_vssrl_vi; break;
3260                 case 43: op = rv_op_vssra_vi; break;
3261                 case 44: op = rv_op_vnsrl_wi; break;
3262                 case 45: op = rv_op_vnsra_wi; break;
3263                 case 46: op = rv_op_vnclipu_wi; break;
3264                 case 47: op = rv_op_vnclip_wi; break;
3265                 }
3266                 break;
3267             case 4:
3268                 switch ((inst >> 26) & 0b111111) {
3269                 case 0: op = rv_op_vadd_vx; break;
3270                 case 2: op = rv_op_vsub_vx; break;
3271                 case 3: op = rv_op_vrsub_vx; break;
3272                 case 4: op = rv_op_vminu_vx; break;
3273                 case 5: op = rv_op_vmin_vx; break;
3274                 case 6: op = rv_op_vmaxu_vx; break;
3275                 case 7: op = rv_op_vmax_vx; break;
3276                 case 9: op = rv_op_vand_vx; break;
3277                 case 10: op = rv_op_vor_vx; break;
3278                 case 11: op = rv_op_vxor_vx; break;
3279                 case 12: op = rv_op_vrgather_vx; break;
3280                 case 14: op = rv_op_vslideup_vx; break;
3281                 case 15: op = rv_op_vslidedown_vx; break;
3282                 case 16:
3283                     if (((inst >> 25) & 1) == 0) {
3284                         op = rv_op_vadc_vxm;
3285                     }
3286                     break;
3287                 case 17: op = rv_op_vmadc_vxm; break;
3288                 case 18:
3289                     if (((inst >> 25) & 1) == 0) {
3290                         op = rv_op_vsbc_vxm;
3291                     }
3292                     break;
3293                 case 19: op = rv_op_vmsbc_vxm; break;
3294                 case 23:
3295                     if (((inst >> 20) & 0b111111) == 32)
3296                         op = rv_op_vmv_v_x;
3297                     else if (((inst >> 25) & 1) == 0)
3298                         op = rv_op_vmerge_vxm;
3299                     break;
3300                 case 24: op = rv_op_vmseq_vx; break;
3301                 case 25: op = rv_op_vmsne_vx; break;
3302                 case 26: op = rv_op_vmsltu_vx; break;
3303                 case 27: op = rv_op_vmslt_vx; break;
3304                 case 28: op = rv_op_vmsleu_vx; break;
3305                 case 29: op = rv_op_vmsle_vx; break;
3306                 case 30: op = rv_op_vmsgtu_vx; break;
3307                 case 31: op = rv_op_vmsgt_vx; break;
3308                 case 32: op = rv_op_vsaddu_vx; break;
3309                 case 33: op = rv_op_vsadd_vx; break;
3310                 case 34: op = rv_op_vssubu_vx; break;
3311                 case 35: op = rv_op_vssub_vx; break;
3312                 case 37: op = rv_op_vsll_vx; break;
3313                 case 39: op = rv_op_vsmul_vx; break;
3314                 case 40: op = rv_op_vsrl_vx; break;
3315                 case 41: op = rv_op_vsra_vx; break;
3316                 case 42: op = rv_op_vssrl_vx; break;
3317                 case 43: op = rv_op_vssra_vx; break;
3318                 case 44: op = rv_op_vnsrl_wx; break;
3319                 case 45: op = rv_op_vnsra_wx; break;
3320                 case 46: op = rv_op_vnclipu_wx; break;
3321                 case 47: op = rv_op_vnclip_wx; break;
3322                 }
3323                 break;
3324             case 5:
3325                 switch ((inst >> 26) & 0b111111) {
3326                 case 0: op = rv_op_vfadd_vf; break;
3327                 case 2: op = rv_op_vfsub_vf; break;
3328                 case 4: op = rv_op_vfmin_vf; break;
3329                 case 6: op = rv_op_vfmax_vf; break;
3330                 case 8: op = rv_op_vfsgnj_vf; break;
3331                 case 9: op = rv_op_vfsgnjn_vf; break;
3332                 case 10: op = rv_op_vfsgnjx_vf; break;
3333                 case 14: op = rv_op_vfslide1up_vf; break;
3334                 case 15: op = rv_op_vfslide1down_vf; break;
3335                 case 16:
3336                     switch ((inst >> 20) & 0b11111) {
3337                     case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break;
3338                     }
3339                     break;
3340                 case 23:
3341                     if (((inst >> 25) & 1) == 0)
3342                         op = rv_op_vfmerge_vfm;
3343                     else if (((inst >> 20) & 0b111111) == 32)
3344                         op = rv_op_vfmv_v_f;
3345                     break;
3346                 case 24: op = rv_op_vmfeq_vf; break;
3347                 case 25: op = rv_op_vmfle_vf; break;
3348                 case 27: op = rv_op_vmflt_vf; break;
3349                 case 28: op = rv_op_vmfne_vf; break;
3350                 case 29: op = rv_op_vmfgt_vf; break;
3351                 case 31: op = rv_op_vmfge_vf; break;
3352                 case 32: op = rv_op_vfdiv_vf; break;
3353                 case 33: op = rv_op_vfrdiv_vf; break;
3354                 case 36: op = rv_op_vfmul_vf; break;
3355                 case 39: op = rv_op_vfrsub_vf; break;
3356                 case 40: op = rv_op_vfmadd_vf; break;
3357                 case 41: op = rv_op_vfnmadd_vf; break;
3358                 case 42: op = rv_op_vfmsub_vf; break;
3359                 case 43: op = rv_op_vfnmsub_vf; break;
3360                 case 44: op = rv_op_vfmacc_vf; break;
3361                 case 45: op = rv_op_vfnmacc_vf; break;
3362                 case 46: op = rv_op_vfmsac_vf; break;
3363                 case 47: op = rv_op_vfnmsac_vf; break;
3364                 case 48: op = rv_op_vfwadd_vf; break;
3365                 case 50: op = rv_op_vfwsub_vf; break;
3366                 case 52: op = rv_op_vfwadd_wf; break;
3367                 case 54: op = rv_op_vfwsub_wf; break;
3368                 case 56: op = rv_op_vfwmul_vf; break;
3369                 case 60: op = rv_op_vfwmacc_vf; break;
3370                 case 61: op = rv_op_vfwnmacc_vf; break;
3371                 case 62: op = rv_op_vfwmsac_vf; break;
3372                 case 63: op = rv_op_vfwnmsac_vf; break;
3373                 }
3374                 break;
3375             case 6:
3376                 switch ((inst >> 26) & 0b111111) {
3377                 case 8: op = rv_op_vaaddu_vx; break;
3378                 case 9: op = rv_op_vaadd_vx; break;
3379                 case 10: op = rv_op_vasubu_vx; break;
3380                 case 11: op = rv_op_vasub_vx; break;
3381                 case 14: op = rv_op_vslide1up_vx; break;
3382                 case 15: op = rv_op_vslide1down_vx; break;
3383                 case 16:
3384                     switch ((inst >> 20) & 0b11111) {
3385                     case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break;
3386                     }
3387                     break;
3388                 case 32: op = rv_op_vdivu_vx; break;
3389                 case 33: op = rv_op_vdiv_vx; break;
3390                 case 34: op = rv_op_vremu_vx; break;
3391                 case 35: op = rv_op_vrem_vx; break;
3392                 case 36: op = rv_op_vmulhu_vx; break;
3393                 case 37: op = rv_op_vmul_vx; break;
3394                 case 38: op = rv_op_vmulhsu_vx; break;
3395                 case 39: op = rv_op_vmulh_vx; break;
3396                 case 41: op = rv_op_vmadd_vx; break;
3397                 case 43: op = rv_op_vnmsub_vx; break;
3398                 case 45: op = rv_op_vmacc_vx; break;
3399                 case 47: op = rv_op_vnmsac_vx; break;
3400                 case 48: op = rv_op_vwaddu_vx; break;
3401                 case 49: op = rv_op_vwadd_vx; break;
3402                 case 50: op = rv_op_vwsubu_vx; break;
3403                 case 51: op = rv_op_vwsub_vx; break;
3404                 case 52: op = rv_op_vwaddu_wx; break;
3405                 case 53: op = rv_op_vwadd_wx; break;
3406                 case 54: op = rv_op_vwsubu_wx; break;
3407                 case 55: op = rv_op_vwsub_wx; break;
3408                 case 56: op = rv_op_vwmulu_vx; break;
3409                 case 58: op = rv_op_vwmulsu_vx; break;
3410                 case 59: op = rv_op_vwmul_vx; break;
3411                 case 60: op = rv_op_vwmaccu_vx; break;
3412                 case 61: op = rv_op_vwmacc_vx; break;
3413                 case 62: op = rv_op_vwmaccus_vx; break;
3414                 case 63: op = rv_op_vwmaccsu_vx; break;
3415                 }
3416                 break;
3417             case 7:
3418                 if (((inst >> 31) & 1) == 0) {
3419                     op = rv_op_vsetvli;
3420                 } else if ((inst >> 30) & 1) {
3421                     op = rv_op_vsetivli;
3422                 } else if (((inst >> 25) & 0b11111) == 0) {
3423                     op = rv_op_vsetvl;
3424                 }
3425                 break;
3426             }
3427             break;
3428         case 22:
3429             switch ((inst >> 12) & 0b111) {
3430             case 0: op = rv_op_addid; break;
3431             case 1:
3432                 switch ((inst >> 26) & 0b111111) {
3433                 case 0: op = rv_op_sllid; break;
3434                 }
3435                 break;
3436             case 5:
3437                 switch ((inst >> 26) & 0b111111) {
3438                 case 0: op = rv_op_srlid; break;
3439                 case 16: op = rv_op_sraid; break;
3440                 }
3441                 break;
3442             }
3443             break;
3444         case 24:
3445             switch ((inst >> 12) & 0b111) {
3446             case 0: op = rv_op_beq; break;
3447             case 1: op = rv_op_bne; break;
3448             case 4: op = rv_op_blt; break;
3449             case 5: op = rv_op_bge; break;
3450             case 6: op = rv_op_bltu; break;
3451             case 7: op = rv_op_bgeu; break;
3452             }
3453             break;
3454         case 25:
3455             switch ((inst >> 12) & 0b111) {
3456             case 0: op = rv_op_jalr; break;
3457             }
3458             break;
3459         case 27: op = rv_op_jal; break;
3460         case 28:
3461             switch ((inst >> 12) & 0b111) {
3462             case 0:
3463                 switch (((inst >> 20) & 0b111111100000) |
3464                         ((inst >> 7) & 0b000000011111)) {
3465                 case 0:
3466                     switch ((inst >> 15) & 0b1111111111) {
3467                     case 0: op = rv_op_ecall; break;
3468                     case 32: op = rv_op_ebreak; break;
3469                     case 64: op = rv_op_uret; break;
3470                     }
3471                     break;
3472                 case 256:
3473                     switch ((inst >> 20) & 0b11111) {
3474                     case 2:
3475                         switch ((inst >> 15) & 0b11111) {
3476                         case 0: op = rv_op_sret; break;
3477                         }
3478                         break;
3479                     case 4: op = rv_op_sfence_vm; break;
3480                     case 5:
3481                         switch ((inst >> 15) & 0b11111) {
3482                         case 0: op = rv_op_wfi; break;
3483                         }
3484                         break;
3485                     }
3486                     break;
3487                 case 288: op = rv_op_sfence_vma; break;
3488                 case 512:
3489                     switch ((inst >> 15) & 0b1111111111) {
3490                     case 64: op = rv_op_hret; break;
3491                     }
3492                     break;
3493                 case 768:
3494                     switch ((inst >> 15) & 0b1111111111) {
3495                     case 64: op = rv_op_mret; break;
3496                     }
3497                     break;
3498                 case 1952:
3499                     switch ((inst >> 15) & 0b1111111111) {
3500                     case 576: op = rv_op_dret; break;
3501                     }
3502                     break;
3503                 }
3504                 break;
3505             case 1: op = rv_op_csrrw; break;
3506             case 2: op = rv_op_csrrs; break;
3507             case 3: op = rv_op_csrrc; break;
3508             case 5: op = rv_op_csrrwi; break;
3509             case 6: op = rv_op_csrrsi; break;
3510             case 7: op = rv_op_csrrci; break;
3511             }
3512             break;
3513         case 30:
3514             switch (((inst >> 22) & 0b1111111000) |
3515                     ((inst >> 12) & 0b0000000111)) {
3516             case 0: op = rv_op_addd; break;
3517             case 1: op = rv_op_slld; break;
3518             case 5: op = rv_op_srld; break;
3519             case 8: op = rv_op_muld; break;
3520             case 12: op = rv_op_divd; break;
3521             case 13: op = rv_op_divud; break;
3522             case 14: op = rv_op_remd; break;
3523             case 15: op = rv_op_remud; break;
3524             case 256: op = rv_op_subd; break;
3525             case 261: op = rv_op_srad; break;
3526             }
3527             break;
3528         }
3529         break;
3530     }
3531     dec->op = op;
3532 }
3533
3534 /* operand extractors */
3535
3536 static uint32_t operand_rd(rv_inst inst)
3537 {
3538     return (inst << 52) >> 59;
3539 }
3540
3541 static uint32_t operand_rs1(rv_inst inst)
3542 {
3543     return (inst << 44) >> 59;
3544 }
3545
3546 static uint32_t operand_rs2(rv_inst inst)
3547 {
3548     return (inst << 39) >> 59;
3549 }
3550
3551 static uint32_t operand_rs3(rv_inst inst)
3552 {
3553     return (inst << 32) >> 59;
3554 }
3555
3556 static uint32_t operand_aq(rv_inst inst)
3557 {
3558     return (inst << 37) >> 63;
3559 }
3560
3561 static uint32_t operand_rl(rv_inst inst)
3562 {
3563     return (inst << 38) >> 63;
3564 }
3565
3566 static uint32_t operand_pred(rv_inst inst)
3567 {
3568     return (inst << 36) >> 60;
3569 }
3570
3571 static uint32_t operand_succ(rv_inst inst)
3572 {
3573     return (inst << 40) >> 60;
3574 }
3575
3576 static uint32_t operand_rm(rv_inst inst)
3577 {
3578     return (inst << 49) >> 61;
3579 }
3580
3581 static uint32_t operand_shamt5(rv_inst inst)
3582 {
3583     return (inst << 39) >> 59;
3584 }
3585
3586 static uint32_t operand_shamt6(rv_inst inst)
3587 {
3588     return (inst << 38) >> 58;
3589 }
3590
3591 static uint32_t operand_shamt7(rv_inst inst)
3592 {
3593     return (inst << 37) >> 57;
3594 }
3595
3596 static uint32_t operand_crdq(rv_inst inst)
3597 {
3598     return (inst << 59) >> 61;
3599 }
3600
3601 static uint32_t operand_crs1q(rv_inst inst)
3602 {
3603     return (inst << 54) >> 61;
3604 }
3605
3606 static uint32_t operand_crs1rdq(rv_inst inst)
3607 {
3608     return (inst << 54) >> 61;
3609 }
3610
3611 static uint32_t operand_crs2q(rv_inst inst)
3612 {
3613     return (inst << 59) >> 61;
3614 }
3615
3616 static uint32_t calculate_xreg(uint32_t sreg)
3617 {
3618     return sreg < 2 ? sreg + 8 : sreg + 16;
3619 }
3620
3621 static uint32_t operand_sreg1(rv_inst inst)
3622 {
3623     return calculate_xreg((inst << 54) >> 61);
3624 }
3625
3626 static uint32_t operand_sreg2(rv_inst inst)
3627 {
3628     return calculate_xreg((inst << 59) >> 61);
3629 }
3630
3631 static uint32_t operand_crd(rv_inst inst)
3632 {
3633     return (inst << 52) >> 59;
3634 }
3635
3636 static uint32_t operand_crs1(rv_inst inst)
3637 {
3638     return (inst << 52) >> 59;
3639 }
3640
3641 static uint32_t operand_crs1rd(rv_inst inst)
3642 {
3643     return (inst << 52) >> 59;
3644 }
3645
3646 static uint32_t operand_crs2(rv_inst inst)
3647 {
3648     return (inst << 57) >> 59;
3649 }
3650
3651 static uint32_t operand_cimmsh5(rv_inst inst)
3652 {
3653     return (inst << 57) >> 59;
3654 }
3655
3656 static uint32_t operand_csr12(rv_inst inst)
3657 {
3658     return (inst << 32) >> 52;
3659 }
3660
3661 static int32_t operand_imm12(rv_inst inst)
3662 {
3663     return ((int64_t)inst << 32) >> 52;
3664 }
3665
3666 static int32_t operand_imm20(rv_inst inst)
3667 {
3668     return (((int64_t)inst << 32) >> 44) << 12;
3669 }
3670
3671 static int32_t operand_jimm20(rv_inst inst)
3672 {
3673     return (((int64_t)inst << 32) >> 63) << 20 |
3674         ((inst << 33) >> 54) << 1 |
3675         ((inst << 43) >> 63) << 11 |
3676         ((inst << 44) >> 56) << 12;
3677 }
3678
3679 static int32_t operand_simm12(rv_inst inst)
3680 {
3681     return (((int64_t)inst << 32) >> 57) << 5 |
3682         (inst << 52) >> 59;
3683 }
3684
3685 static int32_t operand_sbimm12(rv_inst inst)
3686 {
3687     return (((int64_t)inst << 32) >> 63) << 12 |
3688         ((inst << 33) >> 58) << 5 |
3689         ((inst << 52) >> 60) << 1 |
3690         ((inst << 56) >> 63) << 11;
3691 }
3692
3693 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
3694 {
3695     int imm = ((inst << 51) >> 63) << 5 |
3696         (inst << 57) >> 59;
3697     if (isa == rv128) {
3698         imm = imm ? imm : 64;
3699     }
3700     return imm;
3701 }
3702
3703 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
3704 {
3705     int imm = ((inst << 51) >> 63) << 5 |
3706         (inst << 57) >> 59;
3707     if (isa == rv128) {
3708         imm = imm | (imm & 32) << 1;
3709         imm = imm ? imm : 64;
3710     }
3711     return imm;
3712 }
3713
3714 static int32_t operand_cimmi(rv_inst inst)
3715 {
3716     return (((int64_t)inst << 51) >> 63) << 5 |
3717         (inst << 57) >> 59;
3718 }
3719
3720 static int32_t operand_cimmui(rv_inst inst)
3721 {
3722     return (((int64_t)inst << 51) >> 63) << 17 |
3723         ((inst << 57) >> 59) << 12;
3724 }
3725
3726 static uint32_t operand_cimmlwsp(rv_inst inst)
3727 {
3728     return ((inst << 51) >> 63) << 5 |
3729         ((inst << 57) >> 61) << 2 |
3730         ((inst << 60) >> 62) << 6;
3731 }
3732
3733 static uint32_t operand_cimmldsp(rv_inst inst)
3734 {
3735     return ((inst << 51) >> 63) << 5 |
3736         ((inst << 57) >> 62) << 3 |
3737         ((inst << 59) >> 61) << 6;
3738 }
3739
3740 static uint32_t operand_cimmlqsp(rv_inst inst)
3741 {
3742     return ((inst << 51) >> 63) << 5 |
3743         ((inst << 57) >> 63) << 4 |
3744         ((inst << 58) >> 60) << 6;
3745 }
3746
3747 static int32_t operand_cimm16sp(rv_inst inst)
3748 {
3749     return (((int64_t)inst << 51) >> 63) << 9 |
3750         ((inst << 57) >> 63) << 4 |
3751         ((inst << 58) >> 63) << 6 |
3752         ((inst << 59) >> 62) << 7 |
3753         ((inst << 61) >> 63) << 5;
3754 }
3755
3756 static int32_t operand_cimmj(rv_inst inst)
3757 {
3758     return (((int64_t)inst << 51) >> 63) << 11 |
3759         ((inst << 52) >> 63) << 4 |
3760         ((inst << 53) >> 62) << 8 |
3761         ((inst << 55) >> 63) << 10 |
3762         ((inst << 56) >> 63) << 6 |
3763         ((inst << 57) >> 63) << 7 |
3764         ((inst << 58) >> 61) << 1 |
3765         ((inst << 61) >> 63) << 5;
3766 }
3767
3768 static int32_t operand_cimmb(rv_inst inst)
3769 {
3770     return (((int64_t)inst << 51) >> 63) << 8 |
3771         ((inst << 52) >> 62) << 3 |
3772         ((inst << 57) >> 62) << 6 |
3773         ((inst << 59) >> 62) << 1 |
3774         ((inst << 61) >> 63) << 5;
3775 }
3776
3777 static uint32_t operand_cimmswsp(rv_inst inst)
3778 {
3779     return ((inst << 51) >> 60) << 2 |
3780         ((inst << 55) >> 62) << 6;
3781 }
3782
3783 static uint32_t operand_cimmsdsp(rv_inst inst)
3784 {
3785     return ((inst << 51) >> 61) << 3 |
3786         ((inst << 54) >> 61) << 6;
3787 }
3788
3789 static uint32_t operand_cimmsqsp(rv_inst inst)
3790 {
3791     return ((inst << 51) >> 62) << 4 |
3792         ((inst << 53) >> 60) << 6;
3793 }
3794
3795 static uint32_t operand_cimm4spn(rv_inst inst)
3796 {
3797     return ((inst << 51) >> 62) << 4 |
3798         ((inst << 53) >> 60) << 6 |
3799         ((inst << 57) >> 63) << 2 |
3800         ((inst << 58) >> 63) << 3;
3801 }
3802
3803 static uint32_t operand_cimmw(rv_inst inst)
3804 {
3805     return ((inst << 51) >> 61) << 3 |
3806         ((inst << 57) >> 63) << 2 |
3807         ((inst << 58) >> 63) << 6;
3808 }
3809
3810 static uint32_t operand_cimmd(rv_inst inst)
3811 {
3812     return ((inst << 51) >> 61) << 3 |
3813         ((inst << 57) >> 62) << 6;
3814 }
3815
3816 static uint32_t operand_cimmq(rv_inst inst)
3817 {
3818     return ((inst << 51) >> 62) << 4 |
3819         ((inst << 53) >> 63) << 8 |
3820         ((inst << 57) >> 62) << 6;
3821 }
3822
3823 static uint32_t operand_vimm(rv_inst inst)
3824 {
3825     return (int64_t)(inst << 44) >> 59;
3826 }
3827
3828 static uint32_t operand_vzimm11(rv_inst inst)
3829 {
3830     return (inst << 33) >> 53;
3831 }
3832
3833 static uint32_t operand_vzimm10(rv_inst inst)
3834 {
3835     return (inst << 34) >> 54;
3836 }
3837
3838 static uint32_t operand_bs(rv_inst inst)
3839 {
3840     return (inst << 32) >> 62;
3841 }
3842
3843 static uint32_t operand_rnum(rv_inst inst)
3844 {
3845     return (inst << 40) >> 60;
3846 }
3847
3848 static uint32_t operand_vm(rv_inst inst)
3849 {
3850     return (inst << 38) >> 63;
3851 }
3852
3853 static uint32_t operand_uimm_c_lb(rv_inst inst)
3854 {
3855     return (((inst << 58) >> 63) << 1) |
3856         ((inst << 57) >> 63);
3857 }
3858
3859 static uint32_t operand_uimm_c_lh(rv_inst inst)
3860 {
3861     return (((inst << 58) >> 63) << 1);
3862 }
3863
3864 static uint32_t operand_zcmp_spimm(rv_inst inst)
3865 {
3866     return ((inst << 60) >> 62) << 4;
3867 }
3868
3869 static uint32_t operand_zcmp_rlist(rv_inst inst)
3870 {
3871     return ((inst << 56) >> 60);
3872 }
3873
3874 static uint32_t operand_imm6(rv_inst inst)
3875 {
3876     return (inst << 38) >> 60;
3877 }
3878
3879 static uint32_t operand_imm2(rv_inst inst)
3880 {
3881     return (inst << 37) >> 62;
3882 }
3883
3884 static uint32_t operand_immh(rv_inst inst)
3885 {
3886     return (inst << 32) >> 58;
3887 }
3888
3889 static uint32_t operand_imml(rv_inst inst)
3890 {
3891     return (inst << 38) >> 58;
3892 }
3893
3894 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
3895 {
3896     int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
3897     int regs = rlist == 15 ? 13 : rlist - 3;
3898     uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
3899     return stack_adj_base + spimm;
3900 }
3901
3902 static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
3903 {
3904     return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
3905                                operand_zcmp_spimm(inst));
3906 }
3907
3908 static uint32_t operand_tbl_index(rv_inst inst)
3909 {
3910     return ((inst << 54) >> 56);
3911 }
3912
3913 /* decode operands */
3914
3915 static void decode_inst_operands(rv_decode *dec, rv_isa isa)
3916 {
3917     const rv_opcode_data *opcode_data = dec->opcode_data;
3918     rv_inst inst = dec->inst;
3919     dec->codec = opcode_data[dec->op].codec;
3920     switch (dec->codec) {
3921     case rv_codec_none:
3922         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
3923         dec->imm = 0;
3924         break;
3925     case rv_codec_u:
3926         dec->rd = operand_rd(inst);
3927         dec->rs1 = dec->rs2 = rv_ireg_zero;
3928         dec->imm = operand_imm20(inst);
3929         break;
3930     case rv_codec_uj:
3931         dec->rd = operand_rd(inst);
3932         dec->rs1 = dec->rs2 = rv_ireg_zero;
3933         dec->imm = operand_jimm20(inst);
3934         break;
3935     case rv_codec_i:
3936         dec->rd = operand_rd(inst);
3937         dec->rs1 = operand_rs1(inst);
3938         dec->rs2 = rv_ireg_zero;
3939         dec->imm = operand_imm12(inst);
3940         break;
3941     case rv_codec_i_sh5:
3942         dec->rd = operand_rd(inst);
3943         dec->rs1 = operand_rs1(inst);
3944         dec->rs2 = rv_ireg_zero;
3945         dec->imm = operand_shamt5(inst);
3946         break;
3947     case rv_codec_i_sh6:
3948         dec->rd = operand_rd(inst);
3949         dec->rs1 = operand_rs1(inst);
3950         dec->rs2 = rv_ireg_zero;
3951         dec->imm = operand_shamt6(inst);
3952         break;
3953     case rv_codec_i_sh7:
3954         dec->rd = operand_rd(inst);
3955         dec->rs1 = operand_rs1(inst);
3956         dec->rs2 = rv_ireg_zero;
3957         dec->imm = operand_shamt7(inst);
3958         break;
3959     case rv_codec_i_csr:
3960         dec->rd = operand_rd(inst);
3961         dec->rs1 = operand_rs1(inst);
3962         dec->rs2 = rv_ireg_zero;
3963         dec->imm = operand_csr12(inst);
3964         break;
3965     case rv_codec_s:
3966         dec->rd = rv_ireg_zero;
3967         dec->rs1 = operand_rs1(inst);
3968         dec->rs2 = operand_rs2(inst);
3969         dec->imm = operand_simm12(inst);
3970         break;
3971     case rv_codec_sb:
3972         dec->rd = rv_ireg_zero;
3973         dec->rs1 = operand_rs1(inst);
3974         dec->rs2 = operand_rs2(inst);
3975         dec->imm = operand_sbimm12(inst);
3976         break;
3977     case rv_codec_r:
3978         dec->rd = operand_rd(inst);
3979         dec->rs1 = operand_rs1(inst);
3980         dec->rs2 = operand_rs2(inst);
3981         dec->imm = 0;
3982         break;
3983     case rv_codec_r_m:
3984         dec->rd = operand_rd(inst);
3985         dec->rs1 = operand_rs1(inst);
3986         dec->rs2 = operand_rs2(inst);
3987         dec->imm = 0;
3988         dec->rm = operand_rm(inst);
3989         break;
3990     case rv_codec_r4_m:
3991         dec->rd = operand_rd(inst);
3992         dec->rs1 = operand_rs1(inst);
3993         dec->rs2 = operand_rs2(inst);
3994         dec->rs3 = operand_rs3(inst);
3995         dec->imm = 0;
3996         dec->rm = operand_rm(inst);
3997         break;
3998     case rv_codec_r_a:
3999         dec->rd = operand_rd(inst);
4000         dec->rs1 = operand_rs1(inst);
4001         dec->rs2 = operand_rs2(inst);
4002         dec->imm = 0;
4003         dec->aq = operand_aq(inst);
4004         dec->rl = operand_rl(inst);
4005         break;
4006     case rv_codec_r_l:
4007         dec->rd = operand_rd(inst);
4008         dec->rs1 = operand_rs1(inst);
4009         dec->rs2 = rv_ireg_zero;
4010         dec->imm = 0;
4011         dec->aq = operand_aq(inst);
4012         dec->rl = operand_rl(inst);
4013         break;
4014     case rv_codec_r_f:
4015         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4016         dec->pred = operand_pred(inst);
4017         dec->succ = operand_succ(inst);
4018         dec->imm = 0;
4019         break;
4020     case rv_codec_cb:
4021         dec->rd = rv_ireg_zero;
4022         dec->rs1 = operand_crs1q(inst) + 8;
4023         dec->rs2 = rv_ireg_zero;
4024         dec->imm = operand_cimmb(inst);
4025         break;
4026     case rv_codec_cb_imm:
4027         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4028         dec->rs2 = rv_ireg_zero;
4029         dec->imm = operand_cimmi(inst);
4030         break;
4031     case rv_codec_cb_sh5:
4032         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4033         dec->rs2 = rv_ireg_zero;
4034         dec->imm = operand_cimmsh5(inst);
4035         break;
4036     case rv_codec_cb_sh6:
4037         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4038         dec->rs2 = rv_ireg_zero;
4039         dec->imm = operand_cimmshr6(inst, isa);
4040         break;
4041     case rv_codec_ci:
4042         dec->rd = dec->rs1 = operand_crs1rd(inst);
4043         dec->rs2 = rv_ireg_zero;
4044         dec->imm = operand_cimmi(inst);
4045         break;
4046     case rv_codec_ci_sh5:
4047         dec->rd = dec->rs1 = operand_crs1rd(inst);
4048         dec->rs2 = rv_ireg_zero;
4049         dec->imm = operand_cimmsh5(inst);
4050         break;
4051     case rv_codec_ci_sh6:
4052         dec->rd = dec->rs1 = operand_crs1rd(inst);
4053         dec->rs2 = rv_ireg_zero;
4054         dec->imm = operand_cimmshl6(inst, isa);
4055         break;
4056     case rv_codec_ci_16sp:
4057         dec->rd = rv_ireg_sp;
4058         dec->rs1 = rv_ireg_sp;
4059         dec->rs2 = rv_ireg_zero;
4060         dec->imm = operand_cimm16sp(inst);
4061         break;
4062     case rv_codec_ci_lwsp:
4063         dec->rd = operand_crd(inst);
4064         dec->rs1 = rv_ireg_sp;
4065         dec->rs2 = rv_ireg_zero;
4066         dec->imm = operand_cimmlwsp(inst);
4067         break;
4068     case rv_codec_ci_ldsp:
4069         dec->rd = operand_crd(inst);
4070         dec->rs1 = rv_ireg_sp;
4071         dec->rs2 = rv_ireg_zero;
4072         dec->imm = operand_cimmldsp(inst);
4073         break;
4074     case rv_codec_ci_lqsp:
4075         dec->rd = operand_crd(inst);
4076         dec->rs1 = rv_ireg_sp;
4077         dec->rs2 = rv_ireg_zero;
4078         dec->imm = operand_cimmlqsp(inst);
4079         break;
4080     case rv_codec_ci_li:
4081         dec->rd = operand_crd(inst);
4082         dec->rs1 = rv_ireg_zero;
4083         dec->rs2 = rv_ireg_zero;
4084         dec->imm = operand_cimmi(inst);
4085         break;
4086     case rv_codec_ci_lui:
4087         dec->rd = operand_crd(inst);
4088         dec->rs1 = rv_ireg_zero;
4089         dec->rs2 = rv_ireg_zero;
4090         dec->imm = operand_cimmui(inst);
4091         break;
4092     case rv_codec_ci_none:
4093         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4094         dec->imm = 0;
4095         break;
4096     case rv_codec_ciw_4spn:
4097         dec->rd = operand_crdq(inst) + 8;
4098         dec->rs1 = rv_ireg_sp;
4099         dec->rs2 = rv_ireg_zero;
4100         dec->imm = operand_cimm4spn(inst);
4101         break;
4102     case rv_codec_cj:
4103         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4104         dec->imm = operand_cimmj(inst);
4105         break;
4106     case rv_codec_cj_jal:
4107         dec->rd = rv_ireg_ra;
4108         dec->rs1 = dec->rs2 = rv_ireg_zero;
4109         dec->imm = operand_cimmj(inst);
4110         break;
4111     case rv_codec_cl_lw:
4112         dec->rd = operand_crdq(inst) + 8;
4113         dec->rs1 = operand_crs1q(inst) + 8;
4114         dec->rs2 = rv_ireg_zero;
4115         dec->imm = operand_cimmw(inst);
4116         break;
4117     case rv_codec_cl_ld:
4118         dec->rd = operand_crdq(inst) + 8;
4119         dec->rs1 = operand_crs1q(inst) + 8;
4120         dec->rs2 = rv_ireg_zero;
4121         dec->imm = operand_cimmd(inst);
4122         break;
4123     case rv_codec_cl_lq:
4124         dec->rd = operand_crdq(inst) + 8;
4125         dec->rs1 = operand_crs1q(inst) + 8;
4126         dec->rs2 = rv_ireg_zero;
4127         dec->imm = operand_cimmq(inst);
4128         break;
4129     case rv_codec_cr:
4130         dec->rd = dec->rs1 = operand_crs1rd(inst);
4131         dec->rs2 = operand_crs2(inst);
4132         dec->imm = 0;
4133         break;
4134     case rv_codec_cr_mv:
4135         dec->rd = operand_crd(inst);
4136         dec->rs1 = operand_crs2(inst);
4137         dec->rs2 = rv_ireg_zero;
4138         dec->imm = 0;
4139         break;
4140     case rv_codec_cr_jalr:
4141         dec->rd = rv_ireg_ra;
4142         dec->rs1 = operand_crs1(inst);
4143         dec->rs2 = rv_ireg_zero;
4144         dec->imm = 0;
4145         break;
4146     case rv_codec_cr_jr:
4147         dec->rd = rv_ireg_zero;
4148         dec->rs1 = operand_crs1(inst);
4149         dec->rs2 = rv_ireg_zero;
4150         dec->imm = 0;
4151         break;
4152     case rv_codec_cs:
4153         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4154         dec->rs2 = operand_crs2q(inst) + 8;
4155         dec->imm = 0;
4156         break;
4157     case rv_codec_cs_sw:
4158         dec->rd = rv_ireg_zero;
4159         dec->rs1 = operand_crs1q(inst) + 8;
4160         dec->rs2 = operand_crs2q(inst) + 8;
4161         dec->imm = operand_cimmw(inst);
4162         break;
4163     case rv_codec_cs_sd:
4164         dec->rd = rv_ireg_zero;
4165         dec->rs1 = operand_crs1q(inst) + 8;
4166         dec->rs2 = operand_crs2q(inst) + 8;
4167         dec->imm = operand_cimmd(inst);
4168         break;
4169     case rv_codec_cs_sq:
4170         dec->rd = rv_ireg_zero;
4171         dec->rs1 = operand_crs1q(inst) + 8;
4172         dec->rs2 = operand_crs2q(inst) + 8;
4173         dec->imm = operand_cimmq(inst);
4174         break;
4175     case rv_codec_css_swsp:
4176         dec->rd = rv_ireg_zero;
4177         dec->rs1 = rv_ireg_sp;
4178         dec->rs2 = operand_crs2(inst);
4179         dec->imm = operand_cimmswsp(inst);
4180         break;
4181     case rv_codec_css_sdsp:
4182         dec->rd = rv_ireg_zero;
4183         dec->rs1 = rv_ireg_sp;
4184         dec->rs2 = operand_crs2(inst);
4185         dec->imm = operand_cimmsdsp(inst);
4186         break;
4187     case rv_codec_css_sqsp:
4188         dec->rd = rv_ireg_zero;
4189         dec->rs1 = rv_ireg_sp;
4190         dec->rs2 = operand_crs2(inst);
4191         dec->imm = operand_cimmsqsp(inst);
4192         break;
4193     case rv_codec_k_bs:
4194         dec->rs1 = operand_rs1(inst);
4195         dec->rs2 = operand_rs2(inst);
4196         dec->bs = operand_bs(inst);
4197         break;
4198     case rv_codec_k_rnum:
4199         dec->rd = operand_rd(inst);
4200         dec->rs1 = operand_rs1(inst);
4201         dec->rnum = operand_rnum(inst);
4202         break;
4203     case rv_codec_v_r:
4204         dec->rd = operand_rd(inst);
4205         dec->rs1 = operand_rs1(inst);
4206         dec->rs2 = operand_rs2(inst);
4207         dec->vm = operand_vm(inst);
4208         break;
4209     case rv_codec_v_ldst:
4210         dec->rd = operand_rd(inst);
4211         dec->rs1 = operand_rs1(inst);
4212         dec->vm = operand_vm(inst);
4213         break;
4214     case rv_codec_v_i:
4215         dec->rd = operand_rd(inst);
4216         dec->rs2 = operand_rs2(inst);
4217         dec->imm = operand_vimm(inst);
4218         dec->vm = operand_vm(inst);
4219         break;
4220     case rv_codec_vsetvli:
4221         dec->rd = operand_rd(inst);
4222         dec->rs1 = operand_rs1(inst);
4223         dec->vzimm = operand_vzimm11(inst);
4224         break;
4225     case rv_codec_vsetivli:
4226         dec->rd = operand_rd(inst);
4227         dec->imm = operand_vimm(inst);
4228         dec->vzimm = operand_vzimm10(inst);
4229         break;
4230     case rv_codec_zcb_lb:
4231         dec->rs1 = operand_crs1q(inst) + 8;
4232         dec->rs2 = operand_crs2q(inst) + 8;
4233         dec->imm = operand_uimm_c_lb(inst);
4234         break;
4235     case rv_codec_zcb_lh:
4236         dec->rs1 = operand_crs1q(inst) + 8;
4237         dec->rs2 = operand_crs2q(inst) + 8;
4238         dec->imm = operand_uimm_c_lh(inst);
4239         break;
4240     case rv_codec_zcb_ext:
4241         dec->rd = operand_crs1q(inst) + 8;
4242         break;
4243     case rv_codec_zcb_mul:
4244         dec->rd = operand_crs1rdq(inst) + 8;
4245         dec->rs2 = operand_crs2q(inst) + 8;
4246         break;
4247     case rv_codec_zcmp_cm_pushpop:
4248         dec->imm = operand_zcmp_stack_adj(inst, isa);
4249         dec->rlist = operand_zcmp_rlist(inst);
4250         break;
4251     case rv_codec_zcmp_cm_mv:
4252         dec->rd = operand_sreg1(inst);
4253         dec->rs2 = operand_sreg2(inst);
4254         break;
4255     case rv_codec_zcmt_jt:
4256         dec->imm = operand_tbl_index(inst);
4257         break;
4258     case rv_codec_r2_imm5:
4259         dec->rd = operand_rd(inst);
4260         dec->rs1 = operand_rs1(inst);
4261         dec->imm = operand_rs2(inst);
4262         break;
4263     case rv_codec_r2:
4264         dec->rd = operand_rd(inst);
4265         dec->rs1 = operand_rs1(inst);
4266         break;
4267     case rv_codec_r2_imm6:
4268         dec->rd = operand_rd(inst);
4269         dec->rs1 = operand_rs1(inst);
4270         dec->imm = operand_imm6(inst);
4271         break;
4272     case rv_codec_r_imm2:
4273         dec->rd = operand_rd(inst);
4274         dec->rs1 = operand_rs1(inst);
4275         dec->rs2 = operand_rs2(inst);
4276         dec->imm = operand_imm2(inst);
4277         break;
4278     case rv_codec_r2_immhl:
4279         dec->rd = operand_rd(inst);
4280         dec->rs1 = operand_rs1(inst);
4281         dec->imm = operand_immh(inst);
4282         dec->imm1 = operand_imml(inst);
4283         break;
4284     case rv_codec_r2_imm2_imm5:
4285         dec->rd = operand_rd(inst);
4286         dec->rs1 = operand_rs1(inst);
4287         dec->imm = sextract32(operand_rs2(inst), 0, 5);
4288         dec->imm1 = operand_imm2(inst);
4289         break;
4290     };
4291 }
4292
4293 /* check constraint */
4294
4295 static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
4296 {
4297     int32_t imm = dec->imm;
4298     uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2;
4299     while (*c != rvc_end) {
4300         switch (*c) {
4301         case rvc_rd_eq_ra:
4302             if (!(rd == 1)) {
4303                 return false;
4304             }
4305             break;
4306         case rvc_rd_eq_x0:
4307             if (!(rd == 0)) {
4308                 return false;
4309             }
4310             break;
4311         case rvc_rs1_eq_x0:
4312             if (!(rs1 == 0)) {
4313                 return false;
4314             }
4315             break;
4316         case rvc_rs2_eq_x0:
4317             if (!(rs2 == 0)) {
4318                 return false;
4319             }
4320             break;
4321         case rvc_rs2_eq_rs1:
4322             if (!(rs2 == rs1)) {
4323                 return false;
4324             }
4325             break;
4326         case rvc_rs1_eq_ra:
4327             if (!(rs1 == 1)) {
4328                 return false;
4329             }
4330             break;
4331         case rvc_imm_eq_zero:
4332             if (!(imm == 0)) {
4333                 return false;
4334             }
4335             break;
4336         case rvc_imm_eq_n1:
4337             if (!(imm == -1)) {
4338                 return false;
4339             }
4340             break;
4341         case rvc_imm_eq_p1:
4342             if (!(imm == 1)) {
4343                 return false;
4344             }
4345             break;
4346         case rvc_csr_eq_0x001:
4347             if (!(imm == 0x001)) {
4348                 return false;
4349             }
4350             break;
4351         case rvc_csr_eq_0x002:
4352             if (!(imm == 0x002)) {
4353                 return false;
4354             }
4355             break;
4356         case rvc_csr_eq_0x003:
4357             if (!(imm == 0x003)) {
4358                 return false;
4359             }
4360             break;
4361         case rvc_csr_eq_0xc00:
4362             if (!(imm == 0xc00)) {
4363                 return false;
4364             }
4365             break;
4366         case rvc_csr_eq_0xc01:
4367             if (!(imm == 0xc01)) {
4368                 return false;
4369             }
4370             break;
4371         case rvc_csr_eq_0xc02:
4372             if (!(imm == 0xc02)) {
4373                 return false;
4374             }
4375             break;
4376         case rvc_csr_eq_0xc80:
4377             if (!(imm == 0xc80)) {
4378                 return false;
4379             }
4380             break;
4381         case rvc_csr_eq_0xc81:
4382             if (!(imm == 0xc81)) {
4383                 return false;
4384             }
4385             break;
4386         case rvc_csr_eq_0xc82:
4387             if (!(imm == 0xc82)) {
4388                 return false;
4389             }
4390             break;
4391         default: break;
4392         }
4393         c++;
4394     }
4395     return true;
4396 }
4397
4398 /* instruction length */
4399
4400 static size_t inst_length(rv_inst inst)
4401 {
4402     /* NOTE: supports maximum instruction size of 64-bits */
4403
4404     /*
4405      * instruction length coding
4406      *
4407      *      aa - 16 bit aa != 11
4408      *   bbb11 - 32 bit bbb != 111
4409      *  011111 - 48 bit
4410      * 0111111 - 64 bit
4411      */
4412
4413     return (inst &      0b11) != 0b11      ? 2
4414          : (inst &   0b11100) != 0b11100   ? 4
4415          : (inst &  0b111111) == 0b011111  ? 6
4416          : (inst & 0b1111111) == 0b0111111 ? 8
4417          : 0;
4418 }
4419
4420 /* format instruction */
4421
4422 static void append(char *s1, const char *s2, size_t n)
4423 {
4424     size_t l1 = strlen(s1);
4425     if (n - l1 - 1 > 0) {
4426         strncat(s1, s2, n - l1);
4427     }
4428 }
4429
4430 static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
4431 {
4432     const rv_opcode_data *opcode_data = dec->opcode_data;
4433     char tmp[64];
4434     const char *fmt;
4435
4436     fmt = opcode_data[dec->op].format;
4437     while (*fmt) {
4438         switch (*fmt) {
4439         case 'O':
4440             append(buf, opcode_data[dec->op].name, buflen);
4441             break;
4442         case '(':
4443             append(buf, "(", buflen);
4444             break;
4445         case ',':
4446             append(buf, ",", buflen);
4447             break;
4448         case ')':
4449             append(buf, ")", buflen);
4450             break;
4451         case '-':
4452             append(buf, "-", buflen);
4453             break;
4454         case 'b':
4455             snprintf(tmp, sizeof(tmp), "%d", dec->bs);
4456             append(buf, tmp, buflen);
4457             break;
4458         case 'n':
4459             snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
4460             append(buf, tmp, buflen);
4461             break;
4462         case '0':
4463             append(buf, rv_ireg_name_sym[dec->rd], buflen);
4464             break;
4465         case '1':
4466             append(buf, rv_ireg_name_sym[dec->rs1], buflen);
4467             break;
4468         case '2':
4469             append(buf, rv_ireg_name_sym[dec->rs2], buflen);
4470             break;
4471         case '3':
4472             append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rd] :
4473                                               rv_freg_name_sym[dec->rd],
4474                    buflen);
4475             break;
4476         case '4':
4477             append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs1] :
4478                                               rv_freg_name_sym[dec->rs1],
4479                    buflen);
4480             break;
4481         case '5':
4482             append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs2] :
4483                                               rv_freg_name_sym[dec->rs2],
4484                    buflen);
4485             break;
4486         case '6':
4487             append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs3] :
4488                                               rv_freg_name_sym[dec->rs3],
4489                    buflen);
4490             break;
4491         case '7':
4492             snprintf(tmp, sizeof(tmp), "%d", dec->rs1);
4493             append(buf, tmp, buflen);
4494             break;
4495         case 'i':
4496             snprintf(tmp, sizeof(tmp), "%d", dec->imm);
4497             append(buf, tmp, buflen);
4498             break;
4499         case 'u':
4500             snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111));
4501             append(buf, tmp, buflen);
4502             break;
4503         case 'j':
4504             snprintf(tmp, sizeof(tmp), "%d", dec->imm1);
4505             append(buf, tmp, buflen);
4506             break;
4507         case 'o':
4508             snprintf(tmp, sizeof(tmp), "%d", dec->imm);
4509             append(buf, tmp, buflen);
4510             while (strlen(buf) < tab * 2) {
4511                 append(buf, " ", buflen);
4512             }
4513             snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64,
4514                 dec->pc + dec->imm);
4515             append(buf, tmp, buflen);
4516             break;
4517         case 'c': {
4518             const char *name = csr_name(dec->imm & 0xfff);
4519             if (name) {
4520                 append(buf, name, buflen);
4521             } else {
4522                 snprintf(tmp, sizeof(tmp), "0x%03x", dec->imm & 0xfff);
4523                 append(buf, tmp, buflen);
4524             }
4525             break;
4526         }
4527         case 'r':
4528             switch (dec->rm) {
4529             case rv_rm_rne:
4530                 append(buf, "rne", buflen);
4531                 break;
4532             case rv_rm_rtz:
4533                 append(buf, "rtz", buflen);
4534                 break;
4535             case rv_rm_rdn:
4536                 append(buf, "rdn", buflen);
4537                 break;
4538             case rv_rm_rup:
4539                 append(buf, "rup", buflen);
4540                 break;
4541             case rv_rm_rmm:
4542                 append(buf, "rmm", buflen);
4543                 break;
4544             case rv_rm_dyn:
4545                 append(buf, "dyn", buflen);
4546                 break;
4547             default:
4548                 append(buf, "inv", buflen);
4549                 break;
4550             }
4551             break;
4552         case 'p':
4553             if (dec->pred & rv_fence_i) {
4554                 append(buf, "i", buflen);
4555             }
4556             if (dec->pred & rv_fence_o) {
4557                 append(buf, "o", buflen);
4558             }
4559             if (dec->pred & rv_fence_r) {
4560                 append(buf, "r", buflen);
4561             }
4562             if (dec->pred & rv_fence_w) {
4563                 append(buf, "w", buflen);
4564             }
4565             break;
4566         case 's':
4567             if (dec->succ & rv_fence_i) {
4568                 append(buf, "i", buflen);
4569             }
4570             if (dec->succ & rv_fence_o) {
4571                 append(buf, "o", buflen);
4572             }
4573             if (dec->succ & rv_fence_r) {
4574                 append(buf, "r", buflen);
4575             }
4576             if (dec->succ & rv_fence_w) {
4577                 append(buf, "w", buflen);
4578             }
4579             break;
4580         case '\t':
4581             while (strlen(buf) < tab) {
4582                 append(buf, " ", buflen);
4583             }
4584             break;
4585         case 'A':
4586             if (dec->aq) {
4587                 append(buf, ".aq", buflen);
4588             }
4589             break;
4590         case 'R':
4591             if (dec->rl) {
4592                 append(buf, ".rl", buflen);
4593             }
4594             break;
4595         case 'l':
4596             append(buf, ",v0", buflen);
4597             break;
4598         case 'm':
4599             if (dec->vm == 0) {
4600                 append(buf, ",v0.t", buflen);
4601             }
4602             break;
4603         case 'D':
4604             append(buf, rv_vreg_name_sym[dec->rd], buflen);
4605             break;
4606         case 'E':
4607             append(buf, rv_vreg_name_sym[dec->rs1], buflen);
4608             break;
4609         case 'F':
4610             append(buf, rv_vreg_name_sym[dec->rs2], buflen);
4611             break;
4612         case 'G':
4613             append(buf, rv_vreg_name_sym[dec->rs3], buflen);
4614             break;
4615         case 'v': {
4616             char nbuf[32] = {0};
4617             const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3);
4618             sprintf(nbuf, "%d", sew);
4619             const int lmul = dec->vzimm & 0b11;
4620             const int flmul = (dec->vzimm >> 2) & 1;
4621             const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu";
4622             const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu";
4623             append(buf, "e", buflen);
4624             append(buf, nbuf, buflen);
4625             append(buf, ",m", buflen);
4626             if (flmul) {
4627                 switch (lmul) {
4628                 case 3:
4629                     sprintf(nbuf, "f2");
4630                     break;
4631                 case 2:
4632                     sprintf(nbuf, "f4");
4633                     break;
4634                 case 1:
4635                     sprintf(nbuf, "f8");
4636                 break;
4637                 }
4638                 append(buf, nbuf, buflen);
4639             } else {
4640                 sprintf(nbuf, "%d", 1 << lmul);
4641                 append(buf, nbuf, buflen);
4642             }
4643             append(buf, ",", buflen);
4644             append(buf, vta, buflen);
4645             append(buf, ",", buflen);
4646             append(buf, vma, buflen);
4647             break;
4648         }
4649         case 'x': {
4650             switch (dec->rlist) {
4651             case 4:
4652                 snprintf(tmp, sizeof(tmp), "{ra}");
4653                 break;
4654             case 5:
4655                 snprintf(tmp, sizeof(tmp), "{ra, s0}");
4656                 break;
4657             case 15:
4658                 snprintf(tmp, sizeof(tmp), "{ra, s0-s11}");
4659                 break;
4660             default:
4661                 snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5);
4662                 break;
4663             }
4664             append(buf, tmp, buflen);
4665             break;
4666         }
4667         default:
4668             break;
4669         }
4670         fmt++;
4671     }
4672 }
4673
4674 /* lift instruction to pseudo-instruction */
4675
4676 static void decode_inst_lift_pseudo(rv_decode *dec)
4677 {
4678     const rv_opcode_data *opcode_data = dec->opcode_data;
4679     const rv_comp_data *comp_data = opcode_data[dec->op].pseudo;
4680     if (!comp_data) {
4681         return;
4682     }
4683     while (comp_data->constraints) {
4684         if (check_constraints(dec, comp_data->constraints)) {
4685             dec->op = comp_data->op;
4686             dec->codec = opcode_data[dec->op].codec;
4687             return;
4688         }
4689         comp_data++;
4690     }
4691 }
4692
4693 /* decompress instruction */
4694
4695 static void decode_inst_decompress_rv32(rv_decode *dec)
4696 {
4697     const rv_opcode_data *opcode_data = dec->opcode_data;
4698     int decomp_op = opcode_data[dec->op].decomp_rv32;
4699     if (decomp_op != rv_op_illegal) {
4700         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4701             && dec->imm == 0) {
4702             dec->op = rv_op_illegal;
4703         } else {
4704             dec->op = decomp_op;
4705             dec->codec = opcode_data[decomp_op].codec;
4706         }
4707     }
4708 }
4709
4710 static void decode_inst_decompress_rv64(rv_decode *dec)
4711 {
4712     const rv_opcode_data *opcode_data = dec->opcode_data;
4713     int decomp_op = opcode_data[dec->op].decomp_rv64;
4714     if (decomp_op != rv_op_illegal) {
4715         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4716             && dec->imm == 0) {
4717             dec->op = rv_op_illegal;
4718         } else {
4719             dec->op = decomp_op;
4720             dec->codec = opcode_data[decomp_op].codec;
4721         }
4722     }
4723 }
4724
4725 static void decode_inst_decompress_rv128(rv_decode *dec)
4726 {
4727     const rv_opcode_data *opcode_data = dec->opcode_data;
4728     int decomp_op = opcode_data[dec->op].decomp_rv128;
4729     if (decomp_op != rv_op_illegal) {
4730         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4731             && dec->imm == 0) {
4732             dec->op = rv_op_illegal;
4733         } else {
4734             dec->op = decomp_op;
4735             dec->codec = opcode_data[decomp_op].codec;
4736         }
4737     }
4738 }
4739
4740 static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
4741 {
4742     switch (isa) {
4743     case rv32:
4744         decode_inst_decompress_rv32(dec);
4745         break;
4746     case rv64:
4747         decode_inst_decompress_rv64(dec);
4748         break;
4749     case rv128:
4750         decode_inst_decompress_rv128(dec);
4751         break;
4752     }
4753 }
4754
4755 /* disassemble instruction */
4756
4757 static void
4758 disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst,
4759             RISCVCPUConfig *cfg)
4760 {
4761     rv_decode dec = { 0 };
4762     dec.pc = pc;
4763     dec.inst = inst;
4764     dec.cfg = cfg;
4765
4766     static const struct {
4767         bool (*guard_func)(const RISCVCPUConfig *);
4768         const rv_opcode_data *opcode_data;
4769         void (*decode_func)(rv_decode *, rv_isa);
4770     } decoders[] = {
4771         { always_true_p, rvi_opcode_data, decode_inst_opcode },
4772         { has_xtheadba_p, xthead_opcode_data, decode_xtheadba },
4773         { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb },
4774         { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs },
4775         { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo },
4776         { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov },
4777         { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx },
4778         { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv },
4779         { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac },
4780         { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx },
4781         { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
4782         { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
4783         { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
4784     };
4785
4786     for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
4787         bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func;
4788         const rv_opcode_data *opcode_data = decoders[i].opcode_data;
4789         void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func;
4790
4791         if (guard_func(cfg)) {
4792             dec.opcode_data = opcode_data;
4793             decode_func(&dec, isa);
4794             if (dec.op != rv_op_illegal)
4795                 break;
4796         }
4797     }
4798
4799     if (dec.op == rv_op_illegal) {
4800         dec.opcode_data = rvi_opcode_data;
4801     }
4802
4803     decode_inst_operands(&dec, isa);
4804     decode_inst_decompress(&dec, isa);
4805     decode_inst_lift_pseudo(&dec);
4806     format_inst(buf, buflen, 24, &dec);
4807 }
4808
4809 #define INST_FMT_2 "%04" PRIx64 "              "
4810 #define INST_FMT_4 "%08" PRIx64 "          "
4811 #define INST_FMT_6 "%012" PRIx64 "      "
4812 #define INST_FMT_8 "%016" PRIx64 "  "
4813
4814 static int
4815 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
4816 {
4817     char buf[128] = { 0 };
4818     bfd_byte packet[2];
4819     rv_inst inst = 0;
4820     size_t len = 2;
4821     bfd_vma n;
4822     int status;
4823
4824     /* Instructions are made of 2-byte packets in little-endian order */
4825     for (n = 0; n < len; n += 2) {
4826         status = (*info->read_memory_func)(memaddr + n, packet, 2, info);
4827         if (status != 0) {
4828             /* Don't fail just because we fell off the end.  */
4829             if (n > 0) {
4830                 break;
4831             }
4832             (*info->memory_error_func)(status, memaddr, info);
4833             return status;
4834         }
4835         inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n);
4836         if (n == 0) {
4837             len = inst_length(inst);
4838         }
4839     }
4840
4841     switch (len) {
4842     case 2:
4843         (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
4844         break;
4845     case 4:
4846         (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
4847         break;
4848     case 6:
4849         (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
4850         break;
4851     default:
4852         (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
4853         break;
4854     }
4855
4856     disasm_inst(buf, sizeof(buf), isa, memaddr, inst,
4857                 (RISCVCPUConfig *)info->target_info);
4858     (*info->fprintf_func)(info->stream, "%s", buf);
4859
4860     return len;
4861 }
4862
4863 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info)
4864 {
4865     return print_insn_riscv(memaddr, info, rv32);
4866 }
4867
4868 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info)
4869 {
4870     return print_insn_riscv(memaddr, info, rv64);
4871 }
4872
4873 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info)
4874 {
4875     return print_insn_riscv(memaddr, info, rv128);
4876 }