disas/riscv.c

   1 /*
   2  * QEMU RISC-V Disassembler
   3  *
   4  * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com>
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "disas/dis-asm.h"
  22 #include "target/riscv/cpu_cfg.h"
  23
  24 /* types */
  25
  26 typedef uint64_t rv_inst;
  27 typedef uint16_t rv_opcode;
  28
  29 /* enums */
  30
  31 typedef enum {
  32     rv32,
  33     rv64,
  34     rv128
  35 } rv_isa;
  36
  37 typedef enum {
  38     rv_rm_rne = 0,
  39     rv_rm_rtz = 1,
  40     rv_rm_rdn = 2,
  41     rv_rm_rup = 3,
  42     rv_rm_rmm = 4,
  43     rv_rm_dyn = 7,
  44 } rv_rm;
  45
  46 typedef enum {
  47     rv_fence_i = 8,
  48     rv_fence_o = 4,
  49     rv_fence_r = 2,
  50     rv_fence_w = 1,
  51 } rv_fence;
  52
  53 typedef enum {
  54     rv_ireg_zero,
  55     rv_ireg_ra,
  56     rv_ireg_sp,
  57     rv_ireg_gp,
  58     rv_ireg_tp,
  59     rv_ireg_t0,
  60     rv_ireg_t1,
  61     rv_ireg_t2,
  62     rv_ireg_s0,
  63     rv_ireg_s1,
  64     rv_ireg_a0,
  65     rv_ireg_a1,
  66     rv_ireg_a2,
  67     rv_ireg_a3,
  68     rv_ireg_a4,
  69     rv_ireg_a5,
  70     rv_ireg_a6,
  71     rv_ireg_a7,
  72     rv_ireg_s2,
  73     rv_ireg_s3,
  74     rv_ireg_s4,
  75     rv_ireg_s5,
  76     rv_ireg_s6,
  77     rv_ireg_s7,
  78     rv_ireg_s8,
  79     rv_ireg_s9,
  80     rv_ireg_s10,
  81     rv_ireg_s11,
  82     rv_ireg_t3,
  83     rv_ireg_t4,
  84     rv_ireg_t5,
  85     rv_ireg_t6,
  86 } rv_ireg;
  87
  88 typedef enum {
  89     rvc_end,
  90     rvc_rd_eq_ra,
  91     rvc_rd_eq_x0,
  92     rvc_rs1_eq_x0,
  93     rvc_rs2_eq_x0,
  94     rvc_rs2_eq_rs1,
  95     rvc_rs1_eq_ra,
  96     rvc_imm_eq_zero,
  97     rvc_imm_eq_n1,
  98     rvc_imm_eq_p1,
  99     rvc_csr_eq_0x001,
 100     rvc_csr_eq_0x002,
 101     rvc_csr_eq_0x003,
 102     rvc_csr_eq_0xc00,
 103     rvc_csr_eq_0xc01,
 104     rvc_csr_eq_0xc02,
 105     rvc_csr_eq_0xc80,
 106     rvc_csr_eq_0xc81,
 107     rvc_csr_eq_0xc82,
 108 } rvc_constraint;
 109
 110 typedef enum {
 111     rv_codec_illegal,
 112     rv_codec_none,
 113     rv_codec_u,
 114     rv_codec_uj,
 115     rv_codec_i,
 116     rv_codec_i_sh5,
 117     rv_codec_i_sh6,
 118     rv_codec_i_sh7,
 119     rv_codec_i_csr,
 120     rv_codec_s,
 121     rv_codec_sb,
 122     rv_codec_r,
 123     rv_codec_r_m,
 124     rv_codec_r4_m,
 125     rv_codec_r_a,
 126     rv_codec_r_l,
 127     rv_codec_r_f,
 128     rv_codec_cb,
 129     rv_codec_cb_imm,
 130     rv_codec_cb_sh5,
 131     rv_codec_cb_sh6,
 132     rv_codec_ci,
 133     rv_codec_ci_sh5,
 134     rv_codec_ci_sh6,
 135     rv_codec_ci_16sp,
 136     rv_codec_ci_lwsp,
 137     rv_codec_ci_ldsp,
 138     rv_codec_ci_lqsp,
 139     rv_codec_ci_li,
 140     rv_codec_ci_lui,
 141     rv_codec_ci_none,
 142     rv_codec_ciw_4spn,
 143     rv_codec_cj,
 144     rv_codec_cj_jal,
 145     rv_codec_cl_lw,
 146     rv_codec_cl_ld,
 147     rv_codec_cl_lq,
 148     rv_codec_cr,
 149     rv_codec_cr_mv,
 150     rv_codec_cr_jalr,
 151     rv_codec_cr_jr,
 152     rv_codec_cs,
 153     rv_codec_cs_sw,
 154     rv_codec_cs_sd,
 155     rv_codec_cs_sq,
 156     rv_codec_css_swsp,
 157     rv_codec_css_sdsp,
 158     rv_codec_css_sqsp,
 159     rv_codec_k_bs,
 160     rv_codec_k_rnum,
 161     rv_codec_v_r,
 162     rv_codec_v_ldst,
 163     rv_codec_v_i,
 164     rv_codec_vsetvli,
 165     rv_codec_vsetivli,
 166     rv_codec_zcb_ext,
 167     rv_codec_zcb_mul,
 168     rv_codec_zcb_lb,
 169     rv_codec_zcb_lh,
 170     rv_codec_zcmp_cm_pushpop,
 171     rv_codec_zcmp_cm_mv,
 172     rv_codec_zcmt_jt,
 173 } rv_codec;
 174
 175 typedef enum {
 176     rv_op_illegal = 0,
 177     rv_op_lui = 1,
 178     rv_op_auipc = 2,
 179     rv_op_jal = 3,
 180     rv_op_jalr = 4,
 181     rv_op_beq = 5,
 182     rv_op_bne = 6,
 183     rv_op_blt = 7,
 184     rv_op_bge = 8,
 185     rv_op_bltu = 9,
 186     rv_op_bgeu = 10,
 187     rv_op_lb = 11,
 188     rv_op_lh = 12,
 189     rv_op_lw = 13,
 190     rv_op_lbu = 14,
 191     rv_op_lhu = 15,
 192     rv_op_sb = 16,
 193     rv_op_sh = 17,
 194     rv_op_sw = 18,
 195     rv_op_addi = 19,
 196     rv_op_slti = 20,
 197     rv_op_sltiu = 21,
 198     rv_op_xori = 22,
 199     rv_op_ori = 23,
 200     rv_op_andi = 24,
 201     rv_op_slli = 25,
 202     rv_op_srli = 26,
 203     rv_op_srai = 27,
 204     rv_op_add = 28,
 205     rv_op_sub = 29,
 206     rv_op_sll = 30,
 207     rv_op_slt = 31,
 208     rv_op_sltu = 32,
 209     rv_op_xor = 33,
 210     rv_op_srl = 34,
 211     rv_op_sra = 35,
 212     rv_op_or = 36,
 213     rv_op_and = 37,
 214     rv_op_fence = 38,
 215     rv_op_fence_i = 39,
 216     rv_op_lwu = 40,
 217     rv_op_ld = 41,
 218     rv_op_sd = 42,
 219     rv_op_addiw = 43,
 220     rv_op_slliw = 44,
 221     rv_op_srliw = 45,
 222     rv_op_sraiw = 46,
 223     rv_op_addw = 47,
 224     rv_op_subw = 48,
 225     rv_op_sllw = 49,
 226     rv_op_srlw = 50,
 227     rv_op_sraw = 51,
 228     rv_op_ldu = 52,
 229     rv_op_lq = 53,
 230     rv_op_sq = 54,
 231     rv_op_addid = 55,
 232     rv_op_sllid = 56,
 233     rv_op_srlid = 57,
 234     rv_op_sraid = 58,
 235     rv_op_addd = 59,
 236     rv_op_subd = 60,
 237     rv_op_slld = 61,
 238     rv_op_srld = 62,
 239     rv_op_srad = 63,
 240     rv_op_mul = 64,
 241     rv_op_mulh = 65,
 242     rv_op_mulhsu = 66,
 243     rv_op_mulhu = 67,
 244     rv_op_div = 68,
 245     rv_op_divu = 69,
 246     rv_op_rem = 70,
 247     rv_op_remu = 71,
 248     rv_op_mulw = 72,
 249     rv_op_divw = 73,
 250     rv_op_divuw = 74,
 251     rv_op_remw = 75,
 252     rv_op_remuw = 76,
 253     rv_op_muld = 77,
 254     rv_op_divd = 78,
 255     rv_op_divud = 79,
 256     rv_op_remd = 80,
 257     rv_op_remud = 81,
 258     rv_op_lr_w = 82,
 259     rv_op_sc_w = 83,
 260     rv_op_amoswap_w = 84,
 261     rv_op_amoadd_w = 85,
 262     rv_op_amoxor_w = 86,
 263     rv_op_amoor_w = 87,
 264     rv_op_amoand_w = 88,
 265     rv_op_amomin_w = 89,
 266     rv_op_amomax_w = 90,
 267     rv_op_amominu_w = 91,
 268     rv_op_amomaxu_w = 92,
 269     rv_op_lr_d = 93,
 270     rv_op_sc_d = 94,
 271     rv_op_amoswap_d = 95,
 272     rv_op_amoadd_d = 96,
 273     rv_op_amoxor_d = 97,
 274     rv_op_amoor_d = 98,
 275     rv_op_amoand_d = 99,
 276     rv_op_amomin_d = 100,
 277     rv_op_amomax_d = 101,
 278     rv_op_amominu_d = 102,
 279     rv_op_amomaxu_d = 103,
 280     rv_op_lr_q = 104,
 281     rv_op_sc_q = 105,
 282     rv_op_amoswap_q = 106,
 283     rv_op_amoadd_q = 107,
 284     rv_op_amoxor_q = 108,
 285     rv_op_amoor_q = 109,
 286     rv_op_amoand_q = 110,
 287     rv_op_amomin_q = 111,
 288     rv_op_amomax_q = 112,
 289     rv_op_amominu_q = 113,
 290     rv_op_amomaxu_q = 114,
 291     rv_op_ecall = 115,
 292     rv_op_ebreak = 116,
 293     rv_op_uret = 117,
 294     rv_op_sret = 118,
 295     rv_op_hret = 119,
 296     rv_op_mret = 120,
 297     rv_op_dret = 121,
 298     rv_op_sfence_vm = 122,
 299     rv_op_sfence_vma = 123,
 300     rv_op_wfi = 124,
 301     rv_op_csrrw = 125,
 302     rv_op_csrrs = 126,
 303     rv_op_csrrc = 127,
 304     rv_op_csrrwi = 128,
 305     rv_op_csrrsi = 129,
 306     rv_op_csrrci = 130,
 307     rv_op_flw = 131,
 308     rv_op_fsw = 132,
 309     rv_op_fmadd_s = 133,
 310     rv_op_fmsub_s = 134,
 311     rv_op_fnmsub_s = 135,
 312     rv_op_fnmadd_s = 136,
 313     rv_op_fadd_s = 137,
 314     rv_op_fsub_s = 138,
 315     rv_op_fmul_s = 139,
 316     rv_op_fdiv_s = 140,
 317     rv_op_fsgnj_s = 141,
 318     rv_op_fsgnjn_s = 142,
 319     rv_op_fsgnjx_s = 143,
 320     rv_op_fmin_s = 144,
 321     rv_op_fmax_s = 145,
 322     rv_op_fsqrt_s = 146,
 323     rv_op_fle_s = 147,
 324     rv_op_flt_s = 148,
 325     rv_op_feq_s = 149,
 326     rv_op_fcvt_w_s = 150,
 327     rv_op_fcvt_wu_s = 151,
 328     rv_op_fcvt_s_w = 152,
 329     rv_op_fcvt_s_wu = 153,
 330     rv_op_fmv_x_s = 154,
 331     rv_op_fclass_s = 155,
 332     rv_op_fmv_s_x = 156,
 333     rv_op_fcvt_l_s = 157,
 334     rv_op_fcvt_lu_s = 158,
 335     rv_op_fcvt_s_l = 159,
 336     rv_op_fcvt_s_lu = 160,
 337     rv_op_fld = 161,
 338     rv_op_fsd = 162,
 339     rv_op_fmadd_d = 163,
 340     rv_op_fmsub_d = 164,
 341     rv_op_fnmsub_d = 165,
 342     rv_op_fnmadd_d = 166,
 343     rv_op_fadd_d = 167,
 344     rv_op_fsub_d = 168,
 345     rv_op_fmul_d = 169,
 346     rv_op_fdiv_d = 170,
 347     rv_op_fsgnj_d = 171,
 348     rv_op_fsgnjn_d = 172,
 349     rv_op_fsgnjx_d = 173,
 350     rv_op_fmin_d = 174,
 351     rv_op_fmax_d = 175,
 352     rv_op_fcvt_s_d = 176,
 353     rv_op_fcvt_d_s = 177,
 354     rv_op_fsqrt_d = 178,
 355     rv_op_fle_d = 179,
 356     rv_op_flt_d = 180,
 357     rv_op_feq_d = 181,
 358     rv_op_fcvt_w_d = 182,
 359     rv_op_fcvt_wu_d = 183,
 360     rv_op_fcvt_d_w = 184,
 361     rv_op_fcvt_d_wu = 185,
 362     rv_op_fclass_d = 186,
 363     rv_op_fcvt_l_d = 187,
 364     rv_op_fcvt_lu_d = 188,
 365     rv_op_fmv_x_d = 189,
 366     rv_op_fcvt_d_l = 190,
 367     rv_op_fcvt_d_lu = 191,
 368     rv_op_fmv_d_x = 192,
 369     rv_op_flq = 193,
 370     rv_op_fsq = 194,
 371     rv_op_fmadd_q = 195,
 372     rv_op_fmsub_q = 196,
 373     rv_op_fnmsub_q = 197,
 374     rv_op_fnmadd_q = 198,
 375     rv_op_fadd_q = 199,
 376     rv_op_fsub_q = 200,
 377     rv_op_fmul_q = 201,
 378     rv_op_fdiv_q = 202,
 379     rv_op_fsgnj_q = 203,
 380     rv_op_fsgnjn_q = 204,
 381     rv_op_fsgnjx_q = 205,
 382     rv_op_fmin_q = 206,
 383     rv_op_fmax_q = 207,
 384     rv_op_fcvt_s_q = 208,
 385     rv_op_fcvt_q_s = 209,
 386     rv_op_fcvt_d_q = 210,
 387     rv_op_fcvt_q_d = 211,
 388     rv_op_fsqrt_q = 212,
 389     rv_op_fle_q = 213,
 390     rv_op_flt_q = 214,
 391     rv_op_feq_q = 215,
 392     rv_op_fcvt_w_q = 216,
 393     rv_op_fcvt_wu_q = 217,
 394     rv_op_fcvt_q_w = 218,
 395     rv_op_fcvt_q_wu = 219,
 396     rv_op_fclass_q = 220,
 397     rv_op_fcvt_l_q = 221,
 398     rv_op_fcvt_lu_q = 222,
 399     rv_op_fcvt_q_l = 223,
 400     rv_op_fcvt_q_lu = 224,
 401     rv_op_fmv_x_q = 225,
 402     rv_op_fmv_q_x = 226,
 403     rv_op_c_addi4spn = 227,
 404     rv_op_c_fld = 228,
 405     rv_op_c_lw = 229,
 406     rv_op_c_flw = 230,
 407     rv_op_c_fsd = 231,
 408     rv_op_c_sw = 232,
 409     rv_op_c_fsw = 233,
 410     rv_op_c_nop = 234,
 411     rv_op_c_addi = 235,
 412     rv_op_c_jal = 236,
 413     rv_op_c_li = 237,
 414     rv_op_c_addi16sp = 238,
 415     rv_op_c_lui = 239,
 416     rv_op_c_srli = 240,
 417     rv_op_c_srai = 241,
 418     rv_op_c_andi = 242,
 419     rv_op_c_sub = 243,
 420     rv_op_c_xor = 244,
 421     rv_op_c_or = 245,
 422     rv_op_c_and = 246,
 423     rv_op_c_subw = 247,
 424     rv_op_c_addw = 248,
 425     rv_op_c_j = 249,
 426     rv_op_c_beqz = 250,
 427     rv_op_c_bnez = 251,
 428     rv_op_c_slli = 252,
 429     rv_op_c_fldsp = 253,
 430     rv_op_c_lwsp = 254,
 431     rv_op_c_flwsp = 255,
 432     rv_op_c_jr = 256,
 433     rv_op_c_mv = 257,
 434     rv_op_c_ebreak = 258,
 435     rv_op_c_jalr = 259,
 436     rv_op_c_add = 260,
 437     rv_op_c_fsdsp = 261,
 438     rv_op_c_swsp = 262,
 439     rv_op_c_fswsp = 263,
 440     rv_op_c_ld = 264,
 441     rv_op_c_sd = 265,
 442     rv_op_c_addiw = 266,
 443     rv_op_c_ldsp = 267,
 444     rv_op_c_sdsp = 268,
 445     rv_op_c_lq = 269,
 446     rv_op_c_sq = 270,
 447     rv_op_c_lqsp = 271,
 448     rv_op_c_sqsp = 272,
 449     rv_op_nop = 273,
 450     rv_op_mv = 274,
 451     rv_op_not = 275,
 452     rv_op_neg = 276,
 453     rv_op_negw = 277,
 454     rv_op_sext_w = 278,
 455     rv_op_seqz = 279,
 456     rv_op_snez = 280,
 457     rv_op_sltz = 281,
 458     rv_op_sgtz = 282,
 459     rv_op_fmv_s = 283,
 460     rv_op_fabs_s = 284,
 461     rv_op_fneg_s = 285,
 462     rv_op_fmv_d = 286,
 463     rv_op_fabs_d = 287,
 464     rv_op_fneg_d = 288,
 465     rv_op_fmv_q = 289,
 466     rv_op_fabs_q = 290,
 467     rv_op_fneg_q = 291,
 468     rv_op_beqz = 292,
 469     rv_op_bnez = 293,
 470     rv_op_blez = 294,
 471     rv_op_bgez = 295,
 472     rv_op_bltz = 296,
 473     rv_op_bgtz = 297,
 474     rv_op_ble = 298,
 475     rv_op_bleu = 299,
 476     rv_op_bgt = 300,
 477     rv_op_bgtu = 301,
 478     rv_op_j = 302,
 479     rv_op_ret = 303,
 480     rv_op_jr = 304,
 481     rv_op_rdcycle = 305,
 482     rv_op_rdtime = 306,
 483     rv_op_rdinstret = 307,
 484     rv_op_rdcycleh = 308,
 485     rv_op_rdtimeh = 309,
 486     rv_op_rdinstreth = 310,
 487     rv_op_frcsr = 311,
 488     rv_op_frrm = 312,
 489     rv_op_frflags = 313,
 490     rv_op_fscsr = 314,
 491     rv_op_fsrm = 315,
 492     rv_op_fsflags = 316,
 493     rv_op_fsrmi = 317,
 494     rv_op_fsflagsi = 318,
 495     rv_op_bseti = 319,
 496     rv_op_bclri = 320,
 497     rv_op_binvi = 321,
 498     rv_op_bexti = 322,
 499     rv_op_rori = 323,
 500     rv_op_clz = 324,
 501     rv_op_ctz = 325,
 502     rv_op_cpop = 326,
 503     rv_op_sext_h = 327,
 504     rv_op_sext_b = 328,
 505     rv_op_xnor = 329,
 506     rv_op_orn = 330,
 507     rv_op_andn = 331,
 508     rv_op_rol = 332,
 509     rv_op_ror = 333,
 510     rv_op_sh1add = 334,
 511     rv_op_sh2add = 335,
 512     rv_op_sh3add = 336,
 513     rv_op_sh1add_uw = 337,
 514     rv_op_sh2add_uw = 338,
 515     rv_op_sh3add_uw = 339,
 516     rv_op_clmul = 340,
 517     rv_op_clmulr = 341,
 518     rv_op_clmulh = 342,
 519     rv_op_min = 343,
 520     rv_op_minu = 344,
 521     rv_op_max = 345,
 522     rv_op_maxu = 346,
 523     rv_op_clzw = 347,
 524     rv_op_ctzw = 348,
 525     rv_op_cpopw = 349,
 526     rv_op_slli_uw = 350,
 527     rv_op_add_uw = 351,
 528     rv_op_rolw = 352,
 529     rv_op_rorw = 353,
 530     rv_op_rev8 = 354,
 531     rv_op_zext_h = 355,
 532     rv_op_roriw = 356,
 533     rv_op_orc_b = 357,
 534     rv_op_bset = 358,
 535     rv_op_bclr = 359,
 536     rv_op_binv = 360,
 537     rv_op_bext = 361,
 538     rv_op_aes32esmi = 362,
 539     rv_op_aes32esi = 363,
 540     rv_op_aes32dsmi = 364,
 541     rv_op_aes32dsi = 365,
 542     rv_op_aes64ks1i = 366,
 543     rv_op_aes64ks2 = 367,
 544     rv_op_aes64im = 368,
 545     rv_op_aes64esm = 369,
 546     rv_op_aes64es = 370,
 547     rv_op_aes64dsm = 371,
 548     rv_op_aes64ds = 372,
 549     rv_op_sha256sig0 = 373,
 550     rv_op_sha256sig1 = 374,
 551     rv_op_sha256sum0 = 375,
 552     rv_op_sha256sum1 = 376,
 553     rv_op_sha512sig0 = 377,
 554     rv_op_sha512sig1 = 378,
 555     rv_op_sha512sum0 = 379,
 556     rv_op_sha512sum1 = 380,
 557     rv_op_sha512sum0r = 381,
 558     rv_op_sha512sum1r = 382,
 559     rv_op_sha512sig0l = 383,
 560     rv_op_sha512sig0h = 384,
 561     rv_op_sha512sig1l = 385,
 562     rv_op_sha512sig1h = 386,
 563     rv_op_sm3p0 = 387,
 564     rv_op_sm3p1 = 388,
 565     rv_op_sm4ed = 389,
 566     rv_op_sm4ks = 390,
 567     rv_op_brev8 = 391,
 568     rv_op_pack = 392,
 569     rv_op_packh = 393,
 570     rv_op_packw = 394,
 571     rv_op_unzip = 395,
 572     rv_op_zip = 396,
 573     rv_op_xperm4 = 397,
 574     rv_op_xperm8 = 398,
 575     rv_op_vle8_v = 399,
 576     rv_op_vle16_v = 400,
 577     rv_op_vle32_v = 401,
 578     rv_op_vle64_v = 402,
 579     rv_op_vse8_v = 403,
 580     rv_op_vse16_v = 404,
 581     rv_op_vse32_v = 405,
 582     rv_op_vse64_v = 406,
 583     rv_op_vlm_v = 407,
 584     rv_op_vsm_v = 408,
 585     rv_op_vlse8_v = 409,
 586     rv_op_vlse16_v = 410,
 587     rv_op_vlse32_v = 411,
 588     rv_op_vlse64_v = 412,
 589     rv_op_vsse8_v = 413,
 590     rv_op_vsse16_v = 414,
 591     rv_op_vsse32_v = 415,
 592     rv_op_vsse64_v = 416,
 593     rv_op_vluxei8_v = 417,
 594     rv_op_vluxei16_v = 418,
 595     rv_op_vluxei32_v = 419,
 596     rv_op_vluxei64_v = 420,
 597     rv_op_vloxei8_v = 421,
 598     rv_op_vloxei16_v = 422,
 599     rv_op_vloxei32_v = 423,
 600     rv_op_vloxei64_v = 424,
 601     rv_op_vsuxei8_v = 425,
 602     rv_op_vsuxei16_v = 426,
 603     rv_op_vsuxei32_v = 427,
 604     rv_op_vsuxei64_v = 428,
 605     rv_op_vsoxei8_v = 429,
 606     rv_op_vsoxei16_v = 430,
 607     rv_op_vsoxei32_v = 431,
 608     rv_op_vsoxei64_v = 432,
 609     rv_op_vle8ff_v = 433,
 610     rv_op_vle16ff_v = 434,
 611     rv_op_vle32ff_v = 435,
 612     rv_op_vle64ff_v = 436,
 613     rv_op_vl1re8_v = 437,
 614     rv_op_vl1re16_v = 438,
 615     rv_op_vl1re32_v = 439,
 616     rv_op_vl1re64_v = 440,
 617     rv_op_vl2re8_v = 441,
 618     rv_op_vl2re16_v = 442,
 619     rv_op_vl2re32_v = 443,
 620     rv_op_vl2re64_v = 444,
 621     rv_op_vl4re8_v = 445,
 622     rv_op_vl4re16_v = 446,
 623     rv_op_vl4re32_v = 447,
 624     rv_op_vl4re64_v = 448,
 625     rv_op_vl8re8_v = 449,
 626     rv_op_vl8re16_v = 450,
 627     rv_op_vl8re32_v = 451,
 628     rv_op_vl8re64_v = 452,
 629     rv_op_vs1r_v = 453,
 630     rv_op_vs2r_v = 454,
 631     rv_op_vs4r_v = 455,
 632     rv_op_vs8r_v = 456,
 633     rv_op_vadd_vv = 457,
 634     rv_op_vadd_vx = 458,
 635     rv_op_vadd_vi = 459,
 636     rv_op_vsub_vv = 460,
 637     rv_op_vsub_vx = 461,
 638     rv_op_vrsub_vx = 462,
 639     rv_op_vrsub_vi = 463,
 640     rv_op_vwaddu_vv = 464,
 641     rv_op_vwaddu_vx = 465,
 642     rv_op_vwadd_vv = 466,
 643     rv_op_vwadd_vx = 467,
 644     rv_op_vwsubu_vv = 468,
 645     rv_op_vwsubu_vx = 469,
 646     rv_op_vwsub_vv = 470,
 647     rv_op_vwsub_vx = 471,
 648     rv_op_vwaddu_wv = 472,
 649     rv_op_vwaddu_wx = 473,
 650     rv_op_vwadd_wv = 474,
 651     rv_op_vwadd_wx = 475,
 652     rv_op_vwsubu_wv = 476,
 653     rv_op_vwsubu_wx = 477,
 654     rv_op_vwsub_wv = 478,
 655     rv_op_vwsub_wx = 479,
 656     rv_op_vadc_vvm = 480,
 657     rv_op_vadc_vxm = 481,
 658     rv_op_vadc_vim = 482,
 659     rv_op_vmadc_vvm = 483,
 660     rv_op_vmadc_vxm = 484,
 661     rv_op_vmadc_vim = 485,
 662     rv_op_vsbc_vvm = 486,
 663     rv_op_vsbc_vxm = 487,
 664     rv_op_vmsbc_vvm = 488,
 665     rv_op_vmsbc_vxm = 489,
 666     rv_op_vand_vv = 490,
 667     rv_op_vand_vx = 491,
 668     rv_op_vand_vi = 492,
 669     rv_op_vor_vv = 493,
 670     rv_op_vor_vx = 494,
 671     rv_op_vor_vi = 495,
 672     rv_op_vxor_vv = 496,
 673     rv_op_vxor_vx = 497,
 674     rv_op_vxor_vi = 498,
 675     rv_op_vsll_vv = 499,
 676     rv_op_vsll_vx = 500,
 677     rv_op_vsll_vi = 501,
 678     rv_op_vsrl_vv = 502,
 679     rv_op_vsrl_vx = 503,
 680     rv_op_vsrl_vi = 504,
 681     rv_op_vsra_vv = 505,
 682     rv_op_vsra_vx = 506,
 683     rv_op_vsra_vi = 507,
 684     rv_op_vnsrl_wv = 508,
 685     rv_op_vnsrl_wx = 509,
 686     rv_op_vnsrl_wi = 510,
 687     rv_op_vnsra_wv = 511,
 688     rv_op_vnsra_wx = 512,
 689     rv_op_vnsra_wi = 513,
 690     rv_op_vmseq_vv = 514,
 691     rv_op_vmseq_vx = 515,
 692     rv_op_vmseq_vi = 516,
 693     rv_op_vmsne_vv = 517,
 694     rv_op_vmsne_vx = 518,
 695     rv_op_vmsne_vi = 519,
 696     rv_op_vmsltu_vv = 520,
 697     rv_op_vmsltu_vx = 521,
 698     rv_op_vmslt_vv = 522,
 699     rv_op_vmslt_vx = 523,
 700     rv_op_vmsleu_vv = 524,
 701     rv_op_vmsleu_vx = 525,
 702     rv_op_vmsleu_vi = 526,
 703     rv_op_vmsle_vv = 527,
 704     rv_op_vmsle_vx = 528,
 705     rv_op_vmsle_vi = 529,
 706     rv_op_vmsgtu_vx = 530,
 707     rv_op_vmsgtu_vi = 531,
 708     rv_op_vmsgt_vx = 532,
 709     rv_op_vmsgt_vi = 533,
 710     rv_op_vminu_vv = 534,
 711     rv_op_vminu_vx = 535,
 712     rv_op_vmin_vv = 536,
 713     rv_op_vmin_vx = 537,
 714     rv_op_vmaxu_vv = 538,
 715     rv_op_vmaxu_vx = 539,
 716     rv_op_vmax_vv = 540,
 717     rv_op_vmax_vx = 541,
 718     rv_op_vmul_vv = 542,
 719     rv_op_vmul_vx = 543,
 720     rv_op_vmulh_vv = 544,
 721     rv_op_vmulh_vx = 545,
 722     rv_op_vmulhu_vv = 546,
 723     rv_op_vmulhu_vx = 547,
 724     rv_op_vmulhsu_vv = 548,
 725     rv_op_vmulhsu_vx = 549,
 726     rv_op_vdivu_vv = 550,
 727     rv_op_vdivu_vx = 551,
 728     rv_op_vdiv_vv = 552,
 729     rv_op_vdiv_vx = 553,
 730     rv_op_vremu_vv = 554,
 731     rv_op_vremu_vx = 555,
 732     rv_op_vrem_vv = 556,
 733     rv_op_vrem_vx = 557,
 734     rv_op_vwmulu_vv = 558,
 735     rv_op_vwmulu_vx = 559,
 736     rv_op_vwmulsu_vv = 560,
 737     rv_op_vwmulsu_vx = 561,
 738     rv_op_vwmul_vv = 562,
 739     rv_op_vwmul_vx = 563,
 740     rv_op_vmacc_vv = 564,
 741     rv_op_vmacc_vx = 565,
 742     rv_op_vnmsac_vv = 566,
 743     rv_op_vnmsac_vx = 567,
 744     rv_op_vmadd_vv = 568,
 745     rv_op_vmadd_vx = 569,
 746     rv_op_vnmsub_vv = 570,
 747     rv_op_vnmsub_vx = 571,
 748     rv_op_vwmaccu_vv = 572,
 749     rv_op_vwmaccu_vx = 573,
 750     rv_op_vwmacc_vv = 574,
 751     rv_op_vwmacc_vx = 575,
 752     rv_op_vwmaccsu_vv = 576,
 753     rv_op_vwmaccsu_vx = 577,
 754     rv_op_vwmaccus_vx = 578,
 755     rv_op_vmv_v_v = 579,
 756     rv_op_vmv_v_x = 580,
 757     rv_op_vmv_v_i = 581,
 758     rv_op_vmerge_vvm = 582,
 759     rv_op_vmerge_vxm = 583,
 760     rv_op_vmerge_vim = 584,
 761     rv_op_vsaddu_vv = 585,
 762     rv_op_vsaddu_vx = 586,
 763     rv_op_vsaddu_vi = 587,
 764     rv_op_vsadd_vv = 588,
 765     rv_op_vsadd_vx = 589,
 766     rv_op_vsadd_vi = 590,
 767     rv_op_vssubu_vv = 591,
 768     rv_op_vssubu_vx = 592,
 769     rv_op_vssub_vv = 593,
 770     rv_op_vssub_vx = 594,
 771     rv_op_vaadd_vv = 595,
 772     rv_op_vaadd_vx = 596,
 773     rv_op_vaaddu_vv = 597,
 774     rv_op_vaaddu_vx = 598,
 775     rv_op_vasub_vv = 599,
 776     rv_op_vasub_vx = 600,
 777     rv_op_vasubu_vv = 601,
 778     rv_op_vasubu_vx = 602,
 779     rv_op_vsmul_vv = 603,
 780     rv_op_vsmul_vx = 604,
 781     rv_op_vssrl_vv = 605,
 782     rv_op_vssrl_vx = 606,
 783     rv_op_vssrl_vi = 607,
 784     rv_op_vssra_vv = 608,
 785     rv_op_vssra_vx = 609,
 786     rv_op_vssra_vi = 610,
 787     rv_op_vnclipu_wv = 611,
 788     rv_op_vnclipu_wx = 612,
 789     rv_op_vnclipu_wi = 613,
 790     rv_op_vnclip_wv = 614,
 791     rv_op_vnclip_wx = 615,
 792     rv_op_vnclip_wi = 616,
 793     rv_op_vfadd_vv = 617,
 794     rv_op_vfadd_vf = 618,
 795     rv_op_vfsub_vv = 619,
 796     rv_op_vfsub_vf = 620,
 797     rv_op_vfrsub_vf = 621,
 798     rv_op_vfwadd_vv = 622,
 799     rv_op_vfwadd_vf = 623,
 800     rv_op_vfwadd_wv = 624,
 801     rv_op_vfwadd_wf = 625,
 802     rv_op_vfwsub_vv = 626,
 803     rv_op_vfwsub_vf = 627,
 804     rv_op_vfwsub_wv = 628,
 805     rv_op_vfwsub_wf = 629,
 806     rv_op_vfmul_vv = 630,
 807     rv_op_vfmul_vf = 631,
 808     rv_op_vfdiv_vv = 632,
 809     rv_op_vfdiv_vf = 633,
 810     rv_op_vfrdiv_vf = 634,
 811     rv_op_vfwmul_vv = 635,
 812     rv_op_vfwmul_vf = 636,
 813     rv_op_vfmacc_vv = 637,
 814     rv_op_vfmacc_vf = 638,
 815     rv_op_vfnmacc_vv = 639,
 816     rv_op_vfnmacc_vf = 640,
 817     rv_op_vfmsac_vv = 641,
 818     rv_op_vfmsac_vf = 642,
 819     rv_op_vfnmsac_vv = 643,
 820     rv_op_vfnmsac_vf = 644,
 821     rv_op_vfmadd_vv = 645,
 822     rv_op_vfmadd_vf = 646,
 823     rv_op_vfnmadd_vv = 647,
 824     rv_op_vfnmadd_vf = 648,
 825     rv_op_vfmsub_vv = 649,
 826     rv_op_vfmsub_vf = 650,
 827     rv_op_vfnmsub_vv = 651,
 828     rv_op_vfnmsub_vf = 652,
 829     rv_op_vfwmacc_vv = 653,
 830     rv_op_vfwmacc_vf = 654,
 831     rv_op_vfwnmacc_vv = 655,
 832     rv_op_vfwnmacc_vf = 656,
 833     rv_op_vfwmsac_vv = 657,
 834     rv_op_vfwmsac_vf = 658,
 835     rv_op_vfwnmsac_vv = 659,
 836     rv_op_vfwnmsac_vf = 660,
 837     rv_op_vfsqrt_v = 661,
 838     rv_op_vfrsqrt7_v = 662,
 839     rv_op_vfrec7_v = 663,
 840     rv_op_vfmin_vv = 664,
 841     rv_op_vfmin_vf = 665,
 842     rv_op_vfmax_vv = 666,
 843     rv_op_vfmax_vf = 667,
 844     rv_op_vfsgnj_vv = 668,
 845     rv_op_vfsgnj_vf = 669,
 846     rv_op_vfsgnjn_vv = 670,
 847     rv_op_vfsgnjn_vf = 671,
 848     rv_op_vfsgnjx_vv = 672,
 849     rv_op_vfsgnjx_vf = 673,
 850     rv_op_vfslide1up_vf = 674,
 851     rv_op_vfslide1down_vf = 675,
 852     rv_op_vmfeq_vv = 676,
 853     rv_op_vmfeq_vf = 677,
 854     rv_op_vmfne_vv = 678,
 855     rv_op_vmfne_vf = 679,
 856     rv_op_vmflt_vv = 680,
 857     rv_op_vmflt_vf = 681,
 858     rv_op_vmfle_vv = 682,
 859     rv_op_vmfle_vf = 683,
 860     rv_op_vmfgt_vf = 684,
 861     rv_op_vmfge_vf = 685,
 862     rv_op_vfclass_v = 686,
 863     rv_op_vfmerge_vfm = 687,
 864     rv_op_vfmv_v_f = 688,
 865     rv_op_vfcvt_xu_f_v = 689,
 866     rv_op_vfcvt_x_f_v = 690,
 867     rv_op_vfcvt_f_xu_v = 691,
 868     rv_op_vfcvt_f_x_v = 692,
 869     rv_op_vfcvt_rtz_xu_f_v = 693,
 870     rv_op_vfcvt_rtz_x_f_v = 694,
 871     rv_op_vfwcvt_xu_f_v = 695,
 872     rv_op_vfwcvt_x_f_v = 696,
 873     rv_op_vfwcvt_f_xu_v = 697,
 874     rv_op_vfwcvt_f_x_v = 698,
 875     rv_op_vfwcvt_f_f_v = 699,
 876     rv_op_vfwcvt_rtz_xu_f_v = 700,
 877     rv_op_vfwcvt_rtz_x_f_v = 701,
 878     rv_op_vfncvt_xu_f_w = 702,
 879     rv_op_vfncvt_x_f_w = 703,
 880     rv_op_vfncvt_f_xu_w = 704,
 881     rv_op_vfncvt_f_x_w = 705,
 882     rv_op_vfncvt_f_f_w = 706,
 883     rv_op_vfncvt_rod_f_f_w = 707,
 884     rv_op_vfncvt_rtz_xu_f_w = 708,
 885     rv_op_vfncvt_rtz_x_f_w = 709,
 886     rv_op_vredsum_vs = 710,
 887     rv_op_vredand_vs = 711,
 888     rv_op_vredor_vs = 712,
 889     rv_op_vredxor_vs = 713,
 890     rv_op_vredminu_vs = 714,
 891     rv_op_vredmin_vs = 715,
 892     rv_op_vredmaxu_vs = 716,
 893     rv_op_vredmax_vs = 717,
 894     rv_op_vwredsumu_vs = 718,
 895     rv_op_vwredsum_vs = 719,
 896     rv_op_vfredusum_vs = 720,
 897     rv_op_vfredosum_vs = 721,
 898     rv_op_vfredmin_vs = 722,
 899     rv_op_vfredmax_vs = 723,
 900     rv_op_vfwredusum_vs = 724,
 901     rv_op_vfwredosum_vs = 725,
 902     rv_op_vmand_mm = 726,
 903     rv_op_vmnand_mm = 727,
 904     rv_op_vmandn_mm = 728,
 905     rv_op_vmxor_mm = 729,
 906     rv_op_vmor_mm = 730,
 907     rv_op_vmnor_mm = 731,
 908     rv_op_vmorn_mm = 732,
 909     rv_op_vmxnor_mm = 733,
 910     rv_op_vcpop_m = 734,
 911     rv_op_vfirst_m = 735,
 912     rv_op_vmsbf_m = 736,
 913     rv_op_vmsif_m = 737,
 914     rv_op_vmsof_m = 738,
 915     rv_op_viota_m = 739,
 916     rv_op_vid_v = 740,
 917     rv_op_vmv_x_s = 741,
 918     rv_op_vmv_s_x = 742,
 919     rv_op_vfmv_f_s = 743,
 920     rv_op_vfmv_s_f = 744,
 921     rv_op_vslideup_vx = 745,
 922     rv_op_vslideup_vi = 746,
 923     rv_op_vslide1up_vx = 747,
 924     rv_op_vslidedown_vx = 748,
 925     rv_op_vslidedown_vi = 749,
 926     rv_op_vslide1down_vx = 750,
 927     rv_op_vrgather_vv = 751,
 928     rv_op_vrgatherei16_vv = 752,
 929     rv_op_vrgather_vx = 753,
 930     rv_op_vrgather_vi = 754,
 931     rv_op_vcompress_vm = 755,
 932     rv_op_vmv1r_v = 756,
 933     rv_op_vmv2r_v = 757,
 934     rv_op_vmv4r_v = 758,
 935     rv_op_vmv8r_v = 759,
 936     rv_op_vzext_vf2 = 760,
 937     rv_op_vzext_vf4 = 761,
 938     rv_op_vzext_vf8 = 762,
 939     rv_op_vsext_vf2 = 763,
 940     rv_op_vsext_vf4 = 764,
 941     rv_op_vsext_vf8 = 765,
 942     rv_op_vsetvli = 766,
 943     rv_op_vsetivli = 767,
 944     rv_op_vsetvl = 768,
 945     rv_op_c_zext_b = 769,
 946     rv_op_c_sext_b = 770,
 947     rv_op_c_zext_h = 771,
 948     rv_op_c_sext_h = 772,
 949     rv_op_c_zext_w = 773,
 950     rv_op_c_not = 774,
 951     rv_op_c_mul = 775,
 952     rv_op_c_lbu = 776,
 953     rv_op_c_lhu = 777,
 954     rv_op_c_lh = 778,
 955     rv_op_c_sb = 779,
 956     rv_op_c_sh = 780,
 957     rv_op_cm_push = 781,
 958     rv_op_cm_pop = 782,
 959     rv_op_cm_popret = 783,
 960     rv_op_cm_popretz = 784,
 961     rv_op_cm_mva01s = 785,
 962     rv_op_cm_mvsa01 = 786,
 963     rv_op_cm_jt = 787,
 964     rv_op_cm_jalt = 788,
 965     rv_op_czero_eqz = 789,
 966     rv_op_czero_nez = 790,
 967 } rv_op;
 968
 969 /* structures */
 970
 971 typedef struct {
 972     RISCVCPUConfig *cfg;
 973     uint64_t  pc;
 974     uint64_t  inst;
 975     int32_t   imm;
 976     uint16_t  op;
 977     uint8_t   codec;
 978     uint8_t   rd;
 979     uint8_t   rs1;
 980     uint8_t   rs2;
 981     uint8_t   rs3;
 982     uint8_t   rm;
 983     uint8_t   pred;
 984     uint8_t   succ;
 985     uint8_t   aq;
 986     uint8_t   rl;
 987     uint8_t   bs;
 988     uint8_t   rnum;
 989     uint8_t   vm;
 990     uint32_t  vzimm;
 991     uint8_t   rlist;
 992 } rv_decode;
 993
 994 typedef struct {
 995     const int op;
 996     const rvc_constraint *constraints;
 997 } rv_comp_data;
 998
 999 enum {
1000     rvcd_imm_nz = 0x1
1001 };
1002
1003 typedef struct {
1004     const char * const name;
1005     const rv_codec codec;
1006     const char * const format;
1007     const rv_comp_data *pseudo;
1008     const short decomp_rv32;
1009     const short decomp_rv64;
1010     const short decomp_rv128;
1011     const short decomp_data;
1012 } rv_opcode_data;
1013
1014 /* register names */
1015
1016 static const char rv_ireg_name_sym[32][5] = {
1017     "zero", "ra",   "sp",   "gp",   "tp",   "t0",   "t1",   "t2",
1018     "s0",   "s1",   "a0",   "a1",   "a2",   "a3",   "a4",   "a5",
1019     "a6",   "a7",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
1020     "s8",   "s9",   "s10",  "s11",  "t3",   "t4",   "t5",   "t6",
1021 };
1022
1023 static const char rv_freg_name_sym[32][5] = {
1024     "ft0",  "ft1",  "ft2",  "ft3",  "ft4",  "ft5",  "ft6",  "ft7",
1025     "fs0",  "fs1",  "fa0",  "fa1",  "fa2",  "fa3",  "fa4",  "fa5",
1026     "fa6",  "fa7",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7",
1027     "fs8",  "fs9",  "fs10", "fs11", "ft8",  "ft9",  "ft10", "ft11",
1028 };
1029
1030 static const char rv_vreg_name_sym[32][4] = {
1031     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
1032     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
1033     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1034     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
1035 };
1036
1037 /* instruction formats */
1038
1039 #define rv_fmt_none                   "O\t"
1040 #define rv_fmt_rs1                    "O\t1"
1041 #define rv_fmt_offset                 "O\to"
1042 #define rv_fmt_pred_succ              "O\tp,s"
1043 #define rv_fmt_rs1_rs2                "O\t1,2"
1044 #define rv_fmt_rd_imm                 "O\t0,i"
1045 #define rv_fmt_rd_offset              "O\t0,o"
1046 #define rv_fmt_rd_rs1_rs2             "O\t0,1,2"
1047 #define rv_fmt_frd_rs1                "O\t3,1"
1048 #define rv_fmt_frd_frs1               "O\t3,4"
1049 #define rv_fmt_rd_frs1                "O\t0,4"
1050 #define rv_fmt_rd_frs1_frs2           "O\t0,4,5"
1051 #define rv_fmt_frd_frs1_frs2          "O\t3,4,5"
1052 #define rv_fmt_rm_frd_frs1            "O\tr,3,4"
1053 #define rv_fmt_rm_frd_rs1             "O\tr,3,1"
1054 #define rv_fmt_rm_rd_frs1             "O\tr,0,4"
1055 #define rv_fmt_rm_frd_frs1_frs2       "O\tr,3,4,5"
1056 #define rv_fmt_rm_frd_frs1_frs2_frs3  "O\tr,3,4,5,6"
1057 #define rv_fmt_rd_rs1_imm             "O\t0,1,i"
1058 #define rv_fmt_rd_rs1_offset          "O\t0,1,i"
1059 #define rv_fmt_rd_offset_rs1          "O\t0,i(1)"
1060 #define rv_fmt_frd_offset_rs1         "O\t3,i(1)"
1061 #define rv_fmt_rd_csr_rs1             "O\t0,c,1"
1062 #define rv_fmt_rd_csr_zimm            "O\t0,c,7"
1063 #define rv_fmt_rs2_offset_rs1         "O\t2,i(1)"
1064 #define rv_fmt_frs2_offset_rs1        "O\t5,i(1)"
1065 #define rv_fmt_rs1_rs2_offset         "O\t1,2,o"
1066 #define rv_fmt_rs2_rs1_offset         "O\t2,1,o"
1067 #define rv_fmt_aqrl_rd_rs2_rs1        "OAR\t0,2,(1)"
1068 #define rv_fmt_aqrl_rd_rs1            "OAR\t0,(1)"
1069 #define rv_fmt_rd                     "O\t0"
1070 #define rv_fmt_rd_zimm                "O\t0,7"
1071 #define rv_fmt_rd_rs1                 "O\t0,1"
1072 #define rv_fmt_rd_rs2                 "O\t0,2"
1073 #define rv_fmt_rs1_offset             "O\t1,o"
1074 #define rv_fmt_rs2_offset             "O\t2,o"
1075 #define rv_fmt_rs1_rs2_bs             "O\t1,2,b"
1076 #define rv_fmt_rd_rs1_rnum            "O\t0,1,n"
1077 #define rv_fmt_ldst_vd_rs1_vm         "O\tD,(1)m"
1078 #define rv_fmt_ldst_vd_rs1_rs2_vm     "O\tD,(1),2m"
1079 #define rv_fmt_ldst_vd_rs1_vs2_vm     "O\tD,(1),Fm"
1080 #define rv_fmt_vd_vs2_vs1             "O\tD,F,E"
1081 #define rv_fmt_vd_vs2_vs1_vl          "O\tD,F,El"
1082 #define rv_fmt_vd_vs2_vs1_vm          "O\tD,F,Em"
1083 #define rv_fmt_vd_vs2_rs1_vl          "O\tD,F,1l"
1084 #define rv_fmt_vd_vs2_fs1_vl          "O\tD,F,4l"
1085 #define rv_fmt_vd_vs2_rs1_vm          "O\tD,F,1m"
1086 #define rv_fmt_vd_vs2_fs1_vm          "O\tD,F,4m"
1087 #define rv_fmt_vd_vs2_imm_vl          "O\tD,F,il"
1088 #define rv_fmt_vd_vs2_imm_vm          "O\tD,F,im"
1089 #define rv_fmt_vd_vs2_uimm_vm         "O\tD,F,um"
1090 #define rv_fmt_vd_vs1_vs2_vm          "O\tD,E,Fm"
1091 #define rv_fmt_vd_rs1_vs2_vm          "O\tD,1,Fm"
1092 #define rv_fmt_vd_fs1_vs2_vm          "O\tD,4,Fm"
1093 #define rv_fmt_vd_vs1                 "O\tD,E"
1094 #define rv_fmt_vd_rs1                 "O\tD,1"
1095 #define rv_fmt_vd_fs1                 "O\tD,4"
1096 #define rv_fmt_vd_imm                 "O\tD,i"
1097 #define rv_fmt_vd_vs2                 "O\tD,F"
1098 #define rv_fmt_vd_vs2_vm              "O\tD,Fm"
1099 #define rv_fmt_rd_vs2_vm              "O\t0,Fm"
1100 #define rv_fmt_rd_vs2                 "O\t0,F"
1101 #define rv_fmt_fd_vs2                 "O\t3,F"
1102 #define rv_fmt_vd_vm                  "O\tDm"
1103 #define rv_fmt_vsetvli                "O\t0,1,v"
1104 #define rv_fmt_vsetivli               "O\t0,u,v"
1105 #define rv_fmt_rs1_rs2_zce_ldst       "O\t2,i(1)"
1106 #define rv_fmt_push_rlist             "O\tx,-i"
1107 #define rv_fmt_pop_rlist              "O\tx,i"
1108 #define rv_fmt_zcmt_index             "O\ti"
1109
1110 /* pseudo-instruction constraints */
1111
1112 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
1113 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end };
1114 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end };
1115 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
1116 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
1117 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
1118 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
1119 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };
1120 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
1121 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
1122 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };
1123 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end };
1124 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end };
1125 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end };
1126 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end };
1127 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end };
1128 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end };
1129 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end };
1130 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end };
1131 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end };
1132 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end };
1133 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end };
1134 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end };
1135 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end };
1136 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end };
1137 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end };
1138 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end };
1139 static const rvc_constraint rvcc_ble[] = { rvc_end };
1140 static const rvc_constraint rvcc_bleu[] = { rvc_end };
1141 static const rvc_constraint rvcc_bgt[] = { rvc_end };
1142 static const rvc_constraint rvcc_bgtu[] = { rvc_end };
1143 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
1144 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end };
1145 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end };
1146 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end };
1147 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end };
1148 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end };
1149 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };
1150 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end };
1151 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
1152                                                   rvc_csr_eq_0xc82, rvc_end };
1153 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end };
1154 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end };
1155 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end };
1156 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
1157 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
1158 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
1159 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };
1160 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };
1161
1162 /* pseudo-instruction metadata */
1163
1164 static const rv_comp_data rvcp_jal[] = {
1165     { rv_op_j, rvcc_j },
1166     { rv_op_jal, rvcc_jal },
1167     { rv_op_illegal, NULL }
1168 };
1169
1170 static const rv_comp_data rvcp_jalr[] = {
1171     { rv_op_ret, rvcc_ret },
1172     { rv_op_jr, rvcc_jr },
1173     { rv_op_jalr, rvcc_jalr },
1174     { rv_op_illegal, NULL }
1175 };
1176
1177 static const rv_comp_data rvcp_beq[] = {
1178     { rv_op_beqz, rvcc_beqz },
1179     { rv_op_illegal, NULL }
1180 };
1181
1182 static const rv_comp_data rvcp_bne[] = {
1183     { rv_op_bnez, rvcc_bnez },
1184     { rv_op_illegal, NULL }
1185 };
1186
1187 static const rv_comp_data rvcp_blt[] = {
1188     { rv_op_bltz, rvcc_bltz },
1189     { rv_op_bgtz, rvcc_bgtz },
1190     { rv_op_bgt, rvcc_bgt },
1191     { rv_op_illegal, NULL }
1192 };
1193
1194 static const rv_comp_data rvcp_bge[] = {
1195     { rv_op_blez, rvcc_blez },
1196     { rv_op_bgez, rvcc_bgez },
1197     { rv_op_ble, rvcc_ble },
1198     { rv_op_illegal, NULL }
1199 };
1200
1201 static const rv_comp_data rvcp_bltu[] = {
1202     { rv_op_bgtu, rvcc_bgtu },
1203     { rv_op_illegal, NULL }
1204 };
1205
1206 static const rv_comp_data rvcp_bgeu[] = {
1207     { rv_op_bleu, rvcc_bleu },
1208     { rv_op_illegal, NULL }
1209 };
1210
1211 static const rv_comp_data rvcp_addi[] = {
1212     { rv_op_nop, rvcc_nop },
1213     { rv_op_mv, rvcc_mv },
1214     { rv_op_illegal, NULL }
1215 };
1216
1217 static const rv_comp_data rvcp_sltiu[] = {
1218     { rv_op_seqz, rvcc_seqz },
1219     { rv_op_illegal, NULL }
1220 };
1221
1222 static const rv_comp_data rvcp_xori[] = {
1223     { rv_op_not, rvcc_not },
1224     { rv_op_illegal, NULL }
1225 };
1226
1227 static const rv_comp_data rvcp_sub[] = {
1228     { rv_op_neg, rvcc_neg },
1229     { rv_op_illegal, NULL }
1230 };
1231
1232 static const rv_comp_data rvcp_slt[] = {
1233     { rv_op_sltz, rvcc_sltz },
1234     { rv_op_sgtz, rvcc_sgtz },
1235     { rv_op_illegal, NULL }
1236 };
1237
1238 static const rv_comp_data rvcp_sltu[] = {
1239     { rv_op_snez, rvcc_snez },
1240     { rv_op_illegal, NULL }
1241 };
1242
1243 static const rv_comp_data rvcp_addiw[] = {
1244     { rv_op_sext_w, rvcc_sext_w },
1245     { rv_op_illegal, NULL }
1246 };
1247
1248 static const rv_comp_data rvcp_subw[] = {
1249     { rv_op_negw, rvcc_negw },
1250     { rv_op_illegal, NULL }
1251 };
1252
1253 static const rv_comp_data rvcp_csrrw[] = {
1254     { rv_op_fscsr, rvcc_fscsr },
1255     { rv_op_fsrm, rvcc_fsrm },
1256     { rv_op_fsflags, rvcc_fsflags },
1257     { rv_op_illegal, NULL }
1258 };
1259
1260
1261 static const rv_comp_data rvcp_csrrs[] = {
1262     { rv_op_rdcycle, rvcc_rdcycle },
1263     { rv_op_rdtime, rvcc_rdtime },
1264     { rv_op_rdinstret, rvcc_rdinstret },
1265     { rv_op_rdcycleh, rvcc_rdcycleh },
1266     { rv_op_rdtimeh, rvcc_rdtimeh },
1267     { rv_op_rdinstreth, rvcc_rdinstreth },
1268     { rv_op_frcsr, rvcc_frcsr },
1269     { rv_op_frrm, rvcc_frrm },
1270     { rv_op_frflags, rvcc_frflags },
1271     { rv_op_illegal, NULL }
1272 };
1273
1274 static const rv_comp_data rvcp_csrrwi[] = {
1275     { rv_op_fsrmi, rvcc_fsrmi },
1276     { rv_op_fsflagsi, rvcc_fsflagsi },
1277     { rv_op_illegal, NULL }
1278 };
1279
1280 static const rv_comp_data rvcp_fsgnj_s[] = {
1281     { rv_op_fmv_s, rvcc_fmv_s },
1282     { rv_op_illegal, NULL }
1283 };
1284
1285 static const rv_comp_data rvcp_fsgnjn_s[] = {
1286     { rv_op_fneg_s, rvcc_fneg_s },
1287     { rv_op_illegal, NULL }
1288 };
1289
1290 static const rv_comp_data rvcp_fsgnjx_s[] = {
1291     { rv_op_fabs_s, rvcc_fabs_s },
1292     { rv_op_illegal, NULL }
1293 };
1294
1295 static const rv_comp_data rvcp_fsgnj_d[] = {
1296     { rv_op_fmv_d, rvcc_fmv_d },
1297     { rv_op_illegal, NULL }
1298 };
1299
1300 static const rv_comp_data rvcp_fsgnjn_d[] = {
1301     { rv_op_fneg_d, rvcc_fneg_d },
1302     { rv_op_illegal, NULL }
1303 };
1304
1305 static const rv_comp_data rvcp_fsgnjx_d[] = {
1306     { rv_op_fabs_d, rvcc_fabs_d },
1307     { rv_op_illegal, NULL }
1308 };
1309
1310 static const rv_comp_data rvcp_fsgnj_q[] = {
1311     { rv_op_fmv_q, rvcc_fmv_q },
1312     { rv_op_illegal, NULL }
1313 };
1314
1315 static const rv_comp_data rvcp_fsgnjn_q[] = {
1316     { rv_op_fneg_q, rvcc_fneg_q },
1317     { rv_op_illegal, NULL }
1318 };
1319
1320 static const rv_comp_data rvcp_fsgnjx_q[] = {
1321     { rv_op_fabs_q, rvcc_fabs_q },
1322     { rv_op_illegal, NULL }
1323 };
1324
1325 /* instruction metadata */
1326
1327 const rv_opcode_data opcode_data[] = {
1328     { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
1329     { "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 },
1330     { "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 },
1331     { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 },
1332     { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 },
1333     { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 },
1334     { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 },
1335     { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 },
1336     { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 },
1337     { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 },
1338     { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 },
1339     { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1340     { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1341     { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1342     { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1343     { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1344     { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1345     { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1346     { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1347     { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 },
1348     { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1349     { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 },
1350     { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 },
1351     { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1352     { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1353     { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1354     { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1355     { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1356     { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1357     { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 },
1358     { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1359     { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 },
1360     { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 },
1361     { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1362     { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1363     { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1364     { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1365     { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1366     { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 },
1367     { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1368     { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1369     { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1370     { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1371     { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 },
1372     { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1373     { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1374     { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1375     { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1376     { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 },
1377     { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1378     { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1379     { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1380     { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1381     { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1382     { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1383     { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1384     { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1385     { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1386     { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1387     { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1388     { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1389     { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1390     { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1391     { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1392     { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1393     { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1394     { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1395     { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1396     { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1397     { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1398     { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1399     { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1400     { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1401     { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1402     { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1403     { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1404     { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1405     { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1406     { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1407     { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1408     { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1409     { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1410     { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1411     { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1412     { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1413     { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1414     { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1415     { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1416     { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1417     { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1418     { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1419     { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1420     { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1421     { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1422     { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1423     { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1424     { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1425     { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1426     { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1427     { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1428     { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1429     { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1430     { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1431     { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1432     { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1433     { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1434     { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1435     { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1436     { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1437     { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1438     { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1439     { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1440     { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1441     { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1442     { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1443     { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1444     { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1445     { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1446     { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1447     { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1448     { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1449     { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1450     { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
1451     { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
1452     { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1453     { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 },
1454     { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 },
1455     { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 },
1456     { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 },
1457     { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
1458     { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
1459     { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1460     { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1461     { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1462     { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1463     { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1464     { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1465     { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1466     { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1467     { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1468     { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1469     { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 },
1470     { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 },
1471     { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 },
1472     { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1473     { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1474     { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1475     { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1476     { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1477     { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1478     { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1479     { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1480     { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1481     { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1482     { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1483     { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1484     { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1485     { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1486     { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1487     { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1488     { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1489     { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1490     { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1491     { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1492     { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1493     { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1494     { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1495     { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1496     { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1497     { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1498     { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1499     { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 },
1500     { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 },
1501     { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 },
1502     { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1503     { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1504     { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1505     { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1506     { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1507     { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1508     { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1509     { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1510     { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1511     { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1512     { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1513     { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1514     { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1515     { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1516     { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1517     { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1518     { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1519     { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1520     { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1521     { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1522     { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1523     { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1524     { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1525     { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1526     { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1527     { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1528     { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1529     { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1530     { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1531     { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 },
1532     { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 },
1533     { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 },
1534     { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1535     { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1536     { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1537     { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1538     { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1539     { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1540     { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1541     { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1542     { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1543     { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1544     { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1545     { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1546     { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1547     { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1548     { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1549     { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1550     { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1551     { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1552     { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1553     { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1554     { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1555     { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1556       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1557     { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 },
1558     { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
1559     { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
1560     { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 },
1561     { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
1562     { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
1563     { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
1564     { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
1565       rv_op_addi, rvcd_imm_nz },
1566     { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
1567     { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
1568     { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1569       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1570     { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui,
1571       rv_op_lui, rvcd_imm_nz },
1572     { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli,
1573       rv_op_srli, rv_op_srli, rvcd_imm_nz },
1574     { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai,
1575       rv_op_srai, rv_op_srai, rvcd_imm_nz },
1576     { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
1577       rv_op_andi, rv_op_andi },
1578     { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },
1579     { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },
1580     { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },
1581     { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and },
1582     { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw },
1583     { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw },
1584     { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal },
1585     { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq },
1586     { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne },
1587     { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
1588       rv_op_slli, rv_op_slli, rvcd_imm_nz },
1589     { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld },
1590     { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
1591     { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
1592     { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
1593     { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
1594     { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak },
1595     { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
1596     { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add },
1597     { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd },
1598     { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
1599     { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
1600     { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
1601     { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
1602     { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw },
1603     { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
1604     { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
1605     { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
1606     { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
1607     { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
1608     { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
1609     { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
1610     { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1611     { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1612     { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1613     { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1614     { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1615     { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1616     { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1617     { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1618     { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1619     { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1620     { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1621     { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1622     { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1623     { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1624     { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1625     { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1626     { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1627     { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1628     { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1629     { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1630     { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
1631     { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1632     { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1633     { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
1634     { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1635     { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1636     { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1637     { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1638     { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 },
1639     { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
1640     { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 },
1641     { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1642     { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1643     { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1644     { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1645     { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1646     { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1647     { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1648     { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1649     { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1650     { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1651     { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1652     { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1653     { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
1654     { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
1655     { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1656     { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1657     { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1658     { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1659     { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1660     { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1661     { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1662     { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1663     { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1664     { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1665     { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1666     { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1667     { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1668     { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1669     { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1670     { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1671     { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1672     { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1673     { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1674     { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1675     { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1676     { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1677     { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1678     { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1679     { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1680     { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1681     { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1682     { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1683     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1684     { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1685     { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1686     { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1687     { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1688     { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1689     { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1690     { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1691     { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1692     { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1693     { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1694     { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1695     { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1696     { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1697     { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1698     { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1699     { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1700     { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1701     { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1702     { "aes64ks1i", rv_codec_k_rnum,  rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
1703     { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1704     { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1705     { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1706     { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1707     { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1708     { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1709     { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1710     { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1711     { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1712     { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1713     { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1714     { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1715     { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1716     { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1717     { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1718     { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1719     { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1720     { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1721     { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1722     { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1723     { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1724     { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1725     { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1726     { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1727     { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1728     { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1729     { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1730     { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1731     { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1732     { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1733     { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1734     { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1735     { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8_v, rv_op_vle8_v, 0 },
1736     { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16_v, rv_op_vle16_v, 0 },
1737     { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32_v, rv_op_vle32_v, 0 },
1738     { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64_v, rv_op_vle64_v, 0 },
1739     { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse8_v, rv_op_vse8_v, 0 },
1740     { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse16_v, rv_op_vse16_v, 0 },
1741     { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse32_v, rv_op_vse32_v, 0 },
1742     { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse64_v, rv_op_vse64_v, 0 },
1743     { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vlm_v, rv_op_vlm_v, 0 },
1744     { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vsm_v, rv_op_vsm_v, 0 },
1745     { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse8_v, rv_op_vlse8_v, 0 },
1746     { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse16_v, rv_op_vlse16_v, 0 },
1747     { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse32_v, rv_op_vlse32_v, 0 },
1748     { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse64_v, rv_op_vlse64_v, 0 },
1749     { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse8_v, rv_op_vsse8_v, 0 },
1750     { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse16_v, rv_op_vsse16_v, 0 },
1751     { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse32_v, rv_op_vsse32_v, 0 },
1752     { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse64_v, rv_op_vsse64_v, 0 },
1753     { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei8_v, rv_op_vluxei8_v, 0 },
1754     { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei16_v, rv_op_vluxei16_v, 0 },
1755     { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei32_v, rv_op_vluxei32_v, 0 },
1756     { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei64_v, rv_op_vluxei64_v, 0 },
1757     { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei8_v, rv_op_vloxei8_v, 0 },
1758     { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei16_v, rv_op_vloxei16_v, 0 },
1759     { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei32_v, rv_op_vloxei32_v, 0 },
1760     { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei64_v, rv_op_vloxei64_v, 0 },
1761     { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei8_v, rv_op_vsuxei8_v, 0 },
1762     { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei16_v, rv_op_vsuxei16_v, 0 },
1763     { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei32_v, rv_op_vsuxei32_v, 0 },
1764     { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei64_v, rv_op_vsuxei64_v, 0 },
1765     { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei8_v, rv_op_vsoxei8_v, 0 },
1766     { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei16_v, rv_op_vsoxei16_v, 0 },
1767     { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei32_v, rv_op_vsoxei32_v, 0 },
1768     { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei64_v, rv_op_vsoxei64_v, 0 },
1769     { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8ff_v, rv_op_vle8ff_v, 0 },
1770     { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16ff_v, rv_op_vle16ff_v, 0 },
1771     { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32ff_v, rv_op_vle32ff_v, 0 },
1772     { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64ff_v, rv_op_vle64ff_v, 0 },
1773     { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re8_v, rv_op_vl1re8_v, 0 },
1774     { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re16_v, rv_op_vl1re16_v, 0 },
1775     { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re32_v, rv_op_vl1re32_v, 0 },
1776     { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re64_v, rv_op_vl1re64_v, 0 },
1777     { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re8_v, rv_op_vl2re8_v, 0 },
1778     { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re16_v, rv_op_vl2re16_v, 0 },
1779     { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re32_v, rv_op_vl2re32_v, 0 },
1780     { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re64_v, rv_op_vl2re64_v, 0 },
1781     { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re8_v, rv_op_vl4re8_v, 0 },
1782     { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re16_v, rv_op_vl4re16_v, 0 },
1783     { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re32_v, rv_op_vl4re32_v, 0 },
1784     { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re64_v, rv_op_vl4re64_v, 0 },
1785     { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re8_v, rv_op_vl8re8_v, 0 },
1786     { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re16_v, rv_op_vl8re16_v, 0 },
1787     { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re32_v, rv_op_vl8re32_v, 0 },
1788     { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re64_v, rv_op_vl8re64_v, 0 },
1789     { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs1r_v, rv_op_vs1r_v, 0 },
1790     { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs2r_v, rv_op_vs2r_v, 0 },
1791     { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs4r_v, rv_op_vs4r_v, 0 },
1792     { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs8r_v, rv_op_vs8r_v, 0 },
1793     { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vadd_vv, rv_op_vadd_vv, 0 },
1794     { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vadd_vx, rv_op_vadd_vx, 0 },
1795     { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vadd_vi, rv_op_vadd_vi, 0 },
1796     { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsub_vv, rv_op_vsub_vv, 0 },
1797     { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsub_vx, rv_op_vsub_vx, 0 },
1798     { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrsub_vx, rv_op_vrsub_vx, 0 },
1799     { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vrsub_vi, rv_op_vrsub_vi, 0 },
1800     { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_vv, rv_op_vwaddu_vv, 0 },
1801     { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_vx, rv_op_vwaddu_vx, 0 },
1802     { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_vv, rv_op_vwadd_vv, 0 },
1803     { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_vx, rv_op_vwadd_vx, 0 },
1804     { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_vv, rv_op_vwsubu_vv, 0 },
1805     { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_vx, rv_op_vwsubu_vx, 0 },
1806     { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_vv, rv_op_vwsub_vv, 0 },
1807     { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_vx, rv_op_vwsub_vx, 0 },
1808     { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_wv, rv_op_vwaddu_wv, 0 },
1809     { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_wx, rv_op_vwaddu_wx, 0 },
1810     { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_wv, rv_op_vwadd_wv, 0 },
1811     { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_wx, rv_op_vwadd_wx, 0 },
1812     { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_wv, rv_op_vwsubu_wv, 0 },
1813     { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_wx, rv_op_vwsubu_wx, 0 },
1814     { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_wv, rv_op_vwsub_wv, 0 },
1815     { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_wx, rv_op_vwsub_wx, 0 },
1816     { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vadc_vvm, rv_op_vadc_vvm, 0 },
1817     { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vadc_vxm, rv_op_vadc_vxm, 0 },
1818     { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vadc_vim, rv_op_vadc_vim, 0 },
1819     { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmadc_vvm, rv_op_vmadc_vvm, 0 },
1820     { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmadc_vxm, rv_op_vmadc_vxm, 0 },
1821     { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmadc_vim, rv_op_vmadc_vim, 0 },
1822     { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vsbc_vvm, rv_op_vsbc_vvm, 0 },
1823     { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vsbc_vxm, rv_op_vsbc_vxm, 0 },
1824     { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmsbc_vvm, rv_op_vmsbc_vvm, 0 },
1825     { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmsbc_vxm, rv_op_vmsbc_vxm, 0 },
1826     { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vand_vv, rv_op_vand_vv, 0 },
1827     { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vand_vx, rv_op_vand_vx, 0 },
1828     { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vand_vi, rv_op_vand_vi, 0 },
1829     { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vor_vv, rv_op_vor_vv, 0 },
1830     { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vor_vx, rv_op_vor_vx, 0 },
1831     { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vor_vi, rv_op_vor_vi, 0 },
1832     { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vxor_vv, rv_op_vxor_vv, 0 },
1833     { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vxor_vx, rv_op_vxor_vx, 0 },
1834     { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vxor_vi, rv_op_vxor_vi, 0 },
1835     { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsll_vv, rv_op_vsll_vv, 0 },
1836     { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsll_vx, rv_op_vsll_vx, 0 },
1837     { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsll_vi, rv_op_vsll_vi, 0 },
1838     { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsrl_vv, rv_op_vsrl_vv, 0 },
1839     { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsrl_vx, rv_op_vsrl_vx, 0 },
1840     { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsrl_vi, rv_op_vsrl_vi, 0 },
1841     { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsra_vv, rv_op_vsra_vv, 0 },
1842     { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsra_vx, rv_op_vsra_vx, 0 },
1843     { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsra_vi, rv_op_vsra_vi, 0 },
1844     { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsrl_wv, rv_op_vnsrl_wv, 0 },
1845     { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsrl_wx, rv_op_vnsrl_wx, 0 },
1846     { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsrl_wi, rv_op_vnsrl_wi, 0 },
1847     { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsra_wv, rv_op_vnsra_wv, 0 },
1848     { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsra_wx, rv_op_vnsra_wx, 0 },
1849     { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsra_wi, rv_op_vnsra_wi, 0 },
1850     { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmseq_vv, rv_op_vmseq_vv, 0 },
1851     { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmseq_vx, rv_op_vmseq_vx, 0 },
1852     { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmseq_vi, rv_op_vmseq_vi, 0 },
1853     { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsne_vv, rv_op_vmsne_vv, 0 },
1854     { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsne_vx, rv_op_vmsne_vx, 0 },
1855     { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsne_vi, rv_op_vmsne_vi, 0 },
1856     { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsltu_vv, rv_op_vmsltu_vv, 0 },
1857     { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsltu_vx, rv_op_vmsltu_vx, 0 },
1858     { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmslt_vv, rv_op_vmslt_vv, 0 },
1859     { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmslt_vx, rv_op_vmslt_vx, 0 },
1860     { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsleu_vv, rv_op_vmsleu_vv, 0 },
1861     { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsleu_vx, rv_op_vmsleu_vx, 0 },
1862     { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsleu_vi, rv_op_vmsleu_vi, 0 },
1863     { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsle_vv, rv_op_vmsle_vv, 0 },
1864     { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsle_vx, rv_op_vmsle_vx, 0 },
1865     { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsle_vi, rv_op_vmsle_vi, 0 },
1866     { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgtu_vx, rv_op_vmsgtu_vx, 0 },
1867     { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgtu_vi, rv_op_vmsgtu_vi, 0 },
1868     { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgt_vx, rv_op_vmsgt_vx, 0 },
1869     { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgt_vi, rv_op_vmsgt_vi, 0 },
1870     { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vminu_vv, rv_op_vminu_vv, 0 },
1871     { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vminu_vx, rv_op_vminu_vx, 0 },
1872     { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmin_vv, rv_op_vmin_vv, 0 },
1873     { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmin_vx, rv_op_vmin_vx, 0 },
1874     { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmaxu_vv, rv_op_vmaxu_vv, 0 },
1875     { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmaxu_vx, rv_op_vmaxu_vx, 0 },
1876     { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmax_vv, rv_op_vmax_vv, 0 },
1877     { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmax_vx, rv_op_vmax_vx, 0 },
1878     { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmul_vv, rv_op_vmul_vv, 0 },
1879     { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmul_vx, rv_op_vmul_vx, 0 },
1880     { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulh_vv, rv_op_vmulh_vv, 0 },
1881     { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulh_vx, rv_op_vmulh_vx, 0 },
1882     { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhu_vv, rv_op_vmulhu_vv, 0 },
1883     { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhu_vx, rv_op_vmulhu_vx, 0 },
1884     { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhsu_vv, rv_op_vmulhsu_vv, 0 },
1885     { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhsu_vx, rv_op_vmulhsu_vx, 0 },
1886     { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdivu_vv, rv_op_vdivu_vv, 0 },
1887     { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdivu_vx, rv_op_vdivu_vx, 0 },
1888     { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdiv_vv, rv_op_vdiv_vv, 0 },
1889     { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdiv_vx, rv_op_vdiv_vx, 0 },
1890     { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vremu_vv, rv_op_vremu_vv, 0 },
1891     { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vremu_vx, rv_op_vremu_vx, 0 },
1892     { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrem_vv, rv_op_vrem_vv, 0 },
1893     { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrem_vx, rv_op_vrem_vx, 0 },
1894     { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulu_vv, rv_op_vwmulu_vv, 0 },
1895     { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulu_vx, rv_op_vwmulu_vx, 0 },
1896     { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulsu_vv, rv_op_vwmulsu_vv, 0 },
1897     { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulsu_vx, rv_op_vwmulsu_vx, 0 },
1898     { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmul_vv, rv_op_vwmul_vv, 0 },
1899     { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmul_vx, rv_op_vwmul_vx, 0 },
1900     { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmacc_vv, rv_op_vmacc_vv, 0 },
1901     { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmacc_vx, rv_op_vmacc_vx, 0 },
1902     { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsac_vv, rv_op_vnmsac_vv, 0 },
1903     { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsac_vx, rv_op_vnmsac_vx, 0 },
1904     { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmadd_vv, rv_op_vmadd_vv, 0 },
1905     { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmadd_vx, rv_op_vmadd_vx, 0 },
1906     { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsub_vv, rv_op_vnmsub_vv, 0 },
1907     { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsub_vx, rv_op_vnmsub_vx, 0 },
1908     { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccu_vv, rv_op_vwmaccu_vv, 0 },
1909     { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccu_vx, rv_op_vwmaccu_vx, 0 },
1910     { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmacc_vv, rv_op_vwmacc_vv, 0 },
1911     { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmacc_vx, rv_op_vwmacc_vx, 0 },
1912     { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccsu_vv, rv_op_vwmaccsu_vv, 0 },
1913     { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccsu_vx, rv_op_vwmaccsu_vx, 0 },
1914     { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccus_vx, rv_op_vwmaccus_vx, 0 },
1915     { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, rv_op_vmv_v_v, rv_op_vmv_v_v, 0 },
1916     { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_v_x, rv_op_vmv_v_x, 0 },
1917     { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, rv_op_vmv_v_i, rv_op_vmv_v_i, 0 },
1918     { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmerge_vvm, rv_op_vmerge_vvm, 0 },
1919     { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmerge_vxm, rv_op_vmerge_vxm, 0 },
1920     { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmerge_vim, rv_op_vmerge_vim, 0 },
1921     { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsaddu_vv, rv_op_vsaddu_vv, 0 },
1922     { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsaddu_vx, rv_op_vsaddu_vx, 0 },
1923     { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsaddu_vi, rv_op_vsaddu_vi, 0 },
1924     { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsadd_vv, rv_op_vsadd_vv, 0 },
1925     { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsadd_vx, rv_op_vsadd_vx, 0 },
1926     { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsadd_vi, rv_op_vsadd_vi, 0 },
1927     { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssubu_vv, rv_op_vssubu_vv, 0 },
1928     { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssubu_vx, rv_op_vssubu_vx, 0 },
1929     { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssub_vv, rv_op_vssub_vv, 0 },
1930     { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssub_vx, rv_op_vssub_vx, 0 },
1931     { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaadd_vv, rv_op_vaadd_vv, 0 },
1932     { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaadd_vx, rv_op_vaadd_vx, 0 },
1933     { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaaddu_vv, rv_op_vaaddu_vv, 0 },
1934     { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaaddu_vx, rv_op_vaaddu_vx, 0 },
1935     { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasub_vv, rv_op_vasub_vv, 0 },
1936     { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasub_vx, rv_op_vasub_vx, 0 },
1937     { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasubu_vv, rv_op_vasubu_vv, 0 },
1938     { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasubu_vx, rv_op_vasubu_vx, 0 },
1939     { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsmul_vv, rv_op_vsmul_vv, 0 },
1940     { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsmul_vx, rv_op_vsmul_vx, 0 },
1941     { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssrl_vv, rv_op_vssrl_vv, 0 },
1942     { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssrl_vx, rv_op_vssrl_vx, 0 },
1943     { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssrl_vi, rv_op_vssrl_vi, 0 },
1944     { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssra_vv, rv_op_vssra_vv, 0 },
1945     { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssra_vx, rv_op_vssra_vx, 0 },
1946     { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssra_vi, rv_op_vssra_vi, 0 },
1947     { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclipu_wv, rv_op_vnclipu_wv, 0 },
1948     { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclipu_wx, rv_op_vnclipu_wx, 0 },
1949     { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclipu_wi, rv_op_vnclipu_wi, 0 },
1950     { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclip_wv, rv_op_vnclip_wv, 0 },
1951     { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclip_wx, rv_op_vnclip_wx, 0 },
1952     { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclip_wi, rv_op_vnclip_wi, 0 },
1953     { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfadd_vv, rv_op_vfadd_vv, 0 },
1954     { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfadd_vf, rv_op_vfadd_vf, 0 },
1955     { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsub_vv, rv_op_vfsub_vv, 0 },
1956     { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsub_vf, rv_op_vfsub_vf, 0 },
1957     { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrsub_vf, rv_op_vfrsub_vf, 0 },
1958     { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_vv, rv_op_vfwadd_vv, 0 },
1959     { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_vf, rv_op_vfwadd_vf, 0 },
1960     { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_wv, rv_op_vfwadd_wv, 0 },
1961     { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_wf, rv_op_vfwadd_wf, 0 },
1962     { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_vv, rv_op_vfwsub_vv, 0 },
1963     { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_vf, rv_op_vfwsub_vf, 0 },
1964     { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_wv, rv_op_vfwsub_wv, 0 },
1965     { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_wf, rv_op_vfwsub_wf, 0 },
1966     { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmul_vv, rv_op_vfmul_vv, 0 },
1967     { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmul_vf, rv_op_vfmul_vf, 0 },
1968     { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfdiv_vv, rv_op_vfdiv_vv, 0 },
1969     { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfdiv_vf, rv_op_vfdiv_vf, 0 },
1970     { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrdiv_vf, rv_op_vfrdiv_vf, 0 },
1971     { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwmul_vv, rv_op_vfwmul_vv, 0 },
1972     { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwmul_vf, rv_op_vfwmul_vf, 0 },
1973     { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmacc_vv, rv_op_vfmacc_vv, 0 },
1974     { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmacc_vf, rv_op_vfmacc_vf, 0 },
1975     { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmacc_vv, rv_op_vfnmacc_vv, 0 },
1976     { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmacc_vf, rv_op_vfnmacc_vf, 0 },
1977     { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsac_vv, rv_op_vfmsac_vv, 0 },
1978     { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsac_vf, rv_op_vfmsac_vf, 0 },
1979     { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsac_vv, rv_op_vfnmsac_vv, 0 },
1980     { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsac_vf, rv_op_vfnmsac_vf, 0 },
1981     { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmadd_vv, rv_op_vfmadd_vv, 0 },
1982     { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmadd_vf, rv_op_vfmadd_vf, 0 },
1983     { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmadd_vv, rv_op_vfnmadd_vv, 0 },
1984     { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmadd_vf, rv_op_vfnmadd_vf, 0 },
1985     { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsub_vv, rv_op_vfmsub_vv, 0 },
1986     { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsub_vf, rv_op_vfmsub_vf, 0 },
1987     { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsub_vv, rv_op_vfnmsub_vv, 0 },
1988     { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsub_vf, rv_op_vfnmsub_vf, 0 },
1989     { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmacc_vv, rv_op_vfwmacc_vv, 0 },
1990     { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmacc_vf, rv_op_vfwmacc_vf, 0 },
1991     { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmacc_vv, rv_op_vfwnmacc_vv, 0 },
1992     { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmacc_vf, rv_op_vfwnmacc_vf, 0 },
1993     { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmsac_vv, rv_op_vfwmsac_vv, 0 },
1994     { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmsac_vf, rv_op_vfwmsac_vf, 0 },
1995     { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmsac_vv, rv_op_vfwnmsac_vv, 0 },
1996     { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmsac_vf, rv_op_vfwnmsac_vf, 0 },
1997     { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfsqrt_v, rv_op_vfsqrt_v, 0 },
1998     { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrsqrt7_v, rv_op_vfrsqrt7_v, 0 },
1999     { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrec7_v, rv_op_vfrec7_v, 0 },
2000     { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmin_vv, rv_op_vfmin_vv, 0 },
2001     { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmin_vf, rv_op_vfmin_vf, 0 },
2002     { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmax_vv, rv_op_vfmax_vv, 0 },
2003     { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmax_vf, rv_op_vfmax_vf, 0 },
2004     { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnj_vv, rv_op_vfsgnj_vv, 0 },
2005     { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnj_vf, rv_op_vfsgnj_vf, 0 },
2006     { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjn_vv, rv_op_vfsgnjn_vv, 0 },
2007     { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjn_vf, rv_op_vfsgnjn_vf, 0 },
2008     { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjx_vv, rv_op_vfsgnjx_vv, 0 },
2009     { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjx_vf, rv_op_vfsgnjx_vf, 0 },
2010     { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1up_vf, rv_op_vfslide1up_vf, 0 },
2011     { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1down_vf, rv_op_vfslide1down_vf, 0 },
2012     { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfeq_vv, rv_op_vmfeq_vv, 0 },
2013     { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfeq_vf, rv_op_vmfeq_vf, 0 },
2014     { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfne_vv, rv_op_vmfne_vv, 0 },
2015     { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfne_vf, rv_op_vmfne_vf, 0 },
2016     { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmflt_vv, rv_op_vmflt_vv, 0 },
2017     { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmflt_vf, rv_op_vmflt_vf, 0 },
2018     { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfle_vv, rv_op_vmfle_vv, 0 },
2019     { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfle_vf, rv_op_vmfle_vf, 0 },
2020     { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfgt_vf, rv_op_vmfgt_vf, 0 },
2021     { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfge_vf, rv_op_vmfge_vf, 0 },
2022     { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfclass_v, rv_op_vfclass_v, 0 },
2023     { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, rv_op_vfmerge_vfm, rv_op_vfmerge_vfm, 0 },
2024     { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_v_f, rv_op_vfmv_v_f, 0 },
2025     { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_xu_f_v, rv_op_vfcvt_xu_f_v, 0 },
2026     { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_x_f_v, rv_op_vfcvt_x_f_v, 0 },
2027     { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_xu_v, rv_op_vfcvt_f_xu_v, 0 },
2028     { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_x_v, rv_op_vfcvt_f_x_v, 0 },
2029     { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_xu_f_v, rv_op_vfcvt_rtz_xu_f_v, 0 },
2030     { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_x_f_v, rv_op_vfcvt_rtz_x_f_v, 0 },
2031     { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_xu_f_v, rv_op_vfwcvt_xu_f_v, 0 },
2032     { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_x_f_v, rv_op_vfwcvt_x_f_v, 0 },
2033     { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_xu_v, rv_op_vfwcvt_f_xu_v, 0 },
2034     { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_x_v, rv_op_vfwcvt_f_x_v, 0 },
2035     { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_f_v, rv_op_vfwcvt_f_f_v, 0 },
2036     { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_xu_f_v, rv_op_vfwcvt_rtz_xu_f_v, 0 },
2037     { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_x_f_v, rv_op_vfwcvt_rtz_x_f_v, 0 },
2038     { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_xu_f_w, rv_op_vfncvt_xu_f_w, 0 },
2039     { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_x_f_w, rv_op_vfncvt_x_f_w, 0 },
2040     { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_xu_w, rv_op_vfncvt_f_xu_w, 0 },
2041     { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_x_w, rv_op_vfncvt_f_x_w, 0 },
2042     { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_f_w, rv_op_vfncvt_f_f_w, 0 },
2043     { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rod_f_f_w, rv_op_vfncvt_rod_f_f_w, 0 },
2044     { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_xu_f_w, rv_op_vfncvt_rtz_xu_f_w, 0 },
2045     { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_x_f_w, rv_op_vfncvt_rtz_x_f_w, 0 },
2046     { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredsum_vs, rv_op_vredsum_vs, 0 },
2047     { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredand_vs, rv_op_vredand_vs, 0 },
2048     { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredor_vs, rv_op_vredor_vs, 0 },
2049     { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredxor_vs, rv_op_vredxor_vs, 0 },
2050     { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredminu_vs, rv_op_vredminu_vs, 0 },
2051     { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmin_vs, rv_op_vredmin_vs, 0 },
2052     { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmaxu_vs, rv_op_vredmaxu_vs, 0 },
2053     { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmax_vs, rv_op_vredmax_vs, 0 },
2054     { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsumu_vs, rv_op_vwredsumu_vs, 0 },
2055     { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsum_vs, rv_op_vwredsum_vs, 0 },
2056     { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredusum_vs, rv_op_vfredusum_vs, 0 },
2057     { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredosum_vs, rv_op_vfredosum_vs, 0 },
2058     { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmin_vs, rv_op_vfredmin_vs, 0 },
2059     { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmax_vs, rv_op_vfredmax_vs, 0 },
2060     { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredusum_vs, rv_op_vfwredusum_vs, 0 },
2061     { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredosum_vs, rv_op_vfwredosum_vs, 0 },
2062     { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmand_mm, rv_op_vmand_mm, 0 },
2063     { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnand_mm, rv_op_vmnand_mm, 0 },
2064     { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmandn_mm, rv_op_vmandn_mm, 0 },
2065     { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxor_mm, rv_op_vmxor_mm, 0 },
2066     { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmor_mm, rv_op_vmor_mm, 0 },
2067     { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnor_mm, rv_op_vmnor_mm, 0 },
2068     { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmorn_mm, rv_op_vmorn_mm, 0 },
2069     { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxnor_mm, rv_op_vmxnor_mm, 0 },
2070     { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vcpop_m, rv_op_vcpop_m, 0 },
2071     { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vfirst_m, rv_op_vfirst_m, 0 },
2072     { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsbf_m, rv_op_vmsbf_m, 0 },
2073     { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsif_m, rv_op_vmsif_m, 0 },
2074     { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsof_m, rv_op_vmsof_m, 0 },
2075     { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_viota_m, rv_op_viota_m, 0 },
2076     { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, rv_op_vid_v, rv_op_vid_v, 0 },
2077     { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, rv_op_vmv_x_s, rv_op_vmv_x_s, 0 },
2078     { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_s_x, rv_op_vmv_s_x, 0 },
2079     { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, rv_op_vfmv_f_s, rv_op_vfmv_f_s, 0 },
2080     { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_s_f, rv_op_vfmv_s_f, 0 },
2081     { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslideup_vx, rv_op_vslideup_vx, 0 },
2082     { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslideup_vi, rv_op_vslideup_vi, 0 },
2083     { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1up_vx, rv_op_vslide1up_vx, 0 },
2084     { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslidedown_vx, rv_op_vslidedown_vx, 0 },
2085     { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslidedown_vi, rv_op_vslidedown_vi, 0 },
2086     { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1down_vx, rv_op_vslide1down_vx, 0 },
2087     { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgather_vv, rv_op_vrgather_vv, 0 },
2088     { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgatherei16_vv, rv_op_vrgatherei16_vv, 0 },
2089     { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrgather_vx, rv_op_vrgather_vx, 0 },
2090     { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vrgather_vi, rv_op_vrgather_vi, 0 },
2091     { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, rv_op_vcompress_vm, rv_op_vcompress_vm, 0 },
2092     { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv1r_v, rv_op_vmv1r_v, 0 },
2093     { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv2r_v, rv_op_vmv2r_v, 0 },
2094     { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv4r_v, rv_op_vmv4r_v, 0 },
2095     { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv8r_v, rv_op_vmv8r_v, 0 },
2096     { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf2, rv_op_vzext_vf2, 0 },
2097     { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf4, rv_op_vzext_vf4, 0 },
2098     { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf8, rv_op_vzext_vf8, 0 },
2099     { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf2, rv_op_vsext_vf2, 0 },
2100     { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf4, rv_op_vsext_vf4, 0 },
2101     { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 },
2102     { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 },
2103     { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 },
2104     { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 },
2105     { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2106     { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2107     { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2108     { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2109     { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2110     { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2111     { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 },
2112     { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2113     { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2114     { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2115     { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2116     { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2117     { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 },
2118     { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
2119     { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 },
2120     { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
2121     { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
2122     { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
2123     { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
2124     { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
2125     { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2126     { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2127 };
2128
2129 /* CSR names */
2130
2131 static const char *csr_name(int csrno)
2132 {
2133     switch (csrno) {
2134     case 0x0000: return "ustatus";
2135     case 0x0001: return "fflags";
2136     case 0x0002: return "frm";
2137     case 0x0003: return "fcsr";
2138     case 0x0004: return "uie";
2139     case 0x0005: return "utvec";
2140     case 0x0008: return "vstart";
2141     case 0x0009: return "vxsat";
2142     case 0x000a: return "vxrm";
2143     case 0x000f: return "vcsr";
2144     case 0x0015: return "seed";
2145     case 0x0017: return "jvt";
2146     case 0x0040: return "uscratch";
2147     case 0x0041: return "uepc";
2148     case 0x0042: return "ucause";
2149     case 0x0043: return "utval";
2150     case 0x0044: return "uip";
2151     case 0x0100: return "sstatus";
2152     case 0x0104: return "sie";
2153     case 0x0105: return "stvec";
2154     case 0x0106: return "scounteren";
2155     case 0x0140: return "sscratch";
2156     case 0x0141: return "sepc";
2157     case 0x0142: return "scause";
2158     case 0x0143: return "stval";
2159     case 0x0144: return "sip";
2160     case 0x0180: return "satp";
2161     case 0x0200: return "hstatus";
2162     case 0x0202: return "hedeleg";
2163     case 0x0203: return "hideleg";
2164     case 0x0204: return "hie";
2165     case 0x0205: return "htvec";
2166     case 0x0240: return "hscratch";
2167     case 0x0241: return "hepc";
2168     case 0x0242: return "hcause";
2169     case 0x0243: return "hbadaddr";
2170     case 0x0244: return "hip";
2171     case 0x0300: return "mstatus";
2172     case 0x0301: return "misa";
2173     case 0x0302: return "medeleg";
2174     case 0x0303: return "mideleg";
2175     case 0x0304: return "mie";
2176     case 0x0305: return "mtvec";
2177     case 0x0306: return "mcounteren";
2178     case 0x0320: return "mucounteren";
2179     case 0x0321: return "mscounteren";
2180     case 0x0322: return "mhcounteren";
2181     case 0x0323: return "mhpmevent3";
2182     case 0x0324: return "mhpmevent4";
2183     case 0x0325: return "mhpmevent5";
2184     case 0x0326: return "mhpmevent6";
2185     case 0x0327: return "mhpmevent7";
2186     case 0x0328: return "mhpmevent8";
2187     case 0x0329: return "mhpmevent9";
2188     case 0x032a: return "mhpmevent10";
2189     case 0x032b: return "mhpmevent11";
2190     case 0x032c: return "mhpmevent12";
2191     case 0x032d: return "mhpmevent13";
2192     case 0x032e: return "mhpmevent14";
2193     case 0x032f: return "mhpmevent15";
2194     case 0x0330: return "mhpmevent16";
2195     case 0x0331: return "mhpmevent17";
2196     case 0x0332: return "mhpmevent18";
2197     case 0x0333: return "mhpmevent19";
2198     case 0x0334: return "mhpmevent20";
2199     case 0x0335: return "mhpmevent21";
2200     case 0x0336: return "mhpmevent22";
2201     case 0x0337: return "mhpmevent23";
2202     case 0x0338: return "mhpmevent24";
2203     case 0x0339: return "mhpmevent25";
2204     case 0x033a: return "mhpmevent26";
2205     case 0x033b: return "mhpmevent27";
2206     case 0x033c: return "mhpmevent28";
2207     case 0x033d: return "mhpmevent29";
2208     case 0x033e: return "mhpmevent30";
2209     case 0x033f: return "mhpmevent31";
2210     case 0x0340: return "mscratch";
2211     case 0x0341: return "mepc";
2212     case 0x0342: return "mcause";
2213     case 0x0343: return "mtval";
2214     case 0x0344: return "mip";
2215     case 0x0380: return "mbase";
2216     case 0x0381: return "mbound";
2217     case 0x0382: return "mibase";
2218     case 0x0383: return "mibound";
2219     case 0x0384: return "mdbase";
2220     case 0x0385: return "mdbound";
2221     case 0x03a0: return "pmpcfg3";
2222     case 0x03b0: return "pmpaddr0";
2223     case 0x03b1: return "pmpaddr1";
2224     case 0x03b2: return "pmpaddr2";
2225     case 0x03b3: return "pmpaddr3";
2226     case 0x03b4: return "pmpaddr4";
2227     case 0x03b5: return "pmpaddr5";
2228     case 0x03b6: return "pmpaddr6";
2229     case 0x03b7: return "pmpaddr7";
2230     case 0x03b8: return "pmpaddr8";
2231     case 0x03b9: return "pmpaddr9";
2232     case 0x03ba: return "pmpaddr10";
2233     case 0x03bb: return "pmpaddr11";
2234     case 0x03bc: return "pmpaddr12";
2235     case 0x03bd: return "pmpaddr14";
2236     case 0x03be: return "pmpaddr13";
2237     case 0x03bf: return "pmpaddr15";
2238     case 0x0780: return "mtohost";
2239     case 0x0781: return "mfromhost";
2240     case 0x0782: return "mreset";
2241     case 0x0783: return "mipi";
2242     case 0x0784: return "miobase";
2243     case 0x07a0: return "tselect";
2244     case 0x07a1: return "tdata1";
2245     case 0x07a2: return "tdata2";
2246     case 0x07a3: return "tdata3";
2247     case 0x07b0: return "dcsr";
2248     case 0x07b1: return "dpc";
2249     case 0x07b2: return "dscratch";
2250     case 0x0b00: return "mcycle";
2251     case 0x0b01: return "mtime";
2252     case 0x0b02: return "minstret";
2253     case 0x0b03: return "mhpmcounter3";
2254     case 0x0b04: return "mhpmcounter4";
2255     case 0x0b05: return "mhpmcounter5";
2256     case 0x0b06: return "mhpmcounter6";
2257     case 0x0b07: return "mhpmcounter7";
2258     case 0x0b08: return "mhpmcounter8";
2259     case 0x0b09: return "mhpmcounter9";
2260     case 0x0b0a: return "mhpmcounter10";
2261     case 0x0b0b: return "mhpmcounter11";
2262     case 0x0b0c: return "mhpmcounter12";
2263     case 0x0b0d: return "mhpmcounter13";
2264     case 0x0b0e: return "mhpmcounter14";
2265     case 0x0b0f: return "mhpmcounter15";
2266     case 0x0b10: return "mhpmcounter16";
2267     case 0x0b11: return "mhpmcounter17";
2268     case 0x0b12: return "mhpmcounter18";
2269     case 0x0b13: return "mhpmcounter19";
2270     case 0x0b14: return "mhpmcounter20";
2271     case 0x0b15: return "mhpmcounter21";
2272     case 0x0b16: return "mhpmcounter22";
2273     case 0x0b17: return "mhpmcounter23";
2274     case 0x0b18: return "mhpmcounter24";
2275     case 0x0b19: return "mhpmcounter25";
2276     case 0x0b1a: return "mhpmcounter26";
2277     case 0x0b1b: return "mhpmcounter27";
2278     case 0x0b1c: return "mhpmcounter28";
2279     case 0x0b1d: return "mhpmcounter29";
2280     case 0x0b1e: return "mhpmcounter30";
2281     case 0x0b1f: return "mhpmcounter31";
2282     case 0x0b80: return "mcycleh";
2283     case 0x0b81: return "mtimeh";
2284     case 0x0b82: return "minstreth";
2285     case 0x0b83: return "mhpmcounter3h";
2286     case 0x0b84: return "mhpmcounter4h";
2287     case 0x0b85: return "mhpmcounter5h";
2288     case 0x0b86: return "mhpmcounter6h";
2289     case 0x0b87: return "mhpmcounter7h";
2290     case 0x0b88: return "mhpmcounter8h";
2291     case 0x0b89: return "mhpmcounter9h";
2292     case 0x0b8a: return "mhpmcounter10h";
2293     case 0x0b8b: return "mhpmcounter11h";
2294     case 0x0b8c: return "mhpmcounter12h";
2295     case 0x0b8d: return "mhpmcounter13h";
2296     case 0x0b8e: return "mhpmcounter14h";
2297     case 0x0b8f: return "mhpmcounter15h";
2298     case 0x0b90: return "mhpmcounter16h";
2299     case 0x0b91: return "mhpmcounter17h";
2300     case 0x0b92: return "mhpmcounter18h";
2301     case 0x0b93: return "mhpmcounter19h";
2302     case 0x0b94: return "mhpmcounter20h";
2303     case 0x0b95: return "mhpmcounter21h";
2304     case 0x0b96: return "mhpmcounter22h";
2305     case 0x0b97: return "mhpmcounter23h";
2306     case 0x0b98: return "mhpmcounter24h";
2307     case 0x0b99: return "mhpmcounter25h";
2308     case 0x0b9a: return "mhpmcounter26h";
2309     case 0x0b9b: return "mhpmcounter27h";
2310     case 0x0b9c: return "mhpmcounter28h";
2311     case 0x0b9d: return "mhpmcounter29h";
2312     case 0x0b9e: return "mhpmcounter30h";
2313     case 0x0b9f: return "mhpmcounter31h";
2314     case 0x0c00: return "cycle";
2315     case 0x0c01: return "time";
2316     case 0x0c02: return "instret";
2317     case 0x0c20: return "vl";
2318     case 0x0c21: return "vtype";
2319     case 0x0c22: return "vlenb";
2320     case 0x0c80: return "cycleh";
2321     case 0x0c81: return "timeh";
2322     case 0x0c82: return "instreth";
2323     case 0x0d00: return "scycle";
2324     case 0x0d01: return "stime";
2325     case 0x0d02: return "sinstret";
2326     case 0x0d80: return "scycleh";
2327     case 0x0d81: return "stimeh";
2328     case 0x0d82: return "sinstreth";
2329     case 0x0e00: return "hcycle";
2330     case 0x0e01: return "htime";
2331     case 0x0e02: return "hinstret";
2332     case 0x0e80: return "hcycleh";
2333     case 0x0e81: return "htimeh";
2334     case 0x0e82: return "hinstreth";
2335     case 0x0f11: return "mvendorid";
2336     case 0x0f12: return "marchid";
2337     case 0x0f13: return "mimpid";
2338     case 0x0f14: return "mhartid";
2339     default: return NULL;
2340     }
2341 }
2342
2343 /* decode opcode */
2344
2345 static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
2346 {
2347     rv_inst inst = dec->inst;
2348     rv_opcode op = rv_op_illegal;
2349     switch (((inst >> 0) & 0b11)) {
2350     case 0:
2351         switch (((inst >> 13) & 0b111)) {
2352         case 0: op = rv_op_c_addi4spn; break;
2353         case 1:
2354             if (isa == rv128) {
2355                 op = rv_op_c_lq;
2356             } else {
2357                 op = rv_op_c_fld;
2358             }
2359             break;
2360         case 2: op = rv_op_c_lw; break;
2361         case 3:
2362             if (isa == rv32) {
2363                 op = rv_op_c_flw;
2364             } else {
2365                 op = rv_op_c_ld;
2366             }
2367             break;
2368         case 4:
2369             switch ((inst >> 10) & 0b111) {
2370             case 0: op = rv_op_c_lbu; break;
2371             case 1:
2372                 if (((inst >> 6) & 1) == 0) {
2373                     op = rv_op_c_lhu;
2374                 } else {
2375                     op = rv_op_c_lh;
2376                 }
2377                 break;
2378             case 2: op = rv_op_c_sb; break;
2379             case 3:
2380                 if (((inst >> 6) & 1) == 0) {
2381                     op = rv_op_c_sh;
2382                 }
2383                 break;
2384             }
2385             break;
2386         case 5:
2387             if (isa == rv128) {
2388                 op = rv_op_c_sq;
2389             } else {
2390                 op = rv_op_c_fsd;
2391             }
2392             break;
2393         case 6: op = rv_op_c_sw; break;
2394         case 7:
2395             if (isa == rv32) {
2396                 op = rv_op_c_fsw;
2397             } else {
2398                 op = rv_op_c_sd;
2399             }
2400             break;
2401         }
2402         break;
2403     case 1:
2404         switch (((inst >> 13) & 0b111)) {
2405         case 0:
2406             switch (((inst >> 2) & 0b11111111111)) {
2407             case 0: op = rv_op_c_nop; break;
2408             default: op = rv_op_c_addi; break;
2409             }
2410             break;
2411         case 1:
2412             if (isa == rv32) {
2413                 op = rv_op_c_jal;
2414             } else {
2415                 op = rv_op_c_addiw;
2416             }
2417             break;
2418         case 2: op = rv_op_c_li; break;
2419         case 3:
2420             switch (((inst >> 7) & 0b11111)) {
2421             case 2: op = rv_op_c_addi16sp; break;
2422             default: op = rv_op_c_lui; break;
2423             }
2424             break;
2425         case 4:
2426             switch (((inst >> 10) & 0b11)) {
2427             case 0:
2428                 op = rv_op_c_srli;
2429                 break;
2430             case 1:
2431                 op = rv_op_c_srai;
2432                 break;
2433             case 2: op = rv_op_c_andi; break;
2434             case 3:
2435                 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) {
2436                 case 0: op = rv_op_c_sub; break;
2437                 case 1: op = rv_op_c_xor; break;
2438                 case 2: op = rv_op_c_or; break;
2439                 case 3: op = rv_op_c_and; break;
2440                 case 4: op = rv_op_c_subw; break;
2441                 case 5: op = rv_op_c_addw; break;
2442                 case 6: op = rv_op_c_mul; break;
2443                 case 7:
2444                     switch ((inst >> 2) & 0b111) {
2445                     case 0: op = rv_op_c_zext_b; break;
2446                     case 1: op = rv_op_c_sext_b; break;
2447                     case 2: op = rv_op_c_zext_h; break;
2448                     case 3: op = rv_op_c_sext_h; break;
2449                     case 4: op = rv_op_c_zext_w; break;
2450                     case 5: op = rv_op_c_not; break;
2451                     }
2452                     break;
2453                 }
2454                 break;
2455             }
2456             break;
2457         case 5: op = rv_op_c_j; break;
2458         case 6: op = rv_op_c_beqz; break;
2459         case 7: op = rv_op_c_bnez; break;
2460         }
2461         break;
2462     case 2:
2463         switch (((inst >> 13) & 0b111)) {
2464         case 0:
2465             op = rv_op_c_slli;
2466             break;
2467         case 1:
2468             if (isa == rv128) {
2469                 op = rv_op_c_lqsp;
2470             } else {
2471                 op = rv_op_c_fldsp;
2472             }
2473             break;
2474         case 2: op = rv_op_c_lwsp; break;
2475         case 3:
2476             if (isa == rv32) {
2477                 op = rv_op_c_flwsp;
2478             } else {
2479                 op = rv_op_c_ldsp;
2480             }
2481             break;
2482         case 4:
2483             switch (((inst >> 12) & 0b1)) {
2484             case 0:
2485                 switch (((inst >> 2) & 0b11111)) {
2486                 case 0: op = rv_op_c_jr; break;
2487                 default: op = rv_op_c_mv; break;
2488                 }
2489                 break;
2490             case 1:
2491                 switch (((inst >> 2) & 0b11111)) {
2492                 case 0:
2493                     switch (((inst >> 7) & 0b11111)) {
2494                     case 0: op = rv_op_c_ebreak; break;
2495                     default: op = rv_op_c_jalr; break;
2496                     }
2497                     break;
2498                 default: op = rv_op_c_add; break;
2499                 }
2500                 break;
2501             }
2502             break;
2503         case 5:
2504             if (isa == rv128) {
2505                 op = rv_op_c_sqsp;
2506             } else {
2507                 op = rv_op_c_fsdsp;
2508                 if (((inst >> 12) & 0b01)) {
2509                     switch ((inst >> 8) & 0b01111) {
2510                     case 8:
2511                         if (((inst >> 4) & 0b01111) >= 4) {
2512                             op = rv_op_cm_push;
2513                         }
2514                         break;
2515                     case 10:
2516                         if (((inst >> 4) & 0b01111) >= 4) {
2517                             op = rv_op_cm_pop;
2518                         }
2519                         break;
2520                     case 12:
2521                         if (((inst >> 4) & 0b01111) >= 4) {
2522                             op = rv_op_cm_popretz;
2523                         }
2524                         break;
2525                     case 14:
2526                         if (((inst >> 4) & 0b01111) >= 4) {
2527                             op = rv_op_cm_popret;
2528                         }
2529                         break;
2530                     }
2531                 } else {
2532                     switch ((inst >> 10) & 0b011) {
2533                     case 0:
2534                         if (((inst >> 2) & 0xFF) >= 32) {
2535                             op = rv_op_cm_jalt;
2536                         } else {
2537                             op = rv_op_cm_jt;
2538                         }
2539                         break;
2540                     case 3:
2541                         switch ((inst >> 5) & 0b011) {
2542                         case 1: op = rv_op_cm_mvsa01; break;
2543                         case 3: op = rv_op_cm_mva01s; break;
2544                         }
2545                         break;
2546                     }
2547                 }
2548             }
2549             break;
2550         case 6: op = rv_op_c_swsp; break;
2551         case 7:
2552             if (isa == rv32) {
2553                 op = rv_op_c_fswsp;
2554             } else {
2555                 op = rv_op_c_sdsp;
2556             }
2557             break;
2558         }
2559         break;
2560     case 3:
2561         switch (((inst >> 2) & 0b11111)) {
2562         case 0:
2563             switch (((inst >> 12) & 0b111)) {
2564             case 0: op = rv_op_lb; break;
2565             case 1: op = rv_op_lh; break;
2566             case 2: op = rv_op_lw; break;
2567             case 3: op = rv_op_ld; break;
2568             case 4: op = rv_op_lbu; break;
2569             case 5: op = rv_op_lhu; break;
2570             case 6: op = rv_op_lwu; break;
2571             case 7: op = rv_op_ldu; break;
2572             }
2573             break;
2574         case 1:
2575             switch (((inst >> 12) & 0b111)) {
2576             case 0:
2577                 switch (((inst >> 20) & 0b111111111111)) {
2578                 case 40: op = rv_op_vl1re8_v; break;
2579                 case 552: op = rv_op_vl2re8_v; break;
2580                 case 1576: op = rv_op_vl4re8_v; break;
2581                 case 3624: op = rv_op_vl8re8_v; break;
2582                 }
2583                 switch (((inst >> 26) & 0b111)) {
2584                 case 0:
2585                     switch (((inst >> 20) & 0b11111)) {
2586                     case 0: op = rv_op_vle8_v; break;
2587                     case 11: op = rv_op_vlm_v; break;
2588                     case 16: op = rv_op_vle8ff_v; break;
2589                     }
2590                     break;
2591                 case 1: op = rv_op_vluxei8_v; break;
2592                 case 2: op = rv_op_vlse8_v; break;
2593                 case 3: op = rv_op_vloxei8_v; break;
2594                 }
2595                 break;
2596             case 2: op = rv_op_flw; break;
2597             case 3: op = rv_op_fld; break;
2598             case 4: op = rv_op_flq; break;
2599             case 5:
2600                 switch (((inst >> 20) & 0b111111111111)) {
2601                 case 40: op = rv_op_vl1re16_v; break;
2602                 case 552: op = rv_op_vl2re16_v; break;
2603                 case 1576: op = rv_op_vl4re16_v; break;
2604                 case 3624: op = rv_op_vl8re16_v; break;
2605                 }
2606                 switch (((inst >> 26) & 0b111)) {
2607                 case 0:
2608                     switch (((inst >> 20) & 0b11111)) {
2609                     case 0: op = rv_op_vle16_v; break;
2610                     case 16: op = rv_op_vle16ff_v; break;
2611                     }
2612                     break;
2613                 case 1: op = rv_op_vluxei16_v; break;
2614                 case 2: op = rv_op_vlse16_v; break;
2615                 case 3: op = rv_op_vloxei16_v; break;
2616                 }
2617                 break;
2618             case 6:
2619                 switch (((inst >> 20) & 0b111111111111)) {
2620                 case 40: op = rv_op_vl1re32_v; break;
2621                 case 552: op = rv_op_vl2re32_v; break;
2622                 case 1576: op = rv_op_vl4re32_v; break;
2623                 case 3624: op = rv_op_vl8re32_v; break;
2624                 }
2625                 switch (((inst >> 26) & 0b111)) {
2626                 case 0:
2627                     switch (((inst >> 20) & 0b11111)) {
2628                     case 0: op = rv_op_vle32_v; break;
2629                     case 16: op = rv_op_vle32ff_v; break;
2630                     }
2631                     break;
2632                 case 1: op = rv_op_vluxei32_v; break;
2633                 case 2: op = rv_op_vlse32_v; break;
2634                 case 3: op = rv_op_vloxei32_v; break;
2635                 }
2636                 break;
2637             case 7:
2638                 switch (((inst >> 20) & 0b111111111111)) {
2639                 case 40: op = rv_op_vl1re64_v; break;
2640                 case 552: op = rv_op_vl2re64_v; break;
2641                 case 1576: op = rv_op_vl4re64_v; break;
2642                 case 3624: op = rv_op_vl8re64_v; break;
2643                 }
2644                 switch (((inst >> 26) & 0b111)) {
2645                 case 0:
2646                     switch (((inst >> 20) & 0b11111)) {
2647                     case 0: op = rv_op_vle64_v; break;
2648                     case 16: op = rv_op_vle64ff_v; break;
2649                     }
2650                     break;
2651                 case 1: op = rv_op_vluxei64_v; break;
2652                 case 2: op = rv_op_vlse64_v; break;
2653                 case 3: op = rv_op_vloxei64_v; break;
2654                 }
2655                 break;
2656             }
2657             break;
2658         case 3:
2659             switch (((inst >> 12) & 0b111)) {
2660             case 0: op = rv_op_fence; break;
2661             case 1: op = rv_op_fence_i; break;
2662             case 2: op = rv_op_lq; break;
2663             }
2664             break;
2665         case 4:
2666             switch (((inst >> 12) & 0b111)) {
2667             case 0: op = rv_op_addi; break;
2668             case 1:
2669                 switch (((inst >> 27) & 0b11111)) {
2670                 case 0b00000: op = rv_op_slli; break;
2671                 case 0b00001:
2672                     switch (((inst >> 20) & 0b1111111)) {
2673                     case 0b0001111: op = rv_op_zip; break;
2674                     }
2675                     break;
2676                 case 0b00010:
2677                     switch (((inst >> 20) & 0b1111111)) {
2678                     case 0b0000000: op = rv_op_sha256sum0; break;
2679                     case 0b0000001: op = rv_op_sha256sum1; break;
2680                     case 0b0000010: op = rv_op_sha256sig0; break;
2681                     case 0b0000011: op = rv_op_sha256sig1; break;
2682                     case 0b0000100: op = rv_op_sha512sum0; break;
2683                     case 0b0000101: op = rv_op_sha512sum1; break;
2684                     case 0b0000110: op = rv_op_sha512sig0; break;
2685                     case 0b0000111: op = rv_op_sha512sig1; break;
2686                     case 0b0001000: op = rv_op_sm3p0; break;
2687                     case 0b0001001: op = rv_op_sm3p1; break;
2688                     }
2689                     break;
2690                 case 0b00101: op = rv_op_bseti; break;
2691                 case 0b00110:
2692                     switch (((inst >> 20) & 0b1111111)) {
2693                     case 0b0000000: op = rv_op_aes64im; break;
2694                     default:
2695                         if (((inst >> 24) & 0b0111) == 0b001) {
2696                             op = rv_op_aes64ks1i;
2697                         }
2698                         break;
2699                      }
2700                      break;
2701                 case 0b01001: op = rv_op_bclri; break;
2702                 case 0b01101: op = rv_op_binvi; break;
2703                 case 0b01100:
2704                     switch (((inst >> 20) & 0b1111111)) {
2705                     case 0b0000000: op = rv_op_clz; break;
2706                     case 0b0000001: op = rv_op_ctz; break;
2707                     case 0b0000010: op = rv_op_cpop; break;
2708                       /* 0b0000011 */
2709                     case 0b0000100: op = rv_op_sext_b; break;
2710                     case 0b0000101: op = rv_op_sext_h; break;
2711                     }
2712                     break;
2713                 }
2714                 break;
2715             case 2: op = rv_op_slti; break;
2716             case 3: op = rv_op_sltiu; break;
2717             case 4: op = rv_op_xori; break;
2718             case 5:
2719                 switch (((inst >> 27) & 0b11111)) {
2720                 case 0b00000: op = rv_op_srli; break;
2721                 case 0b00001:
2722                     switch (((inst >> 20) & 0b1111111)) {
2723                     case 0b0001111: op = rv_op_unzip; break;
2724                     }
2725                     break;
2726                 case 0b00101: op = rv_op_orc_b; break;
2727                 case 0b01000: op = rv_op_srai; break;
2728                 case 0b01001: op = rv_op_bexti; break;
2729                 case 0b01100: op = rv_op_rori; break;
2730                 case 0b01101:
2731                     switch ((inst >> 20) & 0b1111111) {
2732                     case 0b0011000: op = rv_op_rev8; break;
2733                     case 0b0111000: op = rv_op_rev8; break;
2734                     case 0b0000111: op = rv_op_brev8; break;
2735                     }
2736                     break;
2737                 }
2738                 break;
2739             case 6: op = rv_op_ori; break;
2740             case 7: op = rv_op_andi; break;
2741             }
2742             break;
2743         case 5: op = rv_op_auipc; break;
2744         case 6:
2745             switch (((inst >> 12) & 0b111)) {
2746             case 0: op = rv_op_addiw; break;
2747             case 1:
2748                 switch (((inst >> 26) & 0b111111)) {
2749                 case 0: op = rv_op_slliw; break;
2750                 case 2: op = rv_op_slli_uw; break;
2751                 case 24:
2752                     switch ((inst >> 20) & 0b11111) {
2753                     case 0b00000: op = rv_op_clzw; break;
2754                     case 0b00001: op = rv_op_ctzw; break;
2755                     case 0b00010: op = rv_op_cpopw; break;
2756                     }
2757                     break;
2758                 }
2759                 break;
2760             case 5:
2761                 switch (((inst >> 25) & 0b1111111)) {
2762                 case 0: op = rv_op_srliw; break;
2763                 case 32: op = rv_op_sraiw; break;
2764                 case 48: op = rv_op_roriw; break;
2765                 }
2766                 break;
2767             }
2768             break;
2769         case 8:
2770             switch (((inst >> 12) & 0b111)) {
2771             case 0: op = rv_op_sb; break;
2772             case 1: op = rv_op_sh; break;
2773             case 2: op = rv_op_sw; break;
2774             case 3: op = rv_op_sd; break;
2775             case 4: op = rv_op_sq; break;
2776             }
2777             break;
2778         case 9:
2779             switch (((inst >> 12) & 0b111)) {
2780             case 0:
2781                 switch (((inst >> 20) & 0b111111111111)) {
2782                 case 40: op = rv_op_vs1r_v; break;
2783                 case 552: op = rv_op_vs2r_v; break;
2784                 case 1576: op = rv_op_vs4r_v; break;
2785                 case 3624: op = rv_op_vs8r_v; break;
2786                 }
2787                 switch (((inst >> 26) & 0b111)) {
2788                 case 0:
2789                     switch (((inst >> 20) & 0b11111)) {
2790                     case 0: op = rv_op_vse8_v; break;
2791                     case 11: op = rv_op_vsm_v; break;
2792                     }
2793                     break;
2794                 case 1: op = rv_op_vsuxei8_v; break;
2795                 case 2: op = rv_op_vsse8_v; break;
2796                 case 3: op = rv_op_vsoxei8_v; break;
2797                 }
2798                 break;
2799             case 2: op = rv_op_fsw; break;
2800             case 3: op = rv_op_fsd; break;
2801             case 4: op = rv_op_fsq; break;
2802             case 5:
2803                 switch (((inst >> 26) & 0b111)) {
2804                 case 0:
2805                     switch (((inst >> 20) & 0b11111)) {
2806                     case 0: op = rv_op_vse16_v; break;
2807                     }
2808                     break;
2809                 case 1: op = rv_op_vsuxei16_v; break;
2810                 case 2: op = rv_op_vsse16_v; break;
2811                 case 3: op = rv_op_vsoxei16_v; break;
2812                 }
2813                 break;
2814             case 6:
2815                 switch (((inst >> 26) & 0b111)) {
2816                 case 0:
2817                     switch (((inst >> 20) & 0b11111)) {
2818                     case 0: op = rv_op_vse32_v; break;
2819                     }
2820                     break;
2821                 case 1: op = rv_op_vsuxei32_v; break;
2822                 case 2: op = rv_op_vsse32_v; break;
2823                 case 3: op = rv_op_vsoxei32_v; break;
2824                 }
2825                 break;
2826             case 7:
2827                 switch (((inst >> 26) & 0b111)) {
2828                 case 0:
2829                     switch (((inst >> 20) & 0b11111)) {
2830                     case 0: op = rv_op_vse64_v; break;
2831                     }
2832                     break;
2833                 case 1: op = rv_op_vsuxei64_v; break;
2834                 case 2: op = rv_op_vsse64_v; break;
2835                 case 3: op = rv_op_vsoxei64_v; break;
2836                 }
2837                 break;
2838             }
2839             break;
2840         case 11:
2841             switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
2842             case 2: op = rv_op_amoadd_w; break;
2843             case 3: op = rv_op_amoadd_d; break;
2844             case 4: op = rv_op_amoadd_q; break;
2845             case 10: op = rv_op_amoswap_w; break;
2846             case 11: op = rv_op_amoswap_d; break;
2847             case 12: op = rv_op_amoswap_q; break;
2848             case 18:
2849                 switch (((inst >> 20) & 0b11111)) {
2850                 case 0: op = rv_op_lr_w; break;
2851                 }
2852                 break;
2853             case 19:
2854                 switch (((inst >> 20) & 0b11111)) {
2855                 case 0: op = rv_op_lr_d; break;
2856                 }
2857                 break;
2858             case 20:
2859                 switch (((inst >> 20) & 0b11111)) {
2860                 case 0: op = rv_op_lr_q; break;
2861                 }
2862                 break;
2863             case 26: op = rv_op_sc_w; break;
2864             case 27: op = rv_op_sc_d; break;
2865             case 28: op = rv_op_sc_q; break;
2866             case 34: op = rv_op_amoxor_w; break;
2867             case 35: op = rv_op_amoxor_d; break;
2868             case 36: op = rv_op_amoxor_q; break;
2869             case 66: op = rv_op_amoor_w; break;
2870             case 67: op = rv_op_amoor_d; break;
2871             case 68: op = rv_op_amoor_q; break;
2872             case 98: op = rv_op_amoand_w; break;
2873             case 99: op = rv_op_amoand_d; break;
2874             case 100: op = rv_op_amoand_q; break;
2875             case 130: op = rv_op_amomin_w; break;
2876             case 131: op = rv_op_amomin_d; break;
2877             case 132: op = rv_op_amomin_q; break;
2878             case 162: op = rv_op_amomax_w; break;
2879             case 163: op = rv_op_amomax_d; break;
2880             case 164: op = rv_op_amomax_q; break;
2881             case 194: op = rv_op_amominu_w; break;
2882             case 195: op = rv_op_amominu_d; break;
2883             case 196: op = rv_op_amominu_q; break;
2884             case 226: op = rv_op_amomaxu_w; break;
2885             case 227: op = rv_op_amomaxu_d; break;
2886             case 228: op = rv_op_amomaxu_q; break;
2887             }
2888             break;
2889         case 12:
2890             switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
2891             case 0: op = rv_op_add; break;
2892             case 1: op = rv_op_sll; break;
2893             case 2: op = rv_op_slt; break;
2894             case 3: op = rv_op_sltu; break;
2895             case 4: op = rv_op_xor; break;
2896             case 5: op = rv_op_srl; break;
2897             case 6: op = rv_op_or; break;
2898             case 7: op = rv_op_and; break;
2899             case 8: op = rv_op_mul; break;
2900             case 9: op = rv_op_mulh; break;
2901             case 10: op = rv_op_mulhsu; break;
2902             case 11: op = rv_op_mulhu; break;
2903             case 12: op = rv_op_div; break;
2904             case 13: op = rv_op_divu; break;
2905             case 14: op = rv_op_rem; break;
2906             case 15: op = rv_op_remu; break;
2907             case 36:
2908                 switch ((inst >> 20) & 0b11111) {
2909                 case 0: op = rv_op_zext_h; break;
2910                 default: op = rv_op_pack; break;
2911                 }
2912                 break;
2913             case 39: op = rv_op_packh; break;
2914
2915             case 41: op = rv_op_clmul; break;
2916             case 42: op = rv_op_clmulr; break;
2917             case 43: op = rv_op_clmulh; break;
2918             case 44: op = rv_op_min; break;
2919             case 45: op = rv_op_minu; break;
2920             case 46: op = rv_op_max; break;
2921             case 47: op = rv_op_maxu; break;
2922             case 075: op = rv_op_czero_eqz; break;
2923             case 077: op = rv_op_czero_nez; break;
2924             case 130: op = rv_op_sh1add; break;
2925             case 132: op = rv_op_sh2add; break;
2926             case 134: op = rv_op_sh3add; break;
2927             case 161: op = rv_op_bset; break;
2928             case 162: op = rv_op_xperm4; break;
2929             case 164: op = rv_op_xperm8; break;
2930             case 200: op = rv_op_aes64es; break;
2931             case 216: op = rv_op_aes64esm; break;
2932             case 232: op = rv_op_aes64ds; break;
2933             case 248: op = rv_op_aes64dsm; break;
2934             case 256: op = rv_op_sub; break;
2935             case 260: op = rv_op_xnor; break;
2936             case 261: op = rv_op_sra; break;
2937             case 262: op = rv_op_orn; break;
2938             case 263: op = rv_op_andn; break;
2939             case 289: op = rv_op_bclr; break;
2940             case 293: op = rv_op_bext; break;
2941             case 320: op = rv_op_sha512sum0r; break;
2942             case 328: op = rv_op_sha512sum1r; break;
2943             case 336: op = rv_op_sha512sig0l; break;
2944             case 344: op = rv_op_sha512sig1l; break;
2945             case 368: op = rv_op_sha512sig0h; break;
2946             case 376: op = rv_op_sha512sig1h; break;
2947             case 385: op = rv_op_rol; break;
2948             case 389: op = rv_op_ror; break;
2949             case 417: op = rv_op_binv; break;
2950             case 504: op = rv_op_aes64ks2; break;
2951             }
2952             switch ((inst >> 25) & 0b0011111) {
2953             case 17: op = rv_op_aes32esi; break;
2954             case 19: op = rv_op_aes32esmi; break;
2955             case 21: op = rv_op_aes32dsi; break;
2956             case 23: op = rv_op_aes32dsmi; break;
2957             case 24: op = rv_op_sm4ed; break;
2958             case 26: op = rv_op_sm4ks; break;
2959             }
2960             break;
2961         case 13: op = rv_op_lui; break;
2962         case 14:
2963             switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
2964             case 0: op = rv_op_addw; break;
2965             case 1: op = rv_op_sllw; break;
2966             case 5: op = rv_op_srlw; break;
2967             case 8: op = rv_op_mulw; break;
2968             case 12: op = rv_op_divw; break;
2969             case 13: op = rv_op_divuw; break;
2970             case 14: op = rv_op_remw; break;
2971             case 15: op = rv_op_remuw; break;
2972             case 32: op = rv_op_add_uw; break;
2973             case 36:
2974                 switch ((inst >> 20) & 0b11111) {
2975                 case 0: op = rv_op_zext_h; break;
2976                 default: op = rv_op_packw; break;
2977                 }
2978                 break;
2979             case 130: op = rv_op_sh1add_uw; break;
2980             case 132: op = rv_op_sh2add_uw; break;
2981             case 134: op = rv_op_sh3add_uw; break;
2982             case 256: op = rv_op_subw; break;
2983             case 261: op = rv_op_sraw; break;
2984             case 385: op = rv_op_rolw; break;
2985             case 389: op = rv_op_rorw; break;
2986             }
2987             break;
2988         case 16:
2989             switch (((inst >> 25) & 0b11)) {
2990             case 0: op = rv_op_fmadd_s; break;
2991             case 1: op = rv_op_fmadd_d; break;
2992             case 3: op = rv_op_fmadd_q; break;
2993             }
2994             break;
2995         case 17:
2996             switch (((inst >> 25) & 0b11)) {
2997             case 0: op = rv_op_fmsub_s; break;
2998             case 1: op = rv_op_fmsub_d; break;
2999             case 3: op = rv_op_fmsub_q; break;
3000             }
3001             break;
3002         case 18:
3003             switch (((inst >> 25) & 0b11)) {
3004             case 0: op = rv_op_fnmsub_s; break;
3005             case 1: op = rv_op_fnmsub_d; break;
3006             case 3: op = rv_op_fnmsub_q; break;
3007             }
3008             break;
3009         case 19:
3010             switch (((inst >> 25) & 0b11)) {
3011             case 0: op = rv_op_fnmadd_s; break;
3012             case 1: op = rv_op_fnmadd_d; break;
3013             case 3: op = rv_op_fnmadd_q; break;
3014             }
3015             break;
3016         case 20:
3017             switch (((inst >> 25) & 0b1111111)) {
3018             case 0: op = rv_op_fadd_s; break;
3019             case 1: op = rv_op_fadd_d; break;
3020             case 3: op = rv_op_fadd_q; break;
3021             case 4: op = rv_op_fsub_s; break;
3022             case 5: op = rv_op_fsub_d; break;
3023             case 7: op = rv_op_fsub_q; break;
3024             case 8: op = rv_op_fmul_s; break;
3025             case 9: op = rv_op_fmul_d; break;
3026             case 11: op = rv_op_fmul_q; break;
3027             case 12: op = rv_op_fdiv_s; break;
3028             case 13: op = rv_op_fdiv_d; break;
3029             case 15: op = rv_op_fdiv_q; break;
3030             case 16:
3031                 switch (((inst >> 12) & 0b111)) {
3032                 case 0: op = rv_op_fsgnj_s; break;
3033                 case 1: op = rv_op_fsgnjn_s; break;
3034                 case 2: op = rv_op_fsgnjx_s; break;
3035                 }
3036                 break;
3037             case 17:
3038                 switch (((inst >> 12) & 0b111)) {
3039                 case 0: op = rv_op_fsgnj_d; break;
3040                 case 1: op = rv_op_fsgnjn_d; break;
3041                 case 2: op = rv_op_fsgnjx_d; break;
3042                 }
3043                 break;
3044             case 19:
3045                 switch (((inst >> 12) & 0b111)) {
3046                 case 0: op = rv_op_fsgnj_q; break;
3047                 case 1: op = rv_op_fsgnjn_q; break;
3048                 case 2: op = rv_op_fsgnjx_q; break;
3049                 }
3050                 break;
3051             case 20:
3052                 switch (((inst >> 12) & 0b111)) {
3053                 case 0: op = rv_op_fmin_s; break;
3054                 case 1: op = rv_op_fmax_s; break;
3055                 }
3056                 break;
3057             case 21:
3058                 switch (((inst >> 12) & 0b111)) {
3059                 case 0: op = rv_op_fmin_d; break;
3060                 case 1: op = rv_op_fmax_d; break;
3061                 }
3062                 break;
3063             case 23:
3064                 switch (((inst >> 12) & 0b111)) {
3065                 case 0: op = rv_op_fmin_q; break;
3066                 case 1: op = rv_op_fmax_q; break;
3067                 }
3068                 break;
3069             case 32:
3070                 switch (((inst >> 20) & 0b11111)) {
3071                 case 1: op = rv_op_fcvt_s_d; break;
3072                 case 3: op = rv_op_fcvt_s_q; break;
3073                 }
3074                 break;
3075             case 33:
3076                 switch (((inst >> 20) & 0b11111)) {
3077                 case 0: op = rv_op_fcvt_d_s; break;
3078                 case 3: op = rv_op_fcvt_d_q; break;
3079                 }
3080                 break;
3081             case 35:
3082                 switch (((inst >> 20) & 0b11111)) {
3083                 case 0: op = rv_op_fcvt_q_s; break;
3084                 case 1: op = rv_op_fcvt_q_d; break;
3085                 }
3086                 break;
3087             case 44:
3088                 switch (((inst >> 20) & 0b11111)) {
3089                 case 0: op = rv_op_fsqrt_s; break;
3090                 }
3091                 break;
3092             case 45:
3093                 switch (((inst >> 20) & 0b11111)) {
3094                 case 0: op = rv_op_fsqrt_d; break;
3095                 }
3096                 break;
3097             case 47:
3098                 switch (((inst >> 20) & 0b11111)) {
3099                 case 0: op = rv_op_fsqrt_q; break;
3100                 }
3101                 break;
3102             case 80:
3103                 switch (((inst >> 12) & 0b111)) {
3104                 case 0: op = rv_op_fle_s; break;
3105                 case 1: op = rv_op_flt_s; break;
3106                 case 2: op = rv_op_feq_s; break;
3107                 }
3108                 break;
3109             case 81:
3110                 switch (((inst >> 12) & 0b111)) {
3111                 case 0: op = rv_op_fle_d; break;
3112                 case 1: op = rv_op_flt_d; break;
3113                 case 2: op = rv_op_feq_d; break;
3114                 }
3115                 break;
3116             case 83:
3117                 switch (((inst >> 12) & 0b111)) {
3118                 case 0: op = rv_op_fle_q; break;
3119                 case 1: op = rv_op_flt_q; break;
3120                 case 2: op = rv_op_feq_q; break;
3121                 }
3122                 break;
3123             case 96:
3124                 switch (((inst >> 20) & 0b11111)) {
3125                 case 0: op = rv_op_fcvt_w_s; break;
3126                 case 1: op = rv_op_fcvt_wu_s; break;
3127                 case 2: op = rv_op_fcvt_l_s; break;
3128                 case 3: op = rv_op_fcvt_lu_s; break;
3129                 }
3130                 break;
3131             case 97:
3132                 switch (((inst >> 20) & 0b11111)) {
3133                 case 0: op = rv_op_fcvt_w_d; break;
3134                 case 1: op = rv_op_fcvt_wu_d; break;
3135                 case 2: op = rv_op_fcvt_l_d; break;
3136                 case 3: op = rv_op_fcvt_lu_d; break;
3137                 }
3138                 break;
3139             case 99:
3140                 switch (((inst >> 20) & 0b11111)) {
3141                 case 0: op = rv_op_fcvt_w_q; break;
3142                 case 1: op = rv_op_fcvt_wu_q; break;
3143                 case 2: op = rv_op_fcvt_l_q; break;
3144                 case 3: op = rv_op_fcvt_lu_q; break;
3145                 }
3146                 break;
3147             case 104:
3148                 switch (((inst >> 20) & 0b11111)) {
3149                 case 0: op = rv_op_fcvt_s_w; break;
3150                 case 1: op = rv_op_fcvt_s_wu; break;
3151                 case 2: op = rv_op_fcvt_s_l; break;
3152                 case 3: op = rv_op_fcvt_s_lu; break;
3153                 }
3154                 break;
3155             case 105:
3156                 switch (((inst >> 20) & 0b11111)) {
3157                 case 0: op = rv_op_fcvt_d_w; break;
3158                 case 1: op = rv_op_fcvt_d_wu; break;
3159                 case 2: op = rv_op_fcvt_d_l; break;
3160                 case 3: op = rv_op_fcvt_d_lu; break;
3161                 }
3162                 break;
3163             case 107:
3164                 switch (((inst >> 20) & 0b11111)) {
3165                 case 0: op = rv_op_fcvt_q_w; break;
3166                 case 1: op = rv_op_fcvt_q_wu; break;
3167                 case 2: op = rv_op_fcvt_q_l; break;
3168                 case 3: op = rv_op_fcvt_q_lu; break;
3169                 }
3170                 break;
3171             case 112:
3172                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3173                 case 0: op = rv_op_fmv_x_s; break;
3174                 case 1: op = rv_op_fclass_s; break;
3175                 }
3176                 break;
3177             case 113:
3178                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3179                 case 0: op = rv_op_fmv_x_d; break;
3180                 case 1: op = rv_op_fclass_d; break;
3181                 }
3182                 break;
3183             case 115:
3184                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3185                 case 0: op = rv_op_fmv_x_q; break;
3186                 case 1: op = rv_op_fclass_q; break;
3187                 }
3188                 break;
3189             case 120:
3190                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3191                 case 0: op = rv_op_fmv_s_x; break;
3192                 }
3193                 break;
3194             case 121:
3195                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3196                 case 0: op = rv_op_fmv_d_x; break;
3197                 }
3198                 break;
3199             case 123:
3200                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3201                 case 0: op = rv_op_fmv_q_x; break;
3202                 }
3203                 break;
3204             }
3205             break;
3206         case 21:
3207             switch (((inst >> 12) & 0b111)) {
3208             case 0:
3209                 switch (((inst >> 26) & 0b111111)) {
3210                 case 0: op = rv_op_vadd_vv; break;
3211                 case 2: op = rv_op_vsub_vv; break;
3212                 case 4: op = rv_op_vminu_vv; break;
3213                 case 5: op = rv_op_vmin_vv; break;
3214                 case 6: op = rv_op_vmaxu_vv; break;
3215                 case 7: op = rv_op_vmax_vv; break;
3216                 case 9: op = rv_op_vand_vv; break;
3217                 case 10: op = rv_op_vor_vv; break;
3218                 case 11: op = rv_op_vxor_vv; break;
3219                 case 12: op = rv_op_vrgather_vv; break;
3220                 case 14: op = rv_op_vrgatherei16_vv; break;
3221                 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vvm; break;
3222                 case 17: op = rv_op_vmadc_vvm; break;
3223                 case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vvm; break;
3224                 case 19: op = rv_op_vmsbc_vvm; break;
3225                 case 23:
3226                     if (((inst >> 20) & 0b111111) == 32)
3227                         op = rv_op_vmv_v_v;
3228                     else if (((inst >> 25) & 1) == 0)
3229                         op = rv_op_vmerge_vvm;
3230                     break;
3231                 case 24: op = rv_op_vmseq_vv; break;
3232                 case 25: op = rv_op_vmsne_vv; break;
3233                 case 26: op = rv_op_vmsltu_vv; break;
3234                 case 27: op = rv_op_vmslt_vv; break;
3235                 case 28: op = rv_op_vmsleu_vv; break;
3236                 case 29: op = rv_op_vmsle_vv; break;
3237                 case 32: op = rv_op_vsaddu_vv; break;
3238                 case 33: op = rv_op_vsadd_vv; break;
3239                 case 34: op = rv_op_vssubu_vv; break;
3240                 case 35: op = rv_op_vssub_vv; break;
3241                 case 37: op = rv_op_vsll_vv; break;
3242                 case 39: op = rv_op_vsmul_vv; break;
3243                 case 40: op = rv_op_vsrl_vv; break;
3244                 case 41: op = rv_op_vsra_vv; break;
3245                 case 42: op = rv_op_vssrl_vv; break;
3246                 case 43: op = rv_op_vssra_vv; break;
3247                 case 44: op = rv_op_vnsrl_wv; break;
3248                 case 45: op = rv_op_vnsra_wv; break;
3249                 case 46: op = rv_op_vnclipu_wv; break;
3250                 case 47: op = rv_op_vnclip_wv; break;
3251                 case 48: op = rv_op_vwredsumu_vs; break;
3252                 case 49: op = rv_op_vwredsum_vs; break;
3253                 }
3254                 break;
3255             case 1:
3256                 switch (((inst >> 26) & 0b111111)) {
3257                 case 0: op = rv_op_vfadd_vv; break;
3258                 case 1: op = rv_op_vfredusum_vs; break;
3259                 case 2: op = rv_op_vfsub_vv; break;
3260                 case 3: op = rv_op_vfredosum_vs; break;
3261                 case 4: op = rv_op_vfmin_vv; break;
3262                 case 5: op = rv_op_vfredmin_vs; break;
3263                 case 6: op = rv_op_vfmax_vv; break;
3264                 case 7: op = rv_op_vfredmax_vs; break;
3265                 case 8: op = rv_op_vfsgnj_vv; break;
3266                 case 9: op = rv_op_vfsgnjn_vv; break;
3267                 case 10: op = rv_op_vfsgnjx_vv; break;
3268                 case 16:
3269                     switch (((inst >> 15) & 0b11111)) {
3270                     case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break;
3271                     }
3272                     break;
3273                 case 18:
3274                     switch (((inst >> 15) & 0b11111)) {
3275                     case 0: op = rv_op_vfcvt_xu_f_v; break;
3276                     case 1: op = rv_op_vfcvt_x_f_v; break;
3277                     case 2: op = rv_op_vfcvt_f_xu_v; break;
3278                     case 3: op = rv_op_vfcvt_f_x_v; break;
3279                     case 6: op = rv_op_vfcvt_rtz_xu_f_v; break;
3280                     case 7: op = rv_op_vfcvt_rtz_x_f_v; break;
3281                     case 8: op = rv_op_vfwcvt_xu_f_v; break;
3282                     case 9: op = rv_op_vfwcvt_x_f_v; break;
3283                     case 10: op = rv_op_vfwcvt_f_xu_v; break;
3284                     case 11: op = rv_op_vfwcvt_f_x_v; break;
3285                     case 12: op = rv_op_vfwcvt_f_f_v; break;
3286                     case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
3287                     case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
3288                     case 16: op = rv_op_vfncvt_xu_f_w; break;
3289                     case 17: op = rv_op_vfncvt_x_f_w; break;
3290                     case 18: op = rv_op_vfncvt_f_xu_w; break;
3291                     case 19: op = rv_op_vfncvt_f_x_w; break;
3292                     case 20: op = rv_op_vfncvt_f_f_w; break;
3293                     case 21: op = rv_op_vfncvt_rod_f_f_w; break;
3294                     case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
3295                     case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
3296                     }
3297                     break;
3298                 case 19:
3299                     switch (((inst >> 15) & 0b11111)) {
3300                     case 0: op = rv_op_vfsqrt_v; break;
3301                     case 4: op = rv_op_vfrsqrt7_v; break;
3302                     case 5: op = rv_op_vfrec7_v; break;
3303                     case 16: op = rv_op_vfclass_v; break;
3304                     }
3305                     break;
3306                 case 24: op = rv_op_vmfeq_vv; break;
3307                 case 25: op = rv_op_vmfle_vv; break;
3308                 case 27: op = rv_op_vmflt_vv; break;
3309                 case 28: op = rv_op_vmfne_vv; break;
3310                 case 32: op = rv_op_vfdiv_vv; break;
3311                 case 36: op = rv_op_vfmul_vv; break;
3312                 case 40: op = rv_op_vfmadd_vv; break;
3313                 case 41: op = rv_op_vfnmadd_vv; break;
3314                 case 42: op = rv_op_vfmsub_vv; break;
3315                 case 43: op = rv_op_vfnmsub_vv; break;
3316                 case 44: op = rv_op_vfmacc_vv; break;
3317                 case 45: op = rv_op_vfnmacc_vv; break;
3318                 case 46: op = rv_op_vfmsac_vv; break;
3319                 case 47: op = rv_op_vfnmsac_vv; break;
3320                 case 48: op = rv_op_vfwadd_vv; break;
3321                 case 49: op = rv_op_vfwredusum_vs; break;
3322                 case 50: op = rv_op_vfwsub_vv; break;
3323                 case 51: op = rv_op_vfwredosum_vs; break;
3324                 case 52: op = rv_op_vfwadd_wv; break;
3325                 case 54: op = rv_op_vfwsub_wv; break;
3326                 case 56: op = rv_op_vfwmul_vv; break;
3327                 case 60: op = rv_op_vfwmacc_vv; break;
3328                 case 61: op = rv_op_vfwnmacc_vv; break;
3329                 case 62: op = rv_op_vfwmsac_vv; break;
3330                 case 63: op = rv_op_vfwnmsac_vv; break;
3331                 }
3332                 break;
3333             case 2:
3334                 switch (((inst >> 26) & 0b111111)) {
3335                 case 0: op = rv_op_vredsum_vs; break;
3336                 case 1: op = rv_op_vredand_vs; break;
3337                 case 2: op = rv_op_vredor_vs; break;
3338                 case 3: op = rv_op_vredxor_vs; break;
3339                 case 4: op = rv_op_vredminu_vs; break;
3340                 case 5: op = rv_op_vredmin_vs; break;
3341                 case 6: op = rv_op_vredmaxu_vs; break;
3342                 case 7: op = rv_op_vredmax_vs; break;
3343                 case 8: op = rv_op_vaaddu_vv; break;
3344                 case 9: op = rv_op_vaadd_vv; break;
3345                 case 10: op = rv_op_vasubu_vv; break;
3346                 case 11: op = rv_op_vasub_vv; break;
3347                 case 16:
3348                     switch (((inst >> 15) & 0b11111)) {
3349                     case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
3350                     case 16: op = rv_op_vcpop_m; break;
3351                     case 17: op = rv_op_vfirst_m; break;
3352                     }
3353                     break;
3354                 case 18:
3355                     switch (((inst >> 15) & 0b11111)) {
3356                     case 2: op = rv_op_vzext_vf8; break;
3357                     case 3: op = rv_op_vsext_vf8; break;
3358                     case 4: op = rv_op_vzext_vf4; break;
3359                     case 5: op = rv_op_vsext_vf4; break;
3360                     case 6: op = rv_op_vzext_vf2; break;
3361                     case 7: op = rv_op_vsext_vf2; break;
3362                     }
3363                     break;
3364                 case 20:
3365                     switch (((inst >> 15) & 0b11111)) {
3366                     case 1: op = rv_op_vmsbf_m;  break;
3367                     case 2: op = rv_op_vmsof_m; break;
3368                     case 3: op = rv_op_vmsif_m; break;
3369                     case 16: op = rv_op_viota_m; break;
3370                     case 17: if (((inst >> 20) & 0b11111) == 0) op = rv_op_vid_v; break;
3371                     }
3372                     break;
3373                 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
3374                 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break;
3375                 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break;
3376                 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break;
3377                 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break;
3378                 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break;
3379                 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break;
3380                 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break;
3381                 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break;
3382                 case 32: op = rv_op_vdivu_vv; break;
3383                 case 33: op = rv_op_vdiv_vv; break;
3384                 case 34: op = rv_op_vremu_vv; break;
3385                 case 35: op = rv_op_vrem_vv; break;
3386                 case 36: op = rv_op_vmulhu_vv; break;
3387                 case 37: op = rv_op_vmul_vv; break;
3388                 case 38: op = rv_op_vmulhsu_vv; break;
3389                 case 39: op = rv_op_vmulh_vv; break;
3390                 case 41: op = rv_op_vmadd_vv; break;
3391                 case 43: op = rv_op_vnmsub_vv; break;
3392                 case 45: op = rv_op_vmacc_vv; break;
3393                 case 47: op = rv_op_vnmsac_vv; break;
3394                 case 48: op = rv_op_vwaddu_vv; break;
3395                 case 49: op = rv_op_vwadd_vv; break;
3396                 case 50: op = rv_op_vwsubu_vv; break;
3397                 case 51: op = rv_op_vwsub_vv; break;
3398                 case 52: op = rv_op_vwaddu_wv; break;
3399                 case 53: op = rv_op_vwadd_wv; break;
3400                 case 54: op = rv_op_vwsubu_wv; break;
3401                 case 55: op = rv_op_vwsub_wv; break;
3402                 case 56: op = rv_op_vwmulu_vv; break;
3403                 case 58: op = rv_op_vwmulsu_vv; break;
3404                 case 59: op = rv_op_vwmul_vv; break;
3405                 case 60: op = rv_op_vwmaccu_vv; break;
3406                 case 61: op = rv_op_vwmacc_vv; break;
3407                 case 63: op = rv_op_vwmaccsu_vv; break;
3408                 }
3409                 break;
3410             case 3:
3411                 switch (((inst >> 26) & 0b111111)) {
3412                 case 0: op = rv_op_vadd_vi; break;
3413                 case 3: op = rv_op_vrsub_vi; break;
3414                 case 9: op = rv_op_vand_vi; break;
3415                 case 10: op = rv_op_vor_vi; break;
3416                 case 11: op = rv_op_vxor_vi; break;
3417                 case 12: op = rv_op_vrgather_vi; break;
3418                 case 14: op = rv_op_vslideup_vi; break;
3419                 case 15: op = rv_op_vslidedown_vi; break;
3420                 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vim; break;
3421                 case 17: op = rv_op_vmadc_vim; break;
3422                 case 23:
3423                     if (((inst >> 20) & 0b111111) == 32)
3424                         op = rv_op_vmv_v_i;
3425                     else if (((inst >> 25) & 1) == 0)
3426                         op = rv_op_vmerge_vim;
3427                     break;
3428                 case 24: op = rv_op_vmseq_vi; break;
3429                 case 25: op = rv_op_vmsne_vi; break;
3430                 case 28: op = rv_op_vmsleu_vi; break;
3431                 case 29: op = rv_op_vmsle_vi; break;
3432                 case 30: op = rv_op_vmsgtu_vi; break;
3433                 case 31: op = rv_op_vmsgt_vi; break;
3434                 case 32: op = rv_op_vsaddu_vi; break;
3435                 case 33: op = rv_op_vsadd_vi; break;
3436                 case 37: op = rv_op_vsll_vi; break;
3437                 case 39:
3438                     switch (((inst >> 15) & 0b11111)) {
3439                     case 0: op = rv_op_vmv1r_v; break;
3440                     case 1: op = rv_op_vmv2r_v; break;
3441                     case 3: op = rv_op_vmv4r_v; break;
3442                     case 7: op = rv_op_vmv8r_v; break;
3443                     }
3444                     break;
3445                 case 40: op = rv_op_vsrl_vi; break;
3446                 case 41: op = rv_op_vsra_vi; break;
3447                 case 42: op = rv_op_vssrl_vi; break;
3448                 case 43: op = rv_op_vssra_vi; break;
3449                 case 44: op = rv_op_vnsrl_wi; break;
3450                 case 45: op = rv_op_vnsra_wi; break;
3451                 case 46: op = rv_op_vnclipu_wi; break;
3452                 case 47: op = rv_op_vnclip_wi; break;
3453                 }
3454                 break;
3455             case 4:
3456                 switch (((inst >> 26) & 0b111111)) {
3457                 case 0: op = rv_op_vadd_vx; break;
3458                 case 2: op = rv_op_vsub_vx; break;
3459                 case 3: op = rv_op_vrsub_vx; break;
3460                 case 4: op = rv_op_vminu_vx; break;
3461                 case 5: op = rv_op_vmin_vx; break;
3462                 case 6: op = rv_op_vmaxu_vx; break;
3463                 case 7: op = rv_op_vmax_vx; break;
3464                 case 9: op = rv_op_vand_vx; break;
3465                 case 10: op = rv_op_vor_vx; break;
3466                 case 11: op = rv_op_vxor_vx; break;
3467                 case 12: op = rv_op_vrgather_vx; break;
3468                 case 14: op = rv_op_vslideup_vx; break;
3469                 case 15: op = rv_op_vslidedown_vx; break;
3470                 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vxm; break;
3471                 case 17: op = rv_op_vmadc_vxm; break;
3472                 case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vxm; break;
3473                 case 19: op = rv_op_vmsbc_vxm; break;
3474                 case 23:
3475                     if (((inst >> 20) & 0b111111) == 32)
3476                         op = rv_op_vmv_v_x;
3477                     else if (((inst >> 25) & 1) == 0)
3478                         op = rv_op_vmerge_vxm;
3479                     break;
3480                 case 24: op = rv_op_vmseq_vx; break;
3481                 case 25: op = rv_op_vmsne_vx; break;
3482                 case 26: op = rv_op_vmsltu_vx; break;
3483                 case 27: op = rv_op_vmslt_vx; break;
3484                 case 28: op = rv_op_vmsleu_vx; break;
3485                 case 29: op = rv_op_vmsle_vx; break;
3486                 case 30: op = rv_op_vmsgtu_vx; break;
3487                 case 31: op = rv_op_vmsgt_vx; break;
3488                 case 32: op = rv_op_vsaddu_vx; break;
3489                 case 33: op = rv_op_vsadd_vx; break;
3490                 case 34: op = rv_op_vssubu_vx; break;
3491                 case 35: op = rv_op_vssub_vx; break;
3492                 case 37: op = rv_op_vsll_vx; break;
3493                 case 39: op = rv_op_vsmul_vx; break;
3494                 case 40: op = rv_op_vsrl_vx; break;
3495                 case 41: op = rv_op_vsra_vx; break;
3496                 case 42: op = rv_op_vssrl_vx; break;
3497                 case 43: op = rv_op_vssra_vx; break;
3498                 case 44: op = rv_op_vnsrl_wx; break;
3499                 case 45: op = rv_op_vnsra_wx; break;
3500                 case 46: op = rv_op_vnclipu_wx; break;
3501                 case 47: op = rv_op_vnclip_wx; break;
3502                 }
3503                 break;
3504             case 5:
3505                 switch (((inst >> 26) & 0b111111)) {
3506                 case 0: op = rv_op_vfadd_vf; break;
3507                 case 2: op = rv_op_vfsub_vf; break;
3508                 case 4: op = rv_op_vfmin_vf; break;
3509                 case 6: op = rv_op_vfmax_vf; break;
3510                 case 8: op = rv_op_vfsgnj_vf; break;
3511                 case 9: op = rv_op_vfsgnjn_vf; break;
3512                 case 10: op = rv_op_vfsgnjx_vf; break;
3513                 case 14: op = rv_op_vfslide1up_vf; break;
3514                 case 15: op = rv_op_vfslide1down_vf; break;
3515                 case 16:
3516                     switch (((inst >> 20) & 0b11111)) {
3517                     case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break;
3518                     }
3519                     break;
3520                 case 23:
3521                     if (((inst >> 25) & 1) == 0)
3522                         op = rv_op_vfmerge_vfm;
3523                     else if (((inst >> 20) & 0b111111) == 32)
3524                         op = rv_op_vfmv_v_f;
3525                     break;
3526                 case 24: op = rv_op_vmfeq_vf; break;
3527                 case 25: op = rv_op_vmfle_vf; break;
3528                 case 27: op = rv_op_vmflt_vf; break;
3529                 case 28: op = rv_op_vmfne_vf; break;
3530                 case 29: op = rv_op_vmfgt_vf; break;
3531                 case 31: op = rv_op_vmfge_vf; break;
3532                 case 32: op = rv_op_vfdiv_vf; break;
3533                 case 33: op = rv_op_vfrdiv_vf; break;
3534                 case 36: op = rv_op_vfmul_vf; break;
3535                 case 39: op = rv_op_vfrsub_vf; break;
3536                 case 40: op = rv_op_vfmadd_vf; break;
3537                 case 41: op = rv_op_vfnmadd_vf; break;
3538                 case 42: op = rv_op_vfmsub_vf; break;
3539                 case 43: op = rv_op_vfnmsub_vf; break;
3540                 case 44: op = rv_op_vfmacc_vf; break;
3541                 case 45: op = rv_op_vfnmacc_vf; break;
3542                 case 46: op = rv_op_vfmsac_vf; break;
3543                 case 47: op = rv_op_vfnmsac_vf; break;
3544                 case 48: op = rv_op_vfwadd_vf; break;
3545                 case 50: op = rv_op_vfwsub_vf; break;
3546                 case 52: op = rv_op_vfwadd_wf; break;
3547                 case 54: op = rv_op_vfwsub_wf; break;
3548                 case 56: op = rv_op_vfwmul_vf; break;
3549                 case 60: op = rv_op_vfwmacc_vf; break;
3550                 case 61: op = rv_op_vfwnmacc_vf; break;
3551                 case 62: op = rv_op_vfwmsac_vf; break;
3552                 case 63: op = rv_op_vfwnmsac_vf; break;
3553                 }
3554                 break;
3555             case 6:
3556                 switch (((inst >> 26) & 0b111111)) {
3557                 case 8: op = rv_op_vaaddu_vx; break;
3558                 case 9: op = rv_op_vaadd_vx; break;
3559                 case 10: op = rv_op_vasubu_vx; break;
3560                 case 11: op = rv_op_vasub_vx; break;
3561                 case 14: op = rv_op_vslide1up_vx; break;
3562                 case 15: op = rv_op_vslide1down_vx; break;
3563                 case 16:
3564                     switch (((inst >> 20) & 0b11111)) {
3565                     case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break;
3566                     }
3567                     break;
3568                 case 32: op = rv_op_vdivu_vx; break;
3569                 case 33: op = rv_op_vdiv_vx; break;
3570                 case 34: op = rv_op_vremu_vx; break;
3571                 case 35: op = rv_op_vrem_vx; break;
3572                 case 36: op = rv_op_vmulhu_vx; break;
3573                 case 37: op = rv_op_vmul_vx; break;
3574                 case 38: op = rv_op_vmulhsu_vx; break;
3575                 case 39: op = rv_op_vmulh_vx; break;
3576                 case 41: op = rv_op_vmadd_vx; break;
3577                 case 43: op = rv_op_vnmsub_vx; break;
3578                 case 45: op = rv_op_vmacc_vx; break;
3579                 case 47: op = rv_op_vnmsac_vx; break;
3580                 case 48: op = rv_op_vwaddu_vx; break;
3581                 case 49: op = rv_op_vwadd_vx; break;
3582                 case 50: op = rv_op_vwsubu_vx; break;
3583                 case 51: op = rv_op_vwsub_vx; break;
3584                 case 52: op = rv_op_vwaddu_wx; break;
3585                 case 53: op = rv_op_vwadd_wx; break;
3586                 case 54: op = rv_op_vwsubu_wx; break;
3587                 case 55: op = rv_op_vwsub_wx; break;
3588                 case 56: op = rv_op_vwmulu_vx; break;
3589                 case 58: op = rv_op_vwmulsu_vx; break;
3590                 case 59: op = rv_op_vwmul_vx; break;
3591                 case 60: op = rv_op_vwmaccu_vx; break;
3592                 case 61: op = rv_op_vwmacc_vx; break;
3593                 case 62: op = rv_op_vwmaccus_vx; break;
3594                 case 63: op = rv_op_vwmaccsu_vx; break;
3595                 }
3596                 break;
3597             case 7:
3598                 if (((inst >> 31) & 1) == 0) {
3599                     op = rv_op_vsetvli;
3600                 } else if ((inst >> 30) & 1) {
3601                     op = rv_op_vsetivli;
3602                 } else if (((inst >> 25) & 0b11111) == 0) {
3603                     op = rv_op_vsetvl;
3604                 }
3605                 break;
3606             }
3607             break;
3608         case 22:
3609             switch (((inst >> 12) & 0b111)) {
3610             case 0: op = rv_op_addid; break;
3611             case 1:
3612                 switch (((inst >> 26) & 0b111111)) {
3613                 case 0: op = rv_op_sllid; break;
3614                 }
3615                 break;
3616             case 5:
3617                 switch (((inst >> 26) & 0b111111)) {
3618                 case 0: op = rv_op_srlid; break;
3619                 case 16: op = rv_op_sraid; break;
3620                 }
3621                 break;
3622             }
3623             break;
3624         case 24:
3625             switch (((inst >> 12) & 0b111)) {
3626             case 0: op = rv_op_beq; break;
3627             case 1: op = rv_op_bne; break;
3628             case 4: op = rv_op_blt; break;
3629             case 5: op = rv_op_bge; break;
3630             case 6: op = rv_op_bltu; break;
3631             case 7: op = rv_op_bgeu; break;
3632             }
3633             break;
3634         case 25:
3635             switch (((inst >> 12) & 0b111)) {
3636             case 0: op = rv_op_jalr; break;
3637             }
3638             break;
3639         case 27: op = rv_op_jal; break;
3640         case 28:
3641             switch (((inst >> 12) & 0b111)) {
3642             case 0:
3643                 switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) {
3644                 case 0:
3645                     switch (((inst >> 15) & 0b1111111111)) {
3646                     case 0: op = rv_op_ecall; break;
3647                     case 32: op = rv_op_ebreak; break;
3648                     case 64: op = rv_op_uret; break;
3649                     }
3650                     break;
3651                 case 256:
3652                     switch (((inst >> 20) & 0b11111)) {
3653                     case 2:
3654                         switch (((inst >> 15) & 0b11111)) {
3655                         case 0: op = rv_op_sret; break;
3656                         }
3657                         break;
3658                     case 4: op = rv_op_sfence_vm; break;
3659                     case 5:
3660                         switch (((inst >> 15) & 0b11111)) {
3661                         case 0: op = rv_op_wfi; break;
3662                         }
3663                         break;
3664                     }
3665                     break;
3666                 case 288: op = rv_op_sfence_vma; break;
3667                 case 512:
3668                     switch (((inst >> 15) & 0b1111111111)) {
3669                     case 64: op = rv_op_hret; break;
3670                     }
3671                     break;
3672                 case 768:
3673                     switch (((inst >> 15) & 0b1111111111)) {
3674                     case 64: op = rv_op_mret; break;
3675                     }
3676                     break;
3677                 case 1952:
3678                     switch (((inst >> 15) & 0b1111111111)) {
3679                     case 576: op = rv_op_dret; break;
3680                     }
3681                     break;
3682                 }
3683                 break;
3684             case 1: op = rv_op_csrrw; break;
3685             case 2: op = rv_op_csrrs; break;
3686             case 3: op = rv_op_csrrc; break;
3687             case 5: op = rv_op_csrrwi; break;
3688             case 6: op = rv_op_csrrsi; break;
3689             case 7: op = rv_op_csrrci; break;
3690             }
3691             break;
3692         case 30:
3693             switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
3694             case 0: op = rv_op_addd; break;
3695             case 1: op = rv_op_slld; break;
3696             case 5: op = rv_op_srld; break;
3697             case 8: op = rv_op_muld; break;
3698             case 12: op = rv_op_divd; break;
3699             case 13: op = rv_op_divud; break;
3700             case 14: op = rv_op_remd; break;
3701             case 15: op = rv_op_remud; break;
3702             case 256: op = rv_op_subd; break;
3703             case 261: op = rv_op_srad; break;
3704             }
3705             break;
3706         }
3707         break;
3708     }
3709     dec->op = op;
3710 }
3711
3712 /* operand extractors */
3713
3714 static uint32_t operand_rd(rv_inst inst)
3715 {
3716     return (inst << 52) >> 59;
3717 }
3718
3719 static uint32_t operand_rs1(rv_inst inst)
3720 {
3721     return (inst << 44) >> 59;
3722 }
3723
3724 static uint32_t operand_rs2(rv_inst inst)
3725 {
3726     return (inst << 39) >> 59;
3727 }
3728
3729 static uint32_t operand_rs3(rv_inst inst)
3730 {
3731     return (inst << 32) >> 59;
3732 }
3733
3734 static uint32_t operand_aq(rv_inst inst)
3735 {
3736     return (inst << 37) >> 63;
3737 }
3738
3739 static uint32_t operand_rl(rv_inst inst)
3740 {
3741     return (inst << 38) >> 63;
3742 }
3743
3744 static uint32_t operand_pred(rv_inst inst)
3745 {
3746     return (inst << 36) >> 60;
3747 }
3748
3749 static uint32_t operand_succ(rv_inst inst)
3750 {
3751     return (inst << 40) >> 60;
3752 }
3753
3754 static uint32_t operand_rm(rv_inst inst)
3755 {
3756     return (inst << 49) >> 61;
3757 }
3758
3759 static uint32_t operand_shamt5(rv_inst inst)
3760 {
3761     return (inst << 39) >> 59;
3762 }
3763
3764 static uint32_t operand_shamt6(rv_inst inst)
3765 {
3766     return (inst << 38) >> 58;
3767 }
3768
3769 static uint32_t operand_shamt7(rv_inst inst)
3770 {
3771     return (inst << 37) >> 57;
3772 }
3773
3774 static uint32_t operand_crdq(rv_inst inst)
3775 {
3776     return (inst << 59) >> 61;
3777 }
3778
3779 static uint32_t operand_crs1q(rv_inst inst)
3780 {
3781     return (inst << 54) >> 61;
3782 }
3783
3784 static uint32_t operand_crs1rdq(rv_inst inst)
3785 {
3786     return (inst << 54) >> 61;
3787 }
3788
3789 static uint32_t operand_crs2q(rv_inst inst)
3790 {
3791     return (inst << 59) >> 61;
3792 }
3793
3794 static uint32_t calculate_xreg(uint32_t sreg)
3795 {
3796     return sreg < 2 ? sreg + 8 : sreg + 16;
3797 }
3798
3799 static uint32_t operand_sreg1(rv_inst inst)
3800 {
3801     return calculate_xreg((inst << 54) >> 61);
3802 }
3803
3804 static uint32_t operand_sreg2(rv_inst inst)
3805 {
3806     return calculate_xreg((inst << 59) >> 61);
3807 }
3808
3809 static uint32_t operand_crd(rv_inst inst)
3810 {
3811     return (inst << 52) >> 59;
3812 }
3813
3814 static uint32_t operand_crs1(rv_inst inst)
3815 {
3816     return (inst << 52) >> 59;
3817 }
3818
3819 static uint32_t operand_crs1rd(rv_inst inst)
3820 {
3821     return (inst << 52) >> 59;
3822 }
3823
3824 static uint32_t operand_crs2(rv_inst inst)
3825 {
3826     return (inst << 57) >> 59;
3827 }
3828
3829 static uint32_t operand_cimmsh5(rv_inst inst)
3830 {
3831     return (inst << 57) >> 59;
3832 }
3833
3834 static uint32_t operand_csr12(rv_inst inst)
3835 {
3836     return (inst << 32) >> 52;
3837 }
3838
3839 static int32_t operand_imm12(rv_inst inst)
3840 {
3841     return ((int64_t)inst << 32) >> 52;
3842 }
3843
3844 static int32_t operand_imm20(rv_inst inst)
3845 {
3846     return (((int64_t)inst << 32) >> 44) << 12;
3847 }
3848
3849 static int32_t operand_jimm20(rv_inst inst)
3850 {
3851     return (((int64_t)inst << 32) >> 63) << 20 |
3852         ((inst << 33) >> 54) << 1 |
3853         ((inst << 43) >> 63) << 11 |
3854         ((inst << 44) >> 56) << 12;
3855 }
3856
3857 static int32_t operand_simm12(rv_inst inst)
3858 {
3859     return (((int64_t)inst << 32) >> 57) << 5 |
3860         (inst << 52) >> 59;
3861 }
3862
3863 static int32_t operand_sbimm12(rv_inst inst)
3864 {
3865     return (((int64_t)inst << 32) >> 63) << 12 |
3866         ((inst << 33) >> 58) << 5 |
3867         ((inst << 52) >> 60) << 1 |
3868         ((inst << 56) >> 63) << 11;
3869 }
3870
3871 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
3872 {
3873     int imm = ((inst << 51) >> 63) << 5 |
3874         (inst << 57) >> 59;
3875     if (isa == rv128) {
3876         imm = imm ? imm : 64;
3877     }
3878     return imm;
3879 }
3880
3881 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
3882 {
3883     int imm = ((inst << 51) >> 63) << 5 |
3884         (inst << 57) >> 59;
3885     if (isa == rv128) {
3886         imm = imm | (imm & 32) << 1;
3887         imm = imm ? imm : 64;
3888     }
3889     return imm;
3890 }
3891
3892 static int32_t operand_cimmi(rv_inst inst)
3893 {
3894     return (((int64_t)inst << 51) >> 63) << 5 |
3895         (inst << 57) >> 59;
3896 }
3897
3898 static int32_t operand_cimmui(rv_inst inst)
3899 {
3900     return (((int64_t)inst << 51) >> 63) << 17 |
3901         ((inst << 57) >> 59) << 12;
3902 }
3903
3904 static uint32_t operand_cimmlwsp(rv_inst inst)
3905 {
3906     return ((inst << 51) >> 63) << 5 |
3907         ((inst << 57) >> 61) << 2 |
3908         ((inst << 60) >> 62) << 6;
3909 }
3910
3911 static uint32_t operand_cimmldsp(rv_inst inst)
3912 {
3913     return ((inst << 51) >> 63) << 5 |
3914         ((inst << 57) >> 62) << 3 |
3915         ((inst << 59) >> 61) << 6;
3916 }
3917
3918 static uint32_t operand_cimmlqsp(rv_inst inst)
3919 {
3920     return ((inst << 51) >> 63) << 5 |
3921         ((inst << 57) >> 63) << 4 |
3922         ((inst << 58) >> 60) << 6;
3923 }
3924
3925 static int32_t operand_cimm16sp(rv_inst inst)
3926 {
3927     return (((int64_t)inst << 51) >> 63) << 9 |
3928         ((inst << 57) >> 63) << 4 |
3929         ((inst << 58) >> 63) << 6 |
3930         ((inst << 59) >> 62) << 7 |
3931         ((inst << 61) >> 63) << 5;
3932 }
3933
3934 static int32_t operand_cimmj(rv_inst inst)
3935 {
3936     return (((int64_t)inst << 51) >> 63) << 11 |
3937         ((inst << 52) >> 63) << 4 |
3938         ((inst << 53) >> 62) << 8 |
3939         ((inst << 55) >> 63) << 10 |
3940         ((inst << 56) >> 63) << 6 |
3941         ((inst << 57) >> 63) << 7 |
3942         ((inst << 58) >> 61) << 1 |
3943         ((inst << 61) >> 63) << 5;
3944 }
3945
3946 static int32_t operand_cimmb(rv_inst inst)
3947 {
3948     return (((int64_t)inst << 51) >> 63) << 8 |
3949         ((inst << 52) >> 62) << 3 |
3950         ((inst << 57) >> 62) << 6 |
3951         ((inst << 59) >> 62) << 1 |
3952         ((inst << 61) >> 63) << 5;
3953 }
3954
3955 static uint32_t operand_cimmswsp(rv_inst inst)
3956 {
3957     return ((inst << 51) >> 60) << 2 |
3958         ((inst << 55) >> 62) << 6;
3959 }
3960
3961 static uint32_t operand_cimmsdsp(rv_inst inst)
3962 {
3963     return ((inst << 51) >> 61) << 3 |
3964         ((inst << 54) >> 61) << 6;
3965 }
3966
3967 static uint32_t operand_cimmsqsp(rv_inst inst)
3968 {
3969     return ((inst << 51) >> 62) << 4 |
3970         ((inst << 53) >> 60) << 6;
3971 }
3972
3973 static uint32_t operand_cimm4spn(rv_inst inst)
3974 {
3975     return ((inst << 51) >> 62) << 4 |
3976         ((inst << 53) >> 60) << 6 |
3977         ((inst << 57) >> 63) << 2 |
3978         ((inst << 58) >> 63) << 3;
3979 }
3980
3981 static uint32_t operand_cimmw(rv_inst inst)
3982 {
3983     return ((inst << 51) >> 61) << 3 |
3984         ((inst << 57) >> 63) << 2 |
3985         ((inst << 58) >> 63) << 6;
3986 }
3987
3988 static uint32_t operand_cimmd(rv_inst inst)
3989 {
3990     return ((inst << 51) >> 61) << 3 |
3991         ((inst << 57) >> 62) << 6;
3992 }
3993
3994 static uint32_t operand_cimmq(rv_inst inst)
3995 {
3996     return ((inst << 51) >> 62) << 4 |
3997         ((inst << 53) >> 63) << 8 |
3998         ((inst << 57) >> 62) << 6;
3999 }
4000
4001 static uint32_t operand_vimm(rv_inst inst)
4002 {
4003     return (int64_t)(inst << 44) >> 59;
4004 }
4005
4006 static uint32_t operand_vzimm11(rv_inst inst)
4007 {
4008     return (inst << 33) >> 53;
4009 }
4010
4011 static uint32_t operand_vzimm10(rv_inst inst)
4012 {
4013     return (inst << 34) >> 54;
4014 }
4015
4016 static uint32_t operand_bs(rv_inst inst)
4017 {
4018     return (inst << 32) >> 62;
4019 }
4020
4021 static uint32_t operand_rnum(rv_inst inst)
4022 {
4023     return (inst << 40) >> 60;
4024 }
4025
4026 static uint32_t operand_vm(rv_inst inst)
4027 {
4028     return (inst << 38) >> 63;
4029 }
4030
4031 static uint32_t operand_uimm_c_lb(rv_inst inst)
4032 {
4033     return (((inst << 58) >> 63) << 1) |
4034         ((inst << 57) >> 63);
4035 }
4036
4037 static uint32_t operand_uimm_c_lh(rv_inst inst)
4038 {
4039     return (((inst << 58) >> 63) << 1);
4040 }
4041
4042 static uint32_t operand_zcmp_spimm(rv_inst inst)
4043 {
4044     return ((inst << 60) >> 62) << 4;
4045 }
4046
4047 static uint32_t operand_zcmp_rlist(rv_inst inst)
4048 {
4049     return ((inst << 56) >> 60);
4050 }
4051
4052 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
4053 {
4054     int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
4055     int regs = rlist == 15 ? 13 : rlist - 3;
4056     uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
4057     return stack_adj_base + spimm;
4058 }
4059
4060 static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
4061 {
4062     return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
4063                                operand_zcmp_spimm(inst));
4064 }
4065
4066 static uint32_t operand_tbl_index(rv_inst inst)
4067 {
4068     return ((inst << 54) >> 56);
4069 }
4070
4071 /* decode operands */
4072
4073 static void decode_inst_operands(rv_decode *dec, rv_isa isa)
4074 {
4075     rv_inst inst = dec->inst;
4076     dec->codec = opcode_data[dec->op].codec;
4077     switch (dec->codec) {
4078     case rv_codec_none:
4079         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4080         dec->imm = 0;
4081         break;
4082     case rv_codec_u:
4083         dec->rd = operand_rd(inst);
4084         dec->rs1 = dec->rs2 = rv_ireg_zero;
4085         dec->imm = operand_imm20(inst);
4086         break;
4087     case rv_codec_uj:
4088         dec->rd = operand_rd(inst);
4089         dec->rs1 = dec->rs2 = rv_ireg_zero;
4090         dec->imm = operand_jimm20(inst);
4091         break;
4092     case rv_codec_i:
4093         dec->rd = operand_rd(inst);
4094         dec->rs1 = operand_rs1(inst);
4095         dec->rs2 = rv_ireg_zero;
4096         dec->imm = operand_imm12(inst);
4097         break;
4098     case rv_codec_i_sh5:
4099         dec->rd = operand_rd(inst);
4100         dec->rs1 = operand_rs1(inst);
4101         dec->rs2 = rv_ireg_zero;
4102         dec->imm = operand_shamt5(inst);
4103         break;
4104     case rv_codec_i_sh6:
4105         dec->rd = operand_rd(inst);
4106         dec->rs1 = operand_rs1(inst);
4107         dec->rs2 = rv_ireg_zero;
4108         dec->imm = operand_shamt6(inst);
4109         break;
4110     case rv_codec_i_sh7:
4111         dec->rd = operand_rd(inst);
4112         dec->rs1 = operand_rs1(inst);
4113         dec->rs2 = rv_ireg_zero;
4114         dec->imm = operand_shamt7(inst);
4115         break;
4116     case rv_codec_i_csr:
4117         dec->rd = operand_rd(inst);
4118         dec->rs1 = operand_rs1(inst);
4119         dec->rs2 = rv_ireg_zero;
4120         dec->imm = operand_csr12(inst);
4121         break;
4122     case rv_codec_s:
4123         dec->rd = rv_ireg_zero;
4124         dec->rs1 = operand_rs1(inst);
4125         dec->rs2 = operand_rs2(inst);
4126         dec->imm = operand_simm12(inst);
4127         break;
4128     case rv_codec_sb:
4129         dec->rd = rv_ireg_zero;
4130         dec->rs1 = operand_rs1(inst);
4131         dec->rs2 = operand_rs2(inst);
4132         dec->imm = operand_sbimm12(inst);
4133         break;
4134     case rv_codec_r:
4135         dec->rd = operand_rd(inst);
4136         dec->rs1 = operand_rs1(inst);
4137         dec->rs2 = operand_rs2(inst);
4138         dec->imm = 0;
4139         break;
4140     case rv_codec_r_m:
4141         dec->rd = operand_rd(inst);
4142         dec->rs1 = operand_rs1(inst);
4143         dec->rs2 = operand_rs2(inst);
4144         dec->imm = 0;
4145         dec->rm = operand_rm(inst);
4146         break;
4147     case rv_codec_r4_m:
4148         dec->rd = operand_rd(inst);
4149         dec->rs1 = operand_rs1(inst);
4150         dec->rs2 = operand_rs2(inst);
4151         dec->rs3 = operand_rs3(inst);
4152         dec->imm = 0;
4153         dec->rm = operand_rm(inst);
4154         break;
4155     case rv_codec_r_a:
4156         dec->rd = operand_rd(inst);
4157         dec->rs1 = operand_rs1(inst);
4158         dec->rs2 = operand_rs2(inst);
4159         dec->imm = 0;
4160         dec->aq = operand_aq(inst);
4161         dec->rl = operand_rl(inst);
4162         break;
4163     case rv_codec_r_l:
4164         dec->rd = operand_rd(inst);
4165         dec->rs1 = operand_rs1(inst);
4166         dec->rs2 = rv_ireg_zero;
4167         dec->imm = 0;
4168         dec->aq = operand_aq(inst);
4169         dec->rl = operand_rl(inst);
4170         break;
4171     case rv_codec_r_f:
4172         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4173         dec->pred = operand_pred(inst);
4174         dec->succ = operand_succ(inst);
4175         dec->imm = 0;
4176         break;
4177     case rv_codec_cb:
4178         dec->rd = rv_ireg_zero;
4179         dec->rs1 = operand_crs1q(inst) + 8;
4180         dec->rs2 = rv_ireg_zero;
4181         dec->imm = operand_cimmb(inst);
4182         break;
4183     case rv_codec_cb_imm:
4184         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4185         dec->rs2 = rv_ireg_zero;
4186         dec->imm = operand_cimmi(inst);
4187         break;
4188     case rv_codec_cb_sh5:
4189         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4190         dec->rs2 = rv_ireg_zero;
4191         dec->imm = operand_cimmsh5(inst);
4192         break;
4193     case rv_codec_cb_sh6:
4194         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4195         dec->rs2 = rv_ireg_zero;
4196         dec->imm = operand_cimmshr6(inst, isa);
4197         break;
4198     case rv_codec_ci:
4199         dec->rd = dec->rs1 = operand_crs1rd(inst);
4200         dec->rs2 = rv_ireg_zero;
4201         dec->imm = operand_cimmi(inst);
4202         break;
4203     case rv_codec_ci_sh5:
4204         dec->rd = dec->rs1 = operand_crs1rd(inst);
4205         dec->rs2 = rv_ireg_zero;
4206         dec->imm = operand_cimmsh5(inst);
4207         break;
4208     case rv_codec_ci_sh6:
4209         dec->rd = dec->rs1 = operand_crs1rd(inst);
4210         dec->rs2 = rv_ireg_zero;
4211         dec->imm = operand_cimmshl6(inst, isa);
4212         break;
4213     case rv_codec_ci_16sp:
4214         dec->rd = rv_ireg_sp;
4215         dec->rs1 = rv_ireg_sp;
4216         dec->rs2 = rv_ireg_zero;
4217         dec->imm = operand_cimm16sp(inst);
4218         break;
4219     case rv_codec_ci_lwsp:
4220         dec->rd = operand_crd(inst);
4221         dec->rs1 = rv_ireg_sp;
4222         dec->rs2 = rv_ireg_zero;
4223         dec->imm = operand_cimmlwsp(inst);
4224         break;
4225     case rv_codec_ci_ldsp:
4226         dec->rd = operand_crd(inst);
4227         dec->rs1 = rv_ireg_sp;
4228         dec->rs2 = rv_ireg_zero;
4229         dec->imm = operand_cimmldsp(inst);
4230         break;
4231     case rv_codec_ci_lqsp:
4232         dec->rd = operand_crd(inst);
4233         dec->rs1 = rv_ireg_sp;
4234         dec->rs2 = rv_ireg_zero;
4235         dec->imm = operand_cimmlqsp(inst);
4236         break;
4237     case rv_codec_ci_li:
4238         dec->rd = operand_crd(inst);
4239         dec->rs1 = rv_ireg_zero;
4240         dec->rs2 = rv_ireg_zero;
4241         dec->imm = operand_cimmi(inst);
4242         break;
4243     case rv_codec_ci_lui:
4244         dec->rd = operand_crd(inst);
4245         dec->rs1 = rv_ireg_zero;
4246         dec->rs2 = rv_ireg_zero;
4247         dec->imm = operand_cimmui(inst);
4248         break;
4249     case rv_codec_ci_none:
4250         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4251         dec->imm = 0;
4252         break;
4253     case rv_codec_ciw_4spn:
4254         dec->rd = operand_crdq(inst) + 8;
4255         dec->rs1 = rv_ireg_sp;
4256         dec->rs2 = rv_ireg_zero;
4257         dec->imm = operand_cimm4spn(inst);
4258         break;
4259     case rv_codec_cj:
4260         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4261         dec->imm = operand_cimmj(inst);
4262         break;
4263     case rv_codec_cj_jal:
4264         dec->rd = rv_ireg_ra;
4265         dec->rs1 = dec->rs2 = rv_ireg_zero;
4266         dec->imm = operand_cimmj(inst);
4267         break;
4268     case rv_codec_cl_lw:
4269         dec->rd = operand_crdq(inst) + 8;
4270         dec->rs1 = operand_crs1q(inst) + 8;
4271         dec->rs2 = rv_ireg_zero;
4272         dec->imm = operand_cimmw(inst);
4273         break;
4274     case rv_codec_cl_ld:
4275         dec->rd = operand_crdq(inst) + 8;
4276         dec->rs1 = operand_crs1q(inst) + 8;
4277         dec->rs2 = rv_ireg_zero;
4278         dec->imm = operand_cimmd(inst);
4279         break;
4280     case rv_codec_cl_lq:
4281         dec->rd = operand_crdq(inst) + 8;
4282         dec->rs1 = operand_crs1q(inst) + 8;
4283         dec->rs2 = rv_ireg_zero;
4284         dec->imm = operand_cimmq(inst);
4285         break;
4286     case rv_codec_cr:
4287         dec->rd = dec->rs1 = operand_crs1rd(inst);
4288         dec->rs2 = operand_crs2(inst);
4289         dec->imm = 0;
4290         break;
4291     case rv_codec_cr_mv:
4292         dec->rd = operand_crd(inst);
4293         dec->rs1 = operand_crs2(inst);
4294         dec->rs2 = rv_ireg_zero;
4295         dec->imm = 0;
4296         break;
4297     case rv_codec_cr_jalr:
4298         dec->rd = rv_ireg_ra;
4299         dec->rs1 = operand_crs1(inst);
4300         dec->rs2 = rv_ireg_zero;
4301         dec->imm = 0;
4302         break;
4303     case rv_codec_cr_jr:
4304         dec->rd = rv_ireg_zero;
4305         dec->rs1 = operand_crs1(inst);
4306         dec->rs2 = rv_ireg_zero;
4307         dec->imm = 0;
4308         break;
4309     case rv_codec_cs:
4310         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4311         dec->rs2 = operand_crs2q(inst) + 8;
4312         dec->imm = 0;
4313         break;
4314     case rv_codec_cs_sw:
4315         dec->rd = rv_ireg_zero;
4316         dec->rs1 = operand_crs1q(inst) + 8;
4317         dec->rs2 = operand_crs2q(inst) + 8;
4318         dec->imm = operand_cimmw(inst);
4319         break;
4320     case rv_codec_cs_sd:
4321         dec->rd = rv_ireg_zero;
4322         dec->rs1 = operand_crs1q(inst) + 8;
4323         dec->rs2 = operand_crs2q(inst) + 8;
4324         dec->imm = operand_cimmd(inst);
4325         break;
4326     case rv_codec_cs_sq:
4327         dec->rd = rv_ireg_zero;
4328         dec->rs1 = operand_crs1q(inst) + 8;
4329         dec->rs2 = operand_crs2q(inst) + 8;
4330         dec->imm = operand_cimmq(inst);
4331         break;
4332     case rv_codec_css_swsp:
4333         dec->rd = rv_ireg_zero;
4334         dec->rs1 = rv_ireg_sp;
4335         dec->rs2 = operand_crs2(inst);
4336         dec->imm = operand_cimmswsp(inst);
4337         break;
4338     case rv_codec_css_sdsp:
4339         dec->rd = rv_ireg_zero;
4340         dec->rs1 = rv_ireg_sp;
4341         dec->rs2 = operand_crs2(inst);
4342         dec->imm = operand_cimmsdsp(inst);
4343         break;
4344     case rv_codec_css_sqsp:
4345         dec->rd = rv_ireg_zero;
4346         dec->rs1 = rv_ireg_sp;
4347         dec->rs2 = operand_crs2(inst);
4348         dec->imm = operand_cimmsqsp(inst);
4349         break;
4350     case rv_codec_k_bs:
4351         dec->rs1 = operand_rs1(inst);
4352         dec->rs2 = operand_rs2(inst);
4353         dec->bs = operand_bs(inst);
4354         break;
4355     case rv_codec_k_rnum:
4356         dec->rd = operand_rd(inst);
4357         dec->rs1 = operand_rs1(inst);
4358         dec->rnum = operand_rnum(inst);
4359         break;
4360     case rv_codec_v_r:
4361         dec->rd = operand_rd(inst);
4362         dec->rs1 = operand_rs1(inst);
4363         dec->rs2 = operand_rs2(inst);
4364         dec->vm = operand_vm(inst);
4365         break;
4366     case rv_codec_v_ldst:
4367         dec->rd = operand_rd(inst);
4368         dec->rs1 = operand_rs1(inst);
4369         dec->vm = operand_vm(inst);
4370         break;
4371     case rv_codec_v_i:
4372         dec->rd = operand_rd(inst);
4373         dec->rs2 = operand_rs2(inst);
4374         dec->imm = operand_vimm(inst);
4375         dec->vm = operand_vm(inst);
4376         break;
4377     case rv_codec_vsetvli:
4378         dec->rd = operand_rd(inst);
4379         dec->rs1 = operand_rs1(inst);
4380         dec->vzimm = operand_vzimm11(inst);
4381         break;
4382     case rv_codec_vsetivli:
4383         dec->rd = operand_rd(inst);
4384         dec->imm = operand_vimm(inst);
4385         dec->vzimm = operand_vzimm10(inst);
4386         break;
4387     case rv_codec_zcb_lb:
4388         dec->rs1 = operand_crs1q(inst) + 8;
4389         dec->rs2 = operand_crs2q(inst) + 8;
4390         dec->imm = operand_uimm_c_lb(inst);
4391         break;
4392     case rv_codec_zcb_lh:
4393         dec->rs1 = operand_crs1q(inst) + 8;
4394         dec->rs2 = operand_crs2q(inst) + 8;
4395         dec->imm = operand_uimm_c_lh(inst);
4396         break;
4397     case rv_codec_zcb_ext:
4398         dec->rd = operand_crs1q(inst) + 8;
4399         break;
4400     case rv_codec_zcb_mul:
4401         dec->rd = operand_crs1rdq(inst) + 8;
4402         dec->rs2 = operand_crs2q(inst) + 8;
4403         break;
4404     case rv_codec_zcmp_cm_pushpop:
4405         dec->imm = operand_zcmp_stack_adj(inst, isa);
4406         dec->rlist = operand_zcmp_rlist(inst);
4407         break;
4408     case rv_codec_zcmp_cm_mv:
4409         dec->rd = operand_sreg1(inst);
4410         dec->rs2 = operand_sreg2(inst);
4411         break;
4412     case rv_codec_zcmt_jt:
4413         dec->imm = operand_tbl_index(inst);
4414         break;
4415     };
4416 }
4417
4418 /* check constraint */
4419
4420 static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
4421 {
4422     int32_t imm = dec->imm;
4423     uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2;
4424     while (*c != rvc_end) {
4425         switch (*c) {
4426         case rvc_rd_eq_ra:
4427             if (!(rd == 1)) {
4428                 return false;
4429             }
4430             break;
4431         case rvc_rd_eq_x0:
4432             if (!(rd == 0)) {
4433                 return false;
4434             }
4435             break;
4436         case rvc_rs1_eq_x0:
4437             if (!(rs1 == 0)) {
4438                 return false;
4439             }
4440             break;
4441         case rvc_rs2_eq_x0:
4442             if (!(rs2 == 0)) {
4443                 return false;
4444             }
4445             break;
4446         case rvc_rs2_eq_rs1:
4447             if (!(rs2 == rs1)) {
4448                 return false;
4449             }
4450             break;
4451         case rvc_rs1_eq_ra:
4452             if (!(rs1 == 1)) {
4453                 return false;
4454             }
4455             break;
4456         case rvc_imm_eq_zero:
4457             if (!(imm == 0)) {
4458                 return false;
4459             }
4460             break;
4461         case rvc_imm_eq_n1:
4462             if (!(imm == -1)) {
4463                 return false;
4464             }
4465             break;
4466         case rvc_imm_eq_p1:
4467             if (!(imm == 1)) {
4468                 return false;
4469             }
4470             break;
4471         case rvc_csr_eq_0x001:
4472             if (!(imm == 0x001)) {
4473                 return false;
4474             }
4475             break;
4476         case rvc_csr_eq_0x002:
4477             if (!(imm == 0x002)) {
4478                 return false;
4479             }
4480             break;
4481         case rvc_csr_eq_0x003:
4482             if (!(imm == 0x003)) {
4483                 return false;
4484             }
4485             break;
4486         case rvc_csr_eq_0xc00:
4487             if (!(imm == 0xc00)) {
4488                 return false;
4489             }
4490             break;
4491         case rvc_csr_eq_0xc01:
4492             if (!(imm == 0xc01)) {
4493                 return false;
4494             }
4495             break;
4496         case rvc_csr_eq_0xc02:
4497             if (!(imm == 0xc02)) {
4498                 return false;
4499             }
4500             break;
4501         case rvc_csr_eq_0xc80:
4502             if (!(imm == 0xc80)) {
4503                 return false;
4504             }
4505             break;
4506         case rvc_csr_eq_0xc81:
4507             if (!(imm == 0xc81)) {
4508                 return false;
4509             }
4510             break;
4511         case rvc_csr_eq_0xc82:
4512             if (!(imm == 0xc82)) {
4513                 return false;
4514             }
4515             break;
4516         default: break;
4517         }
4518         c++;
4519     }
4520     return true;
4521 }
4522
4523 /* instruction length */
4524
4525 static size_t inst_length(rv_inst inst)
4526 {
4527     /* NOTE: supports maximum instruction size of 64-bits */
4528
4529     /* instruction length coding
4530      *
4531      *      aa - 16 bit aa != 11
4532      *   bbb11 - 32 bit bbb != 111
4533      *  011111 - 48 bit
4534      * 0111111 - 64 bit
4535      */
4536
4537     return (inst &      0b11) != 0b11      ? 2
4538          : (inst &   0b11100) != 0b11100   ? 4
4539          : (inst &  0b111111) == 0b011111  ? 6
4540          : (inst & 0b1111111) == 0b0111111 ? 8
4541          : 0;
4542 }
4543
4544 /* format instruction */
4545
4546 static void append(char *s1, const char *s2, size_t n)
4547 {
4548     size_t l1 = strlen(s1);
4549     if (n - l1 - 1 > 0) {
4550         strncat(s1, s2, n - l1);
4551     }
4552 }
4553
4554 static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
4555 {
4556     char tmp[64];
4557     const char *fmt;
4558
4559     fmt = opcode_data[dec->op].format;
4560     while (*fmt) {
4561         switch (*fmt) {
4562         case 'O':
4563             append(buf, opcode_data[dec->op].name, buflen);
4564             break;
4565         case '(':
4566             append(buf, "(", buflen);
4567             break;
4568         case ',':
4569             append(buf, ",", buflen);
4570             break;
4571         case ')':
4572             append(buf, ")", buflen);
4573             break;
4574         case '-':
4575             append(buf, "-", buflen);
4576             break;
4577         case 'b':
4578             snprintf(tmp, sizeof(tmp), "%d", dec->bs);
4579             append(buf, tmp, buflen);
4580             break;
4581         case 'n':
4582             snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
4583             append(buf, tmp, buflen);
4584             break;
4585         case '0':
4586             append(buf, rv_ireg_name_sym[dec->rd], buflen);
4587             break;
4588         case '1':
4589             append(buf, rv_ireg_name_sym[dec->rs1], buflen);
4590             break;
4591         case '2':
4592             append(buf, rv_ireg_name_sym[dec->rs2], buflen);
4593             break;
4594         case '3':
4595             append(buf, rv_freg_name_sym[dec->rd], buflen);
4596             break;
4597         case '4':
4598             append(buf, rv_freg_name_sym[dec->rs1], buflen);
4599             break;
4600         case '5':
4601             append(buf, rv_freg_name_sym[dec->rs2], buflen);
4602             break;
4603         case '6':
4604             append(buf, rv_freg_name_sym[dec->rs3], buflen);
4605             break;
4606         case '7':
4607             snprintf(tmp, sizeof(tmp), "%d", dec->rs1);
4608             append(buf, tmp, buflen);
4609             break;
4610         case 'i':
4611             snprintf(tmp, sizeof(tmp), "%d", dec->imm);
4612             append(buf, tmp, buflen);
4613             break;
4614         case 'u':
4615             snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111));
4616             append(buf, tmp, buflen);
4617             break;
4618         case 'o':
4619             snprintf(tmp, sizeof(tmp), "%d", dec->imm);
4620             append(buf, tmp, buflen);
4621             while (strlen(buf) < tab * 2) {
4622                 append(buf, " ", buflen);
4623             }
4624             snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64,
4625                 dec->pc + dec->imm);
4626             append(buf, tmp, buflen);
4627             break;
4628         case 'c': {
4629             const char *name = csr_name(dec->imm & 0xfff);
4630             if (name) {
4631                 append(buf, name, buflen);
4632             } else {
4633                 snprintf(tmp, sizeof(tmp), "0x%03x", dec->imm & 0xfff);
4634                 append(buf, tmp, buflen);
4635             }
4636             break;
4637         }
4638         case 'r':
4639             switch (dec->rm) {
4640             case rv_rm_rne:
4641                 append(buf, "rne", buflen);
4642                 break;
4643             case rv_rm_rtz:
4644                 append(buf, "rtz", buflen);
4645                 break;
4646             case rv_rm_rdn:
4647                 append(buf, "rdn", buflen);
4648                 break;
4649             case rv_rm_rup:
4650                 append(buf, "rup", buflen);
4651                 break;
4652             case rv_rm_rmm:
4653                 append(buf, "rmm", buflen);
4654                 break;
4655             case rv_rm_dyn:
4656                 append(buf, "dyn", buflen);
4657                 break;
4658             default:
4659                 append(buf, "inv", buflen);
4660                 break;
4661             }
4662             break;
4663         case 'p':
4664             if (dec->pred & rv_fence_i) {
4665                 append(buf, "i", buflen);
4666             }
4667             if (dec->pred & rv_fence_o) {
4668                 append(buf, "o", buflen);
4669             }
4670             if (dec->pred & rv_fence_r) {
4671                 append(buf, "r", buflen);
4672             }
4673             if (dec->pred & rv_fence_w) {
4674                 append(buf, "w", buflen);
4675             }
4676             break;
4677         case 's':
4678             if (dec->succ & rv_fence_i) {
4679                 append(buf, "i", buflen);
4680             }
4681             if (dec->succ & rv_fence_o) {
4682                 append(buf, "o", buflen);
4683             }
4684             if (dec->succ & rv_fence_r) {
4685                 append(buf, "r", buflen);
4686             }
4687             if (dec->succ & rv_fence_w) {
4688                 append(buf, "w", buflen);
4689             }
4690             break;
4691         case '\t':
4692             while (strlen(buf) < tab) {
4693                 append(buf, " ", buflen);
4694             }
4695             break;
4696         case 'A':
4697             if (dec->aq) {
4698                 append(buf, ".aq", buflen);
4699             }
4700             break;
4701         case 'R':
4702             if (dec->rl) {
4703                 append(buf, ".rl", buflen);
4704             }
4705             break;
4706         case 'l':
4707             append(buf, ",v0", buflen);
4708             break;
4709         case 'm':
4710             if (dec->vm == 0) {
4711                 append(buf, ",v0.t", buflen);
4712             }
4713             break;
4714         case 'D':
4715             append(buf, rv_vreg_name_sym[dec->rd], buflen);
4716             break;
4717         case 'E':
4718             append(buf, rv_vreg_name_sym[dec->rs1], buflen);
4719             break;
4720         case 'F':
4721             append(buf, rv_vreg_name_sym[dec->rs2], buflen);
4722             break;
4723         case 'G':
4724             append(buf, rv_vreg_name_sym[dec->rs3], buflen);
4725             break;
4726         case 'v': {
4727             char nbuf[32] = {0};
4728             const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3);
4729             sprintf(nbuf, "%d", sew);
4730             const int lmul = dec->vzimm & 0b11;
4731             const int flmul = (dec->vzimm >> 2) & 1;
4732             const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu";
4733             const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu";
4734             append(buf, "e", buflen);
4735             append(buf, nbuf, buflen);
4736             append(buf, ",m", buflen);
4737             if (flmul) {
4738                 switch (lmul) {
4739                 case 3:
4740                     sprintf(nbuf, "f2");
4741                     break;
4742                 case 2:
4743                     sprintf(nbuf, "f4");
4744                     break;
4745                 case 1:
4746                     sprintf(nbuf, "f8");
4747                 break;
4748                 }
4749                 append(buf, nbuf, buflen);
4750             } else {
4751                 sprintf(nbuf, "%d", 1 << lmul);
4752                 append(buf, nbuf, buflen);
4753             }
4754             append(buf, ",", buflen);
4755             append(buf, vta, buflen);
4756             append(buf, ",", buflen);
4757             append(buf, vma, buflen);
4758             break;
4759         }
4760         case 'x': {
4761             switch (dec->rlist) {
4762             case 4:
4763                 snprintf(tmp, sizeof(tmp), "{ra}");
4764                 break;
4765             case 5:
4766                 snprintf(tmp, sizeof(tmp), "{ra, s0}");
4767                 break;
4768             case 15:
4769                 snprintf(tmp, sizeof(tmp), "{ra, s0-s11}");
4770                 break;
4771             default:
4772                 snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5);
4773                 break;
4774             }
4775             append(buf, tmp, buflen);
4776             break;
4777         }
4778         default:
4779             break;
4780         }
4781         fmt++;
4782     }
4783 }
4784
4785 /* lift instruction to pseudo-instruction */
4786
4787 static void decode_inst_lift_pseudo(rv_decode *dec)
4788 {
4789     const rv_comp_data *comp_data = opcode_data[dec->op].pseudo;
4790     if (!comp_data) {
4791         return;
4792     }
4793     while (comp_data->constraints) {
4794         if (check_constraints(dec, comp_data->constraints)) {
4795             dec->op = comp_data->op;
4796             dec->codec = opcode_data[dec->op].codec;
4797             return;
4798         }
4799         comp_data++;
4800     }
4801 }
4802
4803 /* decompress instruction */
4804
4805 static void decode_inst_decompress_rv32(rv_decode *dec)
4806 {
4807     int decomp_op = opcode_data[dec->op].decomp_rv32;
4808     if (decomp_op != rv_op_illegal) {
4809         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4810             && dec->imm == 0) {
4811             dec->op = rv_op_illegal;
4812         } else {
4813             dec->op = decomp_op;
4814             dec->codec = opcode_data[decomp_op].codec;
4815         }
4816     }
4817 }
4818
4819 static void decode_inst_decompress_rv64(rv_decode *dec)
4820 {
4821     int decomp_op = opcode_data[dec->op].decomp_rv64;
4822     if (decomp_op != rv_op_illegal) {
4823         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4824             && dec->imm == 0) {
4825             dec->op = rv_op_illegal;
4826         } else {
4827             dec->op = decomp_op;
4828             dec->codec = opcode_data[decomp_op].codec;
4829         }
4830     }
4831 }
4832
4833 static void decode_inst_decompress_rv128(rv_decode *dec)
4834 {
4835     int decomp_op = opcode_data[dec->op].decomp_rv128;
4836     if (decomp_op != rv_op_illegal) {
4837         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4838             && dec->imm == 0) {
4839             dec->op = rv_op_illegal;
4840         } else {
4841             dec->op = decomp_op;
4842             dec->codec = opcode_data[decomp_op].codec;
4843         }
4844     }
4845 }
4846
4847 static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
4848 {
4849     switch (isa) {
4850     case rv32:
4851         decode_inst_decompress_rv32(dec);
4852         break;
4853     case rv64:
4854         decode_inst_decompress_rv64(dec);
4855         break;
4856     case rv128:
4857         decode_inst_decompress_rv128(dec);
4858         break;
4859     }
4860 }
4861
4862 /* disassemble instruction */
4863
4864 static void
4865 disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst,
4866             RISCVCPUConfig *cfg)
4867 {
4868     rv_decode dec = { 0 };
4869     dec.pc = pc;
4870     dec.inst = inst;
4871     dec.cfg = cfg;
4872     decode_inst_opcode(&dec, isa);
4873     decode_inst_operands(&dec, isa);
4874     decode_inst_decompress(&dec, isa);
4875     decode_inst_lift_pseudo(&dec);
4876     format_inst(buf, buflen, 24, &dec);
4877 }
4878
4879 #define INST_FMT_2 "%04" PRIx64 "              "
4880 #define INST_FMT_4 "%08" PRIx64 "          "
4881 #define INST_FMT_6 "%012" PRIx64 "      "
4882 #define INST_FMT_8 "%016" PRIx64 "  "
4883
4884 static int
4885 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
4886 {
4887     char buf[128] = { 0 };
4888     bfd_byte packet[2];
4889     rv_inst inst = 0;
4890     size_t len = 2;
4891     bfd_vma n;
4892     int status;
4893
4894     /* Instructions are made of 2-byte packets in little-endian order */
4895     for (n = 0; n < len; n += 2) {
4896         status = (*info->read_memory_func)(memaddr + n, packet, 2, info);
4897         if (status != 0) {
4898             /* Don't fail just because we fell off the end.  */
4899             if (n > 0) {
4900                 break;
4901             }
4902             (*info->memory_error_func)(status, memaddr, info);
4903             return status;
4904         }
4905         inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n);
4906         if (n == 0) {
4907             len = inst_length(inst);
4908         }
4909     }
4910
4911     switch (len) {
4912     case 2:
4913         (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
4914         break;
4915     case 4:
4916         (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
4917         break;
4918     case 6:
4919         (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
4920         break;
4921     default:
4922         (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
4923         break;
4924     }
4925
4926     disasm_inst(buf, sizeof(buf), isa, memaddr, inst,
4927                 (RISCVCPUConfig *)info->target_info);
4928     (*info->fprintf_func)(info->stream, "%s", buf);
4929
4930     return len;
4931 }
4932
4933 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info)
4934 {
4935     return print_insn_riscv(memaddr, info, rv32);
4936 }
4937
4938 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info)
4939 {
4940     return print_insn_riscv(memaddr, info, rv64);
4941 }
4942
4943 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info)
4944 {
4945     return print_insn_riscv(memaddr, info, rv128);
4946 }