disas/riscv.c

   1 /*
   2  * QEMU RISC-V Disassembler
   3  *
   4  * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com>
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "disas/dis-asm.h"
  22 #include "target/riscv/cpu_cfg.h"
  23 #include "disas/riscv.h"
  24
  25 /* Vendor extensions */
  26 #include "disas/riscv-xventana.h"
  27
  28 typedef enum {
  29     /* 0 is reserved for rv_op_illegal. */
  30     rv_op_lui = 1,
  31     rv_op_auipc = 2,
  32     rv_op_jal = 3,
  33     rv_op_jalr = 4,
  34     rv_op_beq = 5,
  35     rv_op_bne = 6,
  36     rv_op_blt = 7,
  37     rv_op_bge = 8,
  38     rv_op_bltu = 9,
  39     rv_op_bgeu = 10,
  40     rv_op_lb = 11,
  41     rv_op_lh = 12,
  42     rv_op_lw = 13,
  43     rv_op_lbu = 14,
  44     rv_op_lhu = 15,
  45     rv_op_sb = 16,
  46     rv_op_sh = 17,
  47     rv_op_sw = 18,
  48     rv_op_addi = 19,
  49     rv_op_slti = 20,
  50     rv_op_sltiu = 21,
  51     rv_op_xori = 22,
  52     rv_op_ori = 23,
  53     rv_op_andi = 24,
  54     rv_op_slli = 25,
  55     rv_op_srli = 26,
  56     rv_op_srai = 27,
  57     rv_op_add = 28,
  58     rv_op_sub = 29,
  59     rv_op_sll = 30,
  60     rv_op_slt = 31,
  61     rv_op_sltu = 32,
  62     rv_op_xor = 33,
  63     rv_op_srl = 34,
  64     rv_op_sra = 35,
  65     rv_op_or = 36,
  66     rv_op_and = 37,
  67     rv_op_fence = 38,
  68     rv_op_fence_i = 39,
  69     rv_op_lwu = 40,
  70     rv_op_ld = 41,
  71     rv_op_sd = 42,
  72     rv_op_addiw = 43,
  73     rv_op_slliw = 44,
  74     rv_op_srliw = 45,
  75     rv_op_sraiw = 46,
  76     rv_op_addw = 47,
  77     rv_op_subw = 48,
  78     rv_op_sllw = 49,
  79     rv_op_srlw = 50,
  80     rv_op_sraw = 51,
  81     rv_op_ldu = 52,
  82     rv_op_lq = 53,
  83     rv_op_sq = 54,
  84     rv_op_addid = 55,
  85     rv_op_sllid = 56,
  86     rv_op_srlid = 57,
  87     rv_op_sraid = 58,
  88     rv_op_addd = 59,
  89     rv_op_subd = 60,
  90     rv_op_slld = 61,
  91     rv_op_srld = 62,
  92     rv_op_srad = 63,
  93     rv_op_mul = 64,
  94     rv_op_mulh = 65,
  95     rv_op_mulhsu = 66,
  96     rv_op_mulhu = 67,
  97     rv_op_div = 68,
  98     rv_op_divu = 69,
  99     rv_op_rem = 70,
 100     rv_op_remu = 71,
 101     rv_op_mulw = 72,
 102     rv_op_divw = 73,
 103     rv_op_divuw = 74,
 104     rv_op_remw = 75,
 105     rv_op_remuw = 76,
 106     rv_op_muld = 77,
 107     rv_op_divd = 78,
 108     rv_op_divud = 79,
 109     rv_op_remd = 80,
 110     rv_op_remud = 81,
 111     rv_op_lr_w = 82,
 112     rv_op_sc_w = 83,
 113     rv_op_amoswap_w = 84,
 114     rv_op_amoadd_w = 85,
 115     rv_op_amoxor_w = 86,
 116     rv_op_amoor_w = 87,
 117     rv_op_amoand_w = 88,
 118     rv_op_amomin_w = 89,
 119     rv_op_amomax_w = 90,
 120     rv_op_amominu_w = 91,
 121     rv_op_amomaxu_w = 92,
 122     rv_op_lr_d = 93,
 123     rv_op_sc_d = 94,
 124     rv_op_amoswap_d = 95,
 125     rv_op_amoadd_d = 96,
 126     rv_op_amoxor_d = 97,
 127     rv_op_amoor_d = 98,
 128     rv_op_amoand_d = 99,
 129     rv_op_amomin_d = 100,
 130     rv_op_amomax_d = 101,
 131     rv_op_amominu_d = 102,
 132     rv_op_amomaxu_d = 103,
 133     rv_op_lr_q = 104,
 134     rv_op_sc_q = 105,
 135     rv_op_amoswap_q = 106,
 136     rv_op_amoadd_q = 107,
 137     rv_op_amoxor_q = 108,
 138     rv_op_amoor_q = 109,
 139     rv_op_amoand_q = 110,
 140     rv_op_amomin_q = 111,
 141     rv_op_amomax_q = 112,
 142     rv_op_amominu_q = 113,
 143     rv_op_amomaxu_q = 114,
 144     rv_op_ecall = 115,
 145     rv_op_ebreak = 116,
 146     rv_op_uret = 117,
 147     rv_op_sret = 118,
 148     rv_op_hret = 119,
 149     rv_op_mret = 120,
 150     rv_op_dret = 121,
 151     rv_op_sfence_vm = 122,
 152     rv_op_sfence_vma = 123,
 153     rv_op_wfi = 124,
 154     rv_op_csrrw = 125,
 155     rv_op_csrrs = 126,
 156     rv_op_csrrc = 127,
 157     rv_op_csrrwi = 128,
 158     rv_op_csrrsi = 129,
 159     rv_op_csrrci = 130,
 160     rv_op_flw = 131,
 161     rv_op_fsw = 132,
 162     rv_op_fmadd_s = 133,
 163     rv_op_fmsub_s = 134,
 164     rv_op_fnmsub_s = 135,
 165     rv_op_fnmadd_s = 136,
 166     rv_op_fadd_s = 137,
 167     rv_op_fsub_s = 138,
 168     rv_op_fmul_s = 139,
 169     rv_op_fdiv_s = 140,
 170     rv_op_fsgnj_s = 141,
 171     rv_op_fsgnjn_s = 142,
 172     rv_op_fsgnjx_s = 143,
 173     rv_op_fmin_s = 144,
 174     rv_op_fmax_s = 145,
 175     rv_op_fsqrt_s = 146,
 176     rv_op_fle_s = 147,
 177     rv_op_flt_s = 148,
 178     rv_op_feq_s = 149,
 179     rv_op_fcvt_w_s = 150,
 180     rv_op_fcvt_wu_s = 151,
 181     rv_op_fcvt_s_w = 152,
 182     rv_op_fcvt_s_wu = 153,
 183     rv_op_fmv_x_s = 154,
 184     rv_op_fclass_s = 155,
 185     rv_op_fmv_s_x = 156,
 186     rv_op_fcvt_l_s = 157,
 187     rv_op_fcvt_lu_s = 158,
 188     rv_op_fcvt_s_l = 159,
 189     rv_op_fcvt_s_lu = 160,
 190     rv_op_fld = 161,
 191     rv_op_fsd = 162,
 192     rv_op_fmadd_d = 163,
 193     rv_op_fmsub_d = 164,
 194     rv_op_fnmsub_d = 165,
 195     rv_op_fnmadd_d = 166,
 196     rv_op_fadd_d = 167,
 197     rv_op_fsub_d = 168,
 198     rv_op_fmul_d = 169,
 199     rv_op_fdiv_d = 170,
 200     rv_op_fsgnj_d = 171,
 201     rv_op_fsgnjn_d = 172,
 202     rv_op_fsgnjx_d = 173,
 203     rv_op_fmin_d = 174,
 204     rv_op_fmax_d = 175,
 205     rv_op_fcvt_s_d = 176,
 206     rv_op_fcvt_d_s = 177,
 207     rv_op_fsqrt_d = 178,
 208     rv_op_fle_d = 179,
 209     rv_op_flt_d = 180,
 210     rv_op_feq_d = 181,
 211     rv_op_fcvt_w_d = 182,
 212     rv_op_fcvt_wu_d = 183,
 213     rv_op_fcvt_d_w = 184,
 214     rv_op_fcvt_d_wu = 185,
 215     rv_op_fclass_d = 186,
 216     rv_op_fcvt_l_d = 187,
 217     rv_op_fcvt_lu_d = 188,
 218     rv_op_fmv_x_d = 189,
 219     rv_op_fcvt_d_l = 190,
 220     rv_op_fcvt_d_lu = 191,
 221     rv_op_fmv_d_x = 192,
 222     rv_op_flq = 193,
 223     rv_op_fsq = 194,
 224     rv_op_fmadd_q = 195,
 225     rv_op_fmsub_q = 196,
 226     rv_op_fnmsub_q = 197,
 227     rv_op_fnmadd_q = 198,
 228     rv_op_fadd_q = 199,
 229     rv_op_fsub_q = 200,
 230     rv_op_fmul_q = 201,
 231     rv_op_fdiv_q = 202,
 232     rv_op_fsgnj_q = 203,
 233     rv_op_fsgnjn_q = 204,
 234     rv_op_fsgnjx_q = 205,
 235     rv_op_fmin_q = 206,
 236     rv_op_fmax_q = 207,
 237     rv_op_fcvt_s_q = 208,
 238     rv_op_fcvt_q_s = 209,
 239     rv_op_fcvt_d_q = 210,
 240     rv_op_fcvt_q_d = 211,
 241     rv_op_fsqrt_q = 212,
 242     rv_op_fle_q = 213,
 243     rv_op_flt_q = 214,
 244     rv_op_feq_q = 215,
 245     rv_op_fcvt_w_q = 216,
 246     rv_op_fcvt_wu_q = 217,
 247     rv_op_fcvt_q_w = 218,
 248     rv_op_fcvt_q_wu = 219,
 249     rv_op_fclass_q = 220,
 250     rv_op_fcvt_l_q = 221,
 251     rv_op_fcvt_lu_q = 222,
 252     rv_op_fcvt_q_l = 223,
 253     rv_op_fcvt_q_lu = 224,
 254     rv_op_fmv_x_q = 225,
 255     rv_op_fmv_q_x = 226,
 256     rv_op_c_addi4spn = 227,
 257     rv_op_c_fld = 228,
 258     rv_op_c_lw = 229,
 259     rv_op_c_flw = 230,
 260     rv_op_c_fsd = 231,
 261     rv_op_c_sw = 232,
 262     rv_op_c_fsw = 233,
 263     rv_op_c_nop = 234,
 264     rv_op_c_addi = 235,
 265     rv_op_c_jal = 236,
 266     rv_op_c_li = 237,
 267     rv_op_c_addi16sp = 238,
 268     rv_op_c_lui = 239,
 269     rv_op_c_srli = 240,
 270     rv_op_c_srai = 241,
 271     rv_op_c_andi = 242,
 272     rv_op_c_sub = 243,
 273     rv_op_c_xor = 244,
 274     rv_op_c_or = 245,
 275     rv_op_c_and = 246,
 276     rv_op_c_subw = 247,
 277     rv_op_c_addw = 248,
 278     rv_op_c_j = 249,
 279     rv_op_c_beqz = 250,
 280     rv_op_c_bnez = 251,
 281     rv_op_c_slli = 252,
 282     rv_op_c_fldsp = 253,
 283     rv_op_c_lwsp = 254,
 284     rv_op_c_flwsp = 255,
 285     rv_op_c_jr = 256,
 286     rv_op_c_mv = 257,
 287     rv_op_c_ebreak = 258,
 288     rv_op_c_jalr = 259,
 289     rv_op_c_add = 260,
 290     rv_op_c_fsdsp = 261,
 291     rv_op_c_swsp = 262,
 292     rv_op_c_fswsp = 263,
 293     rv_op_c_ld = 264,
 294     rv_op_c_sd = 265,
 295     rv_op_c_addiw = 266,
 296     rv_op_c_ldsp = 267,
 297     rv_op_c_sdsp = 268,
 298     rv_op_c_lq = 269,
 299     rv_op_c_sq = 270,
 300     rv_op_c_lqsp = 271,
 301     rv_op_c_sqsp = 272,
 302     rv_op_nop = 273,
 303     rv_op_mv = 274,
 304     rv_op_not = 275,
 305     rv_op_neg = 276,
 306     rv_op_negw = 277,
 307     rv_op_sext_w = 278,
 308     rv_op_seqz = 279,
 309     rv_op_snez = 280,
 310     rv_op_sltz = 281,
 311     rv_op_sgtz = 282,
 312     rv_op_fmv_s = 283,
 313     rv_op_fabs_s = 284,
 314     rv_op_fneg_s = 285,
 315     rv_op_fmv_d = 286,
 316     rv_op_fabs_d = 287,
 317     rv_op_fneg_d = 288,
 318     rv_op_fmv_q = 289,
 319     rv_op_fabs_q = 290,
 320     rv_op_fneg_q = 291,
 321     rv_op_beqz = 292,
 322     rv_op_bnez = 293,
 323     rv_op_blez = 294,
 324     rv_op_bgez = 295,
 325     rv_op_bltz = 296,
 326     rv_op_bgtz = 297,
 327     rv_op_ble = 298,
 328     rv_op_bleu = 299,
 329     rv_op_bgt = 300,
 330     rv_op_bgtu = 301,
 331     rv_op_j = 302,
 332     rv_op_ret = 303,
 333     rv_op_jr = 304,
 334     rv_op_rdcycle = 305,
 335     rv_op_rdtime = 306,
 336     rv_op_rdinstret = 307,
 337     rv_op_rdcycleh = 308,
 338     rv_op_rdtimeh = 309,
 339     rv_op_rdinstreth = 310,
 340     rv_op_frcsr = 311,
 341     rv_op_frrm = 312,
 342     rv_op_frflags = 313,
 343     rv_op_fscsr = 314,
 344     rv_op_fsrm = 315,
 345     rv_op_fsflags = 316,
 346     rv_op_fsrmi = 317,
 347     rv_op_fsflagsi = 318,
 348     rv_op_bseti = 319,
 349     rv_op_bclri = 320,
 350     rv_op_binvi = 321,
 351     rv_op_bexti = 322,
 352     rv_op_rori = 323,
 353     rv_op_clz = 324,
 354     rv_op_ctz = 325,
 355     rv_op_cpop = 326,
 356     rv_op_sext_h = 327,
 357     rv_op_sext_b = 328,
 358     rv_op_xnor = 329,
 359     rv_op_orn = 330,
 360     rv_op_andn = 331,
 361     rv_op_rol = 332,
 362     rv_op_ror = 333,
 363     rv_op_sh1add = 334,
 364     rv_op_sh2add = 335,
 365     rv_op_sh3add = 336,
 366     rv_op_sh1add_uw = 337,
 367     rv_op_sh2add_uw = 338,
 368     rv_op_sh3add_uw = 339,
 369     rv_op_clmul = 340,
 370     rv_op_clmulr = 341,
 371     rv_op_clmulh = 342,
 372     rv_op_min = 343,
 373     rv_op_minu = 344,
 374     rv_op_max = 345,
 375     rv_op_maxu = 346,
 376     rv_op_clzw = 347,
 377     rv_op_ctzw = 348,
 378     rv_op_cpopw = 349,
 379     rv_op_slli_uw = 350,
 380     rv_op_add_uw = 351,
 381     rv_op_rolw = 352,
 382     rv_op_rorw = 353,
 383     rv_op_rev8 = 354,
 384     rv_op_zext_h = 355,
 385     rv_op_roriw = 356,
 386     rv_op_orc_b = 357,
 387     rv_op_bset = 358,
 388     rv_op_bclr = 359,
 389     rv_op_binv = 360,
 390     rv_op_bext = 361,
 391     rv_op_aes32esmi = 362,
 392     rv_op_aes32esi = 363,
 393     rv_op_aes32dsmi = 364,
 394     rv_op_aes32dsi = 365,
 395     rv_op_aes64ks1i = 366,
 396     rv_op_aes64ks2 = 367,
 397     rv_op_aes64im = 368,
 398     rv_op_aes64esm = 369,
 399     rv_op_aes64es = 370,
 400     rv_op_aes64dsm = 371,
 401     rv_op_aes64ds = 372,
 402     rv_op_sha256sig0 = 373,
 403     rv_op_sha256sig1 = 374,
 404     rv_op_sha256sum0 = 375,
 405     rv_op_sha256sum1 = 376,
 406     rv_op_sha512sig0 = 377,
 407     rv_op_sha512sig1 = 378,
 408     rv_op_sha512sum0 = 379,
 409     rv_op_sha512sum1 = 380,
 410     rv_op_sha512sum0r = 381,
 411     rv_op_sha512sum1r = 382,
 412     rv_op_sha512sig0l = 383,
 413     rv_op_sha512sig0h = 384,
 414     rv_op_sha512sig1l = 385,
 415     rv_op_sha512sig1h = 386,
 416     rv_op_sm3p0 = 387,
 417     rv_op_sm3p1 = 388,
 418     rv_op_sm4ed = 389,
 419     rv_op_sm4ks = 390,
 420     rv_op_brev8 = 391,
 421     rv_op_pack = 392,
 422     rv_op_packh = 393,
 423     rv_op_packw = 394,
 424     rv_op_unzip = 395,
 425     rv_op_zip = 396,
 426     rv_op_xperm4 = 397,
 427     rv_op_xperm8 = 398,
 428     rv_op_vle8_v = 399,
 429     rv_op_vle16_v = 400,
 430     rv_op_vle32_v = 401,
 431     rv_op_vle64_v = 402,
 432     rv_op_vse8_v = 403,
 433     rv_op_vse16_v = 404,
 434     rv_op_vse32_v = 405,
 435     rv_op_vse64_v = 406,
 436     rv_op_vlm_v = 407,
 437     rv_op_vsm_v = 408,
 438     rv_op_vlse8_v = 409,
 439     rv_op_vlse16_v = 410,
 440     rv_op_vlse32_v = 411,
 441     rv_op_vlse64_v = 412,
 442     rv_op_vsse8_v = 413,
 443     rv_op_vsse16_v = 414,
 444     rv_op_vsse32_v = 415,
 445     rv_op_vsse64_v = 416,
 446     rv_op_vluxei8_v = 417,
 447     rv_op_vluxei16_v = 418,
 448     rv_op_vluxei32_v = 419,
 449     rv_op_vluxei64_v = 420,
 450     rv_op_vloxei8_v = 421,
 451     rv_op_vloxei16_v = 422,
 452     rv_op_vloxei32_v = 423,
 453     rv_op_vloxei64_v = 424,
 454     rv_op_vsuxei8_v = 425,
 455     rv_op_vsuxei16_v = 426,
 456     rv_op_vsuxei32_v = 427,
 457     rv_op_vsuxei64_v = 428,
 458     rv_op_vsoxei8_v = 429,
 459     rv_op_vsoxei16_v = 430,
 460     rv_op_vsoxei32_v = 431,
 461     rv_op_vsoxei64_v = 432,
 462     rv_op_vle8ff_v = 433,
 463     rv_op_vle16ff_v = 434,
 464     rv_op_vle32ff_v = 435,
 465     rv_op_vle64ff_v = 436,
 466     rv_op_vl1re8_v = 437,
 467     rv_op_vl1re16_v = 438,
 468     rv_op_vl1re32_v = 439,
 469     rv_op_vl1re64_v = 440,
 470     rv_op_vl2re8_v = 441,
 471     rv_op_vl2re16_v = 442,
 472     rv_op_vl2re32_v = 443,
 473     rv_op_vl2re64_v = 444,
 474     rv_op_vl4re8_v = 445,
 475     rv_op_vl4re16_v = 446,
 476     rv_op_vl4re32_v = 447,
 477     rv_op_vl4re64_v = 448,
 478     rv_op_vl8re8_v = 449,
 479     rv_op_vl8re16_v = 450,
 480     rv_op_vl8re32_v = 451,
 481     rv_op_vl8re64_v = 452,
 482     rv_op_vs1r_v = 453,
 483     rv_op_vs2r_v = 454,
 484     rv_op_vs4r_v = 455,
 485     rv_op_vs8r_v = 456,
 486     rv_op_vadd_vv = 457,
 487     rv_op_vadd_vx = 458,
 488     rv_op_vadd_vi = 459,
 489     rv_op_vsub_vv = 460,
 490     rv_op_vsub_vx = 461,
 491     rv_op_vrsub_vx = 462,
 492     rv_op_vrsub_vi = 463,
 493     rv_op_vwaddu_vv = 464,
 494     rv_op_vwaddu_vx = 465,
 495     rv_op_vwadd_vv = 466,
 496     rv_op_vwadd_vx = 467,
 497     rv_op_vwsubu_vv = 468,
 498     rv_op_vwsubu_vx = 469,
 499     rv_op_vwsub_vv = 470,
 500     rv_op_vwsub_vx = 471,
 501     rv_op_vwaddu_wv = 472,
 502     rv_op_vwaddu_wx = 473,
 503     rv_op_vwadd_wv = 474,
 504     rv_op_vwadd_wx = 475,
 505     rv_op_vwsubu_wv = 476,
 506     rv_op_vwsubu_wx = 477,
 507     rv_op_vwsub_wv = 478,
 508     rv_op_vwsub_wx = 479,
 509     rv_op_vadc_vvm = 480,
 510     rv_op_vadc_vxm = 481,
 511     rv_op_vadc_vim = 482,
 512     rv_op_vmadc_vvm = 483,
 513     rv_op_vmadc_vxm = 484,
 514     rv_op_vmadc_vim = 485,
 515     rv_op_vsbc_vvm = 486,
 516     rv_op_vsbc_vxm = 487,
 517     rv_op_vmsbc_vvm = 488,
 518     rv_op_vmsbc_vxm = 489,
 519     rv_op_vand_vv = 490,
 520     rv_op_vand_vx = 491,
 521     rv_op_vand_vi = 492,
 522     rv_op_vor_vv = 493,
 523     rv_op_vor_vx = 494,
 524     rv_op_vor_vi = 495,
 525     rv_op_vxor_vv = 496,
 526     rv_op_vxor_vx = 497,
 527     rv_op_vxor_vi = 498,
 528     rv_op_vsll_vv = 499,
 529     rv_op_vsll_vx = 500,
 530     rv_op_vsll_vi = 501,
 531     rv_op_vsrl_vv = 502,
 532     rv_op_vsrl_vx = 503,
 533     rv_op_vsrl_vi = 504,
 534     rv_op_vsra_vv = 505,
 535     rv_op_vsra_vx = 506,
 536     rv_op_vsra_vi = 507,
 537     rv_op_vnsrl_wv = 508,
 538     rv_op_vnsrl_wx = 509,
 539     rv_op_vnsrl_wi = 510,
 540     rv_op_vnsra_wv = 511,
 541     rv_op_vnsra_wx = 512,
 542     rv_op_vnsra_wi = 513,
 543     rv_op_vmseq_vv = 514,
 544     rv_op_vmseq_vx = 515,
 545     rv_op_vmseq_vi = 516,
 546     rv_op_vmsne_vv = 517,
 547     rv_op_vmsne_vx = 518,
 548     rv_op_vmsne_vi = 519,
 549     rv_op_vmsltu_vv = 520,
 550     rv_op_vmsltu_vx = 521,
 551     rv_op_vmslt_vv = 522,
 552     rv_op_vmslt_vx = 523,
 553     rv_op_vmsleu_vv = 524,
 554     rv_op_vmsleu_vx = 525,
 555     rv_op_vmsleu_vi = 526,
 556     rv_op_vmsle_vv = 527,
 557     rv_op_vmsle_vx = 528,
 558     rv_op_vmsle_vi = 529,
 559     rv_op_vmsgtu_vx = 530,
 560     rv_op_vmsgtu_vi = 531,
 561     rv_op_vmsgt_vx = 532,
 562     rv_op_vmsgt_vi = 533,
 563     rv_op_vminu_vv = 534,
 564     rv_op_vminu_vx = 535,
 565     rv_op_vmin_vv = 536,
 566     rv_op_vmin_vx = 537,
 567     rv_op_vmaxu_vv = 538,
 568     rv_op_vmaxu_vx = 539,
 569     rv_op_vmax_vv = 540,
 570     rv_op_vmax_vx = 541,
 571     rv_op_vmul_vv = 542,
 572     rv_op_vmul_vx = 543,
 573     rv_op_vmulh_vv = 544,
 574     rv_op_vmulh_vx = 545,
 575     rv_op_vmulhu_vv = 546,
 576     rv_op_vmulhu_vx = 547,
 577     rv_op_vmulhsu_vv = 548,
 578     rv_op_vmulhsu_vx = 549,
 579     rv_op_vdivu_vv = 550,
 580     rv_op_vdivu_vx = 551,
 581     rv_op_vdiv_vv = 552,
 582     rv_op_vdiv_vx = 553,
 583     rv_op_vremu_vv = 554,
 584     rv_op_vremu_vx = 555,
 585     rv_op_vrem_vv = 556,
 586     rv_op_vrem_vx = 557,
 587     rv_op_vwmulu_vv = 558,
 588     rv_op_vwmulu_vx = 559,
 589     rv_op_vwmulsu_vv = 560,
 590     rv_op_vwmulsu_vx = 561,
 591     rv_op_vwmul_vv = 562,
 592     rv_op_vwmul_vx = 563,
 593     rv_op_vmacc_vv = 564,
 594     rv_op_vmacc_vx = 565,
 595     rv_op_vnmsac_vv = 566,
 596     rv_op_vnmsac_vx = 567,
 597     rv_op_vmadd_vv = 568,
 598     rv_op_vmadd_vx = 569,
 599     rv_op_vnmsub_vv = 570,
 600     rv_op_vnmsub_vx = 571,
 601     rv_op_vwmaccu_vv = 572,
 602     rv_op_vwmaccu_vx = 573,
 603     rv_op_vwmacc_vv = 574,
 604     rv_op_vwmacc_vx = 575,
 605     rv_op_vwmaccsu_vv = 576,
 606     rv_op_vwmaccsu_vx = 577,
 607     rv_op_vwmaccus_vx = 578,
 608     rv_op_vmv_v_v = 579,
 609     rv_op_vmv_v_x = 580,
 610     rv_op_vmv_v_i = 581,
 611     rv_op_vmerge_vvm = 582,
 612     rv_op_vmerge_vxm = 583,
 613     rv_op_vmerge_vim = 584,
 614     rv_op_vsaddu_vv = 585,
 615     rv_op_vsaddu_vx = 586,
 616     rv_op_vsaddu_vi = 587,
 617     rv_op_vsadd_vv = 588,
 618     rv_op_vsadd_vx = 589,
 619     rv_op_vsadd_vi = 590,
 620     rv_op_vssubu_vv = 591,
 621     rv_op_vssubu_vx = 592,
 622     rv_op_vssub_vv = 593,
 623     rv_op_vssub_vx = 594,
 624     rv_op_vaadd_vv = 595,
 625     rv_op_vaadd_vx = 596,
 626     rv_op_vaaddu_vv = 597,
 627     rv_op_vaaddu_vx = 598,
 628     rv_op_vasub_vv = 599,
 629     rv_op_vasub_vx = 600,
 630     rv_op_vasubu_vv = 601,
 631     rv_op_vasubu_vx = 602,
 632     rv_op_vsmul_vv = 603,
 633     rv_op_vsmul_vx = 604,
 634     rv_op_vssrl_vv = 605,
 635     rv_op_vssrl_vx = 606,
 636     rv_op_vssrl_vi = 607,
 637     rv_op_vssra_vv = 608,
 638     rv_op_vssra_vx = 609,
 639     rv_op_vssra_vi = 610,
 640     rv_op_vnclipu_wv = 611,
 641     rv_op_vnclipu_wx = 612,
 642     rv_op_vnclipu_wi = 613,
 643     rv_op_vnclip_wv = 614,
 644     rv_op_vnclip_wx = 615,
 645     rv_op_vnclip_wi = 616,
 646     rv_op_vfadd_vv = 617,
 647     rv_op_vfadd_vf = 618,
 648     rv_op_vfsub_vv = 619,
 649     rv_op_vfsub_vf = 620,
 650     rv_op_vfrsub_vf = 621,
 651     rv_op_vfwadd_vv = 622,
 652     rv_op_vfwadd_vf = 623,
 653     rv_op_vfwadd_wv = 624,
 654     rv_op_vfwadd_wf = 625,
 655     rv_op_vfwsub_vv = 626,
 656     rv_op_vfwsub_vf = 627,
 657     rv_op_vfwsub_wv = 628,
 658     rv_op_vfwsub_wf = 629,
 659     rv_op_vfmul_vv = 630,
 660     rv_op_vfmul_vf = 631,
 661     rv_op_vfdiv_vv = 632,
 662     rv_op_vfdiv_vf = 633,
 663     rv_op_vfrdiv_vf = 634,
 664     rv_op_vfwmul_vv = 635,
 665     rv_op_vfwmul_vf = 636,
 666     rv_op_vfmacc_vv = 637,
 667     rv_op_vfmacc_vf = 638,
 668     rv_op_vfnmacc_vv = 639,
 669     rv_op_vfnmacc_vf = 640,
 670     rv_op_vfmsac_vv = 641,
 671     rv_op_vfmsac_vf = 642,
 672     rv_op_vfnmsac_vv = 643,
 673     rv_op_vfnmsac_vf = 644,
 674     rv_op_vfmadd_vv = 645,
 675     rv_op_vfmadd_vf = 646,
 676     rv_op_vfnmadd_vv = 647,
 677     rv_op_vfnmadd_vf = 648,
 678     rv_op_vfmsub_vv = 649,
 679     rv_op_vfmsub_vf = 650,
 680     rv_op_vfnmsub_vv = 651,
 681     rv_op_vfnmsub_vf = 652,
 682     rv_op_vfwmacc_vv = 653,
 683     rv_op_vfwmacc_vf = 654,
 684     rv_op_vfwnmacc_vv = 655,
 685     rv_op_vfwnmacc_vf = 656,
 686     rv_op_vfwmsac_vv = 657,
 687     rv_op_vfwmsac_vf = 658,
 688     rv_op_vfwnmsac_vv = 659,
 689     rv_op_vfwnmsac_vf = 660,
 690     rv_op_vfsqrt_v = 661,
 691     rv_op_vfrsqrt7_v = 662,
 692     rv_op_vfrec7_v = 663,
 693     rv_op_vfmin_vv = 664,
 694     rv_op_vfmin_vf = 665,
 695     rv_op_vfmax_vv = 666,
 696     rv_op_vfmax_vf = 667,
 697     rv_op_vfsgnj_vv = 668,
 698     rv_op_vfsgnj_vf = 669,
 699     rv_op_vfsgnjn_vv = 670,
 700     rv_op_vfsgnjn_vf = 671,
 701     rv_op_vfsgnjx_vv = 672,
 702     rv_op_vfsgnjx_vf = 673,
 703     rv_op_vfslide1up_vf = 674,
 704     rv_op_vfslide1down_vf = 675,
 705     rv_op_vmfeq_vv = 676,
 706     rv_op_vmfeq_vf = 677,
 707     rv_op_vmfne_vv = 678,
 708     rv_op_vmfne_vf = 679,
 709     rv_op_vmflt_vv = 680,
 710     rv_op_vmflt_vf = 681,
 711     rv_op_vmfle_vv = 682,
 712     rv_op_vmfle_vf = 683,
 713     rv_op_vmfgt_vf = 684,
 714     rv_op_vmfge_vf = 685,
 715     rv_op_vfclass_v = 686,
 716     rv_op_vfmerge_vfm = 687,
 717     rv_op_vfmv_v_f = 688,
 718     rv_op_vfcvt_xu_f_v = 689,
 719     rv_op_vfcvt_x_f_v = 690,
 720     rv_op_vfcvt_f_xu_v = 691,
 721     rv_op_vfcvt_f_x_v = 692,
 722     rv_op_vfcvt_rtz_xu_f_v = 693,
 723     rv_op_vfcvt_rtz_x_f_v = 694,
 724     rv_op_vfwcvt_xu_f_v = 695,
 725     rv_op_vfwcvt_x_f_v = 696,
 726     rv_op_vfwcvt_f_xu_v = 697,
 727     rv_op_vfwcvt_f_x_v = 698,
 728     rv_op_vfwcvt_f_f_v = 699,
 729     rv_op_vfwcvt_rtz_xu_f_v = 700,
 730     rv_op_vfwcvt_rtz_x_f_v = 701,
 731     rv_op_vfncvt_xu_f_w = 702,
 732     rv_op_vfncvt_x_f_w = 703,
 733     rv_op_vfncvt_f_xu_w = 704,
 734     rv_op_vfncvt_f_x_w = 705,
 735     rv_op_vfncvt_f_f_w = 706,
 736     rv_op_vfncvt_rod_f_f_w = 707,
 737     rv_op_vfncvt_rtz_xu_f_w = 708,
 738     rv_op_vfncvt_rtz_x_f_w = 709,
 739     rv_op_vredsum_vs = 710,
 740     rv_op_vredand_vs = 711,
 741     rv_op_vredor_vs = 712,
 742     rv_op_vredxor_vs = 713,
 743     rv_op_vredminu_vs = 714,
 744     rv_op_vredmin_vs = 715,
 745     rv_op_vredmaxu_vs = 716,
 746     rv_op_vredmax_vs = 717,
 747     rv_op_vwredsumu_vs = 718,
 748     rv_op_vwredsum_vs = 719,
 749     rv_op_vfredusum_vs = 720,
 750     rv_op_vfredosum_vs = 721,
 751     rv_op_vfredmin_vs = 722,
 752     rv_op_vfredmax_vs = 723,
 753     rv_op_vfwredusum_vs = 724,
 754     rv_op_vfwredosum_vs = 725,
 755     rv_op_vmand_mm = 726,
 756     rv_op_vmnand_mm = 727,
 757     rv_op_vmandn_mm = 728,
 758     rv_op_vmxor_mm = 729,
 759     rv_op_vmor_mm = 730,
 760     rv_op_vmnor_mm = 731,
 761     rv_op_vmorn_mm = 732,
 762     rv_op_vmxnor_mm = 733,
 763     rv_op_vcpop_m = 734,
 764     rv_op_vfirst_m = 735,
 765     rv_op_vmsbf_m = 736,
 766     rv_op_vmsif_m = 737,
 767     rv_op_vmsof_m = 738,
 768     rv_op_viota_m = 739,
 769     rv_op_vid_v = 740,
 770     rv_op_vmv_x_s = 741,
 771     rv_op_vmv_s_x = 742,
 772     rv_op_vfmv_f_s = 743,
 773     rv_op_vfmv_s_f = 744,
 774     rv_op_vslideup_vx = 745,
 775     rv_op_vslideup_vi = 746,
 776     rv_op_vslide1up_vx = 747,
 777     rv_op_vslidedown_vx = 748,
 778     rv_op_vslidedown_vi = 749,
 779     rv_op_vslide1down_vx = 750,
 780     rv_op_vrgather_vv = 751,
 781     rv_op_vrgatherei16_vv = 752,
 782     rv_op_vrgather_vx = 753,
 783     rv_op_vrgather_vi = 754,
 784     rv_op_vcompress_vm = 755,
 785     rv_op_vmv1r_v = 756,
 786     rv_op_vmv2r_v = 757,
 787     rv_op_vmv4r_v = 758,
 788     rv_op_vmv8r_v = 759,
 789     rv_op_vzext_vf2 = 760,
 790     rv_op_vzext_vf4 = 761,
 791     rv_op_vzext_vf8 = 762,
 792     rv_op_vsext_vf2 = 763,
 793     rv_op_vsext_vf4 = 764,
 794     rv_op_vsext_vf8 = 765,
 795     rv_op_vsetvli = 766,
 796     rv_op_vsetivli = 767,
 797     rv_op_vsetvl = 768,
 798     rv_op_c_zext_b = 769,
 799     rv_op_c_sext_b = 770,
 800     rv_op_c_zext_h = 771,
 801     rv_op_c_sext_h = 772,
 802     rv_op_c_zext_w = 773,
 803     rv_op_c_not = 774,
 804     rv_op_c_mul = 775,
 805     rv_op_c_lbu = 776,
 806     rv_op_c_lhu = 777,
 807     rv_op_c_lh = 778,
 808     rv_op_c_sb = 779,
 809     rv_op_c_sh = 780,
 810     rv_op_cm_push = 781,
 811     rv_op_cm_pop = 782,
 812     rv_op_cm_popret = 783,
 813     rv_op_cm_popretz = 784,
 814     rv_op_cm_mva01s = 785,
 815     rv_op_cm_mvsa01 = 786,
 816     rv_op_cm_jt = 787,
 817     rv_op_cm_jalt = 788,
 818     rv_op_czero_eqz = 789,
 819     rv_op_czero_nez = 790,
 820 } rv_op;
 821
 822 /* register names */
 823
 824 static const char rv_ireg_name_sym[32][5] = {
 825     "zero", "ra",   "sp",   "gp",   "tp",   "t0",   "t1",   "t2",
 826     "s0",   "s1",   "a0",   "a1",   "a2",   "a3",   "a4",   "a5",
 827     "a6",   "a7",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
 828     "s8",   "s9",   "s10",  "s11",  "t3",   "t4",   "t5",   "t6",
 829 };
 830
 831 static const char rv_freg_name_sym[32][5] = {
 832     "ft0",  "ft1",  "ft2",  "ft3",  "ft4",  "ft5",  "ft6",  "ft7",
 833     "fs0",  "fs1",  "fa0",  "fa1",  "fa2",  "fa3",  "fa4",  "fa5",
 834     "fa6",  "fa7",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7",
 835     "fs8",  "fs9",  "fs10", "fs11", "ft8",  "ft9",  "ft10", "ft11",
 836 };
 837
 838 static const char rv_vreg_name_sym[32][4] = {
 839     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
 840     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
 841     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
 842     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
 843 };
 844
 845 /* pseudo-instruction constraints */
 846
 847 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
 848 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero,
 849                                             rvc_end };
 850 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0,
 851                                            rvc_imm_eq_zero, rvc_end };
 852 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
 853 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
 854 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
 855 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
 856 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };
 857 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
 858 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
 859 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };
 860 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end };
 861 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end };
 862 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end };
 863 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end };
 864 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end };
 865 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end };
 866 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end };
 867 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end };
 868 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end };
 869 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end };
 870 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end };
 871 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end };
 872 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end };
 873 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end };
 874 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end };
 875 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end };
 876 static const rvc_constraint rvcc_ble[] = { rvc_end };
 877 static const rvc_constraint rvcc_bleu[] = { rvc_end };
 878 static const rvc_constraint rvcc_bgt[] = { rvc_end };
 879 static const rvc_constraint rvcc_bgtu[] = { rvc_end };
 880 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
 881 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
 882                                            rvc_end };
 883 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
 884                                           rvc_end };
 885 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00,
 886                                                rvc_end };
 887 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01,
 888                                               rvc_end };
 889 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
 890                                                  rvc_csr_eq_0xc02, rvc_end };
 891 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
 892                                                 rvc_csr_eq_0xc80, rvc_end };
 893 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81,
 894                                                rvc_end };
 895 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
 896                                                   rvc_csr_eq_0xc82, rvc_end };
 897 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003,
 898                                              rvc_end };
 899 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002,
 900                                             rvc_end };
 901 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001,
 902                                                rvc_end };
 903 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
 904 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
 905 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
 906 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };
 907 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };
 908
 909 /* pseudo-instruction metadata */
 910
 911 static const rv_comp_data rvcp_jal[] = {
 912     { rv_op_j, rvcc_j },
 913     { rv_op_jal, rvcc_jal },
 914     { rv_op_illegal, NULL }
 915 };
 916
 917 static const rv_comp_data rvcp_jalr[] = {
 918     { rv_op_ret, rvcc_ret },
 919     { rv_op_jr, rvcc_jr },
 920     { rv_op_jalr, rvcc_jalr },
 921     { rv_op_illegal, NULL }
 922 };
 923
 924 static const rv_comp_data rvcp_beq[] = {
 925     { rv_op_beqz, rvcc_beqz },
 926     { rv_op_illegal, NULL }
 927 };
 928
 929 static const rv_comp_data rvcp_bne[] = {
 930     { rv_op_bnez, rvcc_bnez },
 931     { rv_op_illegal, NULL }
 932 };
 933
 934 static const rv_comp_data rvcp_blt[] = {
 935     { rv_op_bltz, rvcc_bltz },
 936     { rv_op_bgtz, rvcc_bgtz },
 937     { rv_op_bgt, rvcc_bgt },
 938     { rv_op_illegal, NULL }
 939 };
 940
 941 static const rv_comp_data rvcp_bge[] = {
 942     { rv_op_blez, rvcc_blez },
 943     { rv_op_bgez, rvcc_bgez },
 944     { rv_op_ble, rvcc_ble },
 945     { rv_op_illegal, NULL }
 946 };
 947
 948 static const rv_comp_data rvcp_bltu[] = {
 949     { rv_op_bgtu, rvcc_bgtu },
 950     { rv_op_illegal, NULL }
 951 };
 952
 953 static const rv_comp_data rvcp_bgeu[] = {
 954     { rv_op_bleu, rvcc_bleu },
 955     { rv_op_illegal, NULL }
 956 };
 957
 958 static const rv_comp_data rvcp_addi[] = {
 959     { rv_op_nop, rvcc_nop },
 960     { rv_op_mv, rvcc_mv },
 961     { rv_op_illegal, NULL }
 962 };
 963
 964 static const rv_comp_data rvcp_sltiu[] = {
 965     { rv_op_seqz, rvcc_seqz },
 966     { rv_op_illegal, NULL }
 967 };
 968
 969 static const rv_comp_data rvcp_xori[] = {
 970     { rv_op_not, rvcc_not },
 971     { rv_op_illegal, NULL }
 972 };
 973
 974 static const rv_comp_data rvcp_sub[] = {
 975     { rv_op_neg, rvcc_neg },
 976     { rv_op_illegal, NULL }
 977 };
 978
 979 static const rv_comp_data rvcp_slt[] = {
 980     { rv_op_sltz, rvcc_sltz },
 981     { rv_op_sgtz, rvcc_sgtz },
 982     { rv_op_illegal, NULL }
 983 };
 984
 985 static const rv_comp_data rvcp_sltu[] = {
 986     { rv_op_snez, rvcc_snez },
 987     { rv_op_illegal, NULL }
 988 };
 989
 990 static const rv_comp_data rvcp_addiw[] = {
 991     { rv_op_sext_w, rvcc_sext_w },
 992     { rv_op_illegal, NULL }
 993 };
 994
 995 static const rv_comp_data rvcp_subw[] = {
 996     { rv_op_negw, rvcc_negw },
 997     { rv_op_illegal, NULL }
 998 };
 999
1000 static const rv_comp_data rvcp_csrrw[] = {
1001     { rv_op_fscsr, rvcc_fscsr },
1002     { rv_op_fsrm, rvcc_fsrm },
1003     { rv_op_fsflags, rvcc_fsflags },
1004     { rv_op_illegal, NULL }
1005 };
1006
1007
1008 static const rv_comp_data rvcp_csrrs[] = {
1009     { rv_op_rdcycle, rvcc_rdcycle },
1010     { rv_op_rdtime, rvcc_rdtime },
1011     { rv_op_rdinstret, rvcc_rdinstret },
1012     { rv_op_rdcycleh, rvcc_rdcycleh },
1013     { rv_op_rdtimeh, rvcc_rdtimeh },
1014     { rv_op_rdinstreth, rvcc_rdinstreth },
1015     { rv_op_frcsr, rvcc_frcsr },
1016     { rv_op_frrm, rvcc_frrm },
1017     { rv_op_frflags, rvcc_frflags },
1018     { rv_op_illegal, NULL }
1019 };
1020
1021 static const rv_comp_data rvcp_csrrwi[] = {
1022     { rv_op_fsrmi, rvcc_fsrmi },
1023     { rv_op_fsflagsi, rvcc_fsflagsi },
1024     { rv_op_illegal, NULL }
1025 };
1026
1027 static const rv_comp_data rvcp_fsgnj_s[] = {
1028     { rv_op_fmv_s, rvcc_fmv_s },
1029     { rv_op_illegal, NULL }
1030 };
1031
1032 static const rv_comp_data rvcp_fsgnjn_s[] = {
1033     { rv_op_fneg_s, rvcc_fneg_s },
1034     { rv_op_illegal, NULL }
1035 };
1036
1037 static const rv_comp_data rvcp_fsgnjx_s[] = {
1038     { rv_op_fabs_s, rvcc_fabs_s },
1039     { rv_op_illegal, NULL }
1040 };
1041
1042 static const rv_comp_data rvcp_fsgnj_d[] = {
1043     { rv_op_fmv_d, rvcc_fmv_d },
1044     { rv_op_illegal, NULL }
1045 };
1046
1047 static const rv_comp_data rvcp_fsgnjn_d[] = {
1048     { rv_op_fneg_d, rvcc_fneg_d },
1049     { rv_op_illegal, NULL }
1050 };
1051
1052 static const rv_comp_data rvcp_fsgnjx_d[] = {
1053     { rv_op_fabs_d, rvcc_fabs_d },
1054     { rv_op_illegal, NULL }
1055 };
1056
1057 static const rv_comp_data rvcp_fsgnj_q[] = {
1058     { rv_op_fmv_q, rvcc_fmv_q },
1059     { rv_op_illegal, NULL }
1060 };
1061
1062 static const rv_comp_data rvcp_fsgnjn_q[] = {
1063     { rv_op_fneg_q, rvcc_fneg_q },
1064     { rv_op_illegal, NULL }
1065 };
1066
1067 static const rv_comp_data rvcp_fsgnjx_q[] = {
1068     { rv_op_fabs_q, rvcc_fabs_q },
1069     { rv_op_illegal, NULL }
1070 };
1071
1072 /* instruction metadata */
1073
1074 const rv_opcode_data rvi_opcode_data[] = {
1075     { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
1076     { "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 },
1077     { "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 },
1078     { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 },
1079     { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 },
1080     { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 },
1081     { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 },
1082     { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 },
1083     { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 },
1084     { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 },
1085     { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 },
1086     { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1087     { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1088     { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1089     { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1090     { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1091     { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1092     { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1093     { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1094     { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 },
1095     { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1096     { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 },
1097     { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 },
1098     { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1099     { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1100     { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1101     { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1102     { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1103     { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1104     { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 },
1105     { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1106     { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 },
1107     { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 },
1108     { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1109     { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1110     { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1111     { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1112     { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1113     { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 },
1114     { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1115     { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1116     { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1117     { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1118     { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 },
1119     { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1120     { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1121     { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1122     { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1123     { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 },
1124     { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1125     { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1126     { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1127     { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1128     { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1129     { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1130     { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1131     { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1132     { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1133     { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1134     { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1135     { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1136     { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1137     { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1138     { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1139     { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1140     { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1141     { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1142     { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1143     { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1144     { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1145     { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1146     { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1147     { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1148     { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1149     { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1150     { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1151     { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1152     { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1153     { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1154     { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1155     { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1156     { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1157     { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1158     { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1159     { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1160     { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1161     { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1162     { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1163     { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1164     { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1165     { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1166     { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1167     { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1168     { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1169     { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1170     { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1171     { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1172     { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1173     { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1174     { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1175     { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1176     { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1177     { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1178     { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1179     { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1180     { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1181     { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1182     { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1183     { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1184     { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1185     { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1186     { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1187     { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1188     { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1189     { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1190     { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1191     { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1192     { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1193     { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1194     { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1195     { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1196     { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1197     { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
1198     { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
1199     { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1200     { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 },
1201     { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 },
1202     { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 },
1203     { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 },
1204     { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
1205     { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
1206     { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1207     { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1208     { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1209     { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1210     { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1211     { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1212     { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1213     { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1214     { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1215     { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1216     { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 },
1217     { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 },
1218     { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 },
1219     { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1220     { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1221     { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1222     { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1223     { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1224     { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1225     { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1226     { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1227     { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1228     { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1229     { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1230     { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1231     { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1232     { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1233     { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1234     { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1235     { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1236     { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1237     { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1238     { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1239     { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1240     { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1241     { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1242     { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1243     { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1244     { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1245     { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1246     { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 },
1247     { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 },
1248     { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 },
1249     { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1250     { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1251     { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1252     { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1253     { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1254     { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1255     { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1256     { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1257     { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1258     { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1259     { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1260     { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1261     { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1262     { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1263     { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1264     { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1265     { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1266     { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1267     { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1268     { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1269     { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1270     { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1271     { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1272     { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1273     { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1274     { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1275     { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1276     { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1277     { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1278     { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 },
1279     { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 },
1280     { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 },
1281     { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1282     { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1283     { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1284     { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1285     { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1286     { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1287     { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1288     { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1289     { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1290     { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1291     { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1292     { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1293     { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1294     { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1295     { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1296     { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1297     { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1298     { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1299     { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1300     { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1301     { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1302     { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1303       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1304     { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
1305       rv_op_fld, 0 },
1306     { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw,
1307       rv_op_lw },
1308     { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
1309     { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
1310       rv_op_fsd, 0 },
1311     { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw,
1312       rv_op_sw },
1313     { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
1314     { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi,
1315       rv_op_addi },
1316     { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
1317       rv_op_addi, rvcd_imm_nz },
1318     { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
1319     { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
1320       rv_op_addi },
1321     { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1322       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1323     { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui,
1324       rv_op_lui, rvcd_imm_nz },
1325     { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli,
1326       rv_op_srli, rv_op_srli, rvcd_imm_nz },
1327     { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai,
1328       rv_op_srai, rv_op_srai, rvcd_imm_nz },
1329     { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
1330       rv_op_andi, rv_op_andi },
1331     { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub,
1332       rv_op_sub },
1333     { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor,
1334       rv_op_xor },
1335     { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or,
1336       rv_op_or },
1337     { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and,
1338       rv_op_and },
1339     { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw,
1340       rv_op_subw },
1341     { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw,
1342       rv_op_addw },
1343     { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal,
1344       rv_op_jal },
1345     { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq,
1346       rv_op_beq },
1347     { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne,
1348       rv_op_bne },
1349     { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
1350       rv_op_slli, rv_op_slli, rvcd_imm_nz },
1351     { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
1352       rv_op_fld, rv_op_fld },
1353     { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
1354       rv_op_lw, rv_op_lw },
1355     { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0,
1356       0 },
1357     { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
1358       rv_op_jalr, rv_op_jalr },
1359     { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi,
1360       rv_op_addi },
1361     { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak,
1362       rv_op_ebreak, rv_op_ebreak },
1363     { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
1364       rv_op_jalr, rv_op_jalr },
1365     { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add,
1366       rv_op_add },
1367     { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
1368       rv_op_fsd, rv_op_fsd },
1369     { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
1370       rv_op_sw, rv_op_sw },
1371     { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0,
1372       0 },
1373     { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
1374       rv_op_ld },
1375     { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
1376       rv_op_sd },
1377     { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw,
1378       rv_op_addiw },
1379     { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
1380       rv_op_ld },
1381     { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
1382       rv_op_sd },
1383     { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
1384     { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
1385     { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
1386     { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
1387       rv_op_sq },
1388     { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
1389     { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1390     { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1391     { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1392     { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1393     { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1394     { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1395     { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1396     { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1397     { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1398     { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1399     { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1400     { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1401     { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1402     { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1403     { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1404     { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1405     { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1406     { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1407     { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1408     { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1409     { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
1410     { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1411     { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1412     { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
1413     { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1414     { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1415     { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1416     { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1417     { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 },
1418     { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
1419     { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 },
1420     { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1421     { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1422     { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1423     { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1424     { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1425     { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1426     { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1427     { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1428     { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1429     { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1430     { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1431     { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1432     { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
1433     { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
1434     { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1435     { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1436     { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1437     { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1438     { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1439     { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1440     { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1441     { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1442     { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1443     { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1444     { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1445     { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1446     { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1447     { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1448     { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1449     { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1450     { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1451     { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1452     { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1453     { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1454     { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1455     { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1456     { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1457     { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1458     { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1459     { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1460     { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1461     { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1462     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1463     { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1464     { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1465     { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1466     { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1467     { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1468     { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1469     { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1470     { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1471     { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1472     { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1473     { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1474     { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1475     { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1476     { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1477     { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1478     { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1479     { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1480     { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1481     { "aes64ks1i", rv_codec_k_rnum,  rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
1482     { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1483     { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1484     { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1485     { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1486     { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1487     { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1488     { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1489     { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1490     { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1491     { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1492     { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1493     { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1494     { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1495     { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1496     { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1497     { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1498     { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1499     { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1500     { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1501     { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1502     { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1503     { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1504     { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1505     { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1506     { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1507     { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1508     { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1509     { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1510     { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1511     { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1512     { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1513     { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1514     { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1515     { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1516     { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1517     { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1518     { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1519     { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1520     { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1521     { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1522     { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1523     { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1524     { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1525     { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1526     { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1527     { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1528     { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1529     { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1530     { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1531     { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1532     { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1533     { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1534     { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1535     { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1536     { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1537     { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1538     { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1539     { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1540     { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1541     { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1542     { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1543     { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1544     { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1545     { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1546     { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1547     { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1548     { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1549     { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1550     { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1551     { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1552     { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1553     { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1554     { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1555     { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1556     { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1557     { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1558     { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1559     { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1560     { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1561     { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1562     { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1563     { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1564     { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1565     { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1566     { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1567     { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1568     { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1569     { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1570     { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1571     { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1572     { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1573     { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1574     { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1575     { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1576     { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1577     { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1578     { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1579     { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1580     { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1581     { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1582     { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1583     { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1584     { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1585     { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1586     { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1587     { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1588     { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1589     { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1590     { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1591     { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1592     { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1593     { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1594     { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1595     { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1596     { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1597     { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
1598     { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1599     { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1600     { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
1601     { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1602     { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1603     { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1604     { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1605     { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1606     { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1607     { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1608     { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1609     { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1610     { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1611     { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1612     { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1613     { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1614     { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1615     { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1616     { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1617     { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1618     { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1619     { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1620     { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1621     { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1622     { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1623     { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1624     { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1625     { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1626     { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1627     { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1628     { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1629     { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1630     { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1631     { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1632     { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1633     { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1634     { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1635     { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1636     { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1637     { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1638     { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1639     { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1640     { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1641     { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1642     { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1643     { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1644     { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1645     { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1646     { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1647     { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1648     { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1649     { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1650     { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1651     { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1652     { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1653     { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1654     { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1655     { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1656     { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1657     { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1658     { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1659     { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1660     { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1661     { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1662     { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1663     { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1664     { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1665     { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1666     { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1667     { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1668     { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1669     { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1670     { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1671     { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1672     { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1673     { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1674     { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1675     { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1676     { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1677     { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1678     { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1679     { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1680     { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1681     { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1682     { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1683     { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1684     { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1685     { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1686     { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1687     { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1688     { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1689     { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1690     { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1691     { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1692     { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1693     { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1694     { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 },
1695     { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
1696     { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 },
1697     { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1698     { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1699     { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
1700     { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1701     { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1702     { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1703     { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1704     { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1705     { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1706     { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1707     { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1708     { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1709     { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1710     { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1711     { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1712     { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1713     { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1714     { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1715     { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1716     { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1717     { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1718     { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1719     { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1720     { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1721     { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1722     { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1723     { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1724     { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1725     { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1726     { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1727     { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1728     { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1729     { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1730     { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1731     { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1732     { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1733     { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1734     { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1735     { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1736     { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1737     { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1738     { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1739     { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1740     { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1741     { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1742     { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1743     { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1744     { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1745     { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1746     { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1747     { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1748     { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1749     { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1750     { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1751     { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1752     { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1753     { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1754     { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1755     { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1756     { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1757     { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1758     { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1759     { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1760     { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1761     { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1762     { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1763     { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1764     { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1765     { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1766     { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1767     { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1768     { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1769     { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1770     { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1771     { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1772     { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1773     { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1774     { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1775     { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1776     { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1777     { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1778     { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1779     { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1780     { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1781     { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1782     { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1783     { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1784     { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1785     { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1786     { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1787     { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1788     { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1789     { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1790     { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1791     { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1792     { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1793     { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1794     { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1795     { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1796     { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1797     { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1798     { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1799     { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1800     { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1801     { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1802     { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 },
1803     { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
1804     { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1805     { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1806     { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1807     { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1808     { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1809     { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1810     { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1811     { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1812     { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1813     { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1814     { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1815     { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1816     { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1817     { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1818     { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1819     { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1820     { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1821     { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1822     { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1823     { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1824     { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1825     { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1826     { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1827     { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1828     { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1829     { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1830     { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1831     { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1832     { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1833     { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1834     { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1835     { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1836     { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1837     { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1838     { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1839     { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1840     { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1841     { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1842     { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1843     { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1844     { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1845     { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1846     { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1847     { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1848     { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1849     { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
1850     { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
1851     { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1852     { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1853     { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1854     { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1855     { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 },
1856     { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 },
1857     { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
1858     { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 },
1859     { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
1860     { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1861     { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1862     { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1863     { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1864     { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1865     { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1866     { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1867     { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1868     { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1869     { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1870     { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
1871     { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1872     { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1873     { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1874     { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1875     { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1876     { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1877     { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1878     { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1879     { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1880     { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1881     { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 },
1882     { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 },
1883     { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1884     { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
1885     { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
1886     { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
1887     { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
1888     { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
1889     { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
1890     { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 },
1891     { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
1892     { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
1893     { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
1894     { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
1895     { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
1896     { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 },
1897     { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
1898     { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 },
1899     { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
1900     { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1901     { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1902     { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
1903     { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
1904     { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1905     { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1906 };
1907
1908 /* CSR names */
1909
1910 static const char *csr_name(int csrno)
1911 {
1912     switch (csrno) {
1913     case 0x0000: return "ustatus";
1914     case 0x0001: return "fflags";
1915     case 0x0002: return "frm";
1916     case 0x0003: return "fcsr";
1917     case 0x0004: return "uie";
1918     case 0x0005: return "utvec";
1919     case 0x0008: return "vstart";
1920     case 0x0009: return "vxsat";
1921     case 0x000a: return "vxrm";
1922     case 0x000f: return "vcsr";
1923     case 0x0015: return "seed";
1924     case 0x0017: return "jvt";
1925     case 0x0040: return "uscratch";
1926     case 0x0041: return "uepc";
1927     case 0x0042: return "ucause";
1928     case 0x0043: return "utval";
1929     case 0x0044: return "uip";
1930     case 0x0100: return "sstatus";
1931     case 0x0104: return "sie";
1932     case 0x0105: return "stvec";
1933     case 0x0106: return "scounteren";
1934     case 0x0140: return "sscratch";
1935     case 0x0141: return "sepc";
1936     case 0x0142: return "scause";
1937     case 0x0143: return "stval";
1938     case 0x0144: return "sip";
1939     case 0x0180: return "satp";
1940     case 0x0200: return "hstatus";
1941     case 0x0202: return "hedeleg";
1942     case 0x0203: return "hideleg";
1943     case 0x0204: return "hie";
1944     case 0x0205: return "htvec";
1945     case 0x0240: return "hscratch";
1946     case 0x0241: return "hepc";
1947     case 0x0242: return "hcause";
1948     case 0x0243: return "hbadaddr";
1949     case 0x0244: return "hip";
1950     case 0x0300: return "mstatus";
1951     case 0x0301: return "misa";
1952     case 0x0302: return "medeleg";
1953     case 0x0303: return "mideleg";
1954     case 0x0304: return "mie";
1955     case 0x0305: return "mtvec";
1956     case 0x0306: return "mcounteren";
1957     case 0x0320: return "mucounteren";
1958     case 0x0321: return "mscounteren";
1959     case 0x0322: return "mhcounteren";
1960     case 0x0323: return "mhpmevent3";
1961     case 0x0324: return "mhpmevent4";
1962     case 0x0325: return "mhpmevent5";
1963     case 0x0326: return "mhpmevent6";
1964     case 0x0327: return "mhpmevent7";
1965     case 0x0328: return "mhpmevent8";
1966     case 0x0329: return "mhpmevent9";
1967     case 0x032a: return "mhpmevent10";
1968     case 0x032b: return "mhpmevent11";
1969     case 0x032c: return "mhpmevent12";
1970     case 0x032d: return "mhpmevent13";
1971     case 0x032e: return "mhpmevent14";
1972     case 0x032f: return "mhpmevent15";
1973     case 0x0330: return "mhpmevent16";
1974     case 0x0331: return "mhpmevent17";
1975     case 0x0332: return "mhpmevent18";
1976     case 0x0333: return "mhpmevent19";
1977     case 0x0334: return "mhpmevent20";
1978     case 0x0335: return "mhpmevent21";
1979     case 0x0336: return "mhpmevent22";
1980     case 0x0337: return "mhpmevent23";
1981     case 0x0338: return "mhpmevent24";
1982     case 0x0339: return "mhpmevent25";
1983     case 0x033a: return "mhpmevent26";
1984     case 0x033b: return "mhpmevent27";
1985     case 0x033c: return "mhpmevent28";
1986     case 0x033d: return "mhpmevent29";
1987     case 0x033e: return "mhpmevent30";
1988     case 0x033f: return "mhpmevent31";
1989     case 0x0340: return "mscratch";
1990     case 0x0341: return "mepc";
1991     case 0x0342: return "mcause";
1992     case 0x0343: return "mtval";
1993     case 0x0344: return "mip";
1994     case 0x0380: return "mbase";
1995     case 0x0381: return "mbound";
1996     case 0x0382: return "mibase";
1997     case 0x0383: return "mibound";
1998     case 0x0384: return "mdbase";
1999     case 0x0385: return "mdbound";
2000     case 0x03a0: return "pmpcfg3";
2001     case 0x03b0: return "pmpaddr0";
2002     case 0x03b1: return "pmpaddr1";
2003     case 0x03b2: return "pmpaddr2";
2004     case 0x03b3: return "pmpaddr3";
2005     case 0x03b4: return "pmpaddr4";
2006     case 0x03b5: return "pmpaddr5";
2007     case 0x03b6: return "pmpaddr6";
2008     case 0x03b7: return "pmpaddr7";
2009     case 0x03b8: return "pmpaddr8";
2010     case 0x03b9: return "pmpaddr9";
2011     case 0x03ba: return "pmpaddr10";
2012     case 0x03bb: return "pmpaddr11";
2013     case 0x03bc: return "pmpaddr12";
2014     case 0x03bd: return "pmpaddr14";
2015     case 0x03be: return "pmpaddr13";
2016     case 0x03bf: return "pmpaddr15";
2017     case 0x0780: return "mtohost";
2018     case 0x0781: return "mfromhost";
2019     case 0x0782: return "mreset";
2020     case 0x0783: return "mipi";
2021     case 0x0784: return "miobase";
2022     case 0x07a0: return "tselect";
2023     case 0x07a1: return "tdata1";
2024     case 0x07a2: return "tdata2";
2025     case 0x07a3: return "tdata3";
2026     case 0x07b0: return "dcsr";
2027     case 0x07b1: return "dpc";
2028     case 0x07b2: return "dscratch";
2029     case 0x0b00: return "mcycle";
2030     case 0x0b01: return "mtime";
2031     case 0x0b02: return "minstret";
2032     case 0x0b03: return "mhpmcounter3";
2033     case 0x0b04: return "mhpmcounter4";
2034     case 0x0b05: return "mhpmcounter5";
2035     case 0x0b06: return "mhpmcounter6";
2036     case 0x0b07: return "mhpmcounter7";
2037     case 0x0b08: return "mhpmcounter8";
2038     case 0x0b09: return "mhpmcounter9";
2039     case 0x0b0a: return "mhpmcounter10";
2040     case 0x0b0b: return "mhpmcounter11";
2041     case 0x0b0c: return "mhpmcounter12";
2042     case 0x0b0d: return "mhpmcounter13";
2043     case 0x0b0e: return "mhpmcounter14";
2044     case 0x0b0f: return "mhpmcounter15";
2045     case 0x0b10: return "mhpmcounter16";
2046     case 0x0b11: return "mhpmcounter17";
2047     case 0x0b12: return "mhpmcounter18";
2048     case 0x0b13: return "mhpmcounter19";
2049     case 0x0b14: return "mhpmcounter20";
2050     case 0x0b15: return "mhpmcounter21";
2051     case 0x0b16: return "mhpmcounter22";
2052     case 0x0b17: return "mhpmcounter23";
2053     case 0x0b18: return "mhpmcounter24";
2054     case 0x0b19: return "mhpmcounter25";
2055     case 0x0b1a: return "mhpmcounter26";
2056     case 0x0b1b: return "mhpmcounter27";
2057     case 0x0b1c: return "mhpmcounter28";
2058     case 0x0b1d: return "mhpmcounter29";
2059     case 0x0b1e: return "mhpmcounter30";
2060     case 0x0b1f: return "mhpmcounter31";
2061     case 0x0b80: return "mcycleh";
2062     case 0x0b81: return "mtimeh";
2063     case 0x0b82: return "minstreth";
2064     case 0x0b83: return "mhpmcounter3h";
2065     case 0x0b84: return "mhpmcounter4h";
2066     case 0x0b85: return "mhpmcounter5h";
2067     case 0x0b86: return "mhpmcounter6h";
2068     case 0x0b87: return "mhpmcounter7h";
2069     case 0x0b88: return "mhpmcounter8h";
2070     case 0x0b89: return "mhpmcounter9h";
2071     case 0x0b8a: return "mhpmcounter10h";
2072     case 0x0b8b: return "mhpmcounter11h";
2073     case 0x0b8c: return "mhpmcounter12h";
2074     case 0x0b8d: return "mhpmcounter13h";
2075     case 0x0b8e: return "mhpmcounter14h";
2076     case 0x0b8f: return "mhpmcounter15h";
2077     case 0x0b90: return "mhpmcounter16h";
2078     case 0x0b91: return "mhpmcounter17h";
2079     case 0x0b92: return "mhpmcounter18h";
2080     case 0x0b93: return "mhpmcounter19h";
2081     case 0x0b94: return "mhpmcounter20h";
2082     case 0x0b95: return "mhpmcounter21h";
2083     case 0x0b96: return "mhpmcounter22h";
2084     case 0x0b97: return "mhpmcounter23h";
2085     case 0x0b98: return "mhpmcounter24h";
2086     case 0x0b99: return "mhpmcounter25h";
2087     case 0x0b9a: return "mhpmcounter26h";
2088     case 0x0b9b: return "mhpmcounter27h";
2089     case 0x0b9c: return "mhpmcounter28h";
2090     case 0x0b9d: return "mhpmcounter29h";
2091     case 0x0b9e: return "mhpmcounter30h";
2092     case 0x0b9f: return "mhpmcounter31h";
2093     case 0x0c00: return "cycle";
2094     case 0x0c01: return "time";
2095     case 0x0c02: return "instret";
2096     case 0x0c20: return "vl";
2097     case 0x0c21: return "vtype";
2098     case 0x0c22: return "vlenb";
2099     case 0x0c80: return "cycleh";
2100     case 0x0c81: return "timeh";
2101     case 0x0c82: return "instreth";
2102     case 0x0d00: return "scycle";
2103     case 0x0d01: return "stime";
2104     case 0x0d02: return "sinstret";
2105     case 0x0d80: return "scycleh";
2106     case 0x0d81: return "stimeh";
2107     case 0x0d82: return "sinstreth";
2108     case 0x0e00: return "hcycle";
2109     case 0x0e01: return "htime";
2110     case 0x0e02: return "hinstret";
2111     case 0x0e80: return "hcycleh";
2112     case 0x0e81: return "htimeh";
2113     case 0x0e82: return "hinstreth";
2114     case 0x0f11: return "mvendorid";
2115     case 0x0f12: return "marchid";
2116     case 0x0f13: return "mimpid";
2117     case 0x0f14: return "mhartid";
2118     default: return NULL;
2119     }
2120 }
2121
2122 /* decode opcode */
2123
2124 static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
2125 {
2126     rv_inst inst = dec->inst;
2127     rv_opcode op = rv_op_illegal;
2128     switch ((inst >> 0) & 0b11) {
2129     case 0:
2130         switch ((inst >> 13) & 0b111) {
2131         case 0: op = rv_op_c_addi4spn; break;
2132         case 1:
2133             if (isa == rv128) {
2134                 op = rv_op_c_lq;
2135             } else {
2136                 op = rv_op_c_fld;
2137             }
2138             break;
2139         case 2: op = rv_op_c_lw; break;
2140         case 3:
2141             if (isa == rv32) {
2142                 op = rv_op_c_flw;
2143             } else {
2144                 op = rv_op_c_ld;
2145             }
2146             break;
2147         case 4:
2148             switch ((inst >> 10) & 0b111) {
2149             case 0: op = rv_op_c_lbu; break;
2150             case 1:
2151                 if (((inst >> 6) & 1) == 0) {
2152                     op = rv_op_c_lhu;
2153                 } else {
2154                     op = rv_op_c_lh;
2155                 }
2156                 break;
2157             case 2: op = rv_op_c_sb; break;
2158             case 3:
2159                 if (((inst >> 6) & 1) == 0) {
2160                     op = rv_op_c_sh;
2161                 }
2162                 break;
2163             }
2164             break;
2165         case 5:
2166             if (isa == rv128) {
2167                 op = rv_op_c_sq;
2168             } else {
2169                 op = rv_op_c_fsd;
2170             }
2171             break;
2172         case 6: op = rv_op_c_sw; break;
2173         case 7:
2174             if (isa == rv32) {
2175                 op = rv_op_c_fsw;
2176             } else {
2177                 op = rv_op_c_sd;
2178             }
2179             break;
2180         }
2181         break;
2182     case 1:
2183         switch ((inst >> 13) & 0b111) {
2184         case 0:
2185             switch ((inst >> 2) & 0b11111111111) {
2186             case 0: op = rv_op_c_nop; break;
2187             default: op = rv_op_c_addi; break;
2188             }
2189             break;
2190         case 1:
2191             if (isa == rv32) {
2192                 op = rv_op_c_jal;
2193             } else {
2194                 op = rv_op_c_addiw;
2195             }
2196             break;
2197         case 2: op = rv_op_c_li; break;
2198         case 3:
2199             switch ((inst >> 7) & 0b11111) {
2200             case 2: op = rv_op_c_addi16sp; break;
2201             default: op = rv_op_c_lui; break;
2202             }
2203             break;
2204         case 4:
2205             switch ((inst >> 10) & 0b11) {
2206             case 0:
2207                 op = rv_op_c_srli;
2208                 break;
2209             case 1:
2210                 op = rv_op_c_srai;
2211                 break;
2212             case 2: op = rv_op_c_andi; break;
2213             case 3:
2214                 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) {
2215                 case 0: op = rv_op_c_sub; break;
2216                 case 1: op = rv_op_c_xor; break;
2217                 case 2: op = rv_op_c_or; break;
2218                 case 3: op = rv_op_c_and; break;
2219                 case 4: op = rv_op_c_subw; break;
2220                 case 5: op = rv_op_c_addw; break;
2221                 case 6: op = rv_op_c_mul; break;
2222                 case 7:
2223                     switch ((inst >> 2) & 0b111) {
2224                     case 0: op = rv_op_c_zext_b; break;
2225                     case 1: op = rv_op_c_sext_b; break;
2226                     case 2: op = rv_op_c_zext_h; break;
2227                     case 3: op = rv_op_c_sext_h; break;
2228                     case 4: op = rv_op_c_zext_w; break;
2229                     case 5: op = rv_op_c_not; break;
2230                     }
2231                     break;
2232                 }
2233                 break;
2234             }
2235             break;
2236         case 5: op = rv_op_c_j; break;
2237         case 6: op = rv_op_c_beqz; break;
2238         case 7: op = rv_op_c_bnez; break;
2239         }
2240         break;
2241     case 2:
2242         switch ((inst >> 13) & 0b111) {
2243         case 0:
2244             op = rv_op_c_slli;
2245             break;
2246         case 1:
2247             if (isa == rv128) {
2248                 op = rv_op_c_lqsp;
2249             } else {
2250                 op = rv_op_c_fldsp;
2251             }
2252             break;
2253         case 2: op = rv_op_c_lwsp; break;
2254         case 3:
2255             if (isa == rv32) {
2256                 op = rv_op_c_flwsp;
2257             } else {
2258                 op = rv_op_c_ldsp;
2259             }
2260             break;
2261         case 4:
2262             switch ((inst >> 12) & 0b1) {
2263             case 0:
2264                 switch ((inst >> 2) & 0b11111) {
2265                 case 0: op = rv_op_c_jr; break;
2266                 default: op = rv_op_c_mv; break;
2267                 }
2268                 break;
2269             case 1:
2270                 switch ((inst >> 2) & 0b11111) {
2271                 case 0:
2272                     switch ((inst >> 7) & 0b11111) {
2273                     case 0: op = rv_op_c_ebreak; break;
2274                     default: op = rv_op_c_jalr; break;
2275                     }
2276                     break;
2277                 default: op = rv_op_c_add; break;
2278                 }
2279                 break;
2280             }
2281             break;
2282         case 5:
2283             if (isa == rv128) {
2284                 op = rv_op_c_sqsp;
2285             } else {
2286                 op = rv_op_c_fsdsp;
2287                 if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
2288                     switch ((inst >> 8) & 0b01111) {
2289                     case 8:
2290                         if (((inst >> 4) & 0b01111) >= 4) {
2291                             op = rv_op_cm_push;
2292                         }
2293                         break;
2294                     case 10:
2295                         if (((inst >> 4) & 0b01111) >= 4) {
2296                             op = rv_op_cm_pop;
2297                         }
2298                         break;
2299                     case 12:
2300                         if (((inst >> 4) & 0b01111) >= 4) {
2301                             op = rv_op_cm_popretz;
2302                         }
2303                         break;
2304                     case 14:
2305                         if (((inst >> 4) & 0b01111) >= 4) {
2306                             op = rv_op_cm_popret;
2307                         }
2308                         break;
2309                     }
2310                 } else {
2311                     switch ((inst >> 10) & 0b011) {
2312                     case 0:
2313                         if (!dec->cfg->ext_zcmt) {
2314                             break;
2315                         }
2316                         if (((inst >> 2) & 0xFF) >= 32) {
2317                             op = rv_op_cm_jalt;
2318                         } else {
2319                             op = rv_op_cm_jt;
2320                         }
2321                         break;
2322                     case 3:
2323                         if (!dec->cfg->ext_zcmp) {
2324                             break;
2325                         }
2326                         switch ((inst >> 5) & 0b011) {
2327                         case 1: op = rv_op_cm_mvsa01; break;
2328                         case 3: op = rv_op_cm_mva01s; break;
2329                         }
2330                         break;
2331                     }
2332                 }
2333             }
2334             break;
2335         case 6: op = rv_op_c_swsp; break;
2336         case 7:
2337             if (isa == rv32) {
2338                 op = rv_op_c_fswsp;
2339             } else {
2340                 op = rv_op_c_sdsp;
2341             }
2342             break;
2343         }
2344         break;
2345     case 3:
2346         switch ((inst >> 2) & 0b11111) {
2347         case 0:
2348             switch ((inst >> 12) & 0b111) {
2349             case 0: op = rv_op_lb; break;
2350             case 1: op = rv_op_lh; break;
2351             case 2: op = rv_op_lw; break;
2352             case 3: op = rv_op_ld; break;
2353             case 4: op = rv_op_lbu; break;
2354             case 5: op = rv_op_lhu; break;
2355             case 6: op = rv_op_lwu; break;
2356             case 7: op = rv_op_ldu; break;
2357             }
2358             break;
2359         case 1:
2360             switch ((inst >> 12) & 0b111) {
2361             case 0:
2362                 switch ((inst >> 20) & 0b111111111111) {
2363                 case 40: op = rv_op_vl1re8_v; break;
2364                 case 552: op = rv_op_vl2re8_v; break;
2365                 case 1576: op = rv_op_vl4re8_v; break;
2366                 case 3624: op = rv_op_vl8re8_v; break;
2367                 }
2368                 switch ((inst >> 26) & 0b111) {
2369                 case 0:
2370                     switch ((inst >> 20) & 0b11111) {
2371                     case 0: op = rv_op_vle8_v; break;
2372                     case 11: op = rv_op_vlm_v; break;
2373                     case 16: op = rv_op_vle8ff_v; break;
2374                     }
2375                     break;
2376                 case 1: op = rv_op_vluxei8_v; break;
2377                 case 2: op = rv_op_vlse8_v; break;
2378                 case 3: op = rv_op_vloxei8_v; break;
2379                 }
2380                 break;
2381             case 2: op = rv_op_flw; break;
2382             case 3: op = rv_op_fld; break;
2383             case 4: op = rv_op_flq; break;
2384             case 5:
2385                 switch ((inst >> 20) & 0b111111111111) {
2386                 case 40: op = rv_op_vl1re16_v; break;
2387                 case 552: op = rv_op_vl2re16_v; break;
2388                 case 1576: op = rv_op_vl4re16_v; break;
2389                 case 3624: op = rv_op_vl8re16_v; break;
2390                 }
2391                 switch ((inst >> 26) & 0b111) {
2392                 case 0:
2393                     switch ((inst >> 20) & 0b11111) {
2394                     case 0: op = rv_op_vle16_v; break;
2395                     case 16: op = rv_op_vle16ff_v; break;
2396                     }
2397                     break;
2398                 case 1: op = rv_op_vluxei16_v; break;
2399                 case 2: op = rv_op_vlse16_v; break;
2400                 case 3: op = rv_op_vloxei16_v; break;
2401                 }
2402                 break;
2403             case 6:
2404                 switch ((inst >> 20) & 0b111111111111) {
2405                 case 40: op = rv_op_vl1re32_v; break;
2406                 case 552: op = rv_op_vl2re32_v; break;
2407                 case 1576: op = rv_op_vl4re32_v; break;
2408                 case 3624: op = rv_op_vl8re32_v; break;
2409                 }
2410                 switch ((inst >> 26) & 0b111) {
2411                 case 0:
2412                     switch ((inst >> 20) & 0b11111) {
2413                     case 0: op = rv_op_vle32_v; break;
2414                     case 16: op = rv_op_vle32ff_v; break;
2415                     }
2416                     break;
2417                 case 1: op = rv_op_vluxei32_v; break;
2418                 case 2: op = rv_op_vlse32_v; break;
2419                 case 3: op = rv_op_vloxei32_v; break;
2420                 }
2421                 break;
2422             case 7:
2423                 switch ((inst >> 20) & 0b111111111111) {
2424                 case 40: op = rv_op_vl1re64_v; break;
2425                 case 552: op = rv_op_vl2re64_v; break;
2426                 case 1576: op = rv_op_vl4re64_v; break;
2427                 case 3624: op = rv_op_vl8re64_v; break;
2428                 }
2429                 switch ((inst >> 26) & 0b111) {
2430                 case 0:
2431                     switch ((inst >> 20) & 0b11111) {
2432                     case 0: op = rv_op_vle64_v; break;
2433                     case 16: op = rv_op_vle64ff_v; break;
2434                     }
2435                     break;
2436                 case 1: op = rv_op_vluxei64_v; break;
2437                 case 2: op = rv_op_vlse64_v; break;
2438                 case 3: op = rv_op_vloxei64_v; break;
2439                 }
2440                 break;
2441             }
2442             break;
2443         case 3:
2444             switch ((inst >> 12) & 0b111) {
2445             case 0: op = rv_op_fence; break;
2446             case 1: op = rv_op_fence_i; break;
2447             case 2: op = rv_op_lq; break;
2448             }
2449             break;
2450         case 4:
2451             switch ((inst >> 12) & 0b111) {
2452             case 0: op = rv_op_addi; break;
2453             case 1:
2454                 switch ((inst >> 27) & 0b11111) {
2455                 case 0b00000: op = rv_op_slli; break;
2456                 case 0b00001:
2457                     switch ((inst >> 20) & 0b1111111) {
2458                     case 0b0001111: op = rv_op_zip; break;
2459                     }
2460                     break;
2461                 case 0b00010:
2462                     switch ((inst >> 20) & 0b1111111) {
2463                     case 0b0000000: op = rv_op_sha256sum0; break;
2464                     case 0b0000001: op = rv_op_sha256sum1; break;
2465                     case 0b0000010: op = rv_op_sha256sig0; break;
2466                     case 0b0000011: op = rv_op_sha256sig1; break;
2467                     case 0b0000100: op = rv_op_sha512sum0; break;
2468                     case 0b0000101: op = rv_op_sha512sum1; break;
2469                     case 0b0000110: op = rv_op_sha512sig0; break;
2470                     case 0b0000111: op = rv_op_sha512sig1; break;
2471                     case 0b0001000: op = rv_op_sm3p0; break;
2472                     case 0b0001001: op = rv_op_sm3p1; break;
2473                     }
2474                     break;
2475                 case 0b00101: op = rv_op_bseti; break;
2476                 case 0b00110:
2477                     switch ((inst >> 20) & 0b1111111) {
2478                     case 0b0000000: op = rv_op_aes64im; break;
2479                     default:
2480                         if (((inst >> 24) & 0b0111) == 0b001) {
2481                             op = rv_op_aes64ks1i;
2482                         }
2483                         break;
2484                      }
2485                      break;
2486                 case 0b01001: op = rv_op_bclri; break;
2487                 case 0b01101: op = rv_op_binvi; break;
2488                 case 0b01100:
2489                     switch ((inst >> 20) & 0b1111111) {
2490                     case 0b0000000: op = rv_op_clz; break;
2491                     case 0b0000001: op = rv_op_ctz; break;
2492                     case 0b0000010: op = rv_op_cpop; break;
2493                       /* 0b0000011 */
2494                     case 0b0000100: op = rv_op_sext_b; break;
2495                     case 0b0000101: op = rv_op_sext_h; break;
2496                     }
2497                     break;
2498                 }
2499                 break;
2500             case 2: op = rv_op_slti; break;
2501             case 3: op = rv_op_sltiu; break;
2502             case 4: op = rv_op_xori; break;
2503             case 5:
2504                 switch ((inst >> 27) & 0b11111) {
2505                 case 0b00000: op = rv_op_srli; break;
2506                 case 0b00001:
2507                     switch ((inst >> 20) & 0b1111111) {
2508                     case 0b0001111: op = rv_op_unzip; break;
2509                     }
2510                     break;
2511                 case 0b00101: op = rv_op_orc_b; break;
2512                 case 0b01000: op = rv_op_srai; break;
2513                 case 0b01001: op = rv_op_bexti; break;
2514                 case 0b01100: op = rv_op_rori; break;
2515                 case 0b01101:
2516                     switch ((inst >> 20) & 0b1111111) {
2517                     case 0b0011000: op = rv_op_rev8; break;
2518                     case 0b0111000: op = rv_op_rev8; break;
2519                     case 0b0000111: op = rv_op_brev8; break;
2520                     }
2521                     break;
2522                 }
2523                 break;
2524             case 6: op = rv_op_ori; break;
2525             case 7: op = rv_op_andi; break;
2526             }
2527             break;
2528         case 5: op = rv_op_auipc; break;
2529         case 6:
2530             switch ((inst >> 12) & 0b111) {
2531             case 0: op = rv_op_addiw; break;
2532             case 1:
2533                 switch ((inst >> 26) & 0b111111) {
2534                 case 0: op = rv_op_slliw; break;
2535                 case 2: op = rv_op_slli_uw; break;
2536                 case 24:
2537                     switch ((inst >> 20) & 0b11111) {
2538                     case 0b00000: op = rv_op_clzw; break;
2539                     case 0b00001: op = rv_op_ctzw; break;
2540                     case 0b00010: op = rv_op_cpopw; break;
2541                     }
2542                     break;
2543                 }
2544                 break;
2545             case 5:
2546                 switch ((inst >> 25) & 0b1111111) {
2547                 case 0: op = rv_op_srliw; break;
2548                 case 32: op = rv_op_sraiw; break;
2549                 case 48: op = rv_op_roriw; break;
2550                 }
2551                 break;
2552             }
2553             break;
2554         case 8:
2555             switch ((inst >> 12) & 0b111) {
2556             case 0: op = rv_op_sb; break;
2557             case 1: op = rv_op_sh; break;
2558             case 2: op = rv_op_sw; break;
2559             case 3: op = rv_op_sd; break;
2560             case 4: op = rv_op_sq; break;
2561             }
2562             break;
2563         case 9:
2564             switch ((inst >> 12) & 0b111) {
2565             case 0:
2566                 switch ((inst >> 20) & 0b111111111111) {
2567                 case 40: op = rv_op_vs1r_v; break;
2568                 case 552: op = rv_op_vs2r_v; break;
2569                 case 1576: op = rv_op_vs4r_v; break;
2570                 case 3624: op = rv_op_vs8r_v; break;
2571                 }
2572                 switch ((inst >> 26) & 0b111) {
2573                 case 0:
2574                     switch ((inst >> 20) & 0b11111) {
2575                     case 0: op = rv_op_vse8_v; break;
2576                     case 11: op = rv_op_vsm_v; break;
2577                     }
2578                     break;
2579                 case 1: op = rv_op_vsuxei8_v; break;
2580                 case 2: op = rv_op_vsse8_v; break;
2581                 case 3: op = rv_op_vsoxei8_v; break;
2582                 }
2583                 break;
2584             case 2: op = rv_op_fsw; break;
2585             case 3: op = rv_op_fsd; break;
2586             case 4: op = rv_op_fsq; break;
2587             case 5:
2588                 switch ((inst >> 26) & 0b111) {
2589                 case 0:
2590                     switch ((inst >> 20) & 0b11111) {
2591                     case 0: op = rv_op_vse16_v; break;
2592                     }
2593                     break;
2594                 case 1: op = rv_op_vsuxei16_v; break;
2595                 case 2: op = rv_op_vsse16_v; break;
2596                 case 3: op = rv_op_vsoxei16_v; break;
2597                 }
2598                 break;
2599             case 6:
2600                 switch ((inst >> 26) & 0b111) {
2601                 case 0:
2602                     switch ((inst >> 20) & 0b11111) {
2603                     case 0: op = rv_op_vse32_v; break;
2604                     }
2605                     break;
2606                 case 1: op = rv_op_vsuxei32_v; break;
2607                 case 2: op = rv_op_vsse32_v; break;
2608                 case 3: op = rv_op_vsoxei32_v; break;
2609                 }
2610                 break;
2611             case 7:
2612                 switch ((inst >> 26) & 0b111) {
2613                 case 0:
2614                     switch ((inst >> 20) & 0b11111) {
2615                     case 0: op = rv_op_vse64_v; break;
2616                     }
2617                     break;
2618                 case 1: op = rv_op_vsuxei64_v; break;
2619                 case 2: op = rv_op_vsse64_v; break;
2620                 case 3: op = rv_op_vsoxei64_v; break;
2621                 }
2622                 break;
2623             }
2624             break;
2625         case 11:
2626             switch (((inst >> 24) & 0b11111000) |
2627                     ((inst >> 12) & 0b00000111)) {
2628             case 2: op = rv_op_amoadd_w; break;
2629             case 3: op = rv_op_amoadd_d; break;
2630             case 4: op = rv_op_amoadd_q; break;
2631             case 10: op = rv_op_amoswap_w; break;
2632             case 11: op = rv_op_amoswap_d; break;
2633             case 12: op = rv_op_amoswap_q; break;
2634             case 18:
2635                 switch ((inst >> 20) & 0b11111) {
2636                 case 0: op = rv_op_lr_w; break;
2637                 }
2638                 break;
2639             case 19:
2640                 switch ((inst >> 20) & 0b11111) {
2641                 case 0: op = rv_op_lr_d; break;
2642                 }
2643                 break;
2644             case 20:
2645                 switch ((inst >> 20) & 0b11111) {
2646                 case 0: op = rv_op_lr_q; break;
2647                 }
2648                 break;
2649             case 26: op = rv_op_sc_w; break;
2650             case 27: op = rv_op_sc_d; break;
2651             case 28: op = rv_op_sc_q; break;
2652             case 34: op = rv_op_amoxor_w; break;
2653             case 35: op = rv_op_amoxor_d; break;
2654             case 36: op = rv_op_amoxor_q; break;
2655             case 66: op = rv_op_amoor_w; break;
2656             case 67: op = rv_op_amoor_d; break;
2657             case 68: op = rv_op_amoor_q; break;
2658             case 98: op = rv_op_amoand_w; break;
2659             case 99: op = rv_op_amoand_d; break;
2660             case 100: op = rv_op_amoand_q; break;
2661             case 130: op = rv_op_amomin_w; break;
2662             case 131: op = rv_op_amomin_d; break;
2663             case 132: op = rv_op_amomin_q; break;
2664             case 162: op = rv_op_amomax_w; break;
2665             case 163: op = rv_op_amomax_d; break;
2666             case 164: op = rv_op_amomax_q; break;
2667             case 194: op = rv_op_amominu_w; break;
2668             case 195: op = rv_op_amominu_d; break;
2669             case 196: op = rv_op_amominu_q; break;
2670             case 226: op = rv_op_amomaxu_w; break;
2671             case 227: op = rv_op_amomaxu_d; break;
2672             case 228: op = rv_op_amomaxu_q; break;
2673             }
2674             break;
2675         case 12:
2676             switch (((inst >> 22) & 0b1111111000) |
2677                     ((inst >> 12) & 0b0000000111)) {
2678             case 0: op = rv_op_add; break;
2679             case 1: op = rv_op_sll; break;
2680             case 2: op = rv_op_slt; break;
2681             case 3: op = rv_op_sltu; break;
2682             case 4: op = rv_op_xor; break;
2683             case 5: op = rv_op_srl; break;
2684             case 6: op = rv_op_or; break;
2685             case 7: op = rv_op_and; break;
2686             case 8: op = rv_op_mul; break;
2687             case 9: op = rv_op_mulh; break;
2688             case 10: op = rv_op_mulhsu; break;
2689             case 11: op = rv_op_mulhu; break;
2690             case 12: op = rv_op_div; break;
2691             case 13: op = rv_op_divu; break;
2692             case 14: op = rv_op_rem; break;
2693             case 15: op = rv_op_remu; break;
2694             case 36:
2695                 switch ((inst >> 20) & 0b11111) {
2696                 case 0: op = rv_op_zext_h; break;
2697                 default: op = rv_op_pack; break;
2698                 }
2699                 break;
2700             case 39: op = rv_op_packh; break;
2701
2702             case 41: op = rv_op_clmul; break;
2703             case 42: op = rv_op_clmulr; break;
2704             case 43: op = rv_op_clmulh; break;
2705             case 44: op = rv_op_min; break;
2706             case 45: op = rv_op_minu; break;
2707             case 46: op = rv_op_max; break;
2708             case 47: op = rv_op_maxu; break;
2709             case 075: op = rv_op_czero_eqz; break;
2710             case 077: op = rv_op_czero_nez; break;
2711             case 130: op = rv_op_sh1add; break;
2712             case 132: op = rv_op_sh2add; break;
2713             case 134: op = rv_op_sh3add; break;
2714             case 161: op = rv_op_bset; break;
2715             case 162: op = rv_op_xperm4; break;
2716             case 164: op = rv_op_xperm8; break;
2717             case 200: op = rv_op_aes64es; break;
2718             case 216: op = rv_op_aes64esm; break;
2719             case 232: op = rv_op_aes64ds; break;
2720             case 248: op = rv_op_aes64dsm; break;
2721             case 256: op = rv_op_sub; break;
2722             case 260: op = rv_op_xnor; break;
2723             case 261: op = rv_op_sra; break;
2724             case 262: op = rv_op_orn; break;
2725             case 263: op = rv_op_andn; break;
2726             case 289: op = rv_op_bclr; break;
2727             case 293: op = rv_op_bext; break;
2728             case 320: op = rv_op_sha512sum0r; break;
2729             case 328: op = rv_op_sha512sum1r; break;
2730             case 336: op = rv_op_sha512sig0l; break;
2731             case 344: op = rv_op_sha512sig1l; break;
2732             case 368: op = rv_op_sha512sig0h; break;
2733             case 376: op = rv_op_sha512sig1h; break;
2734             case 385: op = rv_op_rol; break;
2735             case 389: op = rv_op_ror; break;
2736             case 417: op = rv_op_binv; break;
2737             case 504: op = rv_op_aes64ks2; break;
2738             }
2739             switch ((inst >> 25) & 0b0011111) {
2740             case 17: op = rv_op_aes32esi; break;
2741             case 19: op = rv_op_aes32esmi; break;
2742             case 21: op = rv_op_aes32dsi; break;
2743             case 23: op = rv_op_aes32dsmi; break;
2744             case 24: op = rv_op_sm4ed; break;
2745             case 26: op = rv_op_sm4ks; break;
2746             }
2747             break;
2748         case 13: op = rv_op_lui; break;
2749         case 14:
2750             switch (((inst >> 22) & 0b1111111000) |
2751                     ((inst >> 12) & 0b0000000111)) {
2752             case 0: op = rv_op_addw; break;
2753             case 1: op = rv_op_sllw; break;
2754             case 5: op = rv_op_srlw; break;
2755             case 8: op = rv_op_mulw; break;
2756             case 12: op = rv_op_divw; break;
2757             case 13: op = rv_op_divuw; break;
2758             case 14: op = rv_op_remw; break;
2759             case 15: op = rv_op_remuw; break;
2760             case 32: op = rv_op_add_uw; break;
2761             case 36:
2762                 switch ((inst >> 20) & 0b11111) {
2763                 case 0: op = rv_op_zext_h; break;
2764                 default: op = rv_op_packw; break;
2765                 }
2766                 break;
2767             case 130: op = rv_op_sh1add_uw; break;
2768             case 132: op = rv_op_sh2add_uw; break;
2769             case 134: op = rv_op_sh3add_uw; break;
2770             case 256: op = rv_op_subw; break;
2771             case 261: op = rv_op_sraw; break;
2772             case 385: op = rv_op_rolw; break;
2773             case 389: op = rv_op_rorw; break;
2774             }
2775             break;
2776         case 16:
2777             switch ((inst >> 25) & 0b11) {
2778             case 0: op = rv_op_fmadd_s; break;
2779             case 1: op = rv_op_fmadd_d; break;
2780             case 3: op = rv_op_fmadd_q; break;
2781             }
2782             break;
2783         case 17:
2784             switch ((inst >> 25) & 0b11) {
2785             case 0: op = rv_op_fmsub_s; break;
2786             case 1: op = rv_op_fmsub_d; break;
2787             case 3: op = rv_op_fmsub_q; break;
2788             }
2789             break;
2790         case 18:
2791             switch ((inst >> 25) & 0b11) {
2792             case 0: op = rv_op_fnmsub_s; break;
2793             case 1: op = rv_op_fnmsub_d; break;
2794             case 3: op = rv_op_fnmsub_q; break;
2795             }
2796             break;
2797         case 19:
2798             switch ((inst >> 25) & 0b11) {
2799             case 0: op = rv_op_fnmadd_s; break;
2800             case 1: op = rv_op_fnmadd_d; break;
2801             case 3: op = rv_op_fnmadd_q; break;
2802             }
2803             break;
2804         case 20:
2805             switch ((inst >> 25) & 0b1111111) {
2806             case 0: op = rv_op_fadd_s; break;
2807             case 1: op = rv_op_fadd_d; break;
2808             case 3: op = rv_op_fadd_q; break;
2809             case 4: op = rv_op_fsub_s; break;
2810             case 5: op = rv_op_fsub_d; break;
2811             case 7: op = rv_op_fsub_q; break;
2812             case 8: op = rv_op_fmul_s; break;
2813             case 9: op = rv_op_fmul_d; break;
2814             case 11: op = rv_op_fmul_q; break;
2815             case 12: op = rv_op_fdiv_s; break;
2816             case 13: op = rv_op_fdiv_d; break;
2817             case 15: op = rv_op_fdiv_q; break;
2818             case 16:
2819                 switch ((inst >> 12) & 0b111) {
2820                 case 0: op = rv_op_fsgnj_s; break;
2821                 case 1: op = rv_op_fsgnjn_s; break;
2822                 case 2: op = rv_op_fsgnjx_s; break;
2823                 }
2824                 break;
2825             case 17:
2826                 switch ((inst >> 12) & 0b111) {
2827                 case 0: op = rv_op_fsgnj_d; break;
2828                 case 1: op = rv_op_fsgnjn_d; break;
2829                 case 2: op = rv_op_fsgnjx_d; break;
2830                 }
2831                 break;
2832             case 19:
2833                 switch ((inst >> 12) & 0b111) {
2834                 case 0: op = rv_op_fsgnj_q; break;
2835                 case 1: op = rv_op_fsgnjn_q; break;
2836                 case 2: op = rv_op_fsgnjx_q; break;
2837                 }
2838                 break;
2839             case 20:
2840                 switch ((inst >> 12) & 0b111) {
2841                 case 0: op = rv_op_fmin_s; break;
2842                 case 1: op = rv_op_fmax_s; break;
2843                 }
2844                 break;
2845             case 21:
2846                 switch ((inst >> 12) & 0b111) {
2847                 case 0: op = rv_op_fmin_d; break;
2848                 case 1: op = rv_op_fmax_d; break;
2849                 }
2850                 break;
2851             case 23:
2852                 switch ((inst >> 12) & 0b111) {
2853                 case 0: op = rv_op_fmin_q; break;
2854                 case 1: op = rv_op_fmax_q; break;
2855                 }
2856                 break;
2857             case 32:
2858                 switch ((inst >> 20) & 0b11111) {
2859                 case 1: op = rv_op_fcvt_s_d; break;
2860                 case 3: op = rv_op_fcvt_s_q; break;
2861                 }
2862                 break;
2863             case 33:
2864                 switch ((inst >> 20) & 0b11111) {
2865                 case 0: op = rv_op_fcvt_d_s; break;
2866                 case 3: op = rv_op_fcvt_d_q; break;
2867                 }
2868                 break;
2869             case 35:
2870                 switch ((inst >> 20) & 0b11111) {
2871                 case 0: op = rv_op_fcvt_q_s; break;
2872                 case 1: op = rv_op_fcvt_q_d; break;
2873                 }
2874                 break;
2875             case 44:
2876                 switch ((inst >> 20) & 0b11111) {
2877                 case 0: op = rv_op_fsqrt_s; break;
2878                 }
2879                 break;
2880             case 45:
2881                 switch ((inst >> 20) & 0b11111) {
2882                 case 0: op = rv_op_fsqrt_d; break;
2883                 }
2884                 break;
2885             case 47:
2886                 switch ((inst >> 20) & 0b11111) {
2887                 case 0: op = rv_op_fsqrt_q; break;
2888                 }
2889                 break;
2890             case 80:
2891                 switch ((inst >> 12) & 0b111) {
2892                 case 0: op = rv_op_fle_s; break;
2893                 case 1: op = rv_op_flt_s; break;
2894                 case 2: op = rv_op_feq_s; break;
2895                 }
2896                 break;
2897             case 81:
2898                 switch ((inst >> 12) & 0b111) {
2899                 case 0: op = rv_op_fle_d; break;
2900                 case 1: op = rv_op_flt_d; break;
2901                 case 2: op = rv_op_feq_d; break;
2902                 }
2903                 break;
2904             case 83:
2905                 switch ((inst >> 12) & 0b111) {
2906                 case 0: op = rv_op_fle_q; break;
2907                 case 1: op = rv_op_flt_q; break;
2908                 case 2: op = rv_op_feq_q; break;
2909                 }
2910                 break;
2911             case 96:
2912                 switch ((inst >> 20) & 0b11111) {
2913                 case 0: op = rv_op_fcvt_w_s; break;
2914                 case 1: op = rv_op_fcvt_wu_s; break;
2915                 case 2: op = rv_op_fcvt_l_s; break;
2916                 case 3: op = rv_op_fcvt_lu_s; break;
2917                 }
2918                 break;
2919             case 97:
2920                 switch ((inst >> 20) & 0b11111) {
2921                 case 0: op = rv_op_fcvt_w_d; break;
2922                 case 1: op = rv_op_fcvt_wu_d; break;
2923                 case 2: op = rv_op_fcvt_l_d; break;
2924                 case 3: op = rv_op_fcvt_lu_d; break;
2925                 }
2926                 break;
2927             case 99:
2928                 switch ((inst >> 20) & 0b11111) {
2929                 case 0: op = rv_op_fcvt_w_q; break;
2930                 case 1: op = rv_op_fcvt_wu_q; break;
2931                 case 2: op = rv_op_fcvt_l_q; break;
2932                 case 3: op = rv_op_fcvt_lu_q; break;
2933                 }
2934                 break;
2935             case 104:
2936                 switch ((inst >> 20) & 0b11111) {
2937                 case 0: op = rv_op_fcvt_s_w; break;
2938                 case 1: op = rv_op_fcvt_s_wu; break;
2939                 case 2: op = rv_op_fcvt_s_l; break;
2940                 case 3: op = rv_op_fcvt_s_lu; break;
2941                 }
2942                 break;
2943             case 105:
2944                 switch ((inst >> 20) & 0b11111) {
2945                 case 0: op = rv_op_fcvt_d_w; break;
2946                 case 1: op = rv_op_fcvt_d_wu; break;
2947                 case 2: op = rv_op_fcvt_d_l; break;
2948                 case 3: op = rv_op_fcvt_d_lu; break;
2949                 }
2950                 break;
2951             case 107:
2952                 switch ((inst >> 20) & 0b11111) {
2953                 case 0: op = rv_op_fcvt_q_w; break;
2954                 case 1: op = rv_op_fcvt_q_wu; break;
2955                 case 2: op = rv_op_fcvt_q_l; break;
2956                 case 3: op = rv_op_fcvt_q_lu; break;
2957                 }
2958                 break;
2959             case 112:
2960                 switch (((inst >> 17) & 0b11111000) |
2961                         ((inst >> 12) & 0b00000111)) {
2962                 case 0: op = rv_op_fmv_x_s; break;
2963                 case 1: op = rv_op_fclass_s; break;
2964                 }
2965                 break;
2966             case 113:
2967                 switch (((inst >> 17) & 0b11111000) |
2968                         ((inst >> 12) & 0b00000111)) {
2969                 case 0: op = rv_op_fmv_x_d; break;
2970                 case 1: op = rv_op_fclass_d; break;
2971                 }
2972                 break;
2973             case 115:
2974                 switch (((inst >> 17) & 0b11111000) |
2975                         ((inst >> 12) & 0b00000111)) {
2976                 case 0: op = rv_op_fmv_x_q; break;
2977                 case 1: op = rv_op_fclass_q; break;
2978                 }
2979                 break;
2980             case 120:
2981                 switch (((inst >> 17) & 0b11111000) |
2982                         ((inst >> 12) & 0b00000111)) {
2983                 case 0: op = rv_op_fmv_s_x; break;
2984                 }
2985                 break;
2986             case 121:
2987                 switch (((inst >> 17) & 0b11111000) |
2988                         ((inst >> 12) & 0b00000111)) {
2989                 case 0: op = rv_op_fmv_d_x; break;
2990                 }
2991                 break;
2992             case 123:
2993                 switch (((inst >> 17) & 0b11111000) |
2994                         ((inst >> 12) & 0b00000111)) {
2995                 case 0: op = rv_op_fmv_q_x; break;
2996                 }
2997                 break;
2998             }
2999             break;
3000         case 21:
3001             switch ((inst >> 12) & 0b111) {
3002             case 0:
3003                 switch ((inst >> 26) & 0b111111) {
3004                 case 0: op = rv_op_vadd_vv; break;
3005                 case 2: op = rv_op_vsub_vv; break;
3006                 case 4: op = rv_op_vminu_vv; break;
3007                 case 5: op = rv_op_vmin_vv; break;
3008                 case 6: op = rv_op_vmaxu_vv; break;
3009                 case 7: op = rv_op_vmax_vv; break;
3010                 case 9: op = rv_op_vand_vv; break;
3011                 case 10: op = rv_op_vor_vv; break;
3012                 case 11: op = rv_op_vxor_vv; break;
3013                 case 12: op = rv_op_vrgather_vv; break;
3014                 case 14: op = rv_op_vrgatherei16_vv; break;
3015                 case 16:
3016                     if (((inst >> 25) & 1) == 0) {
3017                         op = rv_op_vadc_vvm;
3018                     }
3019                     break;
3020                 case 17: op = rv_op_vmadc_vvm; break;
3021                 case 18:
3022                     if (((inst >> 25) & 1) == 0) {
3023                         op = rv_op_vsbc_vvm;
3024                     }
3025                     break;
3026                 case 19: op = rv_op_vmsbc_vvm; break;
3027                 case 23:
3028                     if (((inst >> 20) & 0b111111) == 32)
3029                         op = rv_op_vmv_v_v;
3030                     else if (((inst >> 25) & 1) == 0)
3031                         op = rv_op_vmerge_vvm;
3032                     break;
3033                 case 24: op = rv_op_vmseq_vv; break;
3034                 case 25: op = rv_op_vmsne_vv; break;
3035                 case 26: op = rv_op_vmsltu_vv; break;
3036                 case 27: op = rv_op_vmslt_vv; break;
3037                 case 28: op = rv_op_vmsleu_vv; break;
3038                 case 29: op = rv_op_vmsle_vv; break;
3039                 case 32: op = rv_op_vsaddu_vv; break;
3040                 case 33: op = rv_op_vsadd_vv; break;
3041                 case 34: op = rv_op_vssubu_vv; break;
3042                 case 35: op = rv_op_vssub_vv; break;
3043                 case 37: op = rv_op_vsll_vv; break;
3044                 case 39: op = rv_op_vsmul_vv; break;
3045                 case 40: op = rv_op_vsrl_vv; break;
3046                 case 41: op = rv_op_vsra_vv; break;
3047                 case 42: op = rv_op_vssrl_vv; break;
3048                 case 43: op = rv_op_vssra_vv; break;
3049                 case 44: op = rv_op_vnsrl_wv; break;
3050                 case 45: op = rv_op_vnsra_wv; break;
3051                 case 46: op = rv_op_vnclipu_wv; break;
3052                 case 47: op = rv_op_vnclip_wv; break;
3053                 case 48: op = rv_op_vwredsumu_vs; break;
3054                 case 49: op = rv_op_vwredsum_vs; break;
3055                 }
3056                 break;
3057             case 1:
3058                 switch ((inst >> 26) & 0b111111) {
3059                 case 0: op = rv_op_vfadd_vv; break;
3060                 case 1: op = rv_op_vfredusum_vs; break;
3061                 case 2: op = rv_op_vfsub_vv; break;
3062                 case 3: op = rv_op_vfredosum_vs; break;
3063                 case 4: op = rv_op_vfmin_vv; break;
3064                 case 5: op = rv_op_vfredmin_vs; break;
3065                 case 6: op = rv_op_vfmax_vv; break;
3066                 case 7: op = rv_op_vfredmax_vs; break;
3067                 case 8: op = rv_op_vfsgnj_vv; break;
3068                 case 9: op = rv_op_vfsgnjn_vv; break;
3069                 case 10: op = rv_op_vfsgnjx_vv; break;
3070                 case 16:
3071                     switch ((inst >> 15) & 0b11111) {
3072                     case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break;
3073                     }
3074                     break;
3075                 case 18:
3076                     switch ((inst >> 15) & 0b11111) {
3077                     case 0: op = rv_op_vfcvt_xu_f_v; break;
3078                     case 1: op = rv_op_vfcvt_x_f_v; break;
3079                     case 2: op = rv_op_vfcvt_f_xu_v; break;
3080                     case 3: op = rv_op_vfcvt_f_x_v; break;
3081                     case 6: op = rv_op_vfcvt_rtz_xu_f_v; break;
3082                     case 7: op = rv_op_vfcvt_rtz_x_f_v; break;
3083                     case 8: op = rv_op_vfwcvt_xu_f_v; break;
3084                     case 9: op = rv_op_vfwcvt_x_f_v; break;
3085                     case 10: op = rv_op_vfwcvt_f_xu_v; break;
3086                     case 11: op = rv_op_vfwcvt_f_x_v; break;
3087                     case 12: op = rv_op_vfwcvt_f_f_v; break;
3088                     case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
3089                     case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
3090                     case 16: op = rv_op_vfncvt_xu_f_w; break;
3091                     case 17: op = rv_op_vfncvt_x_f_w; break;
3092                     case 18: op = rv_op_vfncvt_f_xu_w; break;
3093                     case 19: op = rv_op_vfncvt_f_x_w; break;
3094                     case 20: op = rv_op_vfncvt_f_f_w; break;
3095                     case 21: op = rv_op_vfncvt_rod_f_f_w; break;
3096                     case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
3097                     case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
3098                     }
3099                     break;
3100                 case 19:
3101                     switch ((inst >> 15) & 0b11111) {
3102                     case 0: op = rv_op_vfsqrt_v; break;
3103                     case 4: op = rv_op_vfrsqrt7_v; break;
3104                     case 5: op = rv_op_vfrec7_v; break;
3105                     case 16: op = rv_op_vfclass_v; break;
3106                     }
3107                     break;
3108                 case 24: op = rv_op_vmfeq_vv; break;
3109                 case 25: op = rv_op_vmfle_vv; break;
3110                 case 27: op = rv_op_vmflt_vv; break;
3111                 case 28: op = rv_op_vmfne_vv; break;
3112                 case 32: op = rv_op_vfdiv_vv; break;
3113                 case 36: op = rv_op_vfmul_vv; break;
3114                 case 40: op = rv_op_vfmadd_vv; break;
3115                 case 41: op = rv_op_vfnmadd_vv; break;
3116                 case 42: op = rv_op_vfmsub_vv; break;
3117                 case 43: op = rv_op_vfnmsub_vv; break;
3118                 case 44: op = rv_op_vfmacc_vv; break;
3119                 case 45: op = rv_op_vfnmacc_vv; break;
3120                 case 46: op = rv_op_vfmsac_vv; break;
3121                 case 47: op = rv_op_vfnmsac_vv; break;
3122                 case 48: op = rv_op_vfwadd_vv; break;
3123                 case 49: op = rv_op_vfwredusum_vs; break;
3124                 case 50: op = rv_op_vfwsub_vv; break;
3125                 case 51: op = rv_op_vfwredosum_vs; break;
3126                 case 52: op = rv_op_vfwadd_wv; break;
3127                 case 54: op = rv_op_vfwsub_wv; break;
3128                 case 56: op = rv_op_vfwmul_vv; break;
3129                 case 60: op = rv_op_vfwmacc_vv; break;
3130                 case 61: op = rv_op_vfwnmacc_vv; break;
3131                 case 62: op = rv_op_vfwmsac_vv; break;
3132                 case 63: op = rv_op_vfwnmsac_vv; break;
3133                 }
3134                 break;
3135             case 2:
3136                 switch ((inst >> 26) & 0b111111) {
3137                 case 0: op = rv_op_vredsum_vs; break;
3138                 case 1: op = rv_op_vredand_vs; break;
3139                 case 2: op = rv_op_vredor_vs; break;
3140                 case 3: op = rv_op_vredxor_vs; break;
3141                 case 4: op = rv_op_vredminu_vs; break;
3142                 case 5: op = rv_op_vredmin_vs; break;
3143                 case 6: op = rv_op_vredmaxu_vs; break;
3144                 case 7: op = rv_op_vredmax_vs; break;
3145                 case 8: op = rv_op_vaaddu_vv; break;
3146                 case 9: op = rv_op_vaadd_vv; break;
3147                 case 10: op = rv_op_vasubu_vv; break;
3148                 case 11: op = rv_op_vasub_vv; break;
3149                 case 16:
3150                     switch ((inst >> 15) & 0b11111) {
3151                     case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
3152                     case 16: op = rv_op_vcpop_m; break;
3153                     case 17: op = rv_op_vfirst_m; break;
3154                     }
3155                     break;
3156                 case 18:
3157                     switch ((inst >> 15) & 0b11111) {
3158                     case 2: op = rv_op_vzext_vf8; break;
3159                     case 3: op = rv_op_vsext_vf8; break;
3160                     case 4: op = rv_op_vzext_vf4; break;
3161                     case 5: op = rv_op_vsext_vf4; break;
3162                     case 6: op = rv_op_vzext_vf2; break;
3163                     case 7: op = rv_op_vsext_vf2; break;
3164                     }
3165                     break;
3166                 case 20:
3167                     switch ((inst >> 15) & 0b11111) {
3168                     case 1: op = rv_op_vmsbf_m;  break;
3169                     case 2: op = rv_op_vmsof_m; break;
3170                     case 3: op = rv_op_vmsif_m; break;
3171                     case 16: op = rv_op_viota_m; break;
3172                     case 17:
3173                         if (((inst >> 20) & 0b11111) == 0) {
3174                             op = rv_op_vid_v;
3175                         }
3176                         break;
3177                     }
3178                     break;
3179                 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
3180                 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break;
3181                 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break;
3182                 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break;
3183                 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break;
3184                 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break;
3185                 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break;
3186                 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break;
3187                 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break;
3188                 case 32: op = rv_op_vdivu_vv; break;
3189                 case 33: op = rv_op_vdiv_vv; break;
3190                 case 34: op = rv_op_vremu_vv; break;
3191                 case 35: op = rv_op_vrem_vv; break;
3192                 case 36: op = rv_op_vmulhu_vv; break;
3193                 case 37: op = rv_op_vmul_vv; break;
3194                 case 38: op = rv_op_vmulhsu_vv; break;
3195                 case 39: op = rv_op_vmulh_vv; break;
3196                 case 41: op = rv_op_vmadd_vv; break;
3197                 case 43: op = rv_op_vnmsub_vv; break;
3198                 case 45: op = rv_op_vmacc_vv; break;
3199                 case 47: op = rv_op_vnmsac_vv; break;
3200                 case 48: op = rv_op_vwaddu_vv; break;
3201                 case 49: op = rv_op_vwadd_vv; break;
3202                 case 50: op = rv_op_vwsubu_vv; break;
3203                 case 51: op = rv_op_vwsub_vv; break;
3204                 case 52: op = rv_op_vwaddu_wv; break;
3205                 case 53: op = rv_op_vwadd_wv; break;
3206                 case 54: op = rv_op_vwsubu_wv; break;
3207                 case 55: op = rv_op_vwsub_wv; break;
3208                 case 56: op = rv_op_vwmulu_vv; break;
3209                 case 58: op = rv_op_vwmulsu_vv; break;
3210                 case 59: op = rv_op_vwmul_vv; break;
3211                 case 60: op = rv_op_vwmaccu_vv; break;
3212                 case 61: op = rv_op_vwmacc_vv; break;
3213                 case 63: op = rv_op_vwmaccsu_vv; break;
3214                 }
3215                 break;
3216             case 3:
3217                 switch ((inst >> 26) & 0b111111) {
3218                 case 0: op = rv_op_vadd_vi; break;
3219                 case 3: op = rv_op_vrsub_vi; break;
3220                 case 9: op = rv_op_vand_vi; break;
3221                 case 10: op = rv_op_vor_vi; break;
3222                 case 11: op = rv_op_vxor_vi; break;
3223                 case 12: op = rv_op_vrgather_vi; break;
3224                 case 14: op = rv_op_vslideup_vi; break;
3225                 case 15: op = rv_op_vslidedown_vi; break;
3226                 case 16:
3227                     if (((inst >> 25) & 1) == 0) {
3228                         op = rv_op_vadc_vim;
3229                     }
3230                     break;
3231                 case 17: op = rv_op_vmadc_vim; break;
3232                 case 23:
3233                     if (((inst >> 20) & 0b111111) == 32)
3234                         op = rv_op_vmv_v_i;
3235                     else if (((inst >> 25) & 1) == 0)
3236                         op = rv_op_vmerge_vim;
3237                     break;
3238                 case 24: op = rv_op_vmseq_vi; break;
3239                 case 25: op = rv_op_vmsne_vi; break;
3240                 case 28: op = rv_op_vmsleu_vi; break;
3241                 case 29: op = rv_op_vmsle_vi; break;
3242                 case 30: op = rv_op_vmsgtu_vi; break;
3243                 case 31: op = rv_op_vmsgt_vi; break;
3244                 case 32: op = rv_op_vsaddu_vi; break;
3245                 case 33: op = rv_op_vsadd_vi; break;
3246                 case 37: op = rv_op_vsll_vi; break;
3247                 case 39:
3248                     switch ((inst >> 15) & 0b11111) {
3249                     case 0: op = rv_op_vmv1r_v; break;
3250                     case 1: op = rv_op_vmv2r_v; break;
3251                     case 3: op = rv_op_vmv4r_v; break;
3252                     case 7: op = rv_op_vmv8r_v; break;
3253                     }
3254                     break;
3255                 case 40: op = rv_op_vsrl_vi; break;
3256                 case 41: op = rv_op_vsra_vi; break;
3257                 case 42: op = rv_op_vssrl_vi; break;
3258                 case 43: op = rv_op_vssra_vi; break;
3259                 case 44: op = rv_op_vnsrl_wi; break;
3260                 case 45: op = rv_op_vnsra_wi; break;
3261                 case 46: op = rv_op_vnclipu_wi; break;
3262                 case 47: op = rv_op_vnclip_wi; break;
3263                 }
3264                 break;
3265             case 4:
3266                 switch ((inst >> 26) & 0b111111) {
3267                 case 0: op = rv_op_vadd_vx; break;
3268                 case 2: op = rv_op_vsub_vx; break;
3269                 case 3: op = rv_op_vrsub_vx; break;
3270                 case 4: op = rv_op_vminu_vx; break;
3271                 case 5: op = rv_op_vmin_vx; break;
3272                 case 6: op = rv_op_vmaxu_vx; break;
3273                 case 7: op = rv_op_vmax_vx; break;
3274                 case 9: op = rv_op_vand_vx; break;
3275                 case 10: op = rv_op_vor_vx; break;
3276                 case 11: op = rv_op_vxor_vx; break;
3277                 case 12: op = rv_op_vrgather_vx; break;
3278                 case 14: op = rv_op_vslideup_vx; break;
3279                 case 15: op = rv_op_vslidedown_vx; break;
3280                 case 16:
3281                     if (((inst >> 25) & 1) == 0) {
3282                         op = rv_op_vadc_vxm;
3283                     }
3284                     break;
3285                 case 17: op = rv_op_vmadc_vxm; break;
3286                 case 18:
3287                     if (((inst >> 25) & 1) == 0) {
3288                         op = rv_op_vsbc_vxm;
3289                     }
3290                     break;
3291                 case 19: op = rv_op_vmsbc_vxm; break;
3292                 case 23:
3293                     if (((inst >> 20) & 0b111111) == 32)
3294                         op = rv_op_vmv_v_x;
3295                     else if (((inst >> 25) & 1) == 0)
3296                         op = rv_op_vmerge_vxm;
3297                     break;
3298                 case 24: op = rv_op_vmseq_vx; break;
3299                 case 25: op = rv_op_vmsne_vx; break;
3300                 case 26: op = rv_op_vmsltu_vx; break;
3301                 case 27: op = rv_op_vmslt_vx; break;
3302                 case 28: op = rv_op_vmsleu_vx; break;
3303                 case 29: op = rv_op_vmsle_vx; break;
3304                 case 30: op = rv_op_vmsgtu_vx; break;
3305                 case 31: op = rv_op_vmsgt_vx; break;
3306                 case 32: op = rv_op_vsaddu_vx; break;
3307                 case 33: op = rv_op_vsadd_vx; break;
3308                 case 34: op = rv_op_vssubu_vx; break;
3309                 case 35: op = rv_op_vssub_vx; break;
3310                 case 37: op = rv_op_vsll_vx; break;
3311                 case 39: op = rv_op_vsmul_vx; break;
3312                 case 40: op = rv_op_vsrl_vx; break;
3313                 case 41: op = rv_op_vsra_vx; break;
3314                 case 42: op = rv_op_vssrl_vx; break;
3315                 case 43: op = rv_op_vssra_vx; break;
3316                 case 44: op = rv_op_vnsrl_wx; break;
3317                 case 45: op = rv_op_vnsra_wx; break;
3318                 case 46: op = rv_op_vnclipu_wx; break;
3319                 case 47: op = rv_op_vnclip_wx; break;
3320                 }
3321                 break;
3322             case 5:
3323                 switch ((inst >> 26) & 0b111111) {
3324                 case 0: op = rv_op_vfadd_vf; break;
3325                 case 2: op = rv_op_vfsub_vf; break;
3326                 case 4: op = rv_op_vfmin_vf; break;
3327                 case 6: op = rv_op_vfmax_vf; break;
3328                 case 8: op = rv_op_vfsgnj_vf; break;
3329                 case 9: op = rv_op_vfsgnjn_vf; break;
3330                 case 10: op = rv_op_vfsgnjx_vf; break;
3331                 case 14: op = rv_op_vfslide1up_vf; break;
3332                 case 15: op = rv_op_vfslide1down_vf; break;
3333                 case 16:
3334                     switch ((inst >> 20) & 0b11111) {
3335                     case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break;
3336                     }
3337                     break;
3338                 case 23:
3339                     if (((inst >> 25) & 1) == 0)
3340                         op = rv_op_vfmerge_vfm;
3341                     else if (((inst >> 20) & 0b111111) == 32)
3342                         op = rv_op_vfmv_v_f;
3343                     break;
3344                 case 24: op = rv_op_vmfeq_vf; break;
3345                 case 25: op = rv_op_vmfle_vf; break;
3346                 case 27: op = rv_op_vmflt_vf; break;
3347                 case 28: op = rv_op_vmfne_vf; break;
3348                 case 29: op = rv_op_vmfgt_vf; break;
3349                 case 31: op = rv_op_vmfge_vf; break;
3350                 case 32: op = rv_op_vfdiv_vf; break;
3351                 case 33: op = rv_op_vfrdiv_vf; break;
3352                 case 36: op = rv_op_vfmul_vf; break;
3353                 case 39: op = rv_op_vfrsub_vf; break;
3354                 case 40: op = rv_op_vfmadd_vf; break;
3355                 case 41: op = rv_op_vfnmadd_vf; break;
3356                 case 42: op = rv_op_vfmsub_vf; break;
3357                 case 43: op = rv_op_vfnmsub_vf; break;
3358                 case 44: op = rv_op_vfmacc_vf; break;
3359                 case 45: op = rv_op_vfnmacc_vf; break;
3360                 case 46: op = rv_op_vfmsac_vf; break;
3361                 case 47: op = rv_op_vfnmsac_vf; break;
3362                 case 48: op = rv_op_vfwadd_vf; break;
3363                 case 50: op = rv_op_vfwsub_vf; break;
3364                 case 52: op = rv_op_vfwadd_wf; break;
3365                 case 54: op = rv_op_vfwsub_wf; break;
3366                 case 56: op = rv_op_vfwmul_vf; break;
3367                 case 60: op = rv_op_vfwmacc_vf; break;
3368                 case 61: op = rv_op_vfwnmacc_vf; break;
3369                 case 62: op = rv_op_vfwmsac_vf; break;
3370                 case 63: op = rv_op_vfwnmsac_vf; break;
3371                 }
3372                 break;
3373             case 6:
3374                 switch ((inst >> 26) & 0b111111) {
3375                 case 8: op = rv_op_vaaddu_vx; break;
3376                 case 9: op = rv_op_vaadd_vx; break;
3377                 case 10: op = rv_op_vasubu_vx; break;
3378                 case 11: op = rv_op_vasub_vx; break;
3379                 case 14: op = rv_op_vslide1up_vx; break;
3380                 case 15: op = rv_op_vslide1down_vx; break;
3381                 case 16:
3382                     switch ((inst >> 20) & 0b11111) {
3383                     case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break;
3384                     }
3385                     break;
3386                 case 32: op = rv_op_vdivu_vx; break;
3387                 case 33: op = rv_op_vdiv_vx; break;
3388                 case 34: op = rv_op_vremu_vx; break;
3389                 case 35: op = rv_op_vrem_vx; break;
3390                 case 36: op = rv_op_vmulhu_vx; break;
3391                 case 37: op = rv_op_vmul_vx; break;
3392                 case 38: op = rv_op_vmulhsu_vx; break;
3393                 case 39: op = rv_op_vmulh_vx; break;
3394                 case 41: op = rv_op_vmadd_vx; break;
3395                 case 43: op = rv_op_vnmsub_vx; break;
3396                 case 45: op = rv_op_vmacc_vx; break;
3397                 case 47: op = rv_op_vnmsac_vx; break;
3398                 case 48: op = rv_op_vwaddu_vx; break;
3399                 case 49: op = rv_op_vwadd_vx; break;
3400                 case 50: op = rv_op_vwsubu_vx; break;
3401                 case 51: op = rv_op_vwsub_vx; break;
3402                 case 52: op = rv_op_vwaddu_wx; break;
3403                 case 53: op = rv_op_vwadd_wx; break;
3404                 case 54: op = rv_op_vwsubu_wx; break;
3405                 case 55: op = rv_op_vwsub_wx; break;
3406                 case 56: op = rv_op_vwmulu_vx; break;
3407                 case 58: op = rv_op_vwmulsu_vx; break;
3408                 case 59: op = rv_op_vwmul_vx; break;
3409                 case 60: op = rv_op_vwmaccu_vx; break;
3410                 case 61: op = rv_op_vwmacc_vx; break;
3411                 case 62: op = rv_op_vwmaccus_vx; break;
3412                 case 63: op = rv_op_vwmaccsu_vx; break;
3413                 }
3414                 break;
3415             case 7:
3416                 if (((inst >> 31) & 1) == 0) {
3417                     op = rv_op_vsetvli;
3418                 } else if ((inst >> 30) & 1) {
3419                     op = rv_op_vsetivli;
3420                 } else if (((inst >> 25) & 0b11111) == 0) {
3421                     op = rv_op_vsetvl;
3422                 }
3423                 break;
3424             }
3425             break;
3426         case 22:
3427             switch ((inst >> 12) & 0b111) {
3428             case 0: op = rv_op_addid; break;
3429             case 1:
3430                 switch ((inst >> 26) & 0b111111) {
3431                 case 0: op = rv_op_sllid; break;
3432                 }
3433                 break;
3434             case 5:
3435                 switch ((inst >> 26) & 0b111111) {
3436                 case 0: op = rv_op_srlid; break;
3437                 case 16: op = rv_op_sraid; break;
3438                 }
3439                 break;
3440             }
3441             break;
3442         case 24:
3443             switch ((inst >> 12) & 0b111) {
3444             case 0: op = rv_op_beq; break;
3445             case 1: op = rv_op_bne; break;
3446             case 4: op = rv_op_blt; break;
3447             case 5: op = rv_op_bge; break;
3448             case 6: op = rv_op_bltu; break;
3449             case 7: op = rv_op_bgeu; break;
3450             }
3451             break;
3452         case 25:
3453             switch ((inst >> 12) & 0b111) {
3454             case 0: op = rv_op_jalr; break;
3455             }
3456             break;
3457         case 27: op = rv_op_jal; break;
3458         case 28:
3459             switch ((inst >> 12) & 0b111) {
3460             case 0:
3461                 switch (((inst >> 20) & 0b111111100000) |
3462                         ((inst >> 7) & 0b000000011111)) {
3463                 case 0:
3464                     switch ((inst >> 15) & 0b1111111111) {
3465                     case 0: op = rv_op_ecall; break;
3466                     case 32: op = rv_op_ebreak; break;
3467                     case 64: op = rv_op_uret; break;
3468                     }
3469                     break;
3470                 case 256:
3471                     switch ((inst >> 20) & 0b11111) {
3472                     case 2:
3473                         switch ((inst >> 15) & 0b11111) {
3474                         case 0: op = rv_op_sret; break;
3475                         }
3476                         break;
3477                     case 4: op = rv_op_sfence_vm; break;
3478                     case 5:
3479                         switch ((inst >> 15) & 0b11111) {
3480                         case 0: op = rv_op_wfi; break;
3481                         }
3482                         break;
3483                     }
3484                     break;
3485                 case 288: op = rv_op_sfence_vma; break;
3486                 case 512:
3487                     switch ((inst >> 15) & 0b1111111111) {
3488                     case 64: op = rv_op_hret; break;
3489                     }
3490                     break;
3491                 case 768:
3492                     switch ((inst >> 15) & 0b1111111111) {
3493                     case 64: op = rv_op_mret; break;
3494                     }
3495                     break;
3496                 case 1952:
3497                     switch ((inst >> 15) & 0b1111111111) {
3498                     case 576: op = rv_op_dret; break;
3499                     }
3500                     break;
3501                 }
3502                 break;
3503             case 1: op = rv_op_csrrw; break;
3504             case 2: op = rv_op_csrrs; break;
3505             case 3: op = rv_op_csrrc; break;
3506             case 5: op = rv_op_csrrwi; break;
3507             case 6: op = rv_op_csrrsi; break;
3508             case 7: op = rv_op_csrrci; break;
3509             }
3510             break;
3511         case 30:
3512             switch (((inst >> 22) & 0b1111111000) |
3513                     ((inst >> 12) & 0b0000000111)) {
3514             case 0: op = rv_op_addd; break;
3515             case 1: op = rv_op_slld; break;
3516             case 5: op = rv_op_srld; break;
3517             case 8: op = rv_op_muld; break;
3518             case 12: op = rv_op_divd; break;
3519             case 13: op = rv_op_divud; break;
3520             case 14: op = rv_op_remd; break;
3521             case 15: op = rv_op_remud; break;
3522             case 256: op = rv_op_subd; break;
3523             case 261: op = rv_op_srad; break;
3524             }
3525             break;
3526         }
3527         break;
3528     }
3529     dec->op = op;
3530 }
3531
3532 /* operand extractors */
3533
3534 static uint32_t operand_rd(rv_inst inst)
3535 {
3536     return (inst << 52) >> 59;
3537 }
3538
3539 static uint32_t operand_rs1(rv_inst inst)
3540 {
3541     return (inst << 44) >> 59;
3542 }
3543
3544 static uint32_t operand_rs2(rv_inst inst)
3545 {
3546     return (inst << 39) >> 59;
3547 }
3548
3549 static uint32_t operand_rs3(rv_inst inst)
3550 {
3551     return (inst << 32) >> 59;
3552 }
3553
3554 static uint32_t operand_aq(rv_inst inst)
3555 {
3556     return (inst << 37) >> 63;
3557 }
3558
3559 static uint32_t operand_rl(rv_inst inst)
3560 {
3561     return (inst << 38) >> 63;
3562 }
3563
3564 static uint32_t operand_pred(rv_inst inst)
3565 {
3566     return (inst << 36) >> 60;
3567 }
3568
3569 static uint32_t operand_succ(rv_inst inst)
3570 {
3571     return (inst << 40) >> 60;
3572 }
3573
3574 static uint32_t operand_rm(rv_inst inst)
3575 {
3576     return (inst << 49) >> 61;
3577 }
3578
3579 static uint32_t operand_shamt5(rv_inst inst)
3580 {
3581     return (inst << 39) >> 59;
3582 }
3583
3584 static uint32_t operand_shamt6(rv_inst inst)
3585 {
3586     return (inst << 38) >> 58;
3587 }
3588
3589 static uint32_t operand_shamt7(rv_inst inst)
3590 {
3591     return (inst << 37) >> 57;
3592 }
3593
3594 static uint32_t operand_crdq(rv_inst inst)
3595 {
3596     return (inst << 59) >> 61;
3597 }
3598
3599 static uint32_t operand_crs1q(rv_inst inst)
3600 {
3601     return (inst << 54) >> 61;
3602 }
3603
3604 static uint32_t operand_crs1rdq(rv_inst inst)
3605 {
3606     return (inst << 54) >> 61;
3607 }
3608
3609 static uint32_t operand_crs2q(rv_inst inst)
3610 {
3611     return (inst << 59) >> 61;
3612 }
3613
3614 static uint32_t calculate_xreg(uint32_t sreg)
3615 {
3616     return sreg < 2 ? sreg + 8 : sreg + 16;
3617 }
3618
3619 static uint32_t operand_sreg1(rv_inst inst)
3620 {
3621     return calculate_xreg((inst << 54) >> 61);
3622 }
3623
3624 static uint32_t operand_sreg2(rv_inst inst)
3625 {
3626     return calculate_xreg((inst << 59) >> 61);
3627 }
3628
3629 static uint32_t operand_crd(rv_inst inst)
3630 {
3631     return (inst << 52) >> 59;
3632 }
3633
3634 static uint32_t operand_crs1(rv_inst inst)
3635 {
3636     return (inst << 52) >> 59;
3637 }
3638
3639 static uint32_t operand_crs1rd(rv_inst inst)
3640 {
3641     return (inst << 52) >> 59;
3642 }
3643
3644 static uint32_t operand_crs2(rv_inst inst)
3645 {
3646     return (inst << 57) >> 59;
3647 }
3648
3649 static uint32_t operand_cimmsh5(rv_inst inst)
3650 {
3651     return (inst << 57) >> 59;
3652 }
3653
3654 static uint32_t operand_csr12(rv_inst inst)
3655 {
3656     return (inst << 32) >> 52;
3657 }
3658
3659 static int32_t operand_imm12(rv_inst inst)
3660 {
3661     return ((int64_t)inst << 32) >> 52;
3662 }
3663
3664 static int32_t operand_imm20(rv_inst inst)
3665 {
3666     return (((int64_t)inst << 32) >> 44) << 12;
3667 }
3668
3669 static int32_t operand_jimm20(rv_inst inst)
3670 {
3671     return (((int64_t)inst << 32) >> 63) << 20 |
3672         ((inst << 33) >> 54) << 1 |
3673         ((inst << 43) >> 63) << 11 |
3674         ((inst << 44) >> 56) << 12;
3675 }
3676
3677 static int32_t operand_simm12(rv_inst inst)
3678 {
3679     return (((int64_t)inst << 32) >> 57) << 5 |
3680         (inst << 52) >> 59;
3681 }
3682
3683 static int32_t operand_sbimm12(rv_inst inst)
3684 {
3685     return (((int64_t)inst << 32) >> 63) << 12 |
3686         ((inst << 33) >> 58) << 5 |
3687         ((inst << 52) >> 60) << 1 |
3688         ((inst << 56) >> 63) << 11;
3689 }
3690
3691 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
3692 {
3693     int imm = ((inst << 51) >> 63) << 5 |
3694         (inst << 57) >> 59;
3695     if (isa == rv128) {
3696         imm = imm ? imm : 64;
3697     }
3698     return imm;
3699 }
3700
3701 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
3702 {
3703     int imm = ((inst << 51) >> 63) << 5 |
3704         (inst << 57) >> 59;
3705     if (isa == rv128) {
3706         imm = imm | (imm & 32) << 1;
3707         imm = imm ? imm : 64;
3708     }
3709     return imm;
3710 }
3711
3712 static int32_t operand_cimmi(rv_inst inst)
3713 {
3714     return (((int64_t)inst << 51) >> 63) << 5 |
3715         (inst << 57) >> 59;
3716 }
3717
3718 static int32_t operand_cimmui(rv_inst inst)
3719 {
3720     return (((int64_t)inst << 51) >> 63) << 17 |
3721         ((inst << 57) >> 59) << 12;
3722 }
3723
3724 static uint32_t operand_cimmlwsp(rv_inst inst)
3725 {
3726     return ((inst << 51) >> 63) << 5 |
3727         ((inst << 57) >> 61) << 2 |
3728         ((inst << 60) >> 62) << 6;
3729 }
3730
3731 static uint32_t operand_cimmldsp(rv_inst inst)
3732 {
3733     return ((inst << 51) >> 63) << 5 |
3734         ((inst << 57) >> 62) << 3 |
3735         ((inst << 59) >> 61) << 6;
3736 }
3737
3738 static uint32_t operand_cimmlqsp(rv_inst inst)
3739 {
3740     return ((inst << 51) >> 63) << 5 |
3741         ((inst << 57) >> 63) << 4 |
3742         ((inst << 58) >> 60) << 6;
3743 }
3744
3745 static int32_t operand_cimm16sp(rv_inst inst)
3746 {
3747     return (((int64_t)inst << 51) >> 63) << 9 |
3748         ((inst << 57) >> 63) << 4 |
3749         ((inst << 58) >> 63) << 6 |
3750         ((inst << 59) >> 62) << 7 |
3751         ((inst << 61) >> 63) << 5;
3752 }
3753
3754 static int32_t operand_cimmj(rv_inst inst)
3755 {
3756     return (((int64_t)inst << 51) >> 63) << 11 |
3757         ((inst << 52) >> 63) << 4 |
3758         ((inst << 53) >> 62) << 8 |
3759         ((inst << 55) >> 63) << 10 |
3760         ((inst << 56) >> 63) << 6 |
3761         ((inst << 57) >> 63) << 7 |
3762         ((inst << 58) >> 61) << 1 |
3763         ((inst << 61) >> 63) << 5;
3764 }
3765
3766 static int32_t operand_cimmb(rv_inst inst)
3767 {
3768     return (((int64_t)inst << 51) >> 63) << 8 |
3769         ((inst << 52) >> 62) << 3 |
3770         ((inst << 57) >> 62) << 6 |
3771         ((inst << 59) >> 62) << 1 |
3772         ((inst << 61) >> 63) << 5;
3773 }
3774
3775 static uint32_t operand_cimmswsp(rv_inst inst)
3776 {
3777     return ((inst << 51) >> 60) << 2 |
3778         ((inst << 55) >> 62) << 6;
3779 }
3780
3781 static uint32_t operand_cimmsdsp(rv_inst inst)
3782 {
3783     return ((inst << 51) >> 61) << 3 |
3784         ((inst << 54) >> 61) << 6;
3785 }
3786
3787 static uint32_t operand_cimmsqsp(rv_inst inst)
3788 {
3789     return ((inst << 51) >> 62) << 4 |
3790         ((inst << 53) >> 60) << 6;
3791 }
3792
3793 static uint32_t operand_cimm4spn(rv_inst inst)
3794 {
3795     return ((inst << 51) >> 62) << 4 |
3796         ((inst << 53) >> 60) << 6 |
3797         ((inst << 57) >> 63) << 2 |
3798         ((inst << 58) >> 63) << 3;
3799 }
3800
3801 static uint32_t operand_cimmw(rv_inst inst)
3802 {
3803     return ((inst << 51) >> 61) << 3 |
3804         ((inst << 57) >> 63) << 2 |
3805         ((inst << 58) >> 63) << 6;
3806 }
3807
3808 static uint32_t operand_cimmd(rv_inst inst)
3809 {
3810     return ((inst << 51) >> 61) << 3 |
3811         ((inst << 57) >> 62) << 6;
3812 }
3813
3814 static uint32_t operand_cimmq(rv_inst inst)
3815 {
3816     return ((inst << 51) >> 62) << 4 |
3817         ((inst << 53) >> 63) << 8 |
3818         ((inst << 57) >> 62) << 6;
3819 }
3820
3821 static uint32_t operand_vimm(rv_inst inst)
3822 {
3823     return (int64_t)(inst << 44) >> 59;
3824 }
3825
3826 static uint32_t operand_vzimm11(rv_inst inst)
3827 {
3828     return (inst << 33) >> 53;
3829 }
3830
3831 static uint32_t operand_vzimm10(rv_inst inst)
3832 {
3833     return (inst << 34) >> 54;
3834 }
3835
3836 static uint32_t operand_bs(rv_inst inst)
3837 {
3838     return (inst << 32) >> 62;
3839 }
3840
3841 static uint32_t operand_rnum(rv_inst inst)
3842 {
3843     return (inst << 40) >> 60;
3844 }
3845
3846 static uint32_t operand_vm(rv_inst inst)
3847 {
3848     return (inst << 38) >> 63;
3849 }
3850
3851 static uint32_t operand_uimm_c_lb(rv_inst inst)
3852 {
3853     return (((inst << 58) >> 63) << 1) |
3854         ((inst << 57) >> 63);
3855 }
3856
3857 static uint32_t operand_uimm_c_lh(rv_inst inst)
3858 {
3859     return (((inst << 58) >> 63) << 1);
3860 }
3861
3862 static uint32_t operand_zcmp_spimm(rv_inst inst)
3863 {
3864     return ((inst << 60) >> 62) << 4;
3865 }
3866
3867 static uint32_t operand_zcmp_rlist(rv_inst inst)
3868 {
3869     return ((inst << 56) >> 60);
3870 }
3871
3872 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
3873 {
3874     int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
3875     int regs = rlist == 15 ? 13 : rlist - 3;
3876     uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
3877     return stack_adj_base + spimm;
3878 }
3879
3880 static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
3881 {
3882     return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
3883                                operand_zcmp_spimm(inst));
3884 }
3885
3886 static uint32_t operand_tbl_index(rv_inst inst)
3887 {
3888     return ((inst << 54) >> 56);
3889 }
3890
3891 /* decode operands */
3892
3893 static void decode_inst_operands(rv_decode *dec, rv_isa isa)
3894 {
3895     const rv_opcode_data *opcode_data = dec->opcode_data;
3896     rv_inst inst = dec->inst;
3897     dec->codec = opcode_data[dec->op].codec;
3898     switch (dec->codec) {
3899     case rv_codec_none:
3900         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
3901         dec->imm = 0;
3902         break;
3903     case rv_codec_u:
3904         dec->rd = operand_rd(inst);
3905         dec->rs1 = dec->rs2 = rv_ireg_zero;
3906         dec->imm = operand_imm20(inst);
3907         break;
3908     case rv_codec_uj:
3909         dec->rd = operand_rd(inst);
3910         dec->rs1 = dec->rs2 = rv_ireg_zero;
3911         dec->imm = operand_jimm20(inst);
3912         break;
3913     case rv_codec_i:
3914         dec->rd = operand_rd(inst);
3915         dec->rs1 = operand_rs1(inst);
3916         dec->rs2 = rv_ireg_zero;
3917         dec->imm = operand_imm12(inst);
3918         break;
3919     case rv_codec_i_sh5:
3920         dec->rd = operand_rd(inst);
3921         dec->rs1 = operand_rs1(inst);
3922         dec->rs2 = rv_ireg_zero;
3923         dec->imm = operand_shamt5(inst);
3924         break;
3925     case rv_codec_i_sh6:
3926         dec->rd = operand_rd(inst);
3927         dec->rs1 = operand_rs1(inst);
3928         dec->rs2 = rv_ireg_zero;
3929         dec->imm = operand_shamt6(inst);
3930         break;
3931     case rv_codec_i_sh7:
3932         dec->rd = operand_rd(inst);
3933         dec->rs1 = operand_rs1(inst);
3934         dec->rs2 = rv_ireg_zero;
3935         dec->imm = operand_shamt7(inst);
3936         break;
3937     case rv_codec_i_csr:
3938         dec->rd = operand_rd(inst);
3939         dec->rs1 = operand_rs1(inst);
3940         dec->rs2 = rv_ireg_zero;
3941         dec->imm = operand_csr12(inst);
3942         break;
3943     case rv_codec_s:
3944         dec->rd = rv_ireg_zero;
3945         dec->rs1 = operand_rs1(inst);
3946         dec->rs2 = operand_rs2(inst);
3947         dec->imm = operand_simm12(inst);
3948         break;
3949     case rv_codec_sb:
3950         dec->rd = rv_ireg_zero;
3951         dec->rs1 = operand_rs1(inst);
3952         dec->rs2 = operand_rs2(inst);
3953         dec->imm = operand_sbimm12(inst);
3954         break;
3955     case rv_codec_r:
3956         dec->rd = operand_rd(inst);
3957         dec->rs1 = operand_rs1(inst);
3958         dec->rs2 = operand_rs2(inst);
3959         dec->imm = 0;
3960         break;
3961     case rv_codec_r_m:
3962         dec->rd = operand_rd(inst);
3963         dec->rs1 = operand_rs1(inst);
3964         dec->rs2 = operand_rs2(inst);
3965         dec->imm = 0;
3966         dec->rm = operand_rm(inst);
3967         break;
3968     case rv_codec_r4_m:
3969         dec->rd = operand_rd(inst);
3970         dec->rs1 = operand_rs1(inst);
3971         dec->rs2 = operand_rs2(inst);
3972         dec->rs3 = operand_rs3(inst);
3973         dec->imm = 0;
3974         dec->rm = operand_rm(inst);
3975         break;
3976     case rv_codec_r_a:
3977         dec->rd = operand_rd(inst);
3978         dec->rs1 = operand_rs1(inst);
3979         dec->rs2 = operand_rs2(inst);
3980         dec->imm = 0;
3981         dec->aq = operand_aq(inst);
3982         dec->rl = operand_rl(inst);
3983         break;
3984     case rv_codec_r_l:
3985         dec->rd = operand_rd(inst);
3986         dec->rs1 = operand_rs1(inst);
3987         dec->rs2 = rv_ireg_zero;
3988         dec->imm = 0;
3989         dec->aq = operand_aq(inst);
3990         dec->rl = operand_rl(inst);
3991         break;
3992     case rv_codec_r_f:
3993         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
3994         dec->pred = operand_pred(inst);
3995         dec->succ = operand_succ(inst);
3996         dec->imm = 0;
3997         break;
3998     case rv_codec_cb:
3999         dec->rd = rv_ireg_zero;
4000         dec->rs1 = operand_crs1q(inst) + 8;
4001         dec->rs2 = rv_ireg_zero;
4002         dec->imm = operand_cimmb(inst);
4003         break;
4004     case rv_codec_cb_imm:
4005         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4006         dec->rs2 = rv_ireg_zero;
4007         dec->imm = operand_cimmi(inst);
4008         break;
4009     case rv_codec_cb_sh5:
4010         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4011         dec->rs2 = rv_ireg_zero;
4012         dec->imm = operand_cimmsh5(inst);
4013         break;
4014     case rv_codec_cb_sh6:
4015         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4016         dec->rs2 = rv_ireg_zero;
4017         dec->imm = operand_cimmshr6(inst, isa);
4018         break;
4019     case rv_codec_ci:
4020         dec->rd = dec->rs1 = operand_crs1rd(inst);
4021         dec->rs2 = rv_ireg_zero;
4022         dec->imm = operand_cimmi(inst);
4023         break;
4024     case rv_codec_ci_sh5:
4025         dec->rd = dec->rs1 = operand_crs1rd(inst);
4026         dec->rs2 = rv_ireg_zero;
4027         dec->imm = operand_cimmsh5(inst);
4028         break;
4029     case rv_codec_ci_sh6:
4030         dec->rd = dec->rs1 = operand_crs1rd(inst);
4031         dec->rs2 = rv_ireg_zero;
4032         dec->imm = operand_cimmshl6(inst, isa);
4033         break;
4034     case rv_codec_ci_16sp:
4035         dec->rd = rv_ireg_sp;
4036         dec->rs1 = rv_ireg_sp;
4037         dec->rs2 = rv_ireg_zero;
4038         dec->imm = operand_cimm16sp(inst);
4039         break;
4040     case rv_codec_ci_lwsp:
4041         dec->rd = operand_crd(inst);
4042         dec->rs1 = rv_ireg_sp;
4043         dec->rs2 = rv_ireg_zero;
4044         dec->imm = operand_cimmlwsp(inst);
4045         break;
4046     case rv_codec_ci_ldsp:
4047         dec->rd = operand_crd(inst);
4048         dec->rs1 = rv_ireg_sp;
4049         dec->rs2 = rv_ireg_zero;
4050         dec->imm = operand_cimmldsp(inst);
4051         break;
4052     case rv_codec_ci_lqsp:
4053         dec->rd = operand_crd(inst);
4054         dec->rs1 = rv_ireg_sp;
4055         dec->rs2 = rv_ireg_zero;
4056         dec->imm = operand_cimmlqsp(inst);
4057         break;
4058     case rv_codec_ci_li:
4059         dec->rd = operand_crd(inst);
4060         dec->rs1 = rv_ireg_zero;
4061         dec->rs2 = rv_ireg_zero;
4062         dec->imm = operand_cimmi(inst);
4063         break;
4064     case rv_codec_ci_lui:
4065         dec->rd = operand_crd(inst);
4066         dec->rs1 = rv_ireg_zero;
4067         dec->rs2 = rv_ireg_zero;
4068         dec->imm = operand_cimmui(inst);
4069         break;
4070     case rv_codec_ci_none:
4071         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4072         dec->imm = 0;
4073         break;
4074     case rv_codec_ciw_4spn:
4075         dec->rd = operand_crdq(inst) + 8;
4076         dec->rs1 = rv_ireg_sp;
4077         dec->rs2 = rv_ireg_zero;
4078         dec->imm = operand_cimm4spn(inst);
4079         break;
4080     case rv_codec_cj:
4081         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4082         dec->imm = operand_cimmj(inst);
4083         break;
4084     case rv_codec_cj_jal:
4085         dec->rd = rv_ireg_ra;
4086         dec->rs1 = dec->rs2 = rv_ireg_zero;
4087         dec->imm = operand_cimmj(inst);
4088         break;
4089     case rv_codec_cl_lw:
4090         dec->rd = operand_crdq(inst) + 8;
4091         dec->rs1 = operand_crs1q(inst) + 8;
4092         dec->rs2 = rv_ireg_zero;
4093         dec->imm = operand_cimmw(inst);
4094         break;
4095     case rv_codec_cl_ld:
4096         dec->rd = operand_crdq(inst) + 8;
4097         dec->rs1 = operand_crs1q(inst) + 8;
4098         dec->rs2 = rv_ireg_zero;
4099         dec->imm = operand_cimmd(inst);
4100         break;
4101     case rv_codec_cl_lq:
4102         dec->rd = operand_crdq(inst) + 8;
4103         dec->rs1 = operand_crs1q(inst) + 8;
4104         dec->rs2 = rv_ireg_zero;
4105         dec->imm = operand_cimmq(inst);
4106         break;
4107     case rv_codec_cr:
4108         dec->rd = dec->rs1 = operand_crs1rd(inst);
4109         dec->rs2 = operand_crs2(inst);
4110         dec->imm = 0;
4111         break;
4112     case rv_codec_cr_mv:
4113         dec->rd = operand_crd(inst);
4114         dec->rs1 = operand_crs2(inst);
4115         dec->rs2 = rv_ireg_zero;
4116         dec->imm = 0;
4117         break;
4118     case rv_codec_cr_jalr:
4119         dec->rd = rv_ireg_ra;
4120         dec->rs1 = operand_crs1(inst);
4121         dec->rs2 = rv_ireg_zero;
4122         dec->imm = 0;
4123         break;
4124     case rv_codec_cr_jr:
4125         dec->rd = rv_ireg_zero;
4126         dec->rs1 = operand_crs1(inst);
4127         dec->rs2 = rv_ireg_zero;
4128         dec->imm = 0;
4129         break;
4130     case rv_codec_cs:
4131         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4132         dec->rs2 = operand_crs2q(inst) + 8;
4133         dec->imm = 0;
4134         break;
4135     case rv_codec_cs_sw:
4136         dec->rd = rv_ireg_zero;
4137         dec->rs1 = operand_crs1q(inst) + 8;
4138         dec->rs2 = operand_crs2q(inst) + 8;
4139         dec->imm = operand_cimmw(inst);
4140         break;
4141     case rv_codec_cs_sd:
4142         dec->rd = rv_ireg_zero;
4143         dec->rs1 = operand_crs1q(inst) + 8;
4144         dec->rs2 = operand_crs2q(inst) + 8;
4145         dec->imm = operand_cimmd(inst);
4146         break;
4147     case rv_codec_cs_sq:
4148         dec->rd = rv_ireg_zero;
4149         dec->rs1 = operand_crs1q(inst) + 8;
4150         dec->rs2 = operand_crs2q(inst) + 8;
4151         dec->imm = operand_cimmq(inst);
4152         break;
4153     case rv_codec_css_swsp:
4154         dec->rd = rv_ireg_zero;
4155         dec->rs1 = rv_ireg_sp;
4156         dec->rs2 = operand_crs2(inst);
4157         dec->imm = operand_cimmswsp(inst);
4158         break;
4159     case rv_codec_css_sdsp:
4160         dec->rd = rv_ireg_zero;
4161         dec->rs1 = rv_ireg_sp;
4162         dec->rs2 = operand_crs2(inst);
4163         dec->imm = operand_cimmsdsp(inst);
4164         break;
4165     case rv_codec_css_sqsp:
4166         dec->rd = rv_ireg_zero;
4167         dec->rs1 = rv_ireg_sp;
4168         dec->rs2 = operand_crs2(inst);
4169         dec->imm = operand_cimmsqsp(inst);
4170         break;
4171     case rv_codec_k_bs:
4172         dec->rs1 = operand_rs1(inst);
4173         dec->rs2 = operand_rs2(inst);
4174         dec->bs = operand_bs(inst);
4175         break;
4176     case rv_codec_k_rnum:
4177         dec->rd = operand_rd(inst);
4178         dec->rs1 = operand_rs1(inst);
4179         dec->rnum = operand_rnum(inst);
4180         break;
4181     case rv_codec_v_r:
4182         dec->rd = operand_rd(inst);
4183         dec->rs1 = operand_rs1(inst);
4184         dec->rs2 = operand_rs2(inst);
4185         dec->vm = operand_vm(inst);
4186         break;
4187     case rv_codec_v_ldst:
4188         dec->rd = operand_rd(inst);
4189         dec->rs1 = operand_rs1(inst);
4190         dec->vm = operand_vm(inst);
4191         break;
4192     case rv_codec_v_i:
4193         dec->rd = operand_rd(inst);
4194         dec->rs2 = operand_rs2(inst);
4195         dec->imm = operand_vimm(inst);
4196         dec->vm = operand_vm(inst);
4197         break;
4198     case rv_codec_vsetvli:
4199         dec->rd = operand_rd(inst);
4200         dec->rs1 = operand_rs1(inst);
4201         dec->vzimm = operand_vzimm11(inst);
4202         break;
4203     case rv_codec_vsetivli:
4204         dec->rd = operand_rd(inst);
4205         dec->imm = operand_vimm(inst);
4206         dec->vzimm = operand_vzimm10(inst);
4207         break;
4208     case rv_codec_zcb_lb:
4209         dec->rs1 = operand_crs1q(inst) + 8;
4210         dec->rs2 = operand_crs2q(inst) + 8;
4211         dec->imm = operand_uimm_c_lb(inst);
4212         break;
4213     case rv_codec_zcb_lh:
4214         dec->rs1 = operand_crs1q(inst) + 8;
4215         dec->rs2 = operand_crs2q(inst) + 8;
4216         dec->imm = operand_uimm_c_lh(inst);
4217         break;
4218     case rv_codec_zcb_ext:
4219         dec->rd = operand_crs1q(inst) + 8;
4220         break;
4221     case rv_codec_zcb_mul:
4222         dec->rd = operand_crs1rdq(inst) + 8;
4223         dec->rs2 = operand_crs2q(inst) + 8;
4224         break;
4225     case rv_codec_zcmp_cm_pushpop:
4226         dec->imm = operand_zcmp_stack_adj(inst, isa);
4227         dec->rlist = operand_zcmp_rlist(inst);
4228         break;
4229     case rv_codec_zcmp_cm_mv:
4230         dec->rd = operand_sreg1(inst);
4231         dec->rs2 = operand_sreg2(inst);
4232         break;
4233     case rv_codec_zcmt_jt:
4234         dec->imm = operand_tbl_index(inst);
4235         break;
4236     };
4237 }
4238
4239 /* check constraint */
4240
4241 static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
4242 {
4243     int32_t imm = dec->imm;
4244     uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2;
4245     while (*c != rvc_end) {
4246         switch (*c) {
4247         case rvc_rd_eq_ra:
4248             if (!(rd == 1)) {
4249                 return false;
4250             }
4251             break;
4252         case rvc_rd_eq_x0:
4253             if (!(rd == 0)) {
4254                 return false;
4255             }
4256             break;
4257         case rvc_rs1_eq_x0:
4258             if (!(rs1 == 0)) {
4259                 return false;
4260             }
4261             break;
4262         case rvc_rs2_eq_x0:
4263             if (!(rs2 == 0)) {
4264                 return false;
4265             }
4266             break;
4267         case rvc_rs2_eq_rs1:
4268             if (!(rs2 == rs1)) {
4269                 return false;
4270             }
4271             break;
4272         case rvc_rs1_eq_ra:
4273             if (!(rs1 == 1)) {
4274                 return false;
4275             }
4276             break;
4277         case rvc_imm_eq_zero:
4278             if (!(imm == 0)) {
4279                 return false;
4280             }
4281             break;
4282         case rvc_imm_eq_n1:
4283             if (!(imm == -1)) {
4284                 return false;
4285             }
4286             break;
4287         case rvc_imm_eq_p1:
4288             if (!(imm == 1)) {
4289                 return false;
4290             }
4291             break;
4292         case rvc_csr_eq_0x001:
4293             if (!(imm == 0x001)) {
4294                 return false;
4295             }
4296             break;
4297         case rvc_csr_eq_0x002:
4298             if (!(imm == 0x002)) {
4299                 return false;
4300             }
4301             break;
4302         case rvc_csr_eq_0x003:
4303             if (!(imm == 0x003)) {
4304                 return false;
4305             }
4306             break;
4307         case rvc_csr_eq_0xc00:
4308             if (!(imm == 0xc00)) {
4309                 return false;
4310             }
4311             break;
4312         case rvc_csr_eq_0xc01:
4313             if (!(imm == 0xc01)) {
4314                 return false;
4315             }
4316             break;
4317         case rvc_csr_eq_0xc02:
4318             if (!(imm == 0xc02)) {
4319                 return false;
4320             }
4321             break;
4322         case rvc_csr_eq_0xc80:
4323             if (!(imm == 0xc80)) {
4324                 return false;
4325             }
4326             break;
4327         case rvc_csr_eq_0xc81:
4328             if (!(imm == 0xc81)) {
4329                 return false;
4330             }
4331             break;
4332         case rvc_csr_eq_0xc82:
4333             if (!(imm == 0xc82)) {
4334                 return false;
4335             }
4336             break;
4337         default: break;
4338         }
4339         c++;
4340     }
4341     return true;
4342 }
4343
4344 /* instruction length */
4345
4346 static size_t inst_length(rv_inst inst)
4347 {
4348     /* NOTE: supports maximum instruction size of 64-bits */
4349
4350     /*
4351      * instruction length coding
4352      *
4353      *      aa - 16 bit aa != 11
4354      *   bbb11 - 32 bit bbb != 111
4355      *  011111 - 48 bit
4356      * 0111111 - 64 bit
4357      */
4358
4359     return (inst &      0b11) != 0b11      ? 2
4360          : (inst &   0b11100) != 0b11100   ? 4
4361          : (inst &  0b111111) == 0b011111  ? 6
4362          : (inst & 0b1111111) == 0b0111111 ? 8
4363          : 0;
4364 }
4365
4366 /* format instruction */
4367
4368 static void append(char *s1, const char *s2, size_t n)
4369 {
4370     size_t l1 = strlen(s1);
4371     if (n - l1 - 1 > 0) {
4372         strncat(s1, s2, n - l1);
4373     }
4374 }
4375
4376 static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
4377 {
4378     const rv_opcode_data *opcode_data = dec->opcode_data;
4379     char tmp[64];
4380     const char *fmt;
4381
4382     fmt = opcode_data[dec->op].format;
4383     while (*fmt) {
4384         switch (*fmt) {
4385         case 'O':
4386             append(buf, opcode_data[dec->op].name, buflen);
4387             break;
4388         case '(':
4389             append(buf, "(", buflen);
4390             break;
4391         case ',':
4392             append(buf, ",", buflen);
4393             break;
4394         case ')':
4395             append(buf, ")", buflen);
4396             break;
4397         case '-':
4398             append(buf, "-", buflen);
4399             break;
4400         case 'b':
4401             snprintf(tmp, sizeof(tmp), "%d", dec->bs);
4402             append(buf, tmp, buflen);
4403             break;
4404         case 'n':
4405             snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
4406             append(buf, tmp, buflen);
4407             break;
4408         case '0':
4409             append(buf, rv_ireg_name_sym[dec->rd], buflen);
4410             break;
4411         case '1':
4412             append(buf, rv_ireg_name_sym[dec->rs1], buflen);
4413             break;
4414         case '2':
4415             append(buf, rv_ireg_name_sym[dec->rs2], buflen);
4416             break;
4417         case '3':
4418             append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rd] :
4419                                               rv_freg_name_sym[dec->rd],
4420                    buflen);
4421             break;
4422         case '4':
4423             append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs1] :
4424                                               rv_freg_name_sym[dec->rs1],
4425                    buflen);
4426             break;
4427         case '5':
4428             append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs2] :
4429                                               rv_freg_name_sym[dec->rs2],
4430                    buflen);
4431             break;
4432         case '6':
4433             append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs3] :
4434                                               rv_freg_name_sym[dec->rs3],
4435                    buflen);
4436             break;
4437         case '7':
4438             snprintf(tmp, sizeof(tmp), "%d", dec->rs1);
4439             append(buf, tmp, buflen);
4440             break;
4441         case 'i':
4442             snprintf(tmp, sizeof(tmp), "%d", dec->imm);
4443             append(buf, tmp, buflen);
4444             break;
4445         case 'u':
4446             snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111));
4447             append(buf, tmp, buflen);
4448             break;
4449         case 'o':
4450             snprintf(tmp, sizeof(tmp), "%d", dec->imm);
4451             append(buf, tmp, buflen);
4452             while (strlen(buf) < tab * 2) {
4453                 append(buf, " ", buflen);
4454             }
4455             snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64,
4456                 dec->pc + dec->imm);
4457             append(buf, tmp, buflen);
4458             break;
4459         case 'c': {
4460             const char *name = csr_name(dec->imm & 0xfff);
4461             if (name) {
4462                 append(buf, name, buflen);
4463             } else {
4464                 snprintf(tmp, sizeof(tmp), "0x%03x", dec->imm & 0xfff);
4465                 append(buf, tmp, buflen);
4466             }
4467             break;
4468         }
4469         case 'r':
4470             switch (dec->rm) {
4471             case rv_rm_rne:
4472                 append(buf, "rne", buflen);
4473                 break;
4474             case rv_rm_rtz:
4475                 append(buf, "rtz", buflen);
4476                 break;
4477             case rv_rm_rdn:
4478                 append(buf, "rdn", buflen);
4479                 break;
4480             case rv_rm_rup:
4481                 append(buf, "rup", buflen);
4482                 break;
4483             case rv_rm_rmm:
4484                 append(buf, "rmm", buflen);
4485                 break;
4486             case rv_rm_dyn:
4487                 append(buf, "dyn", buflen);
4488                 break;
4489             default:
4490                 append(buf, "inv", buflen);
4491                 break;
4492             }
4493             break;
4494         case 'p':
4495             if (dec->pred & rv_fence_i) {
4496                 append(buf, "i", buflen);
4497             }
4498             if (dec->pred & rv_fence_o) {
4499                 append(buf, "o", buflen);
4500             }
4501             if (dec->pred & rv_fence_r) {
4502                 append(buf, "r", buflen);
4503             }
4504             if (dec->pred & rv_fence_w) {
4505                 append(buf, "w", buflen);
4506             }
4507             break;
4508         case 's':
4509             if (dec->succ & rv_fence_i) {
4510                 append(buf, "i", buflen);
4511             }
4512             if (dec->succ & rv_fence_o) {
4513                 append(buf, "o", buflen);
4514             }
4515             if (dec->succ & rv_fence_r) {
4516                 append(buf, "r", buflen);
4517             }
4518             if (dec->succ & rv_fence_w) {
4519                 append(buf, "w", buflen);
4520             }
4521             break;
4522         case '\t':
4523             while (strlen(buf) < tab) {
4524                 append(buf, " ", buflen);
4525             }
4526             break;
4527         case 'A':
4528             if (dec->aq) {
4529                 append(buf, ".aq", buflen);
4530             }
4531             break;
4532         case 'R':
4533             if (dec->rl) {
4534                 append(buf, ".rl", buflen);
4535             }
4536             break;
4537         case 'l':
4538             append(buf, ",v0", buflen);
4539             break;
4540         case 'm':
4541             if (dec->vm == 0) {
4542                 append(buf, ",v0.t", buflen);
4543             }
4544             break;
4545         case 'D':
4546             append(buf, rv_vreg_name_sym[dec->rd], buflen);
4547             break;
4548         case 'E':
4549             append(buf, rv_vreg_name_sym[dec->rs1], buflen);
4550             break;
4551         case 'F':
4552             append(buf, rv_vreg_name_sym[dec->rs2], buflen);
4553             break;
4554         case 'G':
4555             append(buf, rv_vreg_name_sym[dec->rs3], buflen);
4556             break;
4557         case 'v': {
4558             char nbuf[32] = {0};
4559             const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3);
4560             sprintf(nbuf, "%d", sew);
4561             const int lmul = dec->vzimm & 0b11;
4562             const int flmul = (dec->vzimm >> 2) & 1;
4563             const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu";
4564             const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu";
4565             append(buf, "e", buflen);
4566             append(buf, nbuf, buflen);
4567             append(buf, ",m", buflen);
4568             if (flmul) {
4569                 switch (lmul) {
4570                 case 3:
4571                     sprintf(nbuf, "f2");
4572                     break;
4573                 case 2:
4574                     sprintf(nbuf, "f4");
4575                     break;
4576                 case 1:
4577                     sprintf(nbuf, "f8");
4578                 break;
4579                 }
4580                 append(buf, nbuf, buflen);
4581             } else {
4582                 sprintf(nbuf, "%d", 1 << lmul);
4583                 append(buf, nbuf, buflen);
4584             }
4585             append(buf, ",", buflen);
4586             append(buf, vta, buflen);
4587             append(buf, ",", buflen);
4588             append(buf, vma, buflen);
4589             break;
4590         }
4591         case 'x': {
4592             switch (dec->rlist) {
4593             case 4:
4594                 snprintf(tmp, sizeof(tmp), "{ra}");
4595                 break;
4596             case 5:
4597                 snprintf(tmp, sizeof(tmp), "{ra, s0}");
4598                 break;
4599             case 15:
4600                 snprintf(tmp, sizeof(tmp), "{ra, s0-s11}");
4601                 break;
4602             default:
4603                 snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5);
4604                 break;
4605             }
4606             append(buf, tmp, buflen);
4607             break;
4608         }
4609         default:
4610             break;
4611         }
4612         fmt++;
4613     }
4614 }
4615
4616 /* lift instruction to pseudo-instruction */
4617
4618 static void decode_inst_lift_pseudo(rv_decode *dec)
4619 {
4620     const rv_opcode_data *opcode_data = dec->opcode_data;
4621     const rv_comp_data *comp_data = opcode_data[dec->op].pseudo;
4622     if (!comp_data) {
4623         return;
4624     }
4625     while (comp_data->constraints) {
4626         if (check_constraints(dec, comp_data->constraints)) {
4627             dec->op = comp_data->op;
4628             dec->codec = opcode_data[dec->op].codec;
4629             return;
4630         }
4631         comp_data++;
4632     }
4633 }
4634
4635 /* decompress instruction */
4636
4637 static void decode_inst_decompress_rv32(rv_decode *dec)
4638 {
4639     const rv_opcode_data *opcode_data = dec->opcode_data;
4640     int decomp_op = opcode_data[dec->op].decomp_rv32;
4641     if (decomp_op != rv_op_illegal) {
4642         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4643             && dec->imm == 0) {
4644             dec->op = rv_op_illegal;
4645         } else {
4646             dec->op = decomp_op;
4647             dec->codec = opcode_data[decomp_op].codec;
4648         }
4649     }
4650 }
4651
4652 static void decode_inst_decompress_rv64(rv_decode *dec)
4653 {
4654     const rv_opcode_data *opcode_data = dec->opcode_data;
4655     int decomp_op = opcode_data[dec->op].decomp_rv64;
4656     if (decomp_op != rv_op_illegal) {
4657         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4658             && dec->imm == 0) {
4659             dec->op = rv_op_illegal;
4660         } else {
4661             dec->op = decomp_op;
4662             dec->codec = opcode_data[decomp_op].codec;
4663         }
4664     }
4665 }
4666
4667 static void decode_inst_decompress_rv128(rv_decode *dec)
4668 {
4669     const rv_opcode_data *opcode_data = dec->opcode_data;
4670     int decomp_op = opcode_data[dec->op].decomp_rv128;
4671     if (decomp_op != rv_op_illegal) {
4672         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4673             && dec->imm == 0) {
4674             dec->op = rv_op_illegal;
4675         } else {
4676             dec->op = decomp_op;
4677             dec->codec = opcode_data[decomp_op].codec;
4678         }
4679     }
4680 }
4681
4682 static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
4683 {
4684     switch (isa) {
4685     case rv32:
4686         decode_inst_decompress_rv32(dec);
4687         break;
4688     case rv64:
4689         decode_inst_decompress_rv64(dec);
4690         break;
4691     case rv128:
4692         decode_inst_decompress_rv128(dec);
4693         break;
4694     }
4695 }
4696
4697 /* disassemble instruction */
4698
4699 static void
4700 disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst,
4701             RISCVCPUConfig *cfg)
4702 {
4703     rv_decode dec = { 0 };
4704     dec.pc = pc;
4705     dec.inst = inst;
4706     dec.cfg = cfg;
4707
4708     static const struct {
4709         bool (*guard_func)(const RISCVCPUConfig *);
4710         const rv_opcode_data *opcode_data;
4711         void (*decode_func)(rv_decode *, rv_isa);
4712     } decoders[] = {
4713         { always_true_p, rvi_opcode_data, decode_inst_opcode },
4714         { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
4715     };
4716
4717     for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
4718         bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func;
4719         const rv_opcode_data *opcode_data = decoders[i].opcode_data;
4720         void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func;
4721
4722         if (guard_func(cfg)) {
4723             dec.opcode_data = opcode_data;
4724             decode_func(&dec, isa);
4725             if (dec.op != rv_op_illegal)
4726                 break;
4727         }
4728     }
4729
4730     if (dec.op == rv_op_illegal) {
4731         dec.opcode_data = rvi_opcode_data;
4732     }
4733
4734     decode_inst_operands(&dec, isa);
4735     decode_inst_decompress(&dec, isa);
4736     decode_inst_lift_pseudo(&dec);
4737     format_inst(buf, buflen, 24, &dec);
4738 }
4739
4740 #define INST_FMT_2 "%04" PRIx64 "              "
4741 #define INST_FMT_4 "%08" PRIx64 "          "
4742 #define INST_FMT_6 "%012" PRIx64 "      "
4743 #define INST_FMT_8 "%016" PRIx64 "  "
4744
4745 static int
4746 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
4747 {
4748     char buf[128] = { 0 };
4749     bfd_byte packet[2];
4750     rv_inst inst = 0;
4751     size_t len = 2;
4752     bfd_vma n;
4753     int status;
4754
4755     /* Instructions are made of 2-byte packets in little-endian order */
4756     for (n = 0; n < len; n += 2) {
4757         status = (*info->read_memory_func)(memaddr + n, packet, 2, info);
4758         if (status != 0) {
4759             /* Don't fail just because we fell off the end.  */
4760             if (n > 0) {
4761                 break;
4762             }
4763             (*info->memory_error_func)(status, memaddr, info);
4764             return status;
4765         }
4766         inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n);
4767         if (n == 0) {
4768             len = inst_length(inst);
4769         }
4770     }
4771
4772     switch (len) {
4773     case 2:
4774         (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
4775         break;
4776     case 4:
4777         (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
4778         break;
4779     case 6:
4780         (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
4781         break;
4782     default:
4783         (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
4784         break;
4785     }
4786
4787     disasm_inst(buf, sizeof(buf), isa, memaddr, inst,
4788                 (RISCVCPUConfig *)info->target_info);
4789     (*info->fprintf_func)(info->stream, "%s", buf);
4790
4791     return len;
4792 }
4793
4794 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info)
4795 {
4796     return print_insn_riscv(memaddr, info, rv32);
4797 }
4798
4799 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info)
4800 {
4801     return print_insn_riscv(memaddr, info, rv64);
4802 }
4803
4804 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info)
4805 {
4806     return print_insn_riscv(memaddr, info, rv128);
4807 }