docs/system/arm/emulation.rst

   1 A-profile CPU architecture support
   2 ==================================
   3
   4 QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and
   5 Armv8 versions of the A-profile architecture. It also has support for
   6 the following architecture extensions:
   7
   8 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
   9 - FEAT_AA32HPD (AArch32 hierarchical permission disables)
  10 - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
  11 - FEAT_AES (AESD and AESE instructions)
  12 - FEAT_BBM at level 2 (Translation table break-before-make levels)
  13 - FEAT_BF16 (AArch64 BFloat16 instructions)
  14 - FEAT_BTI (Branch Target Identification)
  15 - FEAT_CSV2 (Cache speculation variant 2)
  16 - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
  17 - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
  18 - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
  19 - FEAT_CSV3 (Cache speculation variant 3)
  20 - FEAT_DGH (Data gathering hint)
  21 - FEAT_DIT (Data Independent Timing instructions)
  22 - FEAT_DPB (DC CVAP instruction)
  23 - FEAT_Debugv8p2 (Debug changes for v8.2)
  24 - FEAT_Debugv8p4 (Debug changes for v8.4)
  25 - FEAT_DotProd (Advanced SIMD dot product instructions)
  26 - FEAT_FCMA (Floating-point complex number instructions)
  27 - FEAT_FHM (Floating-point half-precision multiplication instructions)
  28 - FEAT_FP16 (Half-precision floating-point data processing)
  29 - FEAT_FRINTTS (Floating-point to integer instructions)
  30 - FEAT_FlagM (Flag manipulation instructions v2)
  31 - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
  32 - FEAT_HPDS (Hierarchical permission disables)
  33 - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
  34 - FEAT_IESB (Implicit error synchronization event)
  35 - FEAT_JSCVT (JavaScript conversion instructions)
  36 - FEAT_LOR (Limited ordering regions)
  37 - FEAT_LPA (Large Physical Address space)
  38 - FEAT_LPA2 (Large Physical and virtual Address space v2)
  39 - FEAT_LRCPC (Load-acquire RCpc instructions)
  40 - FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
  41 - FEAT_LSE (Large System Extensions)
  42 - FEAT_LVA (Large Virtual Address space)
  43 - FEAT_MTE (Memory Tagging Extension)
  44 - FEAT_MTE2 (Memory Tagging Extension)
  45 - FEAT_MTE3 (MTE Asymmetric Fault Handling)
  46 - FEAT_PAN (Privileged access never)
  47 - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)
  48 - FEAT_PAuth (Pointer authentication)
  49 - FEAT_PMULL (PMULL, PMULL2 instructions)
  50 - FEAT_PMUv3p1 (PMU Extensions v3.1)
  51 - FEAT_PMUv3p4 (PMU Extensions v3.4)
  52 - FEAT_RAS (Reliability, availability, and serviceability)
  53 - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
  54 - FEAT_RNG (Random number generator)
  55 - FEAT_SB (Speculation Barrier)
  56 - FEAT_SEL2 (Secure EL2)
  57 - FEAT_SHA1 (SHA1 instructions)
  58 - FEAT_SHA256 (SHA256 instructions)
  59 - FEAT_SHA3 (Advanced SIMD SHA3 instructions)
  60 - FEAT_SHA512 (Advanced SIMD SHA512 instructions)
  61 - FEAT_SM3 (Advanced SIMD SM3 instructions)
  62 - FEAT_SM4 (Advanced SIMD SM4 instructions)
  63 - FEAT_SPECRES (Speculation restriction instructions)
  64 - FEAT_SSBS (Speculative Store Bypass Safe)
  65 - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
  66 - FEAT_TLBIRANGE (TLB invalidate range instructions)
  67 - FEAT_TTCNP (Translation table Common not private translations)
  68 - FEAT_TTL (Translation Table Level)
  69 - FEAT_TTST (Small translation tables)
  70 - FEAT_UAO (Unprivileged Access Override control)
  71 - FEAT_VHE (Virtualization Host Extensions)
  72 - FEAT_VMID16 (16-bit VMID)
  73 - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
  74 - SVE (The Scalable Vector Extension)
  75 - SVE2 (The Scalable Vector Extension v2)
  76
  77 For information on the specifics of these extensions, please refer
  78 to the `Armv8-A Arm Architecture Reference Manual
  79 <https://developer.arm.com/documentation/ddi0487/latest>`_.
  80
  81 When a specific named CPU is being emulated, only those features which
  82 are present in hardware for that CPU are emulated. (If a feature is
  83 not in the list above then it is not supported, even if the real
  84 hardware should have it.) The ``max`` CPU enables all features.
  85
  86 R-profile CPU architecture support
  87 ==================================
  88
  89 QEMU's TCG emulation support for R-profile CPUs is currently limited.
  90 We emulate only the Cortex-R5 and Cortex-R5F CPUs.
  91
  92 M-profile CPU architecture support
  93 ==================================
  94
  95 QEMU's TCG emulation includes support for Armv6-M, Armv7-M, Armv8-M, and
  96 Armv8.1-M versions of the M-profile architucture.  It also has support
  97 for the following architecture extensions:
  98
  99 - FP (Floating-point Extension)
 100 - FPCXT (FPCXT access instructions)
 101 - HP (Half-precision floating-point instructions)
 102 - LOB (Low Overhead loops and Branch future)
 103 - M (Main Extension)
 104 - MPU (Memory Protection Unit Extension)
 105 - PXN (Privileged Execute Never)
 106 - RAS (Reliability, Serviceability and Availability): "minimum RAS Extension" only
 107 - S (Security Extension)
 108 - ST (System Timer Extension)
 109
 110 For information on the specifics of these extensions, please refer
 111 to the `Armv8-M Arm Architecture Reference Manual
 112 <https://developer.arm.com/documentation/ddi0553/latest>`_.
 113
 114 When a specific named CPU is being emulated, only those features which
 115 are present in hardware for that CPU are emulated. (If a feature is
 116 not in the list above then it is not supported, even if the real
 117 hardware should have it.) There is no equivalent of the ``max`` CPU for
 118 M-profile.