2 * ACPI support for Intel Lynxpoint LPSS.
4 * Copyright (C) 2013, Intel Corporation
5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/acpi.h>
14 #include <linux/clkdev.h>
15 #include <linux/clk-provider.h>
16 #include <linux/err.h>
18 #include <linux/platform_device.h>
19 #include <linux/platform_data/clk-lpss.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/delay.h>
25 ACPI_MODULE_NAME("acpi_lpss");
27 #ifdef CONFIG_X86_INTEL_LPSS
29 #define LPSS_ADDR(desc) ((unsigned long)&desc)
31 #define LPSS_CLK_SIZE 0x04
32 #define LPSS_LTR_SIZE 0x18
34 /* Offsets relative to LPSS_PRIVATE_OFFSET */
35 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
36 #define LPSS_RESETS 0x04
37 #define LPSS_RESETS_RESET_FUNC BIT(0)
38 #define LPSS_RESETS_RESET_APB BIT(1)
39 #define LPSS_GENERAL 0x08
40 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
41 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
42 #define LPSS_SW_LTR 0x10
43 #define LPSS_AUTO_LTR 0x14
44 #define LPSS_LTR_SNOOP_REQ BIT(15)
45 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
46 #define LPSS_LTR_SNOOP_LAT_1US 0x800
47 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
48 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
49 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
50 #define LPSS_LTR_MAX_VAL 0x3FF
51 #define LPSS_TX_INT 0x20
52 #define LPSS_TX_INT_MASK BIT(1)
54 #define LPSS_PRV_REG_COUNT 9
57 #define LPSS_CLK BIT(0)
58 #define LPSS_CLK_GATE BIT(1)
59 #define LPSS_CLK_DIVIDER BIT(2)
60 #define LPSS_LTR BIT(3)
61 #define LPSS_SAVE_CTX BIT(4)
63 struct lpss_private_data
;
65 struct lpss_device_desc
{
67 const char *clk_con_id
;
68 unsigned int prv_offset
;
69 size_t prv_size_override
;
70 void (*setup
)(struct lpss_private_data
*pdata
);
73 static struct lpss_device_desc lpss_dma_desc
= {
77 struct lpss_private_data
{
78 void __iomem
*mmio_base
;
79 resource_size_t mmio_size
;
80 unsigned int fixed_clk_rate
;
82 const struct lpss_device_desc
*dev_desc
;
83 u32 prv_reg_ctx
[LPSS_PRV_REG_COUNT
];
86 /* UART Component Parameter Register */
87 #define LPSS_UART_CPR 0xF4
88 #define LPSS_UART_CPR_AFCE BIT(4)
90 static void lpss_uart_setup(struct lpss_private_data
*pdata
)
95 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_TX_INT
;
96 val
= readl(pdata
->mmio_base
+ offset
);
97 writel(val
| LPSS_TX_INT_MASK
, pdata
->mmio_base
+ offset
);
99 val
= readl(pdata
->mmio_base
+ LPSS_UART_CPR
);
100 if (!(val
& LPSS_UART_CPR_AFCE
)) {
101 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_GENERAL
;
102 val
= readl(pdata
->mmio_base
+ offset
);
103 val
|= LPSS_GENERAL_UART_RTS_OVRD
;
104 writel(val
, pdata
->mmio_base
+ offset
);
108 static void lpss_deassert_reset(struct lpss_private_data
*pdata
)
113 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_RESETS
;
114 val
= readl(pdata
->mmio_base
+ offset
);
115 val
|= LPSS_RESETS_RESET_APB
| LPSS_RESETS_RESET_FUNC
;
116 writel(val
, pdata
->mmio_base
+ offset
);
119 #define LPSS_I2C_ENABLE 0x6c
121 static void byt_i2c_setup(struct lpss_private_data
*pdata
)
123 lpss_deassert_reset(pdata
);
125 if (readl(pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
))
126 pdata
->fixed_clk_rate
= 133000000;
128 writel(0, pdata
->mmio_base
+ LPSS_I2C_ENABLE
);
131 static const struct lpss_device_desc lpt_dev_desc
= {
132 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_LTR
,
136 static const struct lpss_device_desc lpt_i2c_dev_desc
= {
137 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_LTR
,
141 static const struct lpss_device_desc lpt_uart_dev_desc
= {
142 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_LTR
,
143 .clk_con_id
= "baudclk",
145 .setup
= lpss_uart_setup
,
148 static const struct lpss_device_desc lpt_sdio_dev_desc
= {
150 .prv_offset
= 0x1000,
151 .prv_size_override
= 0x1018,
154 static const struct lpss_device_desc byt_pwm_dev_desc
= {
155 .flags
= LPSS_SAVE_CTX
,
158 static const struct lpss_device_desc byt_uart_dev_desc
= {
159 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
,
160 .clk_con_id
= "baudclk",
162 .setup
= lpss_uart_setup
,
165 static const struct lpss_device_desc byt_spi_dev_desc
= {
166 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
,
170 static const struct lpss_device_desc byt_sdio_dev_desc
= {
174 static const struct lpss_device_desc byt_i2c_dev_desc
= {
175 .flags
= LPSS_CLK
| LPSS_SAVE_CTX
,
177 .setup
= byt_i2c_setup
,
180 static struct lpss_device_desc bsw_spi_dev_desc
= {
181 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
,
183 .setup
= lpss_deassert_reset
,
188 #define LPSS_ADDR(desc) (0UL)
190 #endif /* CONFIG_X86_INTEL_LPSS */
192 static const struct acpi_device_id acpi_lpss_device_ids
[] = {
193 /* Generic LPSS devices */
194 { "INTL9C60", LPSS_ADDR(lpss_dma_desc
) },
196 /* Lynxpoint LPSS devices */
197 { "INT33C0", LPSS_ADDR(lpt_dev_desc
) },
198 { "INT33C1", LPSS_ADDR(lpt_dev_desc
) },
199 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc
) },
200 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc
) },
201 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc
) },
202 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc
) },
203 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc
) },
206 /* BayTrail LPSS devices */
207 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc
) },
208 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc
) },
209 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc
) },
210 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc
) },
211 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc
) },
215 /* Braswell LPSS devices */
216 { "80862288", LPSS_ADDR(byt_pwm_dev_desc
) },
217 { "8086228A", LPSS_ADDR(byt_uart_dev_desc
) },
218 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc
) },
219 { "808622C1", LPSS_ADDR(byt_i2c_dev_desc
) },
221 { "INT3430", LPSS_ADDR(lpt_dev_desc
) },
222 { "INT3431", LPSS_ADDR(lpt_dev_desc
) },
223 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc
) },
224 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc
) },
225 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc
) },
226 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc
) },
227 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc
) },
230 /* Wildcat Point LPSS devices */
231 { "INT3438", LPSS_ADDR(lpt_dev_desc
) },
236 #ifdef CONFIG_X86_INTEL_LPSS
238 static int is_memory(struct acpi_resource
*res
, void *not_used
)
241 return !acpi_dev_resource_memory(res
, &r
);
244 /* LPSS main clock device. */
245 static struct platform_device
*lpss_clk_dev
;
247 static inline void lpt_register_clock_device(void)
249 lpss_clk_dev
= platform_device_register_simple("clk-lpt", -1, NULL
, 0);
252 static int register_device_clock(struct acpi_device
*adev
,
253 struct lpss_private_data
*pdata
)
255 const struct lpss_device_desc
*dev_desc
= pdata
->dev_desc
;
256 const char *devname
= dev_name(&adev
->dev
);
257 struct clk
*clk
= ERR_PTR(-ENODEV
);
258 struct lpss_clk_data
*clk_data
;
259 const char *parent
, *clk_name
;
260 void __iomem
*prv_base
;
263 lpt_register_clock_device();
265 clk_data
= platform_get_drvdata(lpss_clk_dev
);
270 if (!pdata
->mmio_base
271 || pdata
->mmio_size
< dev_desc
->prv_offset
+ LPSS_CLK_SIZE
)
274 parent
= clk_data
->name
;
275 prv_base
= pdata
->mmio_base
+ dev_desc
->prv_offset
;
277 if (pdata
->fixed_clk_rate
) {
278 clk
= clk_register_fixed_rate(NULL
, devname
, parent
, 0,
279 pdata
->fixed_clk_rate
);
283 if (dev_desc
->flags
& LPSS_CLK_GATE
) {
284 clk
= clk_register_gate(NULL
, devname
, parent
, 0,
285 prv_base
, 0, 0, NULL
);
289 if (dev_desc
->flags
& LPSS_CLK_DIVIDER
) {
290 /* Prevent division by zero */
291 if (!readl(prv_base
))
292 writel(LPSS_CLK_DIVIDER_DEF_MASK
, prv_base
);
294 clk_name
= kasprintf(GFP_KERNEL
, "%s-div", devname
);
297 clk
= clk_register_fractional_divider(NULL
, clk_name
, parent
,
299 1, 15, 16, 15, 0, NULL
);
302 clk_name
= kasprintf(GFP_KERNEL
, "%s-update", devname
);
307 clk
= clk_register_gate(NULL
, clk_name
, parent
,
308 CLK_SET_RATE_PARENT
| CLK_SET_RATE_GATE
,
309 prv_base
, 31, 0, NULL
);
318 clk_register_clkdev(clk
, dev_desc
->clk_con_id
, devname
);
322 static int acpi_lpss_create_device(struct acpi_device
*adev
,
323 const struct acpi_device_id
*id
)
325 const struct lpss_device_desc
*dev_desc
;
326 struct lpss_private_data
*pdata
;
327 struct resource_entry
*rentry
;
328 struct list_head resource_list
;
329 struct platform_device
*pdev
;
332 dev_desc
= (const struct lpss_device_desc
*)id
->driver_data
;
334 pdev
= acpi_create_platform_device(adev
);
335 return IS_ERR_OR_NULL(pdev
) ? PTR_ERR(pdev
) : 1;
337 pdata
= kzalloc(sizeof(*pdata
), GFP_KERNEL
);
341 INIT_LIST_HEAD(&resource_list
);
342 ret
= acpi_dev_get_resources(adev
, &resource_list
, is_memory
, NULL
);
346 list_for_each_entry(rentry
, &resource_list
, node
)
347 if (resource_type(rentry
->res
) == IORESOURCE_MEM
) {
348 if (dev_desc
->prv_size_override
)
349 pdata
->mmio_size
= dev_desc
->prv_size_override
;
351 pdata
->mmio_size
= resource_size(rentry
->res
);
352 pdata
->mmio_base
= ioremap(rentry
->res
->start
,
357 acpi_dev_free_resource_list(&resource_list
);
359 if (!pdata
->mmio_base
) {
364 pdata
->dev_desc
= dev_desc
;
367 dev_desc
->setup(pdata
);
369 if (dev_desc
->flags
& LPSS_CLK
) {
370 ret
= register_device_clock(adev
, pdata
);
372 /* Skip the device, but continue the namespace scan. */
379 * This works around a known issue in ACPI tables where LPSS devices
380 * have _PS0 and _PS3 without _PSC (and no power resources), so
381 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
383 ret
= acpi_device_fix_up_power(adev
);
385 /* Skip the device, but continue the namespace scan. */
390 adev
->driver_data
= pdata
;
391 pdev
= acpi_create_platform_device(adev
);
392 if (!IS_ERR_OR_NULL(pdev
)) {
397 adev
->driver_data
= NULL
;
404 static u32
__lpss_reg_read(struct lpss_private_data
*pdata
, unsigned int reg
)
406 return readl(pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
+ reg
);
409 static void __lpss_reg_write(u32 val
, struct lpss_private_data
*pdata
,
412 writel(val
, pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
+ reg
);
415 static int lpss_reg_read(struct device
*dev
, unsigned int reg
, u32
*val
)
417 struct acpi_device
*adev
;
418 struct lpss_private_data
*pdata
;
422 ret
= acpi_bus_get_device(ACPI_HANDLE(dev
), &adev
);
426 spin_lock_irqsave(&dev
->power
.lock
, flags
);
427 if (pm_runtime_suspended(dev
)) {
431 pdata
= acpi_driver_data(adev
);
432 if (WARN_ON(!pdata
|| !pdata
->mmio_base
)) {
436 *val
= __lpss_reg_read(pdata
, reg
);
439 spin_unlock_irqrestore(&dev
->power
.lock
, flags
);
443 static ssize_t
lpss_ltr_show(struct device
*dev
, struct device_attribute
*attr
,
450 reg
= strcmp(attr
->attr
.name
, "auto_ltr") ? LPSS_SW_LTR
: LPSS_AUTO_LTR
;
451 ret
= lpss_reg_read(dev
, reg
, <r_value
);
455 return snprintf(buf
, PAGE_SIZE
, "%08x\n", ltr_value
);
458 static ssize_t
lpss_ltr_mode_show(struct device
*dev
,
459 struct device_attribute
*attr
, char *buf
)
465 ret
= lpss_reg_read(dev
, LPSS_GENERAL
, <r_mode
);
469 outstr
= (ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
) ? "sw" : "auto";
470 return sprintf(buf
, "%s\n", outstr
);
473 static DEVICE_ATTR(auto_ltr
, S_IRUSR
, lpss_ltr_show
, NULL
);
474 static DEVICE_ATTR(sw_ltr
, S_IRUSR
, lpss_ltr_show
, NULL
);
475 static DEVICE_ATTR(ltr_mode
, S_IRUSR
, lpss_ltr_mode_show
, NULL
);
477 static struct attribute
*lpss_attrs
[] = {
478 &dev_attr_auto_ltr
.attr
,
479 &dev_attr_sw_ltr
.attr
,
480 &dev_attr_ltr_mode
.attr
,
484 static struct attribute_group lpss_attr_group
= {
489 static void acpi_lpss_set_ltr(struct device
*dev
, s32 val
)
491 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
492 u32 ltr_mode
, ltr_val
;
494 ltr_mode
= __lpss_reg_read(pdata
, LPSS_GENERAL
);
496 if (ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
) {
497 ltr_mode
&= ~LPSS_GENERAL_LTR_MODE_SW
;
498 __lpss_reg_write(ltr_mode
, pdata
, LPSS_GENERAL
);
502 ltr_val
= __lpss_reg_read(pdata
, LPSS_SW_LTR
) & ~LPSS_LTR_SNOOP_MASK
;
503 if (val
>= LPSS_LTR_SNOOP_LAT_CUTOFF
) {
504 ltr_val
|= LPSS_LTR_SNOOP_LAT_32US
;
505 val
= LPSS_LTR_MAX_VAL
;
506 } else if (val
> LPSS_LTR_MAX_VAL
) {
507 ltr_val
|= LPSS_LTR_SNOOP_LAT_32US
| LPSS_LTR_SNOOP_REQ
;
508 val
>>= LPSS_LTR_SNOOP_LAT_SHIFT
;
510 ltr_val
|= LPSS_LTR_SNOOP_LAT_1US
| LPSS_LTR_SNOOP_REQ
;
513 __lpss_reg_write(ltr_val
, pdata
, LPSS_SW_LTR
);
514 if (!(ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
)) {
515 ltr_mode
|= LPSS_GENERAL_LTR_MODE_SW
;
516 __lpss_reg_write(ltr_mode
, pdata
, LPSS_GENERAL
);
522 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
524 * @pdata: pointer to the private data of the LPSS device
526 * Most LPSS devices have private registers which may loose their context when
527 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
530 static void acpi_lpss_save_ctx(struct device
*dev
,
531 struct lpss_private_data
*pdata
)
535 for (i
= 0; i
< LPSS_PRV_REG_COUNT
; i
++) {
536 unsigned long offset
= i
* sizeof(u32
);
538 pdata
->prv_reg_ctx
[i
] = __lpss_reg_read(pdata
, offset
);
539 dev_dbg(dev
, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
540 pdata
->prv_reg_ctx
[i
], offset
);
545 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
547 * @pdata: pointer to the private data of the LPSS device
549 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
551 static void acpi_lpss_restore_ctx(struct device
*dev
,
552 struct lpss_private_data
*pdata
)
557 * The following delay is needed or the subsequent write operations may
558 * fail. The LPSS devices are actually PCI devices and the PCI spec
559 * expects 10ms delay before the device can be accessed after D3 to D0
564 for (i
= 0; i
< LPSS_PRV_REG_COUNT
; i
++) {
565 unsigned long offset
= i
* sizeof(u32
);
567 __lpss_reg_write(pdata
->prv_reg_ctx
[i
], pdata
, offset
);
568 dev_dbg(dev
, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
569 pdata
->prv_reg_ctx
[i
], offset
);
573 #ifdef CONFIG_PM_SLEEP
574 static int acpi_lpss_suspend_late(struct device
*dev
)
576 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
579 ret
= pm_generic_suspend_late(dev
);
583 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
584 acpi_lpss_save_ctx(dev
, pdata
);
586 return acpi_dev_suspend_late(dev
);
589 static int acpi_lpss_resume_early(struct device
*dev
)
591 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
594 ret
= acpi_dev_resume_early(dev
);
598 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
599 acpi_lpss_restore_ctx(dev
, pdata
);
601 return pm_generic_resume_early(dev
);
603 #endif /* CONFIG_PM_SLEEP */
605 static int acpi_lpss_runtime_suspend(struct device
*dev
)
607 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
610 ret
= pm_generic_runtime_suspend(dev
);
614 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
615 acpi_lpss_save_ctx(dev
, pdata
);
617 return acpi_dev_runtime_suspend(dev
);
620 static int acpi_lpss_runtime_resume(struct device
*dev
)
622 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
625 ret
= acpi_dev_runtime_resume(dev
);
629 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
630 acpi_lpss_restore_ctx(dev
, pdata
);
632 return pm_generic_runtime_resume(dev
);
634 #endif /* CONFIG_PM */
636 static struct dev_pm_domain acpi_lpss_pm_domain
= {
639 #ifdef CONFIG_PM_SLEEP
640 .prepare
= acpi_subsys_prepare
,
641 .complete
= acpi_subsys_complete
,
642 .suspend
= acpi_subsys_suspend
,
643 .suspend_late
= acpi_lpss_suspend_late
,
644 .resume_early
= acpi_lpss_resume_early
,
645 .freeze
= acpi_subsys_freeze
,
646 .poweroff
= acpi_subsys_suspend
,
647 .poweroff_late
= acpi_lpss_suspend_late
,
648 .restore_early
= acpi_lpss_resume_early
,
650 .runtime_suspend
= acpi_lpss_runtime_suspend
,
651 .runtime_resume
= acpi_lpss_runtime_resume
,
656 static int acpi_lpss_platform_notify(struct notifier_block
*nb
,
657 unsigned long action
, void *data
)
659 struct platform_device
*pdev
= to_platform_device(data
);
660 struct lpss_private_data
*pdata
;
661 struct acpi_device
*adev
;
662 const struct acpi_device_id
*id
;
664 id
= acpi_match_device(acpi_lpss_device_ids
, &pdev
->dev
);
665 if (!id
|| !id
->driver_data
)
668 if (acpi_bus_get_device(ACPI_HANDLE(&pdev
->dev
), &adev
))
671 pdata
= acpi_driver_data(adev
);
675 if (pdata
->mmio_base
&&
676 pdata
->mmio_size
< pdata
->dev_desc
->prv_offset
+ LPSS_LTR_SIZE
) {
677 dev_err(&pdev
->dev
, "MMIO size insufficient to access LTR\n");
682 case BUS_NOTIFY_ADD_DEVICE
:
683 pdev
->dev
.pm_domain
= &acpi_lpss_pm_domain
;
684 if (pdata
->dev_desc
->flags
& LPSS_LTR
)
685 return sysfs_create_group(&pdev
->dev
.kobj
,
688 case BUS_NOTIFY_DEL_DEVICE
:
689 if (pdata
->dev_desc
->flags
& LPSS_LTR
)
690 sysfs_remove_group(&pdev
->dev
.kobj
, &lpss_attr_group
);
691 pdev
->dev
.pm_domain
= NULL
;
700 static struct notifier_block acpi_lpss_nb
= {
701 .notifier_call
= acpi_lpss_platform_notify
,
704 static void acpi_lpss_bind(struct device
*dev
)
706 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
708 if (!pdata
|| !pdata
->mmio_base
|| !(pdata
->dev_desc
->flags
& LPSS_LTR
))
711 if (pdata
->mmio_size
>= pdata
->dev_desc
->prv_offset
+ LPSS_LTR_SIZE
)
712 dev
->power
.set_latency_tolerance
= acpi_lpss_set_ltr
;
714 dev_err(dev
, "MMIO size insufficient to access LTR\n");
717 static void acpi_lpss_unbind(struct device
*dev
)
719 dev
->power
.set_latency_tolerance
= NULL
;
722 static struct acpi_scan_handler lpss_handler
= {
723 .ids
= acpi_lpss_device_ids
,
724 .attach
= acpi_lpss_create_device
,
725 .bind
= acpi_lpss_bind
,
726 .unbind
= acpi_lpss_unbind
,
729 void __init
acpi_lpss_init(void)
731 if (!lpt_clk_init()) {
732 bus_register_notifier(&platform_bus_type
, &acpi_lpss_nb
);
733 acpi_scan_add_handler(&lpss_handler
);
739 static struct acpi_scan_handler lpss_handler
= {
740 .ids
= acpi_lpss_device_ids
,
743 void __init
acpi_lpss_init(void)
745 acpi_scan_add_handler(&lpss_handler
);
748 #endif /* CONFIG_X86_INTEL_LPSS */