1 // SPDX-License-Identifier: GPL-2.0-only
3 * ACPI support for Intel Lynxpoint LPSS.
5 * Copyright (C) 2013, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
10 #include <linux/acpi.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/err.h>
15 #include <linux/mutex.h>
16 #include <linux/pci.h>
17 #include <linux/platform_device.h>
18 #include <linux/platform_data/x86/clk-lpss.h>
19 #include <linux/platform_data/x86/pmc_atom.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/pwm.h>
23 #include <linux/suspend.h>
24 #include <linux/delay.h>
28 ACPI_MODULE_NAME("acpi_lpss");
30 #ifdef CONFIG_X86_INTEL_LPSS
32 #include <asm/cpu_device_id.h>
33 #include <asm/intel-family.h>
34 #include <asm/iosf_mbi.h>
36 #define LPSS_ADDR(desc) ((unsigned long)&desc)
38 #define LPSS_CLK_SIZE 0x04
39 #define LPSS_LTR_SIZE 0x18
41 /* Offsets relative to LPSS_PRIVATE_OFFSET */
42 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
43 #define LPSS_RESETS 0x04
44 #define LPSS_RESETS_RESET_FUNC BIT(0)
45 #define LPSS_RESETS_RESET_APB BIT(1)
46 #define LPSS_GENERAL 0x08
47 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
48 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
49 #define LPSS_SW_LTR 0x10
50 #define LPSS_AUTO_LTR 0x14
51 #define LPSS_LTR_SNOOP_REQ BIT(15)
52 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
53 #define LPSS_LTR_SNOOP_LAT_1US 0x800
54 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
55 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
56 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
57 #define LPSS_LTR_MAX_VAL 0x3FF
58 #define LPSS_TX_INT 0x20
59 #define LPSS_TX_INT_MASK BIT(1)
61 #define LPSS_PRV_REG_COUNT 9
64 #define LPSS_CLK BIT(0)
65 #define LPSS_CLK_GATE BIT(1)
66 #define LPSS_CLK_DIVIDER BIT(2)
67 #define LPSS_LTR BIT(3)
68 #define LPSS_SAVE_CTX BIT(4)
69 #define LPSS_NO_D3_DELAY BIT(5)
71 /* Crystal Cove PMIC shares same ACPI ID between different platforms */
75 struct lpss_private_data
;
77 struct lpss_device_desc
{
79 const char *clk_con_id
;
80 unsigned int prv_offset
;
81 size_t prv_size_override
;
82 struct property_entry
*properties
;
83 void (*setup
)(struct lpss_private_data
*pdata
);
84 bool resume_from_noirq
;
87 static const struct lpss_device_desc lpss_dma_desc
= {
91 struct lpss_private_data
{
92 struct acpi_device
*adev
;
93 void __iomem
*mmio_base
;
94 resource_size_t mmio_size
;
95 unsigned int fixed_clk_rate
;
97 const struct lpss_device_desc
*dev_desc
;
98 u32 prv_reg_ctx
[LPSS_PRV_REG_COUNT
];
101 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
102 static u32 pmc_atom_d3_mask
= 0xfe000ffe;
104 /* LPSS run time quirks */
105 static unsigned int lpss_quirks
;
108 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
110 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
111 * it can be powered off automatically whenever the last LPSS device goes down.
112 * In case of no power any access to the DMA controller will hang the system.
113 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
114 * well as on ASuS T100TA transformer.
116 * This quirk overrides power state of entire LPSS island to keep DMA powered
117 * on whenever we have at least one other device in use.
119 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0)
121 /* UART Component Parameter Register */
122 #define LPSS_UART_CPR 0xF4
123 #define LPSS_UART_CPR_AFCE BIT(4)
125 static void lpss_uart_setup(struct lpss_private_data
*pdata
)
130 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_TX_INT
;
131 val
= readl(pdata
->mmio_base
+ offset
);
132 writel(val
| LPSS_TX_INT_MASK
, pdata
->mmio_base
+ offset
);
134 val
= readl(pdata
->mmio_base
+ LPSS_UART_CPR
);
135 if (!(val
& LPSS_UART_CPR_AFCE
)) {
136 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_GENERAL
;
137 val
= readl(pdata
->mmio_base
+ offset
);
138 val
|= LPSS_GENERAL_UART_RTS_OVRD
;
139 writel(val
, pdata
->mmio_base
+ offset
);
143 static void lpss_deassert_reset(struct lpss_private_data
*pdata
)
148 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_RESETS
;
149 val
= readl(pdata
->mmio_base
+ offset
);
150 val
|= LPSS_RESETS_RESET_APB
| LPSS_RESETS_RESET_FUNC
;
151 writel(val
, pdata
->mmio_base
+ offset
);
155 * BYT PWM used for backlight control by the i915 driver on systems without
156 * the Crystal Cove PMIC.
158 static struct pwm_lookup byt_pwm_lookup
[] = {
159 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
160 "pwm_backlight", 0, PWM_POLARITY_NORMAL
,
161 "pwm-lpss-platform"),
164 static void byt_pwm_setup(struct lpss_private_data
*pdata
)
166 struct acpi_device
*adev
= pdata
->adev
;
168 /* Only call pwm_add_table for the first PWM controller */
169 if (!adev
->pnp
.unique_id
|| strcmp(adev
->pnp
.unique_id
, "1"))
172 if (!acpi_dev_present("INT33FD", NULL
, BYT_CRC_HRV
))
173 pwm_add_table(byt_pwm_lookup
, ARRAY_SIZE(byt_pwm_lookup
));
176 #define LPSS_I2C_ENABLE 0x6c
178 static void byt_i2c_setup(struct lpss_private_data
*pdata
)
180 const char *uid_str
= acpi_device_uid(pdata
->adev
);
181 acpi_handle handle
= pdata
->adev
->handle
;
182 unsigned long long shared_host
= 0;
186 /* Expected to always be true, but better safe then sorry */
188 uid
= simple_strtol(uid_str
, NULL
, 10);
190 /* Detect I2C bus shared with PUNIT and ignore its d3 status */
191 status
= acpi_evaluate_integer(handle
, "_SEM", NULL
, &shared_host
);
192 if (ACPI_SUCCESS(status
) && shared_host
&& uid
)
193 pmc_atom_d3_mask
&= ~(BIT_LPSS2_F1_I2C1
<< (uid
- 1));
195 lpss_deassert_reset(pdata
);
197 if (readl(pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
))
198 pdata
->fixed_clk_rate
= 133000000;
200 writel(0, pdata
->mmio_base
+ LPSS_I2C_ENABLE
);
203 /* BSW PWM used for backlight control by the i915 driver */
204 static struct pwm_lookup bsw_pwm_lookup
[] = {
205 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
206 "pwm_backlight", 0, PWM_POLARITY_NORMAL
,
207 "pwm-lpss-platform"),
210 static void bsw_pwm_setup(struct lpss_private_data
*pdata
)
212 struct acpi_device
*adev
= pdata
->adev
;
214 /* Only call pwm_add_table for the first PWM controller */
215 if (!adev
->pnp
.unique_id
|| strcmp(adev
->pnp
.unique_id
, "1"))
218 pwm_add_table(bsw_pwm_lookup
, ARRAY_SIZE(bsw_pwm_lookup
));
221 static const struct lpss_device_desc lpt_dev_desc
= {
222 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_LTR
227 static const struct lpss_device_desc lpt_i2c_dev_desc
= {
228 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_LTR
| LPSS_SAVE_CTX
,
232 static struct property_entry uart_properties
[] = {
233 PROPERTY_ENTRY_U32("reg-io-width", 4),
234 PROPERTY_ENTRY_U32("reg-shift", 2),
235 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
239 static const struct lpss_device_desc lpt_uart_dev_desc
= {
240 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_LTR
242 .clk_con_id
= "baudclk",
244 .setup
= lpss_uart_setup
,
245 .properties
= uart_properties
,
248 static const struct lpss_device_desc lpt_sdio_dev_desc
= {
250 .prv_offset
= 0x1000,
251 .prv_size_override
= 0x1018,
254 static const struct lpss_device_desc byt_pwm_dev_desc
= {
255 .flags
= LPSS_SAVE_CTX
,
257 .setup
= byt_pwm_setup
,
260 static const struct lpss_device_desc bsw_pwm_dev_desc
= {
261 .flags
= LPSS_SAVE_CTX
| LPSS_NO_D3_DELAY
,
263 .setup
= bsw_pwm_setup
,
266 static const struct lpss_device_desc byt_uart_dev_desc
= {
267 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
,
268 .clk_con_id
= "baudclk",
270 .setup
= lpss_uart_setup
,
271 .properties
= uart_properties
,
274 static const struct lpss_device_desc bsw_uart_dev_desc
= {
275 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
277 .clk_con_id
= "baudclk",
279 .setup
= lpss_uart_setup
,
280 .properties
= uart_properties
,
283 static const struct lpss_device_desc byt_spi_dev_desc
= {
284 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
,
288 static const struct lpss_device_desc byt_sdio_dev_desc
= {
292 static const struct lpss_device_desc byt_i2c_dev_desc
= {
293 .flags
= LPSS_CLK
| LPSS_SAVE_CTX
,
295 .setup
= byt_i2c_setup
,
296 .resume_from_noirq
= true,
299 static const struct lpss_device_desc bsw_i2c_dev_desc
= {
300 .flags
= LPSS_CLK
| LPSS_SAVE_CTX
| LPSS_NO_D3_DELAY
,
302 .setup
= byt_i2c_setup
,
303 .resume_from_noirq
= true,
306 static const struct lpss_device_desc bsw_spi_dev_desc
= {
307 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
310 .setup
= lpss_deassert_reset
,
313 #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
315 static const struct x86_cpu_id lpss_cpu_ids
[] = {
316 ICPU(INTEL_FAM6_ATOM_SILVERMONT
), /* Valleyview, Bay Trail */
317 ICPU(INTEL_FAM6_ATOM_AIRMONT
), /* Braswell, Cherry Trail */
323 #define LPSS_ADDR(desc) (0UL)
325 #endif /* CONFIG_X86_INTEL_LPSS */
327 static const struct acpi_device_id acpi_lpss_device_ids
[] = {
328 /* Generic LPSS devices */
329 { "INTL9C60", LPSS_ADDR(lpss_dma_desc
) },
331 /* Lynxpoint LPSS devices */
332 { "INT33C0", LPSS_ADDR(lpt_dev_desc
) },
333 { "INT33C1", LPSS_ADDR(lpt_dev_desc
) },
334 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc
) },
335 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc
) },
336 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc
) },
337 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc
) },
338 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc
) },
341 /* BayTrail LPSS devices */
342 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc
) },
343 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc
) },
344 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc
) },
345 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc
) },
346 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc
) },
350 /* Braswell LPSS devices */
351 { "80862286", LPSS_ADDR(lpss_dma_desc
) },
352 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc
) },
353 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc
) },
354 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc
) },
355 { "808622C0", LPSS_ADDR(lpss_dma_desc
) },
356 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc
) },
358 /* Broadwell LPSS devices */
359 { "INT3430", LPSS_ADDR(lpt_dev_desc
) },
360 { "INT3431", LPSS_ADDR(lpt_dev_desc
) },
361 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc
) },
362 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc
) },
363 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc
) },
364 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc
) },
365 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc
) },
368 /* Wildcat Point LPSS devices */
369 { "INT3438", LPSS_ADDR(lpt_dev_desc
) },
374 #ifdef CONFIG_X86_INTEL_LPSS
376 static int is_memory(struct acpi_resource
*res
, void *not_used
)
379 return !acpi_dev_resource_memory(res
, &r
);
382 /* LPSS main clock device. */
383 static struct platform_device
*lpss_clk_dev
;
385 static inline void lpt_register_clock_device(void)
387 lpss_clk_dev
= platform_device_register_simple("clk-lpt", -1, NULL
, 0);
390 static int register_device_clock(struct acpi_device
*adev
,
391 struct lpss_private_data
*pdata
)
393 const struct lpss_device_desc
*dev_desc
= pdata
->dev_desc
;
394 const char *devname
= dev_name(&adev
->dev
);
396 struct lpss_clk_data
*clk_data
;
397 const char *parent
, *clk_name
;
398 void __iomem
*prv_base
;
401 lpt_register_clock_device();
403 clk_data
= platform_get_drvdata(lpss_clk_dev
);
408 if (!pdata
->mmio_base
409 || pdata
->mmio_size
< dev_desc
->prv_offset
+ LPSS_CLK_SIZE
)
412 parent
= clk_data
->name
;
413 prv_base
= pdata
->mmio_base
+ dev_desc
->prv_offset
;
415 if (pdata
->fixed_clk_rate
) {
416 clk
= clk_register_fixed_rate(NULL
, devname
, parent
, 0,
417 pdata
->fixed_clk_rate
);
421 if (dev_desc
->flags
& LPSS_CLK_GATE
) {
422 clk
= clk_register_gate(NULL
, devname
, parent
, 0,
423 prv_base
, 0, 0, NULL
);
427 if (dev_desc
->flags
& LPSS_CLK_DIVIDER
) {
428 /* Prevent division by zero */
429 if (!readl(prv_base
))
430 writel(LPSS_CLK_DIVIDER_DEF_MASK
, prv_base
);
432 clk_name
= kasprintf(GFP_KERNEL
, "%s-div", devname
);
435 clk
= clk_register_fractional_divider(NULL
, clk_name
, parent
,
437 1, 15, 16, 15, 0, NULL
);
440 clk_name
= kasprintf(GFP_KERNEL
, "%s-update", devname
);
445 clk
= clk_register_gate(NULL
, clk_name
, parent
,
446 CLK_SET_RATE_PARENT
| CLK_SET_RATE_GATE
,
447 prv_base
, 31, 0, NULL
);
456 clk_register_clkdev(clk
, dev_desc
->clk_con_id
, devname
);
460 struct lpss_device_links
{
461 const char *supplier_hid
;
462 const char *supplier_uid
;
463 const char *consumer_hid
;
464 const char *consumer_uid
;
469 * The _DEP method is used to identify dependencies but instead of creating
470 * device links for every handle in _DEP, only links in the following list are
471 * created. That is necessary because, in the general case, _DEP can refer to
472 * devices that might not have drivers, or that are on different buses, or where
473 * the supplier is not enumerated until after the consumer is probed.
475 static const struct lpss_device_links lpss_device_links
[] = {
476 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME
},
477 {"808622C1", "7", "LNXVIDEO", NULL
, DL_FLAG_PM_RUNTIME
},
478 {"80860F41", "5", "LNXVIDEO", NULL
, DL_FLAG_PM_RUNTIME
},
481 static bool hid_uid_match(struct acpi_device
*adev
,
482 const char *hid2
, const char *uid2
)
484 const char *hid1
= acpi_device_hid(adev
);
485 const char *uid1
= acpi_device_uid(adev
);
487 if (strcmp(hid1
, hid2
))
493 return uid1
&& !strcmp(uid1
, uid2
);
496 static bool acpi_lpss_is_supplier(struct acpi_device
*adev
,
497 const struct lpss_device_links
*link
)
499 return hid_uid_match(adev
, link
->supplier_hid
, link
->supplier_uid
);
502 static bool acpi_lpss_is_consumer(struct acpi_device
*adev
,
503 const struct lpss_device_links
*link
)
505 return hid_uid_match(adev
, link
->consumer_hid
, link
->consumer_uid
);
513 static int match_hid_uid(struct device
*dev
, const void *data
)
515 struct acpi_device
*adev
= ACPI_COMPANION(dev
);
516 const struct hid_uid
*id
= data
;
521 return hid_uid_match(adev
, id
->hid
, id
->uid
);
524 static struct device
*acpi_lpss_find_device(const char *hid
, const char *uid
)
528 struct hid_uid data
= {
533 dev
= bus_find_device(&platform_bus_type
, NULL
, &data
, match_hid_uid
);
537 return bus_find_device(&pci_bus_type
, NULL
, &data
, match_hid_uid
);
540 static bool acpi_lpss_dep(struct acpi_device
*adev
, acpi_handle handle
)
542 struct acpi_handle_list dep_devices
;
546 if (!acpi_has_method(adev
->handle
, "_DEP"))
549 status
= acpi_evaluate_reference(adev
->handle
, "_DEP", NULL
,
551 if (ACPI_FAILURE(status
)) {
552 dev_dbg(&adev
->dev
, "Failed to evaluate _DEP.\n");
556 for (i
= 0; i
< dep_devices
.count
; i
++) {
557 if (dep_devices
.handles
[i
] == handle
)
564 static void acpi_lpss_link_consumer(struct device
*dev1
,
565 const struct lpss_device_links
*link
)
569 dev2
= acpi_lpss_find_device(link
->consumer_hid
, link
->consumer_uid
);
573 if (acpi_lpss_dep(ACPI_COMPANION(dev2
), ACPI_HANDLE(dev1
)))
574 device_link_add(dev2
, dev1
, link
->flags
);
579 static void acpi_lpss_link_supplier(struct device
*dev1
,
580 const struct lpss_device_links
*link
)
584 dev2
= acpi_lpss_find_device(link
->supplier_hid
, link
->supplier_uid
);
588 if (acpi_lpss_dep(ACPI_COMPANION(dev1
), ACPI_HANDLE(dev2
)))
589 device_link_add(dev1
, dev2
, link
->flags
);
594 static void acpi_lpss_create_device_links(struct acpi_device
*adev
,
595 struct platform_device
*pdev
)
599 for (i
= 0; i
< ARRAY_SIZE(lpss_device_links
); i
++) {
600 const struct lpss_device_links
*link
= &lpss_device_links
[i
];
602 if (acpi_lpss_is_supplier(adev
, link
))
603 acpi_lpss_link_consumer(&pdev
->dev
, link
);
605 if (acpi_lpss_is_consumer(adev
, link
))
606 acpi_lpss_link_supplier(&pdev
->dev
, link
);
610 static int acpi_lpss_create_device(struct acpi_device
*adev
,
611 const struct acpi_device_id
*id
)
613 const struct lpss_device_desc
*dev_desc
;
614 struct lpss_private_data
*pdata
;
615 struct resource_entry
*rentry
;
616 struct list_head resource_list
;
617 struct platform_device
*pdev
;
620 dev_desc
= (const struct lpss_device_desc
*)id
->driver_data
;
622 pdev
= acpi_create_platform_device(adev
, NULL
);
623 return IS_ERR_OR_NULL(pdev
) ? PTR_ERR(pdev
) : 1;
625 pdata
= kzalloc(sizeof(*pdata
), GFP_KERNEL
);
629 INIT_LIST_HEAD(&resource_list
);
630 ret
= acpi_dev_get_resources(adev
, &resource_list
, is_memory
, NULL
);
634 list_for_each_entry(rentry
, &resource_list
, node
)
635 if (resource_type(rentry
->res
) == IORESOURCE_MEM
) {
636 if (dev_desc
->prv_size_override
)
637 pdata
->mmio_size
= dev_desc
->prv_size_override
;
639 pdata
->mmio_size
= resource_size(rentry
->res
);
640 pdata
->mmio_base
= ioremap(rentry
->res
->start
,
645 acpi_dev_free_resource_list(&resource_list
);
647 if (!pdata
->mmio_base
) {
648 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
649 adev
->pnp
.type
.platform_id
= 0;
650 /* Skip the device, but continue the namespace scan. */
656 pdata
->dev_desc
= dev_desc
;
659 dev_desc
->setup(pdata
);
661 if (dev_desc
->flags
& LPSS_CLK
) {
662 ret
= register_device_clock(adev
, pdata
);
664 /* Skip the device, but continue the namespace scan. */
671 * This works around a known issue in ACPI tables where LPSS devices
672 * have _PS0 and _PS3 without _PSC (and no power resources), so
673 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
675 acpi_device_fix_up_power(adev
);
677 adev
->driver_data
= pdata
;
678 pdev
= acpi_create_platform_device(adev
, dev_desc
->properties
);
679 if (!IS_ERR_OR_NULL(pdev
)) {
680 acpi_lpss_create_device_links(adev
, pdev
);
685 adev
->driver_data
= NULL
;
692 static u32
__lpss_reg_read(struct lpss_private_data
*pdata
, unsigned int reg
)
694 return readl(pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
+ reg
);
697 static void __lpss_reg_write(u32 val
, struct lpss_private_data
*pdata
,
700 writel(val
, pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
+ reg
);
703 static int lpss_reg_read(struct device
*dev
, unsigned int reg
, u32
*val
)
705 struct acpi_device
*adev
;
706 struct lpss_private_data
*pdata
;
710 ret
= acpi_bus_get_device(ACPI_HANDLE(dev
), &adev
);
714 spin_lock_irqsave(&dev
->power
.lock
, flags
);
715 if (pm_runtime_suspended(dev
)) {
719 pdata
= acpi_driver_data(adev
);
720 if (WARN_ON(!pdata
|| !pdata
->mmio_base
)) {
724 *val
= __lpss_reg_read(pdata
, reg
);
727 spin_unlock_irqrestore(&dev
->power
.lock
, flags
);
731 static ssize_t
lpss_ltr_show(struct device
*dev
, struct device_attribute
*attr
,
738 reg
= strcmp(attr
->attr
.name
, "auto_ltr") ? LPSS_SW_LTR
: LPSS_AUTO_LTR
;
739 ret
= lpss_reg_read(dev
, reg
, <r_value
);
743 return snprintf(buf
, PAGE_SIZE
, "%08x\n", ltr_value
);
746 static ssize_t
lpss_ltr_mode_show(struct device
*dev
,
747 struct device_attribute
*attr
, char *buf
)
753 ret
= lpss_reg_read(dev
, LPSS_GENERAL
, <r_mode
);
757 outstr
= (ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
) ? "sw" : "auto";
758 return sprintf(buf
, "%s\n", outstr
);
761 static DEVICE_ATTR(auto_ltr
, S_IRUSR
, lpss_ltr_show
, NULL
);
762 static DEVICE_ATTR(sw_ltr
, S_IRUSR
, lpss_ltr_show
, NULL
);
763 static DEVICE_ATTR(ltr_mode
, S_IRUSR
, lpss_ltr_mode_show
, NULL
);
765 static struct attribute
*lpss_attrs
[] = {
766 &dev_attr_auto_ltr
.attr
,
767 &dev_attr_sw_ltr
.attr
,
768 &dev_attr_ltr_mode
.attr
,
772 static const struct attribute_group lpss_attr_group
= {
777 static void acpi_lpss_set_ltr(struct device
*dev
, s32 val
)
779 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
780 u32 ltr_mode
, ltr_val
;
782 ltr_mode
= __lpss_reg_read(pdata
, LPSS_GENERAL
);
784 if (ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
) {
785 ltr_mode
&= ~LPSS_GENERAL_LTR_MODE_SW
;
786 __lpss_reg_write(ltr_mode
, pdata
, LPSS_GENERAL
);
790 ltr_val
= __lpss_reg_read(pdata
, LPSS_SW_LTR
) & ~LPSS_LTR_SNOOP_MASK
;
791 if (val
>= LPSS_LTR_SNOOP_LAT_CUTOFF
) {
792 ltr_val
|= LPSS_LTR_SNOOP_LAT_32US
;
793 val
= LPSS_LTR_MAX_VAL
;
794 } else if (val
> LPSS_LTR_MAX_VAL
) {
795 ltr_val
|= LPSS_LTR_SNOOP_LAT_32US
| LPSS_LTR_SNOOP_REQ
;
796 val
>>= LPSS_LTR_SNOOP_LAT_SHIFT
;
798 ltr_val
|= LPSS_LTR_SNOOP_LAT_1US
| LPSS_LTR_SNOOP_REQ
;
801 __lpss_reg_write(ltr_val
, pdata
, LPSS_SW_LTR
);
802 if (!(ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
)) {
803 ltr_mode
|= LPSS_GENERAL_LTR_MODE_SW
;
804 __lpss_reg_write(ltr_mode
, pdata
, LPSS_GENERAL
);
810 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
812 * @pdata: pointer to the private data of the LPSS device
814 * Most LPSS devices have private registers which may loose their context when
815 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
818 static void acpi_lpss_save_ctx(struct device
*dev
,
819 struct lpss_private_data
*pdata
)
823 for (i
= 0; i
< LPSS_PRV_REG_COUNT
; i
++) {
824 unsigned long offset
= i
* sizeof(u32
);
826 pdata
->prv_reg_ctx
[i
] = __lpss_reg_read(pdata
, offset
);
827 dev_dbg(dev
, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
828 pdata
->prv_reg_ctx
[i
], offset
);
833 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
835 * @pdata: pointer to the private data of the LPSS device
837 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
839 static void acpi_lpss_restore_ctx(struct device
*dev
,
840 struct lpss_private_data
*pdata
)
844 for (i
= 0; i
< LPSS_PRV_REG_COUNT
; i
++) {
845 unsigned long offset
= i
* sizeof(u32
);
847 __lpss_reg_write(pdata
->prv_reg_ctx
[i
], pdata
, offset
);
848 dev_dbg(dev
, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
849 pdata
->prv_reg_ctx
[i
], offset
);
853 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data
*pdata
)
856 * The following delay is needed or the subsequent write operations may
857 * fail. The LPSS devices are actually PCI devices and the PCI spec
858 * expects 10ms delay before the device can be accessed after D3 to D0
859 * transition. However some platforms like BSW does not need this delay.
861 unsigned int delay
= 10; /* default 10ms delay */
863 if (pdata
->dev_desc
->flags
& LPSS_NO_D3_DELAY
)
869 static int acpi_lpss_activate(struct device
*dev
)
871 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
874 ret
= acpi_dev_resume(dev
);
878 acpi_lpss_d3_to_d0_delay(pdata
);
881 * This is called only on ->probe() stage where a device is either in
882 * known state defined by BIOS or most likely powered off. Due to this
883 * we have to deassert reset line to be sure that ->probe() will
884 * recognize the device.
886 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
887 lpss_deassert_reset(pdata
);
892 static void acpi_lpss_dismiss(struct device
*dev
)
894 acpi_dev_suspend(dev
, false);
897 /* IOSF SB for LPSS island */
898 #define LPSS_IOSF_UNIT_LPIOEP 0xA0
899 #define LPSS_IOSF_UNIT_LPIO1 0xAB
900 #define LPSS_IOSF_UNIT_LPIO2 0xAC
902 #define LPSS_IOSF_PMCSR 0x84
903 #define LPSS_PMCSR_D0 0
904 #define LPSS_PMCSR_D3hot 3
905 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0)
907 #define LPSS_IOSF_GPIODEF0 0x154
908 #define LPSS_GPIODEF0_DMA1_D3 BIT(2)
909 #define LPSS_GPIODEF0_DMA2_D3 BIT(3)
910 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)
911 #define LPSS_GPIODEF0_DMA_LLP BIT(13)
913 static DEFINE_MUTEX(lpss_iosf_mutex
);
914 static bool lpss_iosf_d3_entered
= true;
916 static void lpss_iosf_enter_d3_state(void)
919 u32 mask1
= LPSS_GPIODEF0_DMA_D3_MASK
| LPSS_GPIODEF0_DMA_LLP
;
920 u32 value2
= LPSS_PMCSR_D3hot
;
921 u32 mask2
= LPSS_PMCSR_Dx_MASK
;
923 * PMC provides an information about actual status of the LPSS devices.
924 * Here we read the values related to LPSS power island, i.e. LPSS
925 * devices, excluding both LPSS DMA controllers, along with SCC domain.
927 u32 func_dis
, d3_sts_0
, pmc_status
;
930 ret
= pmc_atom_read(PMC_FUNC_DIS
, &func_dis
);
934 mutex_lock(&lpss_iosf_mutex
);
936 ret
= pmc_atom_read(PMC_D3_STS_0
, &d3_sts_0
);
941 * Get the status of entire LPSS power island per device basis.
942 * Shutdown both LPSS DMA controllers if and only if all other devices
943 * are already in D3hot.
945 pmc_status
= (~(d3_sts_0
| func_dis
)) & pmc_atom_d3_mask
;
949 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1
, MBI_CFG_WRITE
,
950 LPSS_IOSF_PMCSR
, value2
, mask2
);
952 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2
, MBI_CFG_WRITE
,
953 LPSS_IOSF_PMCSR
, value2
, mask2
);
955 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP
, MBI_CR_WRITE
,
956 LPSS_IOSF_GPIODEF0
, value1
, mask1
);
958 lpss_iosf_d3_entered
= true;
961 mutex_unlock(&lpss_iosf_mutex
);
964 static void lpss_iosf_exit_d3_state(void)
966 u32 value1
= LPSS_GPIODEF0_DMA1_D3
| LPSS_GPIODEF0_DMA2_D3
|
967 LPSS_GPIODEF0_DMA_LLP
;
968 u32 mask1
= LPSS_GPIODEF0_DMA_D3_MASK
| LPSS_GPIODEF0_DMA_LLP
;
969 u32 value2
= LPSS_PMCSR_D0
;
970 u32 mask2
= LPSS_PMCSR_Dx_MASK
;
972 mutex_lock(&lpss_iosf_mutex
);
974 if (!lpss_iosf_d3_entered
)
977 lpss_iosf_d3_entered
= false;
979 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP
, MBI_CR_WRITE
,
980 LPSS_IOSF_GPIODEF0
, value1
, mask1
);
982 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2
, MBI_CFG_WRITE
,
983 LPSS_IOSF_PMCSR
, value2
, mask2
);
985 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1
, MBI_CFG_WRITE
,
986 LPSS_IOSF_PMCSR
, value2
, mask2
);
989 mutex_unlock(&lpss_iosf_mutex
);
992 static int acpi_lpss_suspend(struct device
*dev
, bool wakeup
)
994 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
997 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
998 acpi_lpss_save_ctx(dev
, pdata
);
1000 ret
= acpi_dev_suspend(dev
, wakeup
);
1003 * This call must be last in the sequence, otherwise PMC will return
1004 * wrong status for devices being about to be powered off. See
1005 * lpss_iosf_enter_d3_state() for further information.
1007 if (acpi_target_system_state() == ACPI_STATE_S0
&&
1008 lpss_quirks
& LPSS_QUIRK_ALWAYS_POWER_ON
&& iosf_mbi_available())
1009 lpss_iosf_enter_d3_state();
1014 static int acpi_lpss_resume(struct device
*dev
)
1016 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
1020 * This call is kept first to be in symmetry with
1021 * acpi_lpss_runtime_suspend() one.
1023 if (lpss_quirks
& LPSS_QUIRK_ALWAYS_POWER_ON
&& iosf_mbi_available())
1024 lpss_iosf_exit_d3_state();
1026 ret
= acpi_dev_resume(dev
);
1030 acpi_lpss_d3_to_d0_delay(pdata
);
1032 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
1033 acpi_lpss_restore_ctx(dev
, pdata
);
1038 #ifdef CONFIG_PM_SLEEP
1039 static int acpi_lpss_do_suspend_late(struct device
*dev
)
1043 if (dev_pm_smart_suspend_and_suspended(dev
))
1046 ret
= pm_generic_suspend_late(dev
);
1047 return ret
? ret
: acpi_lpss_suspend(dev
, device_may_wakeup(dev
));
1050 static int acpi_lpss_suspend_late(struct device
*dev
)
1052 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
1054 if (pdata
->dev_desc
->resume_from_noirq
)
1057 return acpi_lpss_do_suspend_late(dev
);
1060 static int acpi_lpss_suspend_noirq(struct device
*dev
)
1062 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
1065 if (pdata
->dev_desc
->resume_from_noirq
) {
1067 * The driver's ->suspend_late callback will be invoked by
1068 * acpi_lpss_do_suspend_late(), with the assumption that the
1069 * driver really wanted to run that code in ->suspend_noirq, but
1070 * it could not run after acpi_dev_suspend() and the driver
1071 * expected the latter to be called in the "late" phase.
1073 ret
= acpi_lpss_do_suspend_late(dev
);
1078 return acpi_subsys_suspend_noirq(dev
);
1081 static int acpi_lpss_do_resume_early(struct device
*dev
)
1083 int ret
= acpi_lpss_resume(dev
);
1085 return ret
? ret
: pm_generic_resume_early(dev
);
1088 static int acpi_lpss_resume_early(struct device
*dev
)
1090 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
1092 if (pdata
->dev_desc
->resume_from_noirq
)
1095 return acpi_lpss_do_resume_early(dev
);
1098 static int acpi_lpss_resume_noirq(struct device
*dev
)
1100 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
1103 /* Follow acpi_subsys_resume_noirq(). */
1104 if (dev_pm_may_skip_resume(dev
))
1107 if (dev_pm_smart_suspend_and_suspended(dev
))
1108 pm_runtime_set_active(dev
);
1110 ret
= pm_generic_resume_noirq(dev
);
1114 if (!pdata
->dev_desc
->resume_from_noirq
)
1118 * The driver's ->resume_early callback will be invoked by
1119 * acpi_lpss_do_resume_early(), with the assumption that the driver
1120 * really wanted to run that code in ->resume_noirq, but it could not
1121 * run before acpi_dev_resume() and the driver expected the latter to be
1122 * called in the "early" phase.
1124 return acpi_lpss_do_resume_early(dev
);
1127 static int acpi_lpss_do_restore_early(struct device
*dev
)
1129 int ret
= acpi_lpss_resume(dev
);
1131 return ret
? ret
: pm_generic_restore_early(dev
);
1134 static int acpi_lpss_restore_early(struct device
*dev
)
1136 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
1138 if (pdata
->dev_desc
->resume_from_noirq
)
1141 return acpi_lpss_do_restore_early(dev
);
1144 static int acpi_lpss_restore_noirq(struct device
*dev
)
1146 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
1149 ret
= pm_generic_restore_noirq(dev
);
1153 if (!pdata
->dev_desc
->resume_from_noirq
)
1156 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */
1157 return acpi_lpss_do_restore_early(dev
);
1160 static int acpi_lpss_do_poweroff_late(struct device
*dev
)
1162 int ret
= pm_generic_poweroff_late(dev
);
1164 return ret
? ret
: acpi_lpss_suspend(dev
, device_may_wakeup(dev
));
1167 static int acpi_lpss_poweroff_late(struct device
*dev
)
1169 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
1171 if (dev_pm_smart_suspend_and_suspended(dev
))
1174 if (pdata
->dev_desc
->resume_from_noirq
)
1177 return acpi_lpss_do_poweroff_late(dev
);
1180 static int acpi_lpss_poweroff_noirq(struct device
*dev
)
1182 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
1184 if (dev_pm_smart_suspend_and_suspended(dev
))
1187 if (pdata
->dev_desc
->resume_from_noirq
) {
1188 /* This is analogous to the acpi_lpss_suspend_noirq() case. */
1189 int ret
= acpi_lpss_do_poweroff_late(dev
);
1194 return pm_generic_poweroff_noirq(dev
);
1196 #endif /* CONFIG_PM_SLEEP */
1198 static int acpi_lpss_runtime_suspend(struct device
*dev
)
1200 int ret
= pm_generic_runtime_suspend(dev
);
1202 return ret
? ret
: acpi_lpss_suspend(dev
, true);
1205 static int acpi_lpss_runtime_resume(struct device
*dev
)
1207 int ret
= acpi_lpss_resume(dev
);
1209 return ret
? ret
: pm_generic_runtime_resume(dev
);
1211 #endif /* CONFIG_PM */
1213 static struct dev_pm_domain acpi_lpss_pm_domain
= {
1215 .activate
= acpi_lpss_activate
,
1216 .dismiss
= acpi_lpss_dismiss
,
1220 #ifdef CONFIG_PM_SLEEP
1221 .prepare
= acpi_subsys_prepare
,
1222 .complete
= acpi_subsys_complete
,
1223 .suspend
= acpi_subsys_suspend
,
1224 .suspend_late
= acpi_lpss_suspend_late
,
1225 .suspend_noirq
= acpi_lpss_suspend_noirq
,
1226 .resume_noirq
= acpi_lpss_resume_noirq
,
1227 .resume_early
= acpi_lpss_resume_early
,
1228 .freeze
= acpi_subsys_freeze
,
1229 .poweroff
= acpi_subsys_poweroff
,
1230 .poweroff_late
= acpi_lpss_poweroff_late
,
1231 .poweroff_noirq
= acpi_lpss_poweroff_noirq
,
1232 .restore_noirq
= acpi_lpss_restore_noirq
,
1233 .restore_early
= acpi_lpss_restore_early
,
1235 .runtime_suspend
= acpi_lpss_runtime_suspend
,
1236 .runtime_resume
= acpi_lpss_runtime_resume
,
1241 static int acpi_lpss_platform_notify(struct notifier_block
*nb
,
1242 unsigned long action
, void *data
)
1244 struct platform_device
*pdev
= to_platform_device(data
);
1245 struct lpss_private_data
*pdata
;
1246 struct acpi_device
*adev
;
1247 const struct acpi_device_id
*id
;
1249 id
= acpi_match_device(acpi_lpss_device_ids
, &pdev
->dev
);
1250 if (!id
|| !id
->driver_data
)
1253 if (acpi_bus_get_device(ACPI_HANDLE(&pdev
->dev
), &adev
))
1256 pdata
= acpi_driver_data(adev
);
1260 if (pdata
->mmio_base
&&
1261 pdata
->mmio_size
< pdata
->dev_desc
->prv_offset
+ LPSS_LTR_SIZE
) {
1262 dev_err(&pdev
->dev
, "MMIO size insufficient to access LTR\n");
1267 case BUS_NOTIFY_BIND_DRIVER
:
1268 dev_pm_domain_set(&pdev
->dev
, &acpi_lpss_pm_domain
);
1270 case BUS_NOTIFY_DRIVER_NOT_BOUND
:
1271 case BUS_NOTIFY_UNBOUND_DRIVER
:
1272 dev_pm_domain_set(&pdev
->dev
, NULL
);
1274 case BUS_NOTIFY_ADD_DEVICE
:
1275 dev_pm_domain_set(&pdev
->dev
, &acpi_lpss_pm_domain
);
1276 if (pdata
->dev_desc
->flags
& LPSS_LTR
)
1277 return sysfs_create_group(&pdev
->dev
.kobj
,
1280 case BUS_NOTIFY_DEL_DEVICE
:
1281 if (pdata
->dev_desc
->flags
& LPSS_LTR
)
1282 sysfs_remove_group(&pdev
->dev
.kobj
, &lpss_attr_group
);
1283 dev_pm_domain_set(&pdev
->dev
, NULL
);
1292 static struct notifier_block acpi_lpss_nb
= {
1293 .notifier_call
= acpi_lpss_platform_notify
,
1296 static void acpi_lpss_bind(struct device
*dev
)
1298 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
1300 if (!pdata
|| !pdata
->mmio_base
|| !(pdata
->dev_desc
->flags
& LPSS_LTR
))
1303 if (pdata
->mmio_size
>= pdata
->dev_desc
->prv_offset
+ LPSS_LTR_SIZE
)
1304 dev
->power
.set_latency_tolerance
= acpi_lpss_set_ltr
;
1306 dev_err(dev
, "MMIO size insufficient to access LTR\n");
1309 static void acpi_lpss_unbind(struct device
*dev
)
1311 dev
->power
.set_latency_tolerance
= NULL
;
1314 static struct acpi_scan_handler lpss_handler
= {
1315 .ids
= acpi_lpss_device_ids
,
1316 .attach
= acpi_lpss_create_device
,
1317 .bind
= acpi_lpss_bind
,
1318 .unbind
= acpi_lpss_unbind
,
1321 void __init
acpi_lpss_init(void)
1323 const struct x86_cpu_id
*id
;
1326 ret
= lpt_clk_init();
1330 id
= x86_match_cpu(lpss_cpu_ids
);
1332 lpss_quirks
|= LPSS_QUIRK_ALWAYS_POWER_ON
;
1334 bus_register_notifier(&platform_bus_type
, &acpi_lpss_nb
);
1335 acpi_scan_add_handler(&lpss_handler
);
1340 static struct acpi_scan_handler lpss_handler
= {
1341 .ids
= acpi_lpss_device_ids
,
1344 void __init
acpi_lpss_init(void)
1346 acpi_scan_add_handler(&lpss_handler
);
1349 #endif /* CONFIG_X86_INTEL_LPSS */