drivers/acpi/acpi_lpss.c

   1 /*
   2  * ACPI support for Intel Lynxpoint LPSS.
   3  *
   4  * Copyright (C) 2013, Intel Corporation
   5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/clk.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/platform_data/clk-lpss.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/delay.h>
  23
  24 #include "internal.h"
  25
  26 ACPI_MODULE_NAME("acpi_lpss");
  27
  28 #ifdef CONFIG_X86_INTEL_LPSS
  29
  30 #define LPSS_ADDR(desc) ((unsigned long)&desc)
  31
  32 #define LPSS_CLK_SIZE   0x04
  33 #define LPSS_LTR_SIZE   0x18
  34
  35 /* Offsets relative to LPSS_PRIVATE_OFFSET */
  36 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
  37 #define LPSS_RESETS                     0x04
  38 #define LPSS_RESETS_RESET_FUNC          BIT(0)
  39 #define LPSS_RESETS_RESET_APB           BIT(1)
  40 #define LPSS_GENERAL                    0x08
  41 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
  42 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
  43 #define LPSS_SW_LTR                     0x10
  44 #define LPSS_AUTO_LTR                   0x14
  45 #define LPSS_LTR_SNOOP_REQ              BIT(15)
  46 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
  47 #define LPSS_LTR_SNOOP_LAT_1US          0x800
  48 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
  49 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
  50 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
  51 #define LPSS_LTR_MAX_VAL                0x3FF
  52 #define LPSS_TX_INT                     0x20
  53 #define LPSS_TX_INT_MASK                BIT(1)
  54
  55 #define LPSS_PRV_REG_COUNT              9
  56
  57 /* LPSS Flags */
  58 #define LPSS_CLK                        BIT(0)
  59 #define LPSS_CLK_GATE                   BIT(1)
  60 #define LPSS_CLK_DIVIDER                BIT(2)
  61 #define LPSS_LTR                        BIT(3)
  62 #define LPSS_SAVE_CTX                   BIT(4)
  63
  64 struct lpss_private_data;
  65
  66 struct lpss_device_desc {
  67         unsigned int flags;
  68         unsigned int prv_offset;
  69         size_t prv_size_override;
  70         void (*setup)(struct lpss_private_data *pdata);
  71 };
  72
  73 static struct lpss_device_desc lpss_dma_desc = {
  74         .flags = LPSS_CLK,
  75 };
  76
  77 struct lpss_private_data {
  78         void __iomem *mmio_base;
  79         resource_size_t mmio_size;
  80         unsigned int fixed_clk_rate;
  81         struct clk *clk;
  82         const struct lpss_device_desc *dev_desc;
  83         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
  84 };
  85
  86 /* UART Component Parameter Register */
  87 #define LPSS_UART_CPR                   0xF4
  88 #define LPSS_UART_CPR_AFCE              BIT(4)
  89
  90 static void lpss_uart_setup(struct lpss_private_data *pdata)
  91 {
  92         unsigned int offset;
  93         u32 val;
  94
  95         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
  96         val = readl(pdata->mmio_base + offset);
  97         writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
  98
  99         val = readl(pdata->mmio_base + LPSS_UART_CPR);
 100         if (!(val & LPSS_UART_CPR_AFCE)) {
 101                 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
 102                 val = readl(pdata->mmio_base + offset);
 103                 val |= LPSS_GENERAL_UART_RTS_OVRD;
 104                 writel(val, pdata->mmio_base + offset);
 105         }
 106 }
 107
 108 static void byt_i2c_setup(struct lpss_private_data *pdata)
 109 {
 110         unsigned int offset;
 111         u32 val;
 112
 113         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
 114         val = readl(pdata->mmio_base + offset);
 115         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
 116         writel(val, pdata->mmio_base + offset);
 117
 118         if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
 119                 pdata->fixed_clk_rate = 133000000;
 120 }
 121
 122 static struct lpss_device_desc lpt_dev_desc = {
 123         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 124         .prv_offset = 0x800,
 125 };
 126
 127 static struct lpss_device_desc lpt_i2c_dev_desc = {
 128         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
 129         .prv_offset = 0x800,
 130 };
 131
 132 static struct lpss_device_desc lpt_uart_dev_desc = {
 133         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 134         .prv_offset = 0x800,
 135         .setup = lpss_uart_setup,
 136 };
 137
 138 static struct lpss_device_desc lpt_sdio_dev_desc = {
 139         .flags = LPSS_LTR,
 140         .prv_offset = 0x1000,
 141         .prv_size_override = 0x1018,
 142 };
 143
 144 static struct lpss_device_desc byt_pwm_dev_desc = {
 145         .flags = LPSS_SAVE_CTX,
 146 };
 147
 148 static struct lpss_device_desc byt_uart_dev_desc = {
 149         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 150         .prv_offset = 0x800,
 151         .setup = lpss_uart_setup,
 152 };
 153
 154 static struct lpss_device_desc byt_spi_dev_desc = {
 155         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 156         .prv_offset = 0x400,
 157 };
 158
 159 static struct lpss_device_desc byt_sdio_dev_desc = {
 160         .flags = LPSS_CLK,
 161 };
 162
 163 static struct lpss_device_desc byt_i2c_dev_desc = {
 164         .flags = LPSS_CLK | LPSS_SAVE_CTX,
 165         .prv_offset = 0x800,
 166         .setup = byt_i2c_setup,
 167 };
 168
 169 #else
 170
 171 #define LPSS_ADDR(desc) (0UL)
 172
 173 #endif /* CONFIG_X86_INTEL_LPSS */
 174
 175 static const struct acpi_device_id acpi_lpss_device_ids[] = {
 176         /* Generic LPSS devices */
 177         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
 178
 179         /* Lynxpoint LPSS devices */
 180         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
 181         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
 182         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
 183         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
 184         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
 185         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
 186         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
 187         { "INT33C7", },
 188
 189         /* BayTrail LPSS devices */
 190         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
 191         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
 192         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
 193         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
 194         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
 195         { "INT33B2", },
 196         { "INT33FC", },
 197
 198         /* Braswell LPSS devices */
 199         { "80862288", LPSS_ADDR(byt_pwm_dev_desc) },
 200         { "8086228A", LPSS_ADDR(byt_uart_dev_desc) },
 201         { "8086228E", LPSS_ADDR(byt_spi_dev_desc) },
 202         { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) },
 203
 204         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
 205         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
 206         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
 207         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
 208         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
 209         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
 210         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
 211         { "INT3437", },
 212
 213         /* Wildcat Point LPSS devices */
 214         { "INT3438", LPSS_ADDR(lpt_dev_desc) },
 215
 216         { }
 217 };
 218
 219 #ifdef CONFIG_X86_INTEL_LPSS
 220
 221 static int is_memory(struct acpi_resource *res, void *not_used)
 222 {
 223         struct resource r;
 224         return !acpi_dev_resource_memory(res, &r);
 225 }
 226
 227 /* LPSS main clock device. */
 228 static struct platform_device *lpss_clk_dev;
 229
 230 static inline void lpt_register_clock_device(void)
 231 {
 232         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
 233 }
 234
 235 static int register_device_clock(struct acpi_device *adev,
 236                                  struct lpss_private_data *pdata)
 237 {
 238         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
 239         const char *devname = dev_name(&adev->dev);
 240         struct clk *clk = ERR_PTR(-ENODEV);
 241         struct lpss_clk_data *clk_data;
 242         const char *parent, *clk_name;
 243         void __iomem *prv_base;
 244
 245         if (!lpss_clk_dev)
 246                 lpt_register_clock_device();
 247
 248         clk_data = platform_get_drvdata(lpss_clk_dev);
 249         if (!clk_data)
 250                 return -ENODEV;
 251         clk = clk_data->clk;
 252
 253         if (!pdata->mmio_base
 254             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
 255                 return -ENODATA;
 256
 257         parent = clk_data->name;
 258         prv_base = pdata->mmio_base + dev_desc->prv_offset;
 259
 260         if (pdata->fixed_clk_rate) {
 261                 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
 262                                               pdata->fixed_clk_rate);
 263                 goto out;
 264         }
 265
 266         if (dev_desc->flags & LPSS_CLK_GATE) {
 267                 clk = clk_register_gate(NULL, devname, parent, 0,
 268                                         prv_base, 0, 0, NULL);
 269                 parent = devname;
 270         }
 271
 272         if (dev_desc->flags & LPSS_CLK_DIVIDER) {
 273                 /* Prevent division by zero */
 274                 if (!readl(prv_base))
 275                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
 276
 277                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
 278                 if (!clk_name)
 279                         return -ENOMEM;
 280                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
 281                                                       0, prv_base,
 282                                                       1, 15, 16, 15, 0, NULL);
 283                 parent = clk_name;
 284
 285                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
 286                 if (!clk_name) {
 287                         kfree(parent);
 288                         return -ENOMEM;
 289                 }
 290                 clk = clk_register_gate(NULL, clk_name, parent,
 291                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 292                                         prv_base, 31, 0, NULL);
 293                 kfree(parent);
 294                 kfree(clk_name);
 295         }
 296 out:
 297         if (IS_ERR(clk))
 298                 return PTR_ERR(clk);
 299
 300         pdata->clk = clk;
 301         clk_register_clkdev(clk, NULL, devname);
 302         return 0;
 303 }
 304
 305 static int acpi_lpss_create_device(struct acpi_device *adev,
 306                                    const struct acpi_device_id *id)
 307 {
 308         struct lpss_device_desc *dev_desc;
 309         struct lpss_private_data *pdata;
 310         struct resource_list_entry *rentry;
 311         struct list_head resource_list;
 312         struct platform_device *pdev;
 313         int ret;
 314
 315         dev_desc = (struct lpss_device_desc *)id->driver_data;
 316         if (!dev_desc) {
 317                 pdev = acpi_create_platform_device(adev);
 318                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
 319         }
 320         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 321         if (!pdata)
 322                 return -ENOMEM;
 323
 324         INIT_LIST_HEAD(&resource_list);
 325         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
 326         if (ret < 0)
 327                 goto err_out;
 328
 329         list_for_each_entry(rentry, &resource_list, node)
 330                 if (resource_type(&rentry->res) == IORESOURCE_MEM) {
 331                         if (dev_desc->prv_size_override)
 332                                 pdata->mmio_size = dev_desc->prv_size_override;
 333                         else
 334                                 pdata->mmio_size = resource_size(&rentry->res);
 335                         pdata->mmio_base = ioremap(rentry->res.start,
 336                                                    pdata->mmio_size);
 337                         break;
 338                 }
 339
 340         acpi_dev_free_resource_list(&resource_list);
 341
 342         pdata->dev_desc = dev_desc;
 343
 344         if (dev_desc->setup)
 345                 dev_desc->setup(pdata);
 346
 347         if (dev_desc->flags & LPSS_CLK) {
 348                 ret = register_device_clock(adev, pdata);
 349                 if (ret) {
 350                         /* Skip the device, but continue the namespace scan. */
 351                         ret = 0;
 352                         goto err_out;
 353                 }
 354         }
 355
 356         /*
 357          * This works around a known issue in ACPI tables where LPSS devices
 358          * have _PS0 and _PS3 without _PSC (and no power resources), so
 359          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
 360          */
 361         ret = acpi_device_fix_up_power(adev);
 362         if (ret) {
 363                 /* Skip the device, but continue the namespace scan. */
 364                 ret = 0;
 365                 goto err_out;
 366         }
 367
 368         adev->driver_data = pdata;
 369         pdev = acpi_create_platform_device(adev);
 370         if (!IS_ERR_OR_NULL(pdev)) {
 371                 return 1;
 372         }
 373
 374         ret = PTR_ERR(pdev);
 375         adev->driver_data = NULL;
 376
 377  err_out:
 378         kfree(pdata);
 379         return ret;
 380 }
 381
 382 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
 383 {
 384         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 385 }
 386
 387 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
 388                              unsigned int reg)
 389 {
 390         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 391 }
 392
 393 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
 394 {
 395         struct acpi_device *adev;
 396         struct lpss_private_data *pdata;
 397         unsigned long flags;
 398         int ret;
 399
 400         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
 401         if (WARN_ON(ret))
 402                 return ret;
 403
 404         spin_lock_irqsave(&dev->power.lock, flags);
 405         if (pm_runtime_suspended(dev)) {
 406                 ret = -EAGAIN;
 407                 goto out;
 408         }
 409         pdata = acpi_driver_data(adev);
 410         if (WARN_ON(!pdata || !pdata->mmio_base)) {
 411                 ret = -ENODEV;
 412                 goto out;
 413         }
 414         *val = __lpss_reg_read(pdata, reg);
 415
 416  out:
 417         spin_unlock_irqrestore(&dev->power.lock, flags);
 418         return ret;
 419 }
 420
 421 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
 422                              char *buf)
 423 {
 424         u32 ltr_value = 0;
 425         unsigned int reg;
 426         int ret;
 427
 428         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
 429         ret = lpss_reg_read(dev, reg, &ltr_value);
 430         if (ret)
 431                 return ret;
 432
 433         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
 434 }
 435
 436 static ssize_t lpss_ltr_mode_show(struct device *dev,
 437                                   struct device_attribute *attr, char *buf)
 438 {
 439         u32 ltr_mode = 0;
 440         char *outstr;
 441         int ret;
 442
 443         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
 444         if (ret)
 445                 return ret;
 446
 447         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
 448         return sprintf(buf, "%s\n", outstr);
 449 }
 450
 451 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
 452 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
 453 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
 454
 455 static struct attribute *lpss_attrs[] = {
 456         &dev_attr_auto_ltr.attr,
 457         &dev_attr_sw_ltr.attr,
 458         &dev_attr_ltr_mode.attr,
 459         NULL,
 460 };
 461
 462 static struct attribute_group lpss_attr_group = {
 463         .attrs = lpss_attrs,
 464         .name = "lpss_ltr",
 465 };
 466
 467 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
 468 {
 469         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 470         u32 ltr_mode, ltr_val;
 471
 472         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
 473         if (val < 0) {
 474                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
 475                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
 476                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 477                 }
 478                 return;
 479         }
 480         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
 481         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
 482                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
 483                 val = LPSS_LTR_MAX_VAL;
 484         } else if (val > LPSS_LTR_MAX_VAL) {
 485                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
 486                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
 487         } else {
 488                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
 489         }
 490         ltr_val |= val;
 491         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
 492         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
 493                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
 494                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 495         }
 496 }
 497
 498 #ifdef CONFIG_PM
 499 /**
 500  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
 501  * @dev: LPSS device
 502  *
 503  * Most LPSS devices have private registers which may loose their context when
 504  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
 505  * prv_reg_ctx array.
 506  */
 507 static void acpi_lpss_save_ctx(struct device *dev)
 508 {
 509         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 510         unsigned int i;
 511
 512         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 513                 unsigned long offset = i * sizeof(u32);
 514
 515                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
 516                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
 517                         pdata->prv_reg_ctx[i], offset);
 518         }
 519 }
 520
 521 /**
 522  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
 523  * @dev: LPSS device
 524  *
 525  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
 526  */
 527 static void acpi_lpss_restore_ctx(struct device *dev)
 528 {
 529         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 530         unsigned int i;
 531
 532         /*
 533          * The following delay is needed or the subsequent write operations may
 534          * fail. The LPSS devices are actually PCI devices and the PCI spec
 535          * expects 10ms delay before the device can be accessed after D3 to D0
 536          * transition.
 537          */
 538         msleep(10);
 539
 540         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 541                 unsigned long offset = i * sizeof(u32);
 542
 543                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
 544                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
 545                         pdata->prv_reg_ctx[i], offset);
 546         }
 547 }
 548
 549 #ifdef CONFIG_PM_SLEEP
 550 static int acpi_lpss_suspend_late(struct device *dev)
 551 {
 552         int ret = pm_generic_suspend_late(dev);
 553
 554         if (ret)
 555                 return ret;
 556
 557         acpi_lpss_save_ctx(dev);
 558         return acpi_dev_suspend_late(dev);
 559 }
 560
 561 static int acpi_lpss_resume_early(struct device *dev)
 562 {
 563         int ret = acpi_dev_resume_early(dev);
 564
 565         if (ret)
 566                 return ret;
 567
 568         acpi_lpss_restore_ctx(dev);
 569         return pm_generic_resume_early(dev);
 570 }
 571 #endif /* CONFIG_PM_SLEEP */
 572
 573 #ifdef CONFIG_PM_RUNTIME
 574 static int acpi_lpss_runtime_suspend(struct device *dev)
 575 {
 576         int ret = pm_generic_runtime_suspend(dev);
 577
 578         if (ret)
 579                 return ret;
 580
 581         acpi_lpss_save_ctx(dev);
 582         return acpi_dev_runtime_suspend(dev);
 583 }
 584
 585 static int acpi_lpss_runtime_resume(struct device *dev)
 586 {
 587         int ret = acpi_dev_runtime_resume(dev);
 588
 589         if (ret)
 590                 return ret;
 591
 592         acpi_lpss_restore_ctx(dev);
 593         return pm_generic_runtime_resume(dev);
 594 }
 595 #endif /* CONFIG_PM_RUNTIME */
 596 #endif /* CONFIG_PM */
 597
 598 static struct dev_pm_domain acpi_lpss_pm_domain = {
 599         .ops = {
 600 #ifdef CONFIG_PM_SLEEP
 601                 .prepare = acpi_subsys_prepare,
 602                 .complete = acpi_subsys_complete,
 603                 .suspend = acpi_subsys_suspend,
 604                 .suspend_late = acpi_lpss_suspend_late,
 605                 .resume_early = acpi_lpss_resume_early,
 606                 .freeze = acpi_subsys_freeze,
 607                 .poweroff = acpi_subsys_suspend,
 608                 .poweroff_late = acpi_lpss_suspend_late,
 609                 .restore_early = acpi_lpss_resume_early,
 610 #endif
 611 #ifdef CONFIG_PM_RUNTIME
 612                 .runtime_suspend = acpi_lpss_runtime_suspend,
 613                 .runtime_resume = acpi_lpss_runtime_resume,
 614 #endif
 615         },
 616 };
 617
 618 static int acpi_lpss_platform_notify(struct notifier_block *nb,
 619                                      unsigned long action, void *data)
 620 {
 621         struct platform_device *pdev = to_platform_device(data);
 622         struct lpss_private_data *pdata;
 623         struct acpi_device *adev;
 624         const struct acpi_device_id *id;
 625
 626         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
 627         if (!id || !id->driver_data)
 628                 return 0;
 629
 630         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
 631                 return 0;
 632
 633         pdata = acpi_driver_data(adev);
 634         if (!pdata || !pdata->mmio_base)
 635                 return 0;
 636
 637         if (pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
 638                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
 639                 return 0;
 640         }
 641
 642         switch (action) {
 643         case BUS_NOTIFY_BOUND_DRIVER:
 644                 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 645                         pdev->dev.pm_domain = &acpi_lpss_pm_domain;
 646                 break;
 647         case BUS_NOTIFY_UNBOUND_DRIVER:
 648                 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 649                         pdev->dev.pm_domain = NULL;
 650                 break;
 651         case BUS_NOTIFY_ADD_DEVICE:
 652                 if (pdata->dev_desc->flags & LPSS_LTR)
 653                         return sysfs_create_group(&pdev->dev.kobj,
 654                                                   &lpss_attr_group);
 655         case BUS_NOTIFY_DEL_DEVICE:
 656                 if (pdata->dev_desc->flags & LPSS_LTR)
 657                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
 658         default:
 659                 break;
 660         }
 661
 662         return 0;
 663 }
 664
 665 static struct notifier_block acpi_lpss_nb = {
 666         .notifier_call = acpi_lpss_platform_notify,
 667 };
 668
 669 static void acpi_lpss_bind(struct device *dev)
 670 {
 671         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 672
 673         if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
 674                 return;
 675
 676         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
 677                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
 678         else
 679                 dev_err(dev, "MMIO size insufficient to access LTR\n");
 680 }
 681
 682 static void acpi_lpss_unbind(struct device *dev)
 683 {
 684         dev->power.set_latency_tolerance = NULL;
 685 }
 686
 687 static struct acpi_scan_handler lpss_handler = {
 688         .ids = acpi_lpss_device_ids,
 689         .attach = acpi_lpss_create_device,
 690         .bind = acpi_lpss_bind,
 691         .unbind = acpi_lpss_unbind,
 692 };
 693
 694 void __init acpi_lpss_init(void)
 695 {
 696         if (!lpt_clk_init()) {
 697                 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
 698                 acpi_scan_add_handler(&lpss_handler);
 699         }
 700 }
 701
 702 #else
 703
 704 static struct acpi_scan_handler lpss_handler = {
 705         .ids = acpi_lpss_device_ids,
 706 };
 707
 708 void __init acpi_lpss_init(void)
 709 {
 710         acpi_scan_add_handler(&lpss_handler);
 711 }
 712
 713 #endif /* CONFIG_X86_INTEL_LPSS */