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Merge branch 'cleanup-clk-h-includes' into clk-next
[mirror_ubuntu-artful-kernel.git] / drivers / acpi / acpi_lpss.c
1 /*
2 * ACPI support for Intel Lynxpoint LPSS.
3 *
4 * Copyright (C) 2013, Intel Corporation
5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/acpi.h>
14 #include <linux/clkdev.h>
15 #include <linux/clk-provider.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/platform_device.h>
19 #include <linux/platform_data/clk-lpss.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/delay.h>
22
23 #include "internal.h"
24
25 ACPI_MODULE_NAME("acpi_lpss");
26
27 #ifdef CONFIG_X86_INTEL_LPSS
28
29 #define LPSS_ADDR(desc) ((unsigned long)&desc)
30
31 #define LPSS_CLK_SIZE 0x04
32 #define LPSS_LTR_SIZE 0x18
33
34 /* Offsets relative to LPSS_PRIVATE_OFFSET */
35 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
36 #define LPSS_RESETS 0x04
37 #define LPSS_RESETS_RESET_FUNC BIT(0)
38 #define LPSS_RESETS_RESET_APB BIT(1)
39 #define LPSS_GENERAL 0x08
40 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
41 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
42 #define LPSS_SW_LTR 0x10
43 #define LPSS_AUTO_LTR 0x14
44 #define LPSS_LTR_SNOOP_REQ BIT(15)
45 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
46 #define LPSS_LTR_SNOOP_LAT_1US 0x800
47 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
48 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
49 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
50 #define LPSS_LTR_MAX_VAL 0x3FF
51 #define LPSS_TX_INT 0x20
52 #define LPSS_TX_INT_MASK BIT(1)
53
54 #define LPSS_PRV_REG_COUNT 9
55
56 /* LPSS Flags */
57 #define LPSS_CLK BIT(0)
58 #define LPSS_CLK_GATE BIT(1)
59 #define LPSS_CLK_DIVIDER BIT(2)
60 #define LPSS_LTR BIT(3)
61 #define LPSS_SAVE_CTX BIT(4)
62
63 struct lpss_private_data;
64
65 struct lpss_device_desc {
66 unsigned int flags;
67 const char *clk_con_id;
68 unsigned int prv_offset;
69 size_t prv_size_override;
70 void (*setup)(struct lpss_private_data *pdata);
71 };
72
73 static struct lpss_device_desc lpss_dma_desc = {
74 .flags = LPSS_CLK,
75 };
76
77 struct lpss_private_data {
78 void __iomem *mmio_base;
79 resource_size_t mmio_size;
80 unsigned int fixed_clk_rate;
81 struct clk *clk;
82 const struct lpss_device_desc *dev_desc;
83 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
84 };
85
86 /* UART Component Parameter Register */
87 #define LPSS_UART_CPR 0xF4
88 #define LPSS_UART_CPR_AFCE BIT(4)
89
90 static void lpss_uart_setup(struct lpss_private_data *pdata)
91 {
92 unsigned int offset;
93 u32 val;
94
95 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
96 val = readl(pdata->mmio_base + offset);
97 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
98
99 val = readl(pdata->mmio_base + LPSS_UART_CPR);
100 if (!(val & LPSS_UART_CPR_AFCE)) {
101 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
102 val = readl(pdata->mmio_base + offset);
103 val |= LPSS_GENERAL_UART_RTS_OVRD;
104 writel(val, pdata->mmio_base + offset);
105 }
106 }
107
108 static void lpss_deassert_reset(struct lpss_private_data *pdata)
109 {
110 unsigned int offset;
111 u32 val;
112
113 offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
114 val = readl(pdata->mmio_base + offset);
115 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
116 writel(val, pdata->mmio_base + offset);
117 }
118
119 #define LPSS_I2C_ENABLE 0x6c
120
121 static void byt_i2c_setup(struct lpss_private_data *pdata)
122 {
123 lpss_deassert_reset(pdata);
124
125 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
126 pdata->fixed_clk_rate = 133000000;
127
128 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
129 }
130
131 static const struct lpss_device_desc lpt_dev_desc = {
132 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
133 .prv_offset = 0x800,
134 };
135
136 static const struct lpss_device_desc lpt_i2c_dev_desc = {
137 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
138 .prv_offset = 0x800,
139 };
140
141 static const struct lpss_device_desc lpt_uart_dev_desc = {
142 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
143 .clk_con_id = "baudclk",
144 .prv_offset = 0x800,
145 .setup = lpss_uart_setup,
146 };
147
148 static const struct lpss_device_desc lpt_sdio_dev_desc = {
149 .flags = LPSS_LTR,
150 .prv_offset = 0x1000,
151 .prv_size_override = 0x1018,
152 };
153
154 static const struct lpss_device_desc byt_pwm_dev_desc = {
155 .flags = LPSS_SAVE_CTX,
156 };
157
158 static const struct lpss_device_desc byt_uart_dev_desc = {
159 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
160 .clk_con_id = "baudclk",
161 .prv_offset = 0x800,
162 .setup = lpss_uart_setup,
163 };
164
165 static const struct lpss_device_desc byt_spi_dev_desc = {
166 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
167 .prv_offset = 0x400,
168 };
169
170 static const struct lpss_device_desc byt_sdio_dev_desc = {
171 .flags = LPSS_CLK,
172 };
173
174 static const struct lpss_device_desc byt_i2c_dev_desc = {
175 .flags = LPSS_CLK | LPSS_SAVE_CTX,
176 .prv_offset = 0x800,
177 .setup = byt_i2c_setup,
178 };
179
180 static struct lpss_device_desc bsw_spi_dev_desc = {
181 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
182 .prv_offset = 0x400,
183 .setup = lpss_deassert_reset,
184 };
185
186 #else
187
188 #define LPSS_ADDR(desc) (0UL)
189
190 #endif /* CONFIG_X86_INTEL_LPSS */
191
192 static const struct acpi_device_id acpi_lpss_device_ids[] = {
193 /* Generic LPSS devices */
194 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
195
196 /* Lynxpoint LPSS devices */
197 { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
198 { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
199 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
200 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
201 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
202 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
203 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
204 { "INT33C7", },
205
206 /* BayTrail LPSS devices */
207 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
208 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
209 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
210 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
211 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
212 { "INT33B2", },
213 { "INT33FC", },
214
215 /* Braswell LPSS devices */
216 { "80862288", LPSS_ADDR(byt_pwm_dev_desc) },
217 { "8086228A", LPSS_ADDR(byt_uart_dev_desc) },
218 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
219 { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) },
220
221 { "INT3430", LPSS_ADDR(lpt_dev_desc) },
222 { "INT3431", LPSS_ADDR(lpt_dev_desc) },
223 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
224 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
225 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
226 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
227 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
228 { "INT3437", },
229
230 /* Wildcat Point LPSS devices */
231 { "INT3438", LPSS_ADDR(lpt_dev_desc) },
232
233 { }
234 };
235
236 #ifdef CONFIG_X86_INTEL_LPSS
237
238 static int is_memory(struct acpi_resource *res, void *not_used)
239 {
240 struct resource r;
241 return !acpi_dev_resource_memory(res, &r);
242 }
243
244 /* LPSS main clock device. */
245 static struct platform_device *lpss_clk_dev;
246
247 static inline void lpt_register_clock_device(void)
248 {
249 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
250 }
251
252 static int register_device_clock(struct acpi_device *adev,
253 struct lpss_private_data *pdata)
254 {
255 const struct lpss_device_desc *dev_desc = pdata->dev_desc;
256 const char *devname = dev_name(&adev->dev);
257 struct clk *clk = ERR_PTR(-ENODEV);
258 struct lpss_clk_data *clk_data;
259 const char *parent, *clk_name;
260 void __iomem *prv_base;
261
262 if (!lpss_clk_dev)
263 lpt_register_clock_device();
264
265 clk_data = platform_get_drvdata(lpss_clk_dev);
266 if (!clk_data)
267 return -ENODEV;
268 clk = clk_data->clk;
269
270 if (!pdata->mmio_base
271 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
272 return -ENODATA;
273
274 parent = clk_data->name;
275 prv_base = pdata->mmio_base + dev_desc->prv_offset;
276
277 if (pdata->fixed_clk_rate) {
278 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
279 pdata->fixed_clk_rate);
280 goto out;
281 }
282
283 if (dev_desc->flags & LPSS_CLK_GATE) {
284 clk = clk_register_gate(NULL, devname, parent, 0,
285 prv_base, 0, 0, NULL);
286 parent = devname;
287 }
288
289 if (dev_desc->flags & LPSS_CLK_DIVIDER) {
290 /* Prevent division by zero */
291 if (!readl(prv_base))
292 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
293
294 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
295 if (!clk_name)
296 return -ENOMEM;
297 clk = clk_register_fractional_divider(NULL, clk_name, parent,
298 0, prv_base,
299 1, 15, 16, 15, 0, NULL);
300 parent = clk_name;
301
302 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
303 if (!clk_name) {
304 kfree(parent);
305 return -ENOMEM;
306 }
307 clk = clk_register_gate(NULL, clk_name, parent,
308 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
309 prv_base, 31, 0, NULL);
310 kfree(parent);
311 kfree(clk_name);
312 }
313 out:
314 if (IS_ERR(clk))
315 return PTR_ERR(clk);
316
317 pdata->clk = clk;
318 clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
319 return 0;
320 }
321
322 static int acpi_lpss_create_device(struct acpi_device *adev,
323 const struct acpi_device_id *id)
324 {
325 const struct lpss_device_desc *dev_desc;
326 struct lpss_private_data *pdata;
327 struct resource_entry *rentry;
328 struct list_head resource_list;
329 struct platform_device *pdev;
330 int ret;
331
332 dev_desc = (const struct lpss_device_desc *)id->driver_data;
333 if (!dev_desc) {
334 pdev = acpi_create_platform_device(adev);
335 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
336 }
337 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
338 if (!pdata)
339 return -ENOMEM;
340
341 INIT_LIST_HEAD(&resource_list);
342 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
343 if (ret < 0)
344 goto err_out;
345
346 list_for_each_entry(rentry, &resource_list, node)
347 if (resource_type(rentry->res) == IORESOURCE_MEM) {
348 if (dev_desc->prv_size_override)
349 pdata->mmio_size = dev_desc->prv_size_override;
350 else
351 pdata->mmio_size = resource_size(rentry->res);
352 pdata->mmio_base = ioremap(rentry->res->start,
353 pdata->mmio_size);
354 if (!pdata->mmio_base)
355 goto err_out;
356 break;
357 }
358
359 acpi_dev_free_resource_list(&resource_list);
360
361 pdata->dev_desc = dev_desc;
362
363 if (dev_desc->setup)
364 dev_desc->setup(pdata);
365
366 if (dev_desc->flags & LPSS_CLK) {
367 ret = register_device_clock(adev, pdata);
368 if (ret) {
369 /* Skip the device, but continue the namespace scan. */
370 ret = 0;
371 goto err_out;
372 }
373 }
374
375 /*
376 * This works around a known issue in ACPI tables where LPSS devices
377 * have _PS0 and _PS3 without _PSC (and no power resources), so
378 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
379 */
380 ret = acpi_device_fix_up_power(adev);
381 if (ret) {
382 /* Skip the device, but continue the namespace scan. */
383 ret = 0;
384 goto err_out;
385 }
386
387 adev->driver_data = pdata;
388 pdev = acpi_create_platform_device(adev);
389 if (!IS_ERR_OR_NULL(pdev)) {
390 return 1;
391 }
392
393 ret = PTR_ERR(pdev);
394 adev->driver_data = NULL;
395
396 err_out:
397 kfree(pdata);
398 return ret;
399 }
400
401 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
402 {
403 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
404 }
405
406 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
407 unsigned int reg)
408 {
409 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
410 }
411
412 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
413 {
414 struct acpi_device *adev;
415 struct lpss_private_data *pdata;
416 unsigned long flags;
417 int ret;
418
419 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
420 if (WARN_ON(ret))
421 return ret;
422
423 spin_lock_irqsave(&dev->power.lock, flags);
424 if (pm_runtime_suspended(dev)) {
425 ret = -EAGAIN;
426 goto out;
427 }
428 pdata = acpi_driver_data(adev);
429 if (WARN_ON(!pdata || !pdata->mmio_base)) {
430 ret = -ENODEV;
431 goto out;
432 }
433 *val = __lpss_reg_read(pdata, reg);
434
435 out:
436 spin_unlock_irqrestore(&dev->power.lock, flags);
437 return ret;
438 }
439
440 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
441 char *buf)
442 {
443 u32 ltr_value = 0;
444 unsigned int reg;
445 int ret;
446
447 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
448 ret = lpss_reg_read(dev, reg, &ltr_value);
449 if (ret)
450 return ret;
451
452 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
453 }
454
455 static ssize_t lpss_ltr_mode_show(struct device *dev,
456 struct device_attribute *attr, char *buf)
457 {
458 u32 ltr_mode = 0;
459 char *outstr;
460 int ret;
461
462 ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
463 if (ret)
464 return ret;
465
466 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
467 return sprintf(buf, "%s\n", outstr);
468 }
469
470 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
471 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
472 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
473
474 static struct attribute *lpss_attrs[] = {
475 &dev_attr_auto_ltr.attr,
476 &dev_attr_sw_ltr.attr,
477 &dev_attr_ltr_mode.attr,
478 NULL,
479 };
480
481 static struct attribute_group lpss_attr_group = {
482 .attrs = lpss_attrs,
483 .name = "lpss_ltr",
484 };
485
486 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
487 {
488 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
489 u32 ltr_mode, ltr_val;
490
491 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
492 if (val < 0) {
493 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
494 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
495 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
496 }
497 return;
498 }
499 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
500 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
501 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
502 val = LPSS_LTR_MAX_VAL;
503 } else if (val > LPSS_LTR_MAX_VAL) {
504 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
505 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
506 } else {
507 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
508 }
509 ltr_val |= val;
510 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
511 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
512 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
513 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
514 }
515 }
516
517 #ifdef CONFIG_PM
518 /**
519 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
520 * @dev: LPSS device
521 * @pdata: pointer to the private data of the LPSS device
522 *
523 * Most LPSS devices have private registers which may loose their context when
524 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
525 * prv_reg_ctx array.
526 */
527 static void acpi_lpss_save_ctx(struct device *dev,
528 struct lpss_private_data *pdata)
529 {
530 unsigned int i;
531
532 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
533 unsigned long offset = i * sizeof(u32);
534
535 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
536 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
537 pdata->prv_reg_ctx[i], offset);
538 }
539 }
540
541 /**
542 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
543 * @dev: LPSS device
544 * @pdata: pointer to the private data of the LPSS device
545 *
546 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
547 */
548 static void acpi_lpss_restore_ctx(struct device *dev,
549 struct lpss_private_data *pdata)
550 {
551 unsigned int i;
552
553 /*
554 * The following delay is needed or the subsequent write operations may
555 * fail. The LPSS devices are actually PCI devices and the PCI spec
556 * expects 10ms delay before the device can be accessed after D3 to D0
557 * transition.
558 */
559 msleep(10);
560
561 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
562 unsigned long offset = i * sizeof(u32);
563
564 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
565 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
566 pdata->prv_reg_ctx[i], offset);
567 }
568 }
569
570 #ifdef CONFIG_PM_SLEEP
571 static int acpi_lpss_suspend_late(struct device *dev)
572 {
573 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
574 int ret;
575
576 ret = pm_generic_suspend_late(dev);
577 if (ret)
578 return ret;
579
580 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
581 acpi_lpss_save_ctx(dev, pdata);
582
583 return acpi_dev_suspend_late(dev);
584 }
585
586 static int acpi_lpss_resume_early(struct device *dev)
587 {
588 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
589 int ret;
590
591 ret = acpi_dev_resume_early(dev);
592 if (ret)
593 return ret;
594
595 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
596 acpi_lpss_restore_ctx(dev, pdata);
597
598 return pm_generic_resume_early(dev);
599 }
600 #endif /* CONFIG_PM_SLEEP */
601
602 static int acpi_lpss_runtime_suspend(struct device *dev)
603 {
604 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
605 int ret;
606
607 ret = pm_generic_runtime_suspend(dev);
608 if (ret)
609 return ret;
610
611 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
612 acpi_lpss_save_ctx(dev, pdata);
613
614 return acpi_dev_runtime_suspend(dev);
615 }
616
617 static int acpi_lpss_runtime_resume(struct device *dev)
618 {
619 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
620 int ret;
621
622 ret = acpi_dev_runtime_resume(dev);
623 if (ret)
624 return ret;
625
626 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
627 acpi_lpss_restore_ctx(dev, pdata);
628
629 return pm_generic_runtime_resume(dev);
630 }
631 #endif /* CONFIG_PM */
632
633 static struct dev_pm_domain acpi_lpss_pm_domain = {
634 .ops = {
635 #ifdef CONFIG_PM
636 #ifdef CONFIG_PM_SLEEP
637 .prepare = acpi_subsys_prepare,
638 .complete = acpi_subsys_complete,
639 .suspend = acpi_subsys_suspend,
640 .suspend_late = acpi_lpss_suspend_late,
641 .resume_early = acpi_lpss_resume_early,
642 .freeze = acpi_subsys_freeze,
643 .poweroff = acpi_subsys_suspend,
644 .poweroff_late = acpi_lpss_suspend_late,
645 .restore_early = acpi_lpss_resume_early,
646 #endif
647 .runtime_suspend = acpi_lpss_runtime_suspend,
648 .runtime_resume = acpi_lpss_runtime_resume,
649 #endif
650 },
651 };
652
653 static int acpi_lpss_platform_notify(struct notifier_block *nb,
654 unsigned long action, void *data)
655 {
656 struct platform_device *pdev = to_platform_device(data);
657 struct lpss_private_data *pdata;
658 struct acpi_device *adev;
659 const struct acpi_device_id *id;
660
661 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
662 if (!id || !id->driver_data)
663 return 0;
664
665 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
666 return 0;
667
668 pdata = acpi_driver_data(adev);
669 if (!pdata)
670 return 0;
671
672 if (pdata->mmio_base &&
673 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
674 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
675 return 0;
676 }
677
678 switch (action) {
679 case BUS_NOTIFY_ADD_DEVICE:
680 pdev->dev.pm_domain = &acpi_lpss_pm_domain;
681 if (pdata->dev_desc->flags & LPSS_LTR)
682 return sysfs_create_group(&pdev->dev.kobj,
683 &lpss_attr_group);
684 break;
685 case BUS_NOTIFY_DEL_DEVICE:
686 if (pdata->dev_desc->flags & LPSS_LTR)
687 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
688 pdev->dev.pm_domain = NULL;
689 break;
690 default:
691 break;
692 }
693
694 return 0;
695 }
696
697 static struct notifier_block acpi_lpss_nb = {
698 .notifier_call = acpi_lpss_platform_notify,
699 };
700
701 static void acpi_lpss_bind(struct device *dev)
702 {
703 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
704
705 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
706 return;
707
708 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
709 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
710 else
711 dev_err(dev, "MMIO size insufficient to access LTR\n");
712 }
713
714 static void acpi_lpss_unbind(struct device *dev)
715 {
716 dev->power.set_latency_tolerance = NULL;
717 }
718
719 static struct acpi_scan_handler lpss_handler = {
720 .ids = acpi_lpss_device_ids,
721 .attach = acpi_lpss_create_device,
722 .bind = acpi_lpss_bind,
723 .unbind = acpi_lpss_unbind,
724 };
725
726 void __init acpi_lpss_init(void)
727 {
728 if (!lpt_clk_init()) {
729 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
730 acpi_scan_add_handler(&lpss_handler);
731 }
732 }
733
734 #else
735
736 static struct acpi_scan_handler lpss_handler = {
737 .ids = acpi_lpss_device_ids,
738 };
739
740 void __init acpi_lpss_init(void)
741 {
742 acpi_scan_add_handler(&lpss_handler);
743 }
744
745 #endif /* CONFIG_X86_INTEL_LPSS */
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