2 * ACPI support for Intel Lynxpoint LPSS.
4 * Copyright (C) 2013, Intel Corporation
5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/acpi.h>
14 #include <linux/clk.h>
15 #include <linux/clkdev.h>
16 #include <linux/clk-provider.h>
17 #include <linux/err.h>
19 #include <linux/platform_device.h>
20 #include <linux/platform_data/clk-lpss.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/delay.h>
26 ACPI_MODULE_NAME("acpi_lpss");
28 #ifdef CONFIG_X86_INTEL_LPSS
30 #define LPSS_ADDR(desc) ((unsigned long)&desc)
32 #define LPSS_CLK_SIZE 0x04
33 #define LPSS_LTR_SIZE 0x18
35 /* Offsets relative to LPSS_PRIVATE_OFFSET */
36 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
37 #define LPSS_RESETS 0x04
38 #define LPSS_RESETS_RESET_FUNC BIT(0)
39 #define LPSS_RESETS_RESET_APB BIT(1)
40 #define LPSS_GENERAL 0x08
41 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
42 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
43 #define LPSS_SW_LTR 0x10
44 #define LPSS_AUTO_LTR 0x14
45 #define LPSS_LTR_SNOOP_REQ BIT(15)
46 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
47 #define LPSS_LTR_SNOOP_LAT_1US 0x800
48 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
49 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
50 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
51 #define LPSS_LTR_MAX_VAL 0x3FF
52 #define LPSS_TX_INT 0x20
53 #define LPSS_TX_INT_MASK BIT(1)
55 #define LPSS_PRV_REG_COUNT 9
57 struct lpss_shared_clock
{
63 struct lpss_private_data
;
65 struct lpss_device_desc
{
67 const char *clkdev_name
;
69 unsigned int prv_offset
;
70 size_t prv_size_override
;
74 struct lpss_shared_clock
*shared_clock
;
75 void (*setup
)(struct lpss_private_data
*pdata
);
78 static struct lpss_device_desc lpss_dma_desc
= {
80 .clkdev_name
= "hclk",
83 struct lpss_private_data
{
84 void __iomem
*mmio_base
;
85 resource_size_t mmio_size
;
87 const struct lpss_device_desc
*dev_desc
;
88 u32 prv_reg_ctx
[LPSS_PRV_REG_COUNT
];
91 static void lpss_uart_setup(struct lpss_private_data
*pdata
)
96 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_TX_INT
;
97 reg
= readl(pdata
->mmio_base
+ offset
);
98 writel(reg
| LPSS_TX_INT_MASK
, pdata
->mmio_base
+ offset
);
100 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_GENERAL
;
101 reg
= readl(pdata
->mmio_base
+ offset
);
102 writel(reg
| LPSS_GENERAL_UART_RTS_OVRD
, pdata
->mmio_base
+ offset
);
105 static void lpss_i2c_setup(struct lpss_private_data
*pdata
)
110 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_RESETS
;
111 val
= readl(pdata
->mmio_base
+ offset
);
112 val
|= LPSS_RESETS_RESET_APB
| LPSS_RESETS_RESET_FUNC
;
113 writel(val
, pdata
->mmio_base
+ offset
);
116 static struct lpss_device_desc wpt_dev_desc
= {
117 .clk_required
= true,
119 .ltr_required
= true,
124 static struct lpss_device_desc lpt_dev_desc
= {
125 .clk_required
= true,
127 .ltr_required
= true,
132 static struct lpss_device_desc lpt_i2c_dev_desc
= {
133 .clk_required
= true,
135 .ltr_required
= true,
139 static struct lpss_device_desc lpt_uart_dev_desc
= {
140 .clk_required
= true,
142 .ltr_required
= true,
145 .setup
= lpss_uart_setup
,
148 static struct lpss_device_desc lpt_sdio_dev_desc
= {
149 .prv_offset
= 0x1000,
150 .prv_size_override
= 0x1018,
151 .ltr_required
= true,
154 static struct lpss_shared_clock pwm_clock
= {
159 static struct lpss_device_desc byt_pwm_dev_desc
= {
160 .clk_required
= true,
162 .shared_clock
= &pwm_clock
,
165 static struct lpss_device_desc byt_uart_dev_desc
= {
166 .clk_required
= true,
171 .setup
= lpss_uart_setup
,
174 static struct lpss_device_desc byt_spi_dev_desc
= {
175 .clk_required
= true,
182 static struct lpss_device_desc byt_sdio_dev_desc
= {
183 .clk_required
= true,
186 static struct lpss_shared_clock i2c_clock
= {
191 static struct lpss_device_desc byt_i2c_dev_desc
= {
192 .clk_required
= true,
195 .shared_clock
= &i2c_clock
,
196 .setup
= lpss_i2c_setup
,
199 static struct lpss_shared_clock bsw_pwm_clock
= {
204 static struct lpss_device_desc bsw_pwm_dev_desc
= {
205 .clk_required
= true,
207 .shared_clock
= &bsw_pwm_clock
,
212 #define LPSS_ADDR(desc) (0UL)
214 #endif /* CONFIG_X86_INTEL_LPSS */
216 static const struct acpi_device_id acpi_lpss_device_ids
[] = {
217 /* Generic LPSS devices */
218 { "INTL9C60", LPSS_ADDR(lpss_dma_desc
) },
220 /* Lynxpoint LPSS devices */
221 { "INT33C0", LPSS_ADDR(lpt_dev_desc
) },
222 { "INT33C1", LPSS_ADDR(lpt_dev_desc
) },
223 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc
) },
224 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc
) },
225 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc
) },
226 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc
) },
227 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc
) },
230 /* BayTrail LPSS devices */
231 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc
) },
232 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc
) },
233 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc
) },
234 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc
) },
235 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc
) },
239 /* Braswell LPSS devices */
240 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc
) },
241 { "8086228A", LPSS_ADDR(byt_uart_dev_desc
) },
242 { "8086228E", LPSS_ADDR(byt_spi_dev_desc
) },
243 { "808622C1", LPSS_ADDR(byt_i2c_dev_desc
) },
245 { "INT3430", LPSS_ADDR(lpt_dev_desc
) },
246 { "INT3431", LPSS_ADDR(lpt_dev_desc
) },
247 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc
) },
248 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc
) },
249 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc
) },
250 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc
) },
251 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc
) },
254 { "INT3438", LPSS_ADDR(wpt_dev_desc
) },
259 #ifdef CONFIG_X86_INTEL_LPSS
261 static int is_memory(struct acpi_resource
*res
, void *not_used
)
264 return !acpi_dev_resource_memory(res
, &r
);
267 /* LPSS main clock device. */
268 static struct platform_device
*lpss_clk_dev
;
270 static inline void lpt_register_clock_device(void)
272 lpss_clk_dev
= platform_device_register_simple("clk-lpt", -1, NULL
, 0);
275 static int register_device_clock(struct acpi_device
*adev
,
276 struct lpss_private_data
*pdata
)
278 const struct lpss_device_desc
*dev_desc
= pdata
->dev_desc
;
279 struct lpss_shared_clock
*shared_clock
= dev_desc
->shared_clock
;
280 const char *devname
= dev_name(&adev
->dev
);
281 struct clk
*clk
= ERR_PTR(-ENODEV
);
282 struct lpss_clk_data
*clk_data
;
283 const char *parent
, *clk_name
;
284 void __iomem
*prv_base
;
287 lpt_register_clock_device();
289 clk_data
= platform_get_drvdata(lpss_clk_dev
);
293 if (dev_desc
->clkdev_name
) {
294 clk_register_clkdev(clk_data
->clk
, dev_desc
->clkdev_name
,
299 if (!pdata
->mmio_base
300 || pdata
->mmio_size
< dev_desc
->prv_offset
+ LPSS_CLK_SIZE
)
303 parent
= clk_data
->name
;
304 prv_base
= pdata
->mmio_base
+ dev_desc
->prv_offset
;
307 clk
= shared_clock
->clk
;
309 clk
= clk_register_fixed_rate(NULL
, shared_clock
->name
,
312 shared_clock
->clk
= clk
;
314 parent
= shared_clock
->name
;
317 if (dev_desc
->clk_gate
) {
318 clk
= clk_register_gate(NULL
, devname
, parent
, 0,
319 prv_base
, 0, 0, NULL
);
323 if (dev_desc
->clk_divider
) {
324 /* Prevent division by zero */
325 if (!readl(prv_base
))
326 writel(LPSS_CLK_DIVIDER_DEF_MASK
, prv_base
);
328 clk_name
= kasprintf(GFP_KERNEL
, "%s-div", devname
);
331 clk
= clk_register_fractional_divider(NULL
, clk_name
, parent
,
333 1, 15, 16, 15, 0, NULL
);
336 clk_name
= kasprintf(GFP_KERNEL
, "%s-update", devname
);
341 clk
= clk_register_gate(NULL
, clk_name
, parent
,
342 CLK_SET_RATE_PARENT
| CLK_SET_RATE_GATE
,
343 prv_base
, 31, 0, NULL
);
352 clk_register_clkdev(clk
, NULL
, devname
);
356 static int acpi_lpss_create_device(struct acpi_device
*adev
,
357 const struct acpi_device_id
*id
)
359 struct lpss_device_desc
*dev_desc
;
360 struct lpss_private_data
*pdata
;
361 struct resource_list_entry
*rentry
;
362 struct list_head resource_list
;
363 struct platform_device
*pdev
;
366 dev_desc
= (struct lpss_device_desc
*)id
->driver_data
;
368 pdev
= acpi_create_platform_device(adev
);
369 return IS_ERR_OR_NULL(pdev
) ? PTR_ERR(pdev
) : 1;
371 pdata
= kzalloc(sizeof(*pdata
), GFP_KERNEL
);
375 INIT_LIST_HEAD(&resource_list
);
376 ret
= acpi_dev_get_resources(adev
, &resource_list
, is_memory
, NULL
);
380 list_for_each_entry(rentry
, &resource_list
, node
)
381 if (resource_type(&rentry
->res
) == IORESOURCE_MEM
) {
382 if (dev_desc
->prv_size_override
)
383 pdata
->mmio_size
= dev_desc
->prv_size_override
;
385 pdata
->mmio_size
= resource_size(&rentry
->res
);
386 pdata
->mmio_base
= ioremap(rentry
->res
.start
,
391 acpi_dev_free_resource_list(&resource_list
);
393 pdata
->dev_desc
= dev_desc
;
395 if (dev_desc
->clk_required
) {
396 ret
= register_device_clock(adev
, pdata
);
398 /* Skip the device, but continue the namespace scan. */
405 * This works around a known issue in ACPI tables where LPSS devices
406 * have _PS0 and _PS3 without _PSC (and no power resources), so
407 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
409 ret
= acpi_device_fix_up_power(adev
);
411 /* Skip the device, but continue the namespace scan. */
417 dev_desc
->setup(pdata
);
419 adev
->driver_data
= pdata
;
420 pdev
= acpi_create_platform_device(adev
);
421 if (!IS_ERR_OR_NULL(pdev
)) {
422 device_enable_async_suspend(&pdev
->dev
);
427 adev
->driver_data
= NULL
;
434 static u32
__lpss_reg_read(struct lpss_private_data
*pdata
, unsigned int reg
)
436 return readl(pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
+ reg
);
439 static void __lpss_reg_write(u32 val
, struct lpss_private_data
*pdata
,
442 writel(val
, pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
+ reg
);
445 static int lpss_reg_read(struct device
*dev
, unsigned int reg
, u32
*val
)
447 struct acpi_device
*adev
;
448 struct lpss_private_data
*pdata
;
452 ret
= acpi_bus_get_device(ACPI_HANDLE(dev
), &adev
);
456 spin_lock_irqsave(&dev
->power
.lock
, flags
);
457 if (pm_runtime_suspended(dev
)) {
461 pdata
= acpi_driver_data(adev
);
462 if (WARN_ON(!pdata
|| !pdata
->mmio_base
)) {
466 *val
= __lpss_reg_read(pdata
, reg
);
469 spin_unlock_irqrestore(&dev
->power
.lock
, flags
);
473 static ssize_t
lpss_ltr_show(struct device
*dev
, struct device_attribute
*attr
,
480 reg
= strcmp(attr
->attr
.name
, "auto_ltr") ? LPSS_SW_LTR
: LPSS_AUTO_LTR
;
481 ret
= lpss_reg_read(dev
, reg
, <r_value
);
485 return snprintf(buf
, PAGE_SIZE
, "%08x\n", ltr_value
);
488 static ssize_t
lpss_ltr_mode_show(struct device
*dev
,
489 struct device_attribute
*attr
, char *buf
)
495 ret
= lpss_reg_read(dev
, LPSS_GENERAL
, <r_mode
);
499 outstr
= (ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
) ? "sw" : "auto";
500 return sprintf(buf
, "%s\n", outstr
);
503 static DEVICE_ATTR(auto_ltr
, S_IRUSR
, lpss_ltr_show
, NULL
);
504 static DEVICE_ATTR(sw_ltr
, S_IRUSR
, lpss_ltr_show
, NULL
);
505 static DEVICE_ATTR(ltr_mode
, S_IRUSR
, lpss_ltr_mode_show
, NULL
);
507 static struct attribute
*lpss_attrs
[] = {
508 &dev_attr_auto_ltr
.attr
,
509 &dev_attr_sw_ltr
.attr
,
510 &dev_attr_ltr_mode
.attr
,
514 static struct attribute_group lpss_attr_group
= {
519 static void acpi_lpss_set_ltr(struct device
*dev
, s32 val
)
521 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
522 u32 ltr_mode
, ltr_val
;
524 ltr_mode
= __lpss_reg_read(pdata
, LPSS_GENERAL
);
526 if (ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
) {
527 ltr_mode
&= ~LPSS_GENERAL_LTR_MODE_SW
;
528 __lpss_reg_write(ltr_mode
, pdata
, LPSS_GENERAL
);
532 ltr_val
= __lpss_reg_read(pdata
, LPSS_SW_LTR
) & ~LPSS_LTR_SNOOP_MASK
;
533 if (val
>= LPSS_LTR_SNOOP_LAT_CUTOFF
) {
534 ltr_val
|= LPSS_LTR_SNOOP_LAT_32US
;
535 val
= LPSS_LTR_MAX_VAL
;
536 } else if (val
> LPSS_LTR_MAX_VAL
) {
537 ltr_val
|= LPSS_LTR_SNOOP_LAT_32US
| LPSS_LTR_SNOOP_REQ
;
538 val
>>= LPSS_LTR_SNOOP_LAT_SHIFT
;
540 ltr_val
|= LPSS_LTR_SNOOP_LAT_1US
| LPSS_LTR_SNOOP_REQ
;
543 __lpss_reg_write(ltr_val
, pdata
, LPSS_SW_LTR
);
544 if (!(ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
)) {
545 ltr_mode
|= LPSS_GENERAL_LTR_MODE_SW
;
546 __lpss_reg_write(ltr_mode
, pdata
, LPSS_GENERAL
);
552 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
555 * Most LPSS devices have private registers which may loose their context when
556 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
559 static void acpi_lpss_save_ctx(struct device
*dev
)
561 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
564 for (i
= 0; i
< LPSS_PRV_REG_COUNT
; i
++) {
565 unsigned long offset
= i
* sizeof(u32
);
567 pdata
->prv_reg_ctx
[i
] = __lpss_reg_read(pdata
, offset
);
568 dev_dbg(dev
, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
569 pdata
->prv_reg_ctx
[i
], offset
);
574 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
577 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
579 static void acpi_lpss_restore_ctx(struct device
*dev
)
581 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
585 * The following delay is needed or the subsequent write operations may
586 * fail. The LPSS devices are actually PCI devices and the PCI spec
587 * expects 10ms delay before the device can be accessed after D3 to D0
592 for (i
= 0; i
< LPSS_PRV_REG_COUNT
; i
++) {
593 unsigned long offset
= i
* sizeof(u32
);
595 __lpss_reg_write(pdata
->prv_reg_ctx
[i
], pdata
, offset
);
596 dev_dbg(dev
, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
597 pdata
->prv_reg_ctx
[i
], offset
);
601 #ifdef CONFIG_PM_SLEEP
602 static int acpi_lpss_suspend_late(struct device
*dev
)
604 int ret
= pm_generic_suspend_late(dev
);
609 acpi_lpss_save_ctx(dev
);
610 return acpi_dev_suspend_late(dev
);
613 static int acpi_lpss_restore_early(struct device
*dev
)
615 int ret
= acpi_dev_resume_early(dev
);
620 acpi_lpss_restore_ctx(dev
);
621 return pm_generic_resume_early(dev
);
623 #endif /* CONFIG_PM_SLEEP */
625 #ifdef CONFIG_PM_RUNTIME
626 static int acpi_lpss_runtime_suspend(struct device
*dev
)
628 int ret
= pm_generic_runtime_suspend(dev
);
633 acpi_lpss_save_ctx(dev
);
634 return acpi_dev_runtime_suspend(dev
);
637 static int acpi_lpss_runtime_resume(struct device
*dev
)
639 int ret
= acpi_dev_runtime_resume(dev
);
644 acpi_lpss_restore_ctx(dev
);
645 return pm_generic_runtime_resume(dev
);
647 #endif /* CONFIG_PM_RUNTIME */
648 #endif /* CONFIG_PM */
650 static struct dev_pm_domain acpi_lpss_pm_domain
= {
652 #ifdef CONFIG_PM_SLEEP
653 .suspend_late
= acpi_lpss_suspend_late
,
654 .restore_early
= acpi_lpss_restore_early
,
655 .prepare
= acpi_subsys_prepare
,
656 .complete
= acpi_subsys_complete
,
657 .suspend
= acpi_subsys_suspend
,
658 .resume_early
= acpi_subsys_resume_early
,
659 .freeze
= acpi_subsys_freeze
,
660 .poweroff
= acpi_subsys_suspend
,
661 .poweroff_late
= acpi_subsys_suspend_late
,
663 #ifdef CONFIG_PM_RUNTIME
664 .runtime_suspend
= acpi_lpss_runtime_suspend
,
665 .runtime_resume
= acpi_lpss_runtime_resume
,
670 static int acpi_lpss_platform_notify(struct notifier_block
*nb
,
671 unsigned long action
, void *data
)
673 struct platform_device
*pdev
= to_platform_device(data
);
674 struct lpss_private_data
*pdata
;
675 struct acpi_device
*adev
;
676 const struct acpi_device_id
*id
;
678 id
= acpi_match_device(acpi_lpss_device_ids
, &pdev
->dev
);
679 if (!id
|| !id
->driver_data
)
682 if (acpi_bus_get_device(ACPI_HANDLE(&pdev
->dev
), &adev
))
685 pdata
= acpi_driver_data(adev
);
686 if (!pdata
|| !pdata
->mmio_base
)
689 if (pdata
->mmio_size
< pdata
->dev_desc
->prv_offset
+ LPSS_LTR_SIZE
) {
690 dev_err(&pdev
->dev
, "MMIO size insufficient to access LTR\n");
695 case BUS_NOTIFY_BOUND_DRIVER
:
696 if (pdata
->dev_desc
->save_ctx
)
697 pdev
->dev
.pm_domain
= &acpi_lpss_pm_domain
;
699 case BUS_NOTIFY_UNBOUND_DRIVER
:
700 if (pdata
->dev_desc
->save_ctx
)
701 pdev
->dev
.pm_domain
= NULL
;
703 case BUS_NOTIFY_ADD_DEVICE
:
704 if (pdata
->dev_desc
->ltr_required
)
705 return sysfs_create_group(&pdev
->dev
.kobj
,
707 case BUS_NOTIFY_DEL_DEVICE
:
708 if (pdata
->dev_desc
->ltr_required
)
709 sysfs_remove_group(&pdev
->dev
.kobj
, &lpss_attr_group
);
717 static struct notifier_block acpi_lpss_nb
= {
718 .notifier_call
= acpi_lpss_platform_notify
,
721 static void acpi_lpss_bind(struct device
*dev
)
723 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
725 if (!pdata
|| !pdata
->mmio_base
|| !pdata
->dev_desc
->ltr_required
)
728 if (pdata
->mmio_size
>= pdata
->dev_desc
->prv_offset
+ LPSS_LTR_SIZE
)
729 dev
->power
.set_latency_tolerance
= acpi_lpss_set_ltr
;
731 dev_err(dev
, "MMIO size insufficient to access LTR\n");
734 static void acpi_lpss_unbind(struct device
*dev
)
736 dev
->power
.set_latency_tolerance
= NULL
;
739 static struct acpi_scan_handler lpss_handler
= {
740 .ids
= acpi_lpss_device_ids
,
741 .attach
= acpi_lpss_create_device
,
742 .bind
= acpi_lpss_bind
,
743 .unbind
= acpi_lpss_unbind
,
746 void __init
acpi_lpss_init(void)
748 if (!lpt_clk_init()) {
749 bus_register_notifier(&platform_bus_type
, &acpi_lpss_nb
);
750 acpi_scan_add_handler(&lpss_handler
);
756 static struct acpi_scan_handler lpss_handler
= {
757 .ids
= acpi_lpss_device_ids
,
760 void __init
acpi_lpss_init(void)
762 acpi_scan_add_handler(&lpss_handler
);
765 #endif /* CONFIG_X86_INTEL_LPSS */