1 /*******************************************************************************
3 * Module Name: hwregs - Read/write access functions for the various ACPI
4 * control and status registers.
6 ******************************************************************************/
9 * Copyright (C) 2000 - 2017, Intel Corp.
10 * All rights reserved.
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13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
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17 * without modification.
18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
19 * substantially similar to the "NO WARRANTY" disclaimer below
20 * ("Disclaimer") and any redistribution must be conditioned upon
21 * including a substantially similar Disclaimer requirement for further
22 * binary redistribution.
23 * 3. Neither the names of the above-listed copyright holders nor the names
24 * of any contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
27 * Alternatively, this software may be distributed under the terms of the
28 * GNU General Public License ("GPL") version 2 as published by the Free
29 * Software Foundation.
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45 #include <acpi/acpi.h>
49 #define _COMPONENT ACPI_HARDWARE
50 ACPI_MODULE_NAME("hwregs")
52 #if (!ACPI_REDUCED_HARDWARE)
53 /* Local Prototypes */
55 acpi_hw_get_access_bit_width(u64 address
,
56 struct acpi_generic_address
*reg
,
60 acpi_hw_read_multiple(u32
*value
,
61 struct acpi_generic_address
*register_a
,
62 struct acpi_generic_address
*register_b
);
65 acpi_hw_write_multiple(u32 value
,
66 struct acpi_generic_address
*register_a
,
67 struct acpi_generic_address
*register_b
);
69 #endif /* !ACPI_REDUCED_HARDWARE */
71 /******************************************************************************
73 * FUNCTION: acpi_hw_get_access_bit_width
75 * PARAMETERS: address - GAS register address
76 * reg - GAS register structure
77 * max_bit_width - Max bit_width supported (32 or 64)
81 * DESCRIPTION: Obtain optimal access bit width
83 ******************************************************************************/
86 acpi_hw_get_access_bit_width(u64 address
,
87 struct acpi_generic_address
*reg
, u8 max_bit_width
)
92 * GAS format "register", used by FADT:
93 * 1. Detected if bit_offset is 0 and bit_width is 8/16/32/64;
94 * 2. access_size field is ignored and bit_width field is used for
95 * determining the boundary of the IO accesses.
96 * GAS format "region", used by APEI registers:
97 * 1. Detected if bit_offset is not 0 or bit_width is not 8/16/32/64;
98 * 2. access_size field is used for determining the boundary of the
100 * 3. bit_offset/bit_width fields are used to describe the "region".
102 * Note: This algorithm assumes that the "Address" fields should always
103 * contain aligned values.
105 if (!reg
->bit_offset
&& reg
->bit_width
&&
106 ACPI_IS_POWER_OF_TWO(reg
->bit_width
) &&
107 ACPI_IS_ALIGNED(reg
->bit_width
, 8)) {
108 access_bit_width
= reg
->bit_width
;
109 } else if (reg
->access_width
) {
110 access_bit_width
= (1 << (reg
->access_width
+ 2));
113 ACPI_ROUND_UP_POWER_OF_TWO_8(reg
->bit_offset
+
115 if (access_bit_width
<= 8) {
116 access_bit_width
= 8;
118 while (!ACPI_IS_ALIGNED(address
, access_bit_width
>> 3)) {
119 access_bit_width
>>= 1;
124 /* Maximum IO port access bit width is 32 */
126 if (reg
->space_id
== ACPI_ADR_SPACE_SYSTEM_IO
) {
131 * Return access width according to the requested maximum access bit width,
132 * as the caller should know the format of the register and may enforce
135 if (access_bit_width
< max_bit_width
) {
136 return (access_bit_width
);
138 return (max_bit_width
);
141 /******************************************************************************
143 * FUNCTION: acpi_hw_validate_register
145 * PARAMETERS: reg - GAS register structure
146 * max_bit_width - Max bit_width supported (32 or 64)
147 * address - Pointer to where the gas->address
152 * DESCRIPTION: Validate the contents of a GAS register. Checks the GAS
153 * pointer, Address, space_id, bit_width, and bit_offset.
155 ******************************************************************************/
158 acpi_hw_validate_register(struct acpi_generic_address
*reg
,
159 u8 max_bit_width
, u64
*address
)
164 /* Must have a valid pointer to a GAS structure */
167 return (AE_BAD_PARAMETER
);
171 * Copy the target address. This handles possible alignment issues.
172 * Address must not be null. A null address also indicates an optional
173 * ACPI register that is not supported, so no error message.
175 ACPI_MOVE_64_TO_64(address
, ®
->address
);
177 return (AE_BAD_ADDRESS
);
180 /* Validate the space_ID */
182 if ((reg
->space_id
!= ACPI_ADR_SPACE_SYSTEM_MEMORY
) &&
183 (reg
->space_id
!= ACPI_ADR_SPACE_SYSTEM_IO
)) {
185 "Unsupported address space: 0x%X", reg
->space_id
));
189 /* Validate the access_width */
191 if (reg
->access_width
> 4) {
193 "Unsupported register access width: 0x%X",
198 /* Validate the bit_width, convert access_width into number of bits */
201 acpi_hw_get_access_bit_width(*address
, reg
, max_bit_width
);
203 ACPI_ROUND_UP(reg
->bit_offset
+ reg
->bit_width
, access_width
);
204 if (max_bit_width
< bit_width
) {
205 ACPI_WARNING((AE_INFO
,
206 "Requested bit width 0x%X is smaller than register bit width 0x%X",
207 max_bit_width
, bit_width
));
214 /******************************************************************************
216 * FUNCTION: acpi_hw_read
218 * PARAMETERS: value - Where the value is returned
219 * reg - GAS register structure
223 * DESCRIPTION: Read from either memory or IO space. This is a 32-bit max
224 * version of acpi_read, used internally since the overhead of
225 * 64-bit values is not needed.
227 * LIMITATIONS: <These limitations also apply to acpi_hw_write>
228 * space_ID must be system_memory or system_IO.
230 ******************************************************************************/
232 acpi_status
acpi_hw_read(u32
*value
, struct acpi_generic_address
*reg
)
243 ACPI_FUNCTION_NAME(hw_read
);
245 /* Validate contents of the GAS register */
247 status
= acpi_hw_validate_register(reg
, 32, &address
);
248 if (ACPI_FAILURE(status
)) {
253 * Initialize entire 32-bit return value to zero, convert access_width
254 * into number of bits based
257 access_width
= acpi_hw_get_access_bit_width(address
, reg
, 32);
258 bit_width
= reg
->bit_offset
+ reg
->bit_width
;
259 bit_offset
= reg
->bit_offset
;
262 * Two address spaces supported: Memory or IO. PCI_Config is
263 * not supported here because the GAS structure is insufficient
267 if (bit_offset
>= access_width
) {
269 bit_offset
-= access_width
;
271 if (reg
->space_id
== ACPI_ADR_SPACE_SYSTEM_MEMORY
) {
273 acpi_os_read_memory((acpi_physical_address
)
278 &value64
, access_width
);
279 value32
= (u32
)value64
;
280 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
282 status
= acpi_hw_read_port((acpi_io_address
)
293 * Use offset style bit writes because "Index * AccessWidth" is
294 * ensured to be less than 32-bits by acpi_hw_validate_register().
296 ACPI_SET_BITS(value
, index
* access_width
,
297 ACPI_MASK_BITS_ABOVE_32(access_width
), value32
);
300 bit_width
> access_width
? access_width
: bit_width
;
304 ACPI_DEBUG_PRINT((ACPI_DB_IO
,
305 "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n",
306 *value
, access_width
, ACPI_FORMAT_UINT64(address
),
307 acpi_ut_get_region_name(reg
->space_id
)));
312 /******************************************************************************
314 * FUNCTION: acpi_hw_write
316 * PARAMETERS: value - Value to be written
317 * reg - GAS register structure
321 * DESCRIPTION: Write to either memory or IO space. This is a 32-bit max
322 * version of acpi_write, used internally since the overhead of
323 * 64-bit values is not needed.
325 ******************************************************************************/
327 acpi_status
acpi_hw_write(u32 value
, struct acpi_generic_address
*reg
)
338 ACPI_FUNCTION_NAME(hw_write
);
340 /* Validate contents of the GAS register */
342 status
= acpi_hw_validate_register(reg
, 32, &address
);
343 if (ACPI_FAILURE(status
)) {
347 /* Convert access_width into number of bits based */
349 access_width
= acpi_hw_get_access_bit_width(address
, reg
, 32);
350 bit_width
= reg
->bit_offset
+ reg
->bit_width
;
351 bit_offset
= reg
->bit_offset
;
354 * Two address spaces supported: Memory or IO. PCI_Config is
355 * not supported here because the GAS structure is insufficient
360 * Use offset style bit reads because "Index * AccessWidth" is
361 * ensured to be less than 32-bits by acpi_hw_validate_register().
363 value32
= ACPI_GET_BITS(&value
, index
* access_width
,
364 ACPI_MASK_BITS_ABOVE_32(access_width
));
366 if (bit_offset
>= access_width
) {
367 bit_offset
-= access_width
;
369 if (reg
->space_id
== ACPI_ADR_SPACE_SYSTEM_MEMORY
) {
370 value64
= (u64
)value32
;
372 acpi_os_write_memory((acpi_physical_address
)
377 value64
, access_width
);
378 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
380 status
= acpi_hw_write_port((acpi_io_address
)
391 * Index * access_width is ensured to be less than 32-bits by
392 * acpi_hw_validate_register().
395 bit_width
> access_width
? access_width
: bit_width
;
399 ACPI_DEBUG_PRINT((ACPI_DB_IO
,
400 "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n",
401 value
, access_width
, ACPI_FORMAT_UINT64(address
),
402 acpi_ut_get_region_name(reg
->space_id
)));
407 #if (!ACPI_REDUCED_HARDWARE)
408 /*******************************************************************************
410 * FUNCTION: acpi_hw_clear_acpi_status
416 * DESCRIPTION: Clears all fixed and general purpose status bits
418 ******************************************************************************/
420 acpi_status
acpi_hw_clear_acpi_status(void)
423 acpi_cpu_flags lock_flags
= 0;
425 ACPI_FUNCTION_TRACE(hw_clear_acpi_status
);
427 ACPI_DEBUG_PRINT((ACPI_DB_IO
, "About to write %04X to %8.8X%8.8X\n",
428 ACPI_BITMASK_ALL_FIXED_STATUS
,
429 ACPI_FORMAT_UINT64(acpi_gbl_xpm1a_status
.address
)));
431 lock_flags
= acpi_os_acquire_lock(acpi_gbl_hardware_lock
);
433 /* Clear the fixed events in PM1 A/B */
435 status
= acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS
,
436 ACPI_BITMASK_ALL_FIXED_STATUS
);
438 acpi_os_release_lock(acpi_gbl_hardware_lock
, lock_flags
);
440 if (ACPI_FAILURE(status
)) {
444 /* Clear the GPE Bits in all GPE registers in all GPE blocks */
446 status
= acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block
, NULL
);
449 return_ACPI_STATUS(status
);
452 /*******************************************************************************
454 * FUNCTION: acpi_hw_get_bit_register_info
456 * PARAMETERS: register_id - Index of ACPI Register to access
458 * RETURN: The bitmask to be used when accessing the register
460 * DESCRIPTION: Map register_id into a register bitmask.
462 ******************************************************************************/
464 struct acpi_bit_register_info
*acpi_hw_get_bit_register_info(u32 register_id
)
466 ACPI_FUNCTION_ENTRY();
468 if (register_id
> ACPI_BITREG_MAX
) {
469 ACPI_ERROR((AE_INFO
, "Invalid BitRegister ID: 0x%X",
474 return (&acpi_gbl_bit_register_info
[register_id
]);
477 /******************************************************************************
479 * FUNCTION: acpi_hw_write_pm1_control
481 * PARAMETERS: pm1a_control - Value to be written to PM1A control
482 * pm1b_control - Value to be written to PM1B control
486 * DESCRIPTION: Write the PM1 A/B control registers. These registers are
487 * different than than the PM1 A/B status and enable registers
488 * in that different values can be written to the A/B registers.
489 * Most notably, the SLP_TYP bits can be different, as per the
490 * values returned from the _Sx predefined methods.
492 ******************************************************************************/
494 acpi_status
acpi_hw_write_pm1_control(u32 pm1a_control
, u32 pm1b_control
)
498 ACPI_FUNCTION_TRACE(hw_write_pm1_control
);
501 acpi_hw_write(pm1a_control
, &acpi_gbl_FADT
.xpm1a_control_block
);
502 if (ACPI_FAILURE(status
)) {
503 return_ACPI_STATUS(status
);
506 if (acpi_gbl_FADT
.xpm1b_control_block
.address
) {
508 acpi_hw_write(pm1b_control
,
509 &acpi_gbl_FADT
.xpm1b_control_block
);
511 return_ACPI_STATUS(status
);
514 /******************************************************************************
516 * FUNCTION: acpi_hw_register_read
518 * PARAMETERS: register_id - ACPI Register ID
519 * return_value - Where the register value is returned
521 * RETURN: Status and the value read.
523 * DESCRIPTION: Read from the specified ACPI register
525 ******************************************************************************/
526 acpi_status
acpi_hw_register_read(u32 register_id
, u32
*return_value
)
531 ACPI_FUNCTION_TRACE(hw_register_read
);
533 switch (register_id
) {
534 case ACPI_REGISTER_PM1_STATUS
: /* PM1 A/B: 16-bit access each */
536 status
= acpi_hw_read_multiple(&value
,
537 &acpi_gbl_xpm1a_status
,
538 &acpi_gbl_xpm1b_status
);
541 case ACPI_REGISTER_PM1_ENABLE
: /* PM1 A/B: 16-bit access each */
543 status
= acpi_hw_read_multiple(&value
,
544 &acpi_gbl_xpm1a_enable
,
545 &acpi_gbl_xpm1b_enable
);
548 case ACPI_REGISTER_PM1_CONTROL
: /* PM1 A/B: 16-bit access each */
550 status
= acpi_hw_read_multiple(&value
,
554 xpm1b_control_block
);
557 * Zero the write-only bits. From the ACPI specification, "Hardware
558 * Write-Only Bits": "Upon reads to registers with write-only bits,
559 * software masks out all write-only bits."
561 value
&= ~ACPI_PM1_CONTROL_WRITEONLY_BITS
;
564 case ACPI_REGISTER_PM2_CONTROL
: /* 8-bit access */
567 acpi_hw_read(&value
, &acpi_gbl_FADT
.xpm2_control_block
);
570 case ACPI_REGISTER_PM_TIMER
: /* 32-bit access */
572 status
= acpi_hw_read(&value
, &acpi_gbl_FADT
.xpm_timer_block
);
575 case ACPI_REGISTER_SMI_COMMAND_BLOCK
: /* 8-bit access */
578 acpi_hw_read_port(acpi_gbl_FADT
.smi_command
, &value
, 8);
583 ACPI_ERROR((AE_INFO
, "Unknown Register ID: 0x%X", register_id
));
584 status
= AE_BAD_PARAMETER
;
588 if (ACPI_SUCCESS(status
)) {
589 *return_value
= value
;
592 return_ACPI_STATUS(status
);
595 /******************************************************************************
597 * FUNCTION: acpi_hw_register_write
599 * PARAMETERS: register_id - ACPI Register ID
600 * value - The value to write
604 * DESCRIPTION: Write to the specified ACPI register
606 * NOTE: In accordance with the ACPI specification, this function automatically
607 * preserves the value of the following bits, meaning that these bits cannot be
608 * changed via this interface:
610 * PM1_CONTROL[0] = SCI_EN
615 * 1) Hardware Ignored Bits: When software writes to a register with ignored
616 * bit fields, it preserves the ignored bit fields
617 * 2) SCI_EN: OSPM always preserves this bit position
619 ******************************************************************************/
621 acpi_status
acpi_hw_register_write(u32 register_id
, u32 value
)
626 ACPI_FUNCTION_TRACE(hw_register_write
);
628 switch (register_id
) {
629 case ACPI_REGISTER_PM1_STATUS
: /* PM1 A/B: 16-bit access each */
631 * Handle the "ignored" bit in PM1 Status. According to the ACPI
632 * specification, ignored bits are to be preserved when writing.
633 * Normally, this would mean a read/modify/write sequence. However,
634 * preserving a bit in the status register is different. Writing a
635 * one clears the status, and writing a zero preserves the status.
636 * Therefore, we must always write zero to the ignored bit.
638 * This behavior is clarified in the ACPI 4.0 specification.
640 value
&= ~ACPI_PM1_STATUS_PRESERVED_BITS
;
642 status
= acpi_hw_write_multiple(value
,
643 &acpi_gbl_xpm1a_status
,
644 &acpi_gbl_xpm1b_status
);
647 case ACPI_REGISTER_PM1_ENABLE
: /* PM1 A/B: 16-bit access each */
649 status
= acpi_hw_write_multiple(value
,
650 &acpi_gbl_xpm1a_enable
,
651 &acpi_gbl_xpm1b_enable
);
654 case ACPI_REGISTER_PM1_CONTROL
: /* PM1 A/B: 16-bit access each */
656 * Perform a read first to preserve certain bits (per ACPI spec)
657 * Note: This includes SCI_EN, we never want to change this bit
659 status
= acpi_hw_read_multiple(&read_value
,
663 xpm1b_control_block
);
664 if (ACPI_FAILURE(status
)) {
668 /* Insert the bits to be preserved */
670 ACPI_INSERT_BITS(value
, ACPI_PM1_CONTROL_PRESERVED_BITS
,
673 /* Now we can write the data */
675 status
= acpi_hw_write_multiple(value
,
679 xpm1b_control_block
);
682 case ACPI_REGISTER_PM2_CONTROL
: /* 8-bit access */
684 * For control registers, all reserved bits must be preserved,
685 * as per the ACPI spec.
688 acpi_hw_read(&read_value
,
689 &acpi_gbl_FADT
.xpm2_control_block
);
690 if (ACPI_FAILURE(status
)) {
694 /* Insert the bits to be preserved */
696 ACPI_INSERT_BITS(value
, ACPI_PM2_CONTROL_PRESERVED_BITS
,
700 acpi_hw_write(value
, &acpi_gbl_FADT
.xpm2_control_block
);
703 case ACPI_REGISTER_PM_TIMER
: /* 32-bit access */
705 status
= acpi_hw_write(value
, &acpi_gbl_FADT
.xpm_timer_block
);
708 case ACPI_REGISTER_SMI_COMMAND_BLOCK
: /* 8-bit access */
710 /* SMI_CMD is currently always in IO space */
713 acpi_hw_write_port(acpi_gbl_FADT
.smi_command
, value
, 8);
718 ACPI_ERROR((AE_INFO
, "Unknown Register ID: 0x%X", register_id
));
719 status
= AE_BAD_PARAMETER
;
724 return_ACPI_STATUS(status
);
727 /******************************************************************************
729 * FUNCTION: acpi_hw_read_multiple
731 * PARAMETERS: value - Where the register value is returned
732 * register_a - First ACPI register (required)
733 * register_b - Second ACPI register (optional)
737 * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
739 ******************************************************************************/
742 acpi_hw_read_multiple(u32
*value
,
743 struct acpi_generic_address
*register_a
,
744 struct acpi_generic_address
*register_b
)
750 /* The first register is always required */
752 status
= acpi_hw_read(&value_a
, register_a
);
753 if (ACPI_FAILURE(status
)) {
757 /* Second register is optional */
759 if (register_b
->address
) {
760 status
= acpi_hw_read(&value_b
, register_b
);
761 if (ACPI_FAILURE(status
)) {
767 * OR the two return values together. No shifting or masking is necessary,
768 * because of how the PM1 registers are defined in the ACPI specification:
770 * "Although the bits can be split between the two register blocks (each
771 * register block has a unique pointer within the FADT), the bit positions
772 * are maintained. The register block with unimplemented bits (that is,
773 * those implemented in the other register block) always returns zeros,
774 * and writes have no side effects"
776 *value
= (value_a
| value_b
);
780 /******************************************************************************
782 * FUNCTION: acpi_hw_write_multiple
784 * PARAMETERS: value - The value to write
785 * register_a - First ACPI register (required)
786 * register_b - Second ACPI register (optional)
790 * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
792 ******************************************************************************/
795 acpi_hw_write_multiple(u32 value
,
796 struct acpi_generic_address
*register_a
,
797 struct acpi_generic_address
*register_b
)
801 /* The first register is always required */
803 status
= acpi_hw_write(value
, register_a
);
804 if (ACPI_FAILURE(status
)) {
809 * Second register is optional
811 * No bit shifting or clearing is necessary, because of how the PM1
812 * registers are defined in the ACPI specification:
814 * "Although the bits can be split between the two register blocks (each
815 * register block has a unique pointer within the FADT), the bit positions
816 * are maintained. The register block with unimplemented bits (that is,
817 * those implemented in the other register block) always returns zeros,
818 * and writes have no side effects"
820 if (register_b
->address
) {
821 status
= acpi_hw_write(value
, register_b
);
827 #endif /* !ACPI_REDUCED_HARDWARE */