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ACPICA: Hardware: Add optimized access bit width support
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1 /*******************************************************************************
2 *
3 * Module Name: hwregs - Read/write access functions for the various ACPI
4 * control and status registers.
5 *
6 ******************************************************************************/
7
8 /*
9 * Copyright (C) 2000 - 2016, Intel Corp.
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions, and the following disclaimer,
17 * without modification.
18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
19 * substantially similar to the "NO WARRANTY" disclaimer below
20 * ("Disclaimer") and any redistribution must be conditioned upon
21 * including a substantially similar Disclaimer requirement for further
22 * binary redistribution.
23 * 3. Neither the names of the above-listed copyright holders nor the names
24 * of any contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * Alternatively, this software may be distributed under the terms of the
28 * GNU General Public License ("GPL") version 2 as published by the Free
29 * Software Foundation.
30 *
31 * NO WARRANTY
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
35 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
36 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
40 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
41 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 * POSSIBILITY OF SUCH DAMAGES.
43 */
44
45 #include <acpi/acpi.h>
46 #include "accommon.h"
47 #include "acevents.h"
48
49 #define _COMPONENT ACPI_HARDWARE
50 ACPI_MODULE_NAME("hwregs")
51
52 #if (!ACPI_REDUCED_HARDWARE)
53 /* Local Prototypes */
54 static u8
55 acpi_hw_get_access_bit_width(struct acpi_generic_address *reg,
56 u8 max_bit_width);
57
58 static acpi_status
59 acpi_hw_read_multiple(u32 *value,
60 struct acpi_generic_address *register_a,
61 struct acpi_generic_address *register_b);
62
63 static acpi_status
64 acpi_hw_write_multiple(u32 value,
65 struct acpi_generic_address *register_a,
66 struct acpi_generic_address *register_b);
67
68 #endif /* !ACPI_REDUCED_HARDWARE */
69
70 /******************************************************************************
71 *
72 * FUNCTION: acpi_hw_get_access_bit_width
73 *
74 * PARAMETERS: reg - GAS register structure
75 * max_bit_width - Max bit_width supported (32 or 64)
76 *
77 * RETURN: Status
78 *
79 * DESCRIPTION: Obtain optimal access bit width
80 *
81 ******************************************************************************/
82
83 static u8
84 acpi_hw_get_access_bit_width(struct acpi_generic_address *reg, u8 max_bit_width)
85 {
86 u64 address;
87
88 if (!reg->access_width) {
89 /*
90 * Detect old register descriptors where only the bit_width field
91 * makes senses. The target address is copied to handle possible
92 * alignment issues.
93 */
94 ACPI_MOVE_64_TO_64(&address, &reg->address);
95 if (!reg->bit_offset && reg->bit_width &&
96 ACPI_IS_POWER_OF_TWO(reg->bit_width) &&
97 ACPI_IS_ALIGNED(reg->bit_width, 8) &&
98 ACPI_IS_ALIGNED(address, reg->bit_width)) {
99 return (reg->bit_width);
100 } else {
101 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
102 return (32);
103 } else {
104 return (max_bit_width);
105 }
106 }
107 } else {
108 return (1 << (reg->access_width + 2));
109 }
110 }
111
112 /******************************************************************************
113 *
114 * FUNCTION: acpi_hw_validate_register
115 *
116 * PARAMETERS: reg - GAS register structure
117 * max_bit_width - Max bit_width supported (32 or 64)
118 * address - Pointer to where the gas->address
119 * is returned
120 *
121 * RETURN: Status
122 *
123 * DESCRIPTION: Validate the contents of a GAS register. Checks the GAS
124 * pointer, Address, space_id, bit_width, and bit_offset.
125 *
126 ******************************************************************************/
127
128 acpi_status
129 acpi_hw_validate_register(struct acpi_generic_address *reg,
130 u8 max_bit_width, u64 *address)
131 {
132 u8 bit_width;
133 u8 access_width;
134
135 /* Must have a valid pointer to a GAS structure */
136
137 if (!reg) {
138 return (AE_BAD_PARAMETER);
139 }
140
141 /*
142 * Copy the target address. This handles possible alignment issues.
143 * Address must not be null. A null address also indicates an optional
144 * ACPI register that is not supported, so no error message.
145 */
146 ACPI_MOVE_64_TO_64(address, &reg->address);
147 if (!(*address)) {
148 return (AE_BAD_ADDRESS);
149 }
150
151 /* Validate the space_ID */
152
153 if ((reg->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) &&
154 (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO)) {
155 ACPI_ERROR((AE_INFO,
156 "Unsupported address space: 0x%X", reg->space_id));
157 return (AE_SUPPORT);
158 }
159
160 /* Validate the access_width */
161
162 if (reg->access_width > 4) {
163 ACPI_ERROR((AE_INFO,
164 "Unsupported register access width: 0x%X",
165 reg->access_width));
166 return (AE_SUPPORT);
167 }
168
169 /* Validate the bit_width, convert access_width into number of bits */
170
171 access_width = acpi_hw_get_access_bit_width(reg, max_bit_width);
172 bit_width =
173 ACPI_ROUND_UP(reg->bit_offset + reg->bit_width, access_width);
174 if (max_bit_width < bit_width) {
175 ACPI_WARNING((AE_INFO,
176 "Requested bit width 0x%X is smaller than register bit width 0x%X",
177 max_bit_width, bit_width));
178 return (AE_SUPPORT);
179 }
180
181 return (AE_OK);
182 }
183
184 /******************************************************************************
185 *
186 * FUNCTION: acpi_hw_read
187 *
188 * PARAMETERS: value - Where the value is returned
189 * reg - GAS register structure
190 *
191 * RETURN: Status
192 *
193 * DESCRIPTION: Read from either memory or IO space. This is a 32-bit max
194 * version of acpi_read, used internally since the overhead of
195 * 64-bit values is not needed.
196 *
197 * LIMITATIONS: <These limitations also apply to acpi_hw_write>
198 * bit_width must be exactly 8, 16, or 32.
199 * space_ID must be system_memory or system_IO.
200 * bit_offset and access_width are currently ignored, as there has
201 * not been a need to implement these.
202 *
203 ******************************************************************************/
204
205 acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg)
206 {
207 u64 address;
208 u64 value64;
209 acpi_status status;
210
211 ACPI_FUNCTION_NAME(hw_read);
212
213 /* Validate contents of the GAS register */
214
215 status = acpi_hw_validate_register(reg, 32, &address);
216 if (ACPI_FAILURE(status)) {
217 return (status);
218 }
219
220 /* Initialize entire 32-bit return value to zero */
221
222 *value = 0;
223
224 /*
225 * Two address spaces supported: Memory or IO. PCI_Config is
226 * not supported here because the GAS structure is insufficient
227 */
228 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
229 status = acpi_os_read_memory((acpi_physical_address)
230 address, &value64, reg->bit_width);
231
232 *value = (u32)value64;
233 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
234
235 status = acpi_hw_read_port((acpi_io_address)
236 address, value, reg->bit_width);
237 }
238
239 ACPI_DEBUG_PRINT((ACPI_DB_IO,
240 "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n",
241 *value, reg->bit_width, ACPI_FORMAT_UINT64(address),
242 acpi_ut_get_region_name(reg->space_id)));
243
244 return (status);
245 }
246
247 /******************************************************************************
248 *
249 * FUNCTION: acpi_hw_write
250 *
251 * PARAMETERS: value - Value to be written
252 * reg - GAS register structure
253 *
254 * RETURN: Status
255 *
256 * DESCRIPTION: Write to either memory or IO space. This is a 32-bit max
257 * version of acpi_write, used internally since the overhead of
258 * 64-bit values is not needed.
259 *
260 ******************************************************************************/
261
262 acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg)
263 {
264 u64 address;
265 acpi_status status;
266
267 ACPI_FUNCTION_NAME(hw_write);
268
269 /* Validate contents of the GAS register */
270
271 status = acpi_hw_validate_register(reg, 32, &address);
272 if (ACPI_FAILURE(status)) {
273 return (status);
274 }
275
276 /*
277 * Two address spaces supported: Memory or IO. PCI_Config is
278 * not supported here because the GAS structure is insufficient
279 */
280 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
281 status = acpi_os_write_memory((acpi_physical_address)
282 address, (u64)value,
283 reg->bit_width);
284 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
285
286 status = acpi_hw_write_port((acpi_io_address)
287 address, value, reg->bit_width);
288 }
289
290 ACPI_DEBUG_PRINT((ACPI_DB_IO,
291 "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n",
292 value, reg->bit_width, ACPI_FORMAT_UINT64(address),
293 acpi_ut_get_region_name(reg->space_id)));
294
295 return (status);
296 }
297
298 #if (!ACPI_REDUCED_HARDWARE)
299 /*******************************************************************************
300 *
301 * FUNCTION: acpi_hw_clear_acpi_status
302 *
303 * PARAMETERS: None
304 *
305 * RETURN: Status
306 *
307 * DESCRIPTION: Clears all fixed and general purpose status bits
308 *
309 ******************************************************************************/
310
311 acpi_status acpi_hw_clear_acpi_status(void)
312 {
313 acpi_status status;
314 acpi_cpu_flags lock_flags = 0;
315
316 ACPI_FUNCTION_TRACE(hw_clear_acpi_status);
317
318 ACPI_DEBUG_PRINT((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n",
319 ACPI_BITMASK_ALL_FIXED_STATUS,
320 ACPI_FORMAT_UINT64(acpi_gbl_xpm1a_status.address)));
321
322 lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock);
323
324 /* Clear the fixed events in PM1 A/B */
325
326 status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS,
327 ACPI_BITMASK_ALL_FIXED_STATUS);
328
329 acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags);
330
331 if (ACPI_FAILURE(status)) {
332 goto exit;
333 }
334
335 /* Clear the GPE Bits in all GPE registers in all GPE blocks */
336
337 status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block, NULL);
338
339 exit:
340 return_ACPI_STATUS(status);
341 }
342
343 /*******************************************************************************
344 *
345 * FUNCTION: acpi_hw_get_bit_register_info
346 *
347 * PARAMETERS: register_id - Index of ACPI Register to access
348 *
349 * RETURN: The bitmask to be used when accessing the register
350 *
351 * DESCRIPTION: Map register_id into a register bitmask.
352 *
353 ******************************************************************************/
354
355 struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id)
356 {
357 ACPI_FUNCTION_ENTRY();
358
359 if (register_id > ACPI_BITREG_MAX) {
360 ACPI_ERROR((AE_INFO, "Invalid BitRegister ID: 0x%X",
361 register_id));
362 return (NULL);
363 }
364
365 return (&acpi_gbl_bit_register_info[register_id]);
366 }
367
368 /******************************************************************************
369 *
370 * FUNCTION: acpi_hw_write_pm1_control
371 *
372 * PARAMETERS: pm1a_control - Value to be written to PM1A control
373 * pm1b_control - Value to be written to PM1B control
374 *
375 * RETURN: Status
376 *
377 * DESCRIPTION: Write the PM1 A/B control registers. These registers are
378 * different than than the PM1 A/B status and enable registers
379 * in that different values can be written to the A/B registers.
380 * Most notably, the SLP_TYP bits can be different, as per the
381 * values returned from the _Sx predefined methods.
382 *
383 ******************************************************************************/
384
385 acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control)
386 {
387 acpi_status status;
388
389 ACPI_FUNCTION_TRACE(hw_write_pm1_control);
390
391 status =
392 acpi_hw_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block);
393 if (ACPI_FAILURE(status)) {
394 return_ACPI_STATUS(status);
395 }
396
397 if (acpi_gbl_FADT.xpm1b_control_block.address) {
398 status =
399 acpi_hw_write(pm1b_control,
400 &acpi_gbl_FADT.xpm1b_control_block);
401 }
402 return_ACPI_STATUS(status);
403 }
404
405 /******************************************************************************
406 *
407 * FUNCTION: acpi_hw_register_read
408 *
409 * PARAMETERS: register_id - ACPI Register ID
410 * return_value - Where the register value is returned
411 *
412 * RETURN: Status and the value read.
413 *
414 * DESCRIPTION: Read from the specified ACPI register
415 *
416 ******************************************************************************/
417 acpi_status acpi_hw_register_read(u32 register_id, u32 *return_value)
418 {
419 u32 value = 0;
420 acpi_status status;
421
422 ACPI_FUNCTION_TRACE(hw_register_read);
423
424 switch (register_id) {
425 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
426
427 status = acpi_hw_read_multiple(&value,
428 &acpi_gbl_xpm1a_status,
429 &acpi_gbl_xpm1b_status);
430 break;
431
432 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
433
434 status = acpi_hw_read_multiple(&value,
435 &acpi_gbl_xpm1a_enable,
436 &acpi_gbl_xpm1b_enable);
437 break;
438
439 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
440
441 status = acpi_hw_read_multiple(&value,
442 &acpi_gbl_FADT.
443 xpm1a_control_block,
444 &acpi_gbl_FADT.
445 xpm1b_control_block);
446
447 /*
448 * Zero the write-only bits. From the ACPI specification, "Hardware
449 * Write-Only Bits": "Upon reads to registers with write-only bits,
450 * software masks out all write-only bits."
451 */
452 value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
453 break;
454
455 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
456
457 status =
458 acpi_hw_read(&value, &acpi_gbl_FADT.xpm2_control_block);
459 break;
460
461 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
462
463 status = acpi_hw_read(&value, &acpi_gbl_FADT.xpm_timer_block);
464 break;
465
466 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
467
468 status =
469 acpi_hw_read_port(acpi_gbl_FADT.smi_command, &value, 8);
470 break;
471
472 default:
473
474 ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id));
475 status = AE_BAD_PARAMETER;
476 break;
477 }
478
479 if (ACPI_SUCCESS(status)) {
480 *return_value = value;
481 }
482
483 return_ACPI_STATUS(status);
484 }
485
486 /******************************************************************************
487 *
488 * FUNCTION: acpi_hw_register_write
489 *
490 * PARAMETERS: register_id - ACPI Register ID
491 * value - The value to write
492 *
493 * RETURN: Status
494 *
495 * DESCRIPTION: Write to the specified ACPI register
496 *
497 * NOTE: In accordance with the ACPI specification, this function automatically
498 * preserves the value of the following bits, meaning that these bits cannot be
499 * changed via this interface:
500 *
501 * PM1_CONTROL[0] = SCI_EN
502 * PM1_CONTROL[9]
503 * PM1_STATUS[11]
504 *
505 * ACPI References:
506 * 1) Hardware Ignored Bits: When software writes to a register with ignored
507 * bit fields, it preserves the ignored bit fields
508 * 2) SCI_EN: OSPM always preserves this bit position
509 *
510 ******************************************************************************/
511
512 acpi_status acpi_hw_register_write(u32 register_id, u32 value)
513 {
514 acpi_status status;
515 u32 read_value;
516
517 ACPI_FUNCTION_TRACE(hw_register_write);
518
519 switch (register_id) {
520 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
521 /*
522 * Handle the "ignored" bit in PM1 Status. According to the ACPI
523 * specification, ignored bits are to be preserved when writing.
524 * Normally, this would mean a read/modify/write sequence. However,
525 * preserving a bit in the status register is different. Writing a
526 * one clears the status, and writing a zero preserves the status.
527 * Therefore, we must always write zero to the ignored bit.
528 *
529 * This behavior is clarified in the ACPI 4.0 specification.
530 */
531 value &= ~ACPI_PM1_STATUS_PRESERVED_BITS;
532
533 status = acpi_hw_write_multiple(value,
534 &acpi_gbl_xpm1a_status,
535 &acpi_gbl_xpm1b_status);
536 break;
537
538 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
539
540 status = acpi_hw_write_multiple(value,
541 &acpi_gbl_xpm1a_enable,
542 &acpi_gbl_xpm1b_enable);
543 break;
544
545 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
546 /*
547 * Perform a read first to preserve certain bits (per ACPI spec)
548 * Note: This includes SCI_EN, we never want to change this bit
549 */
550 status = acpi_hw_read_multiple(&read_value,
551 &acpi_gbl_FADT.
552 xpm1a_control_block,
553 &acpi_gbl_FADT.
554 xpm1b_control_block);
555 if (ACPI_FAILURE(status)) {
556 goto exit;
557 }
558
559 /* Insert the bits to be preserved */
560
561 ACPI_INSERT_BITS(value, ACPI_PM1_CONTROL_PRESERVED_BITS,
562 read_value);
563
564 /* Now we can write the data */
565
566 status = acpi_hw_write_multiple(value,
567 &acpi_gbl_FADT.
568 xpm1a_control_block,
569 &acpi_gbl_FADT.
570 xpm1b_control_block);
571 break;
572
573 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
574 /*
575 * For control registers, all reserved bits must be preserved,
576 * as per the ACPI spec.
577 */
578 status =
579 acpi_hw_read(&read_value,
580 &acpi_gbl_FADT.xpm2_control_block);
581 if (ACPI_FAILURE(status)) {
582 goto exit;
583 }
584
585 /* Insert the bits to be preserved */
586
587 ACPI_INSERT_BITS(value, ACPI_PM2_CONTROL_PRESERVED_BITS,
588 read_value);
589
590 status =
591 acpi_hw_write(value, &acpi_gbl_FADT.xpm2_control_block);
592 break;
593
594 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
595
596 status = acpi_hw_write(value, &acpi_gbl_FADT.xpm_timer_block);
597 break;
598
599 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
600
601 /* SMI_CMD is currently always in IO space */
602
603 status =
604 acpi_hw_write_port(acpi_gbl_FADT.smi_command, value, 8);
605 break;
606
607 default:
608
609 ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id));
610 status = AE_BAD_PARAMETER;
611 break;
612 }
613
614 exit:
615 return_ACPI_STATUS(status);
616 }
617
618 /******************************************************************************
619 *
620 * FUNCTION: acpi_hw_read_multiple
621 *
622 * PARAMETERS: value - Where the register value is returned
623 * register_a - First ACPI register (required)
624 * register_b - Second ACPI register (optional)
625 *
626 * RETURN: Status
627 *
628 * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
629 *
630 ******************************************************************************/
631
632 static acpi_status
633 acpi_hw_read_multiple(u32 *value,
634 struct acpi_generic_address *register_a,
635 struct acpi_generic_address *register_b)
636 {
637 u32 value_a = 0;
638 u32 value_b = 0;
639 acpi_status status;
640
641 /* The first register is always required */
642
643 status = acpi_hw_read(&value_a, register_a);
644 if (ACPI_FAILURE(status)) {
645 return (status);
646 }
647
648 /* Second register is optional */
649
650 if (register_b->address) {
651 status = acpi_hw_read(&value_b, register_b);
652 if (ACPI_FAILURE(status)) {
653 return (status);
654 }
655 }
656
657 /*
658 * OR the two return values together. No shifting or masking is necessary,
659 * because of how the PM1 registers are defined in the ACPI specification:
660 *
661 * "Although the bits can be split between the two register blocks (each
662 * register block has a unique pointer within the FADT), the bit positions
663 * are maintained. The register block with unimplemented bits (that is,
664 * those implemented in the other register block) always returns zeros,
665 * and writes have no side effects"
666 */
667 *value = (value_a | value_b);
668 return (AE_OK);
669 }
670
671 /******************************************************************************
672 *
673 * FUNCTION: acpi_hw_write_multiple
674 *
675 * PARAMETERS: value - The value to write
676 * register_a - First ACPI register (required)
677 * register_b - Second ACPI register (optional)
678 *
679 * RETURN: Status
680 *
681 * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
682 *
683 ******************************************************************************/
684
685 static acpi_status
686 acpi_hw_write_multiple(u32 value,
687 struct acpi_generic_address *register_a,
688 struct acpi_generic_address *register_b)
689 {
690 acpi_status status;
691
692 /* The first register is always required */
693
694 status = acpi_hw_write(value, register_a);
695 if (ACPI_FAILURE(status)) {
696 return (status);
697 }
698
699 /*
700 * Second register is optional
701 *
702 * No bit shifting or clearing is necessary, because of how the PM1
703 * registers are defined in the ACPI specification:
704 *
705 * "Although the bits can be split between the two register blocks (each
706 * register block has a unique pointer within the FADT), the bit positions
707 * are maintained. The register block with unimplemented bits (that is,
708 * those implemented in the other register block) always returns zeros,
709 * and writes have no side effects"
710 */
711 if (register_b->address) {
712 status = acpi_hw_write(value, register_b);
713 }
714
715 return (status);
716 }
717
718 #endif /* !ACPI_REDUCED_HARDWARE */