drivers/amba/tegra-ahb.c

   1 /*
   2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   3  * Copyright (C) 2011 Google, Inc.
   4  *
   5  * Author:
   6  *      Jay Cheng <jacheng@nvidia.com>
   7  *      James Wylder <james.wylder@motorola.com>
   8  *      Benoit Goby <benoit@android.com>
   9  *      Colin Cross <ccross@android.com>
  10  *      Hiroshi DOYU <hdoyu@nvidia.com>
  11  *
  12  * This software is licensed under the terms of the GNU General Public
  13  * License version 2, as published by the Free Software Foundation, and
  14  * may be copied, distributed, and modified under those terms.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  */
  22
  23 #include <linux/err.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/io.h>
  28 #include <linux/of.h>
  29
  30 #include <soc/tegra/ahb.h>
  31
  32 #define DRV_NAME "tegra-ahb"
  33
  34 #define AHB_ARBITRATION_DISABLE         0x04
  35 #define AHB_ARBITRATION_PRIORITY_CTRL   0x08
  36 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
  37 #define   PRIORITY_SELECT_USB BIT(6)
  38 #define   PRIORITY_SELECT_USB2 BIT(18)
  39 #define   PRIORITY_SELECT_USB3 BIT(17)
  40
  41 #define AHB_GIZMO_AHB_MEM               0x10
  42 #define   ENB_FAST_REARBITRATE BIT(2)
  43 #define   DONT_SPLIT_AHB_WR     BIT(7)
  44
  45 #define AHB_GIZMO_APB_DMA               0x14
  46 #define AHB_GIZMO_IDE                   0x1c
  47 #define AHB_GIZMO_USB                   0x20
  48 #define AHB_GIZMO_AHB_XBAR_BRIDGE       0x24
  49 #define AHB_GIZMO_CPU_AHB_BRIDGE        0x28
  50 #define AHB_GIZMO_COP_AHB_BRIDGE        0x2c
  51 #define AHB_GIZMO_XBAR_APB_CTLR         0x30
  52 #define AHB_GIZMO_VCP_AHB_BRIDGE        0x34
  53 #define AHB_GIZMO_NAND                  0x40
  54 #define AHB_GIZMO_SDMMC4                0x48
  55 #define AHB_GIZMO_XIO                   0x4c
  56 #define AHB_GIZMO_BSEV                  0x64
  57 #define AHB_GIZMO_BSEA                  0x74
  58 #define AHB_GIZMO_NOR                   0x78
  59 #define AHB_GIZMO_USB2                  0x7c
  60 #define AHB_GIZMO_USB3                  0x80
  61 #define   IMMEDIATE     BIT(18)
  62
  63 #define AHB_GIZMO_SDMMC1                0x84
  64 #define AHB_GIZMO_SDMMC2                0x88
  65 #define AHB_GIZMO_SDMMC3                0x8c
  66 #define AHB_MEM_PREFETCH_CFG_X          0xdc
  67 #define AHB_ARBITRATION_XBAR_CTRL       0xe0
  68 #define AHB_MEM_PREFETCH_CFG3           0xe4
  69 #define AHB_MEM_PREFETCH_CFG4           0xe8
  70 #define AHB_MEM_PREFETCH_CFG1           0xf0
  71 #define AHB_MEM_PREFETCH_CFG2           0xf4
  72 #define   PREFETCH_ENB  BIT(31)
  73 #define   MST_ID(x)     (((x) & 0x1f) << 26)
  74 #define   AHBDMA_MST_ID MST_ID(5)
  75 #define   USB_MST_ID    MST_ID(6)
  76 #define   USB2_MST_ID   MST_ID(18)
  77 #define   USB3_MST_ID   MST_ID(17)
  78 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
  79 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
  80
  81 #define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID    0xfc
  82
  83 #define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)
  84
  85 static struct platform_driver tegra_ahb_driver;
  86
  87 static const u32 tegra_ahb_gizmo[] = {
  88         AHB_ARBITRATION_DISABLE,
  89         AHB_ARBITRATION_PRIORITY_CTRL,
  90         AHB_GIZMO_AHB_MEM,
  91         AHB_GIZMO_APB_DMA,
  92         AHB_GIZMO_IDE,
  93         AHB_GIZMO_USB,
  94         AHB_GIZMO_AHB_XBAR_BRIDGE,
  95         AHB_GIZMO_CPU_AHB_BRIDGE,
  96         AHB_GIZMO_COP_AHB_BRIDGE,
  97         AHB_GIZMO_XBAR_APB_CTLR,
  98         AHB_GIZMO_VCP_AHB_BRIDGE,
  99         AHB_GIZMO_NAND,
 100         AHB_GIZMO_SDMMC4,
 101         AHB_GIZMO_XIO,
 102         AHB_GIZMO_BSEV,
 103         AHB_GIZMO_BSEA,
 104         AHB_GIZMO_NOR,
 105         AHB_GIZMO_USB2,
 106         AHB_GIZMO_USB3,
 107         AHB_GIZMO_SDMMC1,
 108         AHB_GIZMO_SDMMC2,
 109         AHB_GIZMO_SDMMC3,
 110         AHB_MEM_PREFETCH_CFG_X,
 111         AHB_ARBITRATION_XBAR_CTRL,
 112         AHB_MEM_PREFETCH_CFG3,
 113         AHB_MEM_PREFETCH_CFG4,
 114         AHB_MEM_PREFETCH_CFG1,
 115         AHB_MEM_PREFETCH_CFG2,
 116         AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
 117 };
 118
 119 struct tegra_ahb {
 120         void __iomem    *regs;
 121         struct device   *dev;
 122         u32             ctx[0];
 123 };
 124
 125 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
 126 {
 127         return readl(ahb->regs - 4 + offset);
 128 }
 129
 130 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
 131 {
 132         writel(value, ahb->regs - 4 + offset);
 133 }
 134
 135 #ifdef CONFIG_TEGRA_IOMMU_SMMU
 136 static int tegra_ahb_match_by_smmu(struct device *dev, void *data)
 137 {
 138         struct tegra_ahb *ahb = dev_get_drvdata(dev);
 139         struct device_node *dn = data;
 140
 141         return (ahb->dev->of_node == dn) ? 1 : 0;
 142 }
 143
 144 int tegra_ahb_enable_smmu(struct device_node *dn)
 145 {
 146         struct device *dev;
 147         u32 val;
 148         struct tegra_ahb *ahb;
 149
 150         dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn,
 151                                  tegra_ahb_match_by_smmu);
 152         if (!dev)
 153                 return -EPROBE_DEFER;
 154         ahb = dev_get_drvdata(dev);
 155         val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
 156         val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
 157         gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
 158         return 0;
 159 }
 160 EXPORT_SYMBOL(tegra_ahb_enable_smmu);
 161 #endif
 162
 163 #ifdef CONFIG_PM
 164 static int tegra_ahb_suspend(struct device *dev)
 165 {
 166         int i;
 167         struct tegra_ahb *ahb = dev_get_drvdata(dev);
 168
 169         for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
 170                 ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
 171         return 0;
 172 }
 173
 174 static int tegra_ahb_resume(struct device *dev)
 175 {
 176         int i;
 177         struct tegra_ahb *ahb = dev_get_drvdata(dev);
 178
 179         for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
 180                 gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
 181         return 0;
 182 }
 183 #endif
 184
 185 static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
 186                             tegra_ahb_suspend,
 187                             tegra_ahb_resume, NULL);
 188
 189 static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
 190 {
 191         u32 val;
 192
 193         val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
 194         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
 195         gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
 196
 197         val = gizmo_readl(ahb, AHB_GIZMO_USB);
 198         val |= IMMEDIATE;
 199         gizmo_writel(ahb, val, AHB_GIZMO_USB);
 200
 201         val = gizmo_readl(ahb, AHB_GIZMO_USB2);
 202         val |= IMMEDIATE;
 203         gizmo_writel(ahb, val, AHB_GIZMO_USB2);
 204
 205         val = gizmo_readl(ahb, AHB_GIZMO_USB3);
 206         val |= IMMEDIATE;
 207         gizmo_writel(ahb, val, AHB_GIZMO_USB3);
 208
 209         val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
 210         val |= PRIORITY_SELECT_USB |
 211                 PRIORITY_SELECT_USB2 |
 212                 PRIORITY_SELECT_USB3 |
 213                 AHB_PRIORITY_WEIGHT(7);
 214         gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
 215
 216         val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
 217         val &= ~MST_ID(~0);
 218         val |= PREFETCH_ENB |
 219                 AHBDMA_MST_ID |
 220                 ADDR_BNDRY(0xc) |
 221                 INACTIVITY_TIMEOUT(0x1000);
 222         gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
 223
 224         val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
 225         val &= ~MST_ID(~0);
 226         val |= PREFETCH_ENB |
 227                 USB_MST_ID |
 228                 ADDR_BNDRY(0xc) |
 229                 INACTIVITY_TIMEOUT(0x1000);
 230         gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
 231
 232         val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
 233         val &= ~MST_ID(~0);
 234         val |= PREFETCH_ENB |
 235                 USB3_MST_ID |
 236                 ADDR_BNDRY(0xc) |
 237                 INACTIVITY_TIMEOUT(0x1000);
 238         gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
 239
 240         val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
 241         val &= ~MST_ID(~0);
 242         val |= PREFETCH_ENB |
 243                 USB2_MST_ID |
 244                 ADDR_BNDRY(0xc) |
 245                 INACTIVITY_TIMEOUT(0x1000);
 246         gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
 247 }
 248
 249 static int tegra_ahb_probe(struct platform_device *pdev)
 250 {
 251         struct resource *res;
 252         struct tegra_ahb *ahb;
 253         size_t bytes;
 254
 255         bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
 256         ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
 257         if (!ahb)
 258                 return -ENOMEM;
 259
 260         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 261         ahb->regs = devm_ioremap_resource(&pdev->dev, res);
 262         if (IS_ERR(ahb->regs))
 263                 return PTR_ERR(ahb->regs);
 264
 265         ahb->dev = &pdev->dev;
 266         platform_set_drvdata(pdev, ahb);
 267         tegra_ahb_gizmo_init(ahb);
 268         return 0;
 269 }
 270
 271 static const struct of_device_id tegra_ahb_of_match[] = {
 272         { .compatible = "nvidia,tegra30-ahb", },
 273         { .compatible = "nvidia,tegra20-ahb", },
 274         {},
 275 };
 276
 277 static struct platform_driver tegra_ahb_driver = {
 278         .probe = tegra_ahb_probe,
 279         .driver = {
 280                 .name = DRV_NAME,
 281                 .of_match_table = tegra_ahb_of_match,
 282                 .pm = &tegra_ahb_pm,
 283         },
 284 };
 285 module_platform_driver(tegra_ahb_driver);
 286
 287 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
 288 MODULE_DESCRIPTION("Tegra AHB driver");
 289 MODULE_LICENSE("GPL v2");
 290 MODULE_ALIAS("platform:" DRV_NAME);