2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
52 static int ahci_skip_host_reset
;
53 module_param_named(skip_host_reset
, ahci_skip_host_reset
, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset
, "skip global host reset (0=don't skip, 1=skip)");
56 static int ahci_enable_alpm(struct ata_port
*ap
,
58 static void ahci_disable_alpm(struct ata_port
*ap
);
63 AHCI_MAX_SG
= 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY
= 0xffffffff,
65 AHCI_USE_CLUSTERING
= 1,
68 AHCI_CMD_SLOT_SZ
= AHCI_MAX_CMDS
* AHCI_CMD_SZ
,
70 AHCI_CMD_TBL_CDB
= 0x40,
71 AHCI_CMD_TBL_HDR_SZ
= 0x80,
72 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR_SZ
+ (AHCI_MAX_SG
* 16),
73 AHCI_CMD_TBL_AR_SZ
= AHCI_CMD_TBL_SZ
* AHCI_MAX_CMDS
,
74 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_AR_SZ
+
76 AHCI_IRQ_ON_SG
= (1 << 31),
77 AHCI_CMD_ATAPI
= (1 << 5),
78 AHCI_CMD_WRITE
= (1 << 6),
79 AHCI_CMD_PREFETCH
= (1 << 7),
80 AHCI_CMD_RESET
= (1 << 8),
81 AHCI_CMD_CLR_BUSY
= (1 << 10),
83 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
84 RX_FIS_SDB
= 0x58, /* offset of SDB FIS data */
85 RX_FIS_UNK
= 0x60, /* offset of Unknown FIS data */
88 board_ahci_vt8251
= 1,
89 board_ahci_ign_iferr
= 2,
94 /* global controller registers */
95 HOST_CAP
= 0x00, /* host capabilities */
96 HOST_CTL
= 0x04, /* global host control */
97 HOST_IRQ_STAT
= 0x08, /* interrupt status */
98 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
99 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
102 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
103 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
104 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
107 HOST_CAP_SSC
= (1 << 14), /* Slumber capable */
108 HOST_CAP_PMP
= (1 << 17), /* Port Multiplier support */
109 HOST_CAP_CLO
= (1 << 24), /* Command List Override support */
110 HOST_CAP_ALPM
= (1 << 26), /* Aggressive Link PM support */
111 HOST_CAP_SSS
= (1 << 27), /* Staggered Spin-up */
112 HOST_CAP_SNTF
= (1 << 29), /* SNotification register */
113 HOST_CAP_NCQ
= (1 << 30), /* Native Command Queueing */
114 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
116 /* registers for each SATA port */
117 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
118 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
119 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
120 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
121 PORT_IRQ_STAT
= 0x10, /* interrupt status */
122 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
123 PORT_CMD
= 0x18, /* port command */
124 PORT_TFDATA
= 0x20, /* taskfile data */
125 PORT_SIG
= 0x24, /* device TF signature */
126 PORT_CMD_ISSUE
= 0x38, /* command issue */
127 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
128 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
129 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
130 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
131 PORT_SCR_NTF
= 0x3c, /* SATA phy register: SNotification */
133 /* PORT_IRQ_{STAT,MASK} bits */
134 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
135 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
136 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
137 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
138 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
139 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
140 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
141 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
143 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
144 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
145 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
146 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
147 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
148 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
149 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
150 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
151 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
153 PORT_IRQ_FREEZE
= PORT_IRQ_HBUS_ERR
|
159 PORT_IRQ_ERROR
= PORT_IRQ_FREEZE
|
161 PORT_IRQ_HBUS_DATA_ERR
,
162 DEF_PORT_IRQ
= PORT_IRQ_ERROR
| PORT_IRQ_SG_DONE
|
163 PORT_IRQ_SDB_FIS
| PORT_IRQ_DMAS_FIS
|
164 PORT_IRQ_PIOS_FIS
| PORT_IRQ_D2H_REG_FIS
,
167 PORT_CMD_ASP
= (1 << 27), /* Aggressive Slumber/Partial */
168 PORT_CMD_ALPE
= (1 << 26), /* Aggressive Link PM enable */
169 PORT_CMD_ATAPI
= (1 << 24), /* Device is ATAPI */
170 PORT_CMD_PMP
= (1 << 17), /* PMP attached */
171 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
172 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
173 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
174 PORT_CMD_CLO
= (1 << 3), /* Command list override */
175 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
176 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
177 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
179 PORT_CMD_ICC_MASK
= (0xf << 28), /* i/f ICC state mask */
180 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
181 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
182 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
184 /* hpriv->flags bits */
185 AHCI_HFLAG_NO_NCQ
= (1 << 0),
186 AHCI_HFLAG_IGN_IRQ_IF_ERR
= (1 << 1), /* ignore IRQ_IF_ERR */
187 AHCI_HFLAG_IGN_SERR_INTERNAL
= (1 << 2), /* ignore SERR_INTERNAL */
188 AHCI_HFLAG_32BIT_ONLY
= (1 << 3), /* force 32bit */
189 AHCI_HFLAG_MV_PATA
= (1 << 4), /* PATA port */
190 AHCI_HFLAG_NO_MSI
= (1 << 5), /* no PCI MSI */
191 AHCI_HFLAG_NO_PMP
= (1 << 6), /* no PMP */
192 AHCI_HFLAG_NO_HOTPLUG
= (1 << 7), /* ignore PxSERR.DIAG.N */
193 AHCI_HFLAG_SECT255
= (1 << 8), /* max 255 sectors */
197 AHCI_FLAG_COMMON
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
198 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
199 ATA_FLAG_ACPI_SATA
| ATA_FLAG_AN
|
202 ICH_MAP
= 0x90, /* ICH MAP register */
205 struct ahci_cmd_hdr
{
220 struct ahci_host_priv
{
221 unsigned int flags
; /* AHCI_HFLAG_* */
222 u32 cap
; /* cap to use */
223 u32 port_map
; /* port map to use */
224 u32 saved_cap
; /* saved initial cap */
225 u32 saved_port_map
; /* saved initial port_map */
228 struct ahci_port_priv
{
229 struct ata_link
*active_link
;
230 struct ahci_cmd_hdr
*cmd_slot
;
231 dma_addr_t cmd_slot_dma
;
233 dma_addr_t cmd_tbl_dma
;
235 dma_addr_t rx_fis_dma
;
236 /* for NCQ spurious interrupt analysis */
237 unsigned int ncq_saw_d2h
:1;
238 unsigned int ncq_saw_dmas
:1;
239 unsigned int ncq_saw_sdb
:1;
240 u32 intr_mask
; /* interrupts to enable */
243 static int ahci_scr_read(struct ata_port
*ap
, unsigned int sc_reg
, u32
*val
);
244 static int ahci_scr_write(struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
245 static int ahci_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
246 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
);
247 static void ahci_irq_clear(struct ata_port
*ap
);
248 static int ahci_port_start(struct ata_port
*ap
);
249 static void ahci_port_stop(struct ata_port
*ap
);
250 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
251 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
252 static u8
ahci_check_status(struct ata_port
*ap
);
253 static void ahci_freeze(struct ata_port
*ap
);
254 static void ahci_thaw(struct ata_port
*ap
);
255 static void ahci_pmp_attach(struct ata_port
*ap
);
256 static void ahci_pmp_detach(struct ata_port
*ap
);
257 static void ahci_error_handler(struct ata_port
*ap
);
258 static void ahci_vt8251_error_handler(struct ata_port
*ap
);
259 static void ahci_p5wdh_error_handler(struct ata_port
*ap
);
260 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
);
261 static int ahci_port_resume(struct ata_port
*ap
);
262 static void ahci_dev_config(struct ata_device
*dev
);
263 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_tbl
);
264 static void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, unsigned int tag
,
267 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
);
268 static int ahci_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
);
269 static int ahci_pci_device_resume(struct pci_dev
*pdev
);
272 static struct class_device_attribute
*ahci_shost_attrs
[] = {
273 &class_device_attr_link_power_management_policy
,
277 static struct scsi_host_template ahci_sht
= {
278 .module
= THIS_MODULE
,
280 .ioctl
= ata_scsi_ioctl
,
281 .queuecommand
= ata_scsi_queuecmd
,
282 .change_queue_depth
= ata_scsi_change_queue_depth
,
283 .can_queue
= AHCI_MAX_CMDS
- 1,
284 .this_id
= ATA_SHT_THIS_ID
,
285 .sg_tablesize
= AHCI_MAX_SG
,
286 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
287 .emulated
= ATA_SHT_EMULATED
,
288 .use_clustering
= AHCI_USE_CLUSTERING
,
289 .proc_name
= DRV_NAME
,
290 .dma_boundary
= AHCI_DMA_BOUNDARY
,
291 .slave_configure
= ata_scsi_slave_config
,
292 .slave_destroy
= ata_scsi_slave_destroy
,
293 .bios_param
= ata_std_bios_param
,
294 .shost_attrs
= ahci_shost_attrs
,
297 static const struct ata_port_operations ahci_ops
= {
298 .check_status
= ahci_check_status
,
299 .check_altstatus
= ahci_check_status
,
300 .dev_select
= ata_noop_dev_select
,
302 .dev_config
= ahci_dev_config
,
304 .tf_read
= ahci_tf_read
,
306 .qc_defer
= sata_pmp_qc_defer_cmd_switch
,
307 .qc_prep
= ahci_qc_prep
,
308 .qc_issue
= ahci_qc_issue
,
310 .irq_clear
= ahci_irq_clear
,
312 .scr_read
= ahci_scr_read
,
313 .scr_write
= ahci_scr_write
,
315 .freeze
= ahci_freeze
,
318 .error_handler
= ahci_error_handler
,
319 .post_internal_cmd
= ahci_post_internal_cmd
,
321 .pmp_attach
= ahci_pmp_attach
,
322 .pmp_detach
= ahci_pmp_detach
,
325 .port_suspend
= ahci_port_suspend
,
326 .port_resume
= ahci_port_resume
,
328 .enable_pm
= ahci_enable_alpm
,
329 .disable_pm
= ahci_disable_alpm
,
331 .port_start
= ahci_port_start
,
332 .port_stop
= ahci_port_stop
,
335 static const struct ata_port_operations ahci_vt8251_ops
= {
336 .check_status
= ahci_check_status
,
337 .check_altstatus
= ahci_check_status
,
338 .dev_select
= ata_noop_dev_select
,
340 .tf_read
= ahci_tf_read
,
342 .qc_defer
= sata_pmp_qc_defer_cmd_switch
,
343 .qc_prep
= ahci_qc_prep
,
344 .qc_issue
= ahci_qc_issue
,
346 .irq_clear
= ahci_irq_clear
,
348 .scr_read
= ahci_scr_read
,
349 .scr_write
= ahci_scr_write
,
351 .freeze
= ahci_freeze
,
354 .error_handler
= ahci_vt8251_error_handler
,
355 .post_internal_cmd
= ahci_post_internal_cmd
,
357 .pmp_attach
= ahci_pmp_attach
,
358 .pmp_detach
= ahci_pmp_detach
,
361 .port_suspend
= ahci_port_suspend
,
362 .port_resume
= ahci_port_resume
,
365 .port_start
= ahci_port_start
,
366 .port_stop
= ahci_port_stop
,
369 static const struct ata_port_operations ahci_p5wdh_ops
= {
370 .check_status
= ahci_check_status
,
371 .check_altstatus
= ahci_check_status
,
372 .dev_select
= ata_noop_dev_select
,
374 .tf_read
= ahci_tf_read
,
376 .qc_defer
= sata_pmp_qc_defer_cmd_switch
,
377 .qc_prep
= ahci_qc_prep
,
378 .qc_issue
= ahci_qc_issue
,
380 .irq_clear
= ahci_irq_clear
,
382 .scr_read
= ahci_scr_read
,
383 .scr_write
= ahci_scr_write
,
385 .freeze
= ahci_freeze
,
388 .error_handler
= ahci_p5wdh_error_handler
,
389 .post_internal_cmd
= ahci_post_internal_cmd
,
391 .pmp_attach
= ahci_pmp_attach
,
392 .pmp_detach
= ahci_pmp_detach
,
395 .port_suspend
= ahci_port_suspend
,
396 .port_resume
= ahci_port_resume
,
399 .port_start
= ahci_port_start
,
400 .port_stop
= ahci_port_stop
,
403 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
405 static const struct ata_port_info ahci_port_info
[] = {
408 .flags
= AHCI_FLAG_COMMON
,
409 .pio_mask
= 0x1f, /* pio0-4 */
410 .udma_mask
= ATA_UDMA6
,
411 .port_ops
= &ahci_ops
,
413 /* board_ahci_vt8251 */
415 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ
| AHCI_HFLAG_NO_PMP
),
416 .flags
= AHCI_FLAG_COMMON
,
417 .pio_mask
= 0x1f, /* pio0-4 */
418 .udma_mask
= ATA_UDMA6
,
419 .port_ops
= &ahci_vt8251_ops
,
421 /* board_ahci_ign_iferr */
423 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR
),
424 .flags
= AHCI_FLAG_COMMON
,
425 .pio_mask
= 0x1f, /* pio0-4 */
426 .udma_mask
= ATA_UDMA6
,
427 .port_ops
= &ahci_ops
,
429 /* board_ahci_sb600 */
431 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL
|
432 AHCI_HFLAG_32BIT_ONLY
|
433 AHCI_HFLAG_SECT255
| AHCI_HFLAG_NO_PMP
),
434 .flags
= AHCI_FLAG_COMMON
,
435 .pio_mask
= 0x1f, /* pio0-4 */
436 .udma_mask
= ATA_UDMA6
,
437 .port_ops
= &ahci_ops
,
441 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ
| AHCI_HFLAG_NO_MSI
|
443 .flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
444 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
,
445 .pio_mask
= 0x1f, /* pio0-4 */
446 .udma_mask
= ATA_UDMA6
,
447 .port_ops
= &ahci_ops
,
449 /* board_ahci_sb700 */
451 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL
|
453 .flags
= AHCI_FLAG_COMMON
,
454 .pio_mask
= 0x1f, /* pio0-4 */
455 .udma_mask
= ATA_UDMA6
,
456 .port_ops
= &ahci_ops
,
460 static const struct pci_device_id ahci_pci_tbl
[] = {
462 { PCI_VDEVICE(INTEL
, 0x2652), board_ahci
}, /* ICH6 */
463 { PCI_VDEVICE(INTEL
, 0x2653), board_ahci
}, /* ICH6M */
464 { PCI_VDEVICE(INTEL
, 0x27c1), board_ahci
}, /* ICH7 */
465 { PCI_VDEVICE(INTEL
, 0x27c5), board_ahci
}, /* ICH7M */
466 { PCI_VDEVICE(INTEL
, 0x27c3), board_ahci
}, /* ICH7R */
467 { PCI_VDEVICE(AL
, 0x5288), board_ahci_ign_iferr
}, /* ULi M5288 */
468 { PCI_VDEVICE(INTEL
, 0x2681), board_ahci
}, /* ESB2 */
469 { PCI_VDEVICE(INTEL
, 0x2682), board_ahci
}, /* ESB2 */
470 { PCI_VDEVICE(INTEL
, 0x2683), board_ahci
}, /* ESB2 */
471 { PCI_VDEVICE(INTEL
, 0x27c6), board_ahci
}, /* ICH7-M DH */
472 { PCI_VDEVICE(INTEL
, 0x2821), board_ahci
}, /* ICH8 */
473 { PCI_VDEVICE(INTEL
, 0x2822), board_ahci
}, /* ICH8 */
474 { PCI_VDEVICE(INTEL
, 0x2824), board_ahci
}, /* ICH8 */
475 { PCI_VDEVICE(INTEL
, 0x2829), board_ahci
}, /* ICH8M */
476 { PCI_VDEVICE(INTEL
, 0x282a), board_ahci
}, /* ICH8M */
477 { PCI_VDEVICE(INTEL
, 0x2922), board_ahci
}, /* ICH9 */
478 { PCI_VDEVICE(INTEL
, 0x2923), board_ahci
}, /* ICH9 */
479 { PCI_VDEVICE(INTEL
, 0x2924), board_ahci
}, /* ICH9 */
480 { PCI_VDEVICE(INTEL
, 0x2925), board_ahci
}, /* ICH9 */
481 { PCI_VDEVICE(INTEL
, 0x2927), board_ahci
}, /* ICH9 */
482 { PCI_VDEVICE(INTEL
, 0x2929), board_ahci
}, /* ICH9M */
483 { PCI_VDEVICE(INTEL
, 0x292a), board_ahci
}, /* ICH9M */
484 { PCI_VDEVICE(INTEL
, 0x292b), board_ahci
}, /* ICH9M */
485 { PCI_VDEVICE(INTEL
, 0x292c), board_ahci
}, /* ICH9M */
486 { PCI_VDEVICE(INTEL
, 0x292f), board_ahci
}, /* ICH9M */
487 { PCI_VDEVICE(INTEL
, 0x294d), board_ahci
}, /* ICH9 */
488 { PCI_VDEVICE(INTEL
, 0x294e), board_ahci
}, /* ICH9M */
489 { PCI_VDEVICE(INTEL
, 0x502a), board_ahci
}, /* Tolapai */
490 { PCI_VDEVICE(INTEL
, 0x502b), board_ahci
}, /* Tolapai */
491 { PCI_VDEVICE(INTEL
, 0x3a05), board_ahci
}, /* ICH10 */
492 { PCI_VDEVICE(INTEL
, 0x3a25), board_ahci
}, /* ICH10 */
494 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
495 { PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
,
496 PCI_CLASS_STORAGE_SATA_AHCI
, 0xffffff, board_ahci_ign_iferr
},
499 { PCI_VDEVICE(ATI
, 0x4380), board_ahci_sb600
}, /* ATI SB600 */
500 { PCI_VDEVICE(ATI
, 0x4390), board_ahci_sb700
}, /* ATI SB700/800 */
501 { PCI_VDEVICE(ATI
, 0x4391), board_ahci_sb700
}, /* ATI SB700/800 */
502 { PCI_VDEVICE(ATI
, 0x4392), board_ahci_sb700
}, /* ATI SB700/800 */
503 { PCI_VDEVICE(ATI
, 0x4393), board_ahci_sb700
}, /* ATI SB700/800 */
504 { PCI_VDEVICE(ATI
, 0x4394), board_ahci_sb700
}, /* ATI SB700/800 */
505 { PCI_VDEVICE(ATI
, 0x4395), board_ahci_sb700
}, /* ATI SB700/800 */
508 { PCI_VDEVICE(VIA
, 0x3349), board_ahci_vt8251
}, /* VIA VT8251 */
509 { PCI_VDEVICE(VIA
, 0x6287), board_ahci_vt8251
}, /* VIA VT8251 */
512 { PCI_VDEVICE(NVIDIA
, 0x044c), board_ahci
}, /* MCP65 */
513 { PCI_VDEVICE(NVIDIA
, 0x044d), board_ahci
}, /* MCP65 */
514 { PCI_VDEVICE(NVIDIA
, 0x044e), board_ahci
}, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA
, 0x044f), board_ahci
}, /* MCP65 */
516 { PCI_VDEVICE(NVIDIA
, 0x045c), board_ahci
}, /* MCP65 */
517 { PCI_VDEVICE(NVIDIA
, 0x045d), board_ahci
}, /* MCP65 */
518 { PCI_VDEVICE(NVIDIA
, 0x045e), board_ahci
}, /* MCP65 */
519 { PCI_VDEVICE(NVIDIA
, 0x045f), board_ahci
}, /* MCP65 */
520 { PCI_VDEVICE(NVIDIA
, 0x0550), board_ahci
}, /* MCP67 */
521 { PCI_VDEVICE(NVIDIA
, 0x0551), board_ahci
}, /* MCP67 */
522 { PCI_VDEVICE(NVIDIA
, 0x0552), board_ahci
}, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA
, 0x0553), board_ahci
}, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA
, 0x0554), board_ahci
}, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA
, 0x0555), board_ahci
}, /* MCP67 */
526 { PCI_VDEVICE(NVIDIA
, 0x0556), board_ahci
}, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA
, 0x0557), board_ahci
}, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA
, 0x0558), board_ahci
}, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA
, 0x0559), board_ahci
}, /* MCP67 */
530 { PCI_VDEVICE(NVIDIA
, 0x055a), board_ahci
}, /* MCP67 */
531 { PCI_VDEVICE(NVIDIA
, 0x055b), board_ahci
}, /* MCP67 */
532 { PCI_VDEVICE(NVIDIA
, 0x07f0), board_ahci
}, /* MCP73 */
533 { PCI_VDEVICE(NVIDIA
, 0x07f1), board_ahci
}, /* MCP73 */
534 { PCI_VDEVICE(NVIDIA
, 0x07f2), board_ahci
}, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA
, 0x07f3), board_ahci
}, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA
, 0x07f4), board_ahci
}, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA
, 0x07f5), board_ahci
}, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA
, 0x07f6), board_ahci
}, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA
, 0x07f7), board_ahci
}, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA
, 0x07f8), board_ahci
}, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA
, 0x07f9), board_ahci
}, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA
, 0x07fa), board_ahci
}, /* MCP73 */
543 { PCI_VDEVICE(NVIDIA
, 0x07fb), board_ahci
}, /* MCP73 */
544 { PCI_VDEVICE(NVIDIA
, 0x0ad0), board_ahci
}, /* MCP77 */
545 { PCI_VDEVICE(NVIDIA
, 0x0ad1), board_ahci
}, /* MCP77 */
546 { PCI_VDEVICE(NVIDIA
, 0x0ad2), board_ahci
}, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA
, 0x0ad3), board_ahci
}, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA
, 0x0ad4), board_ahci
}, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA
, 0x0ad5), board_ahci
}, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA
, 0x0ad6), board_ahci
}, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA
, 0x0ad7), board_ahci
}, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA
, 0x0ad8), board_ahci
}, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA
, 0x0ad9), board_ahci
}, /* MCP77 */
554 { PCI_VDEVICE(NVIDIA
, 0x0ada), board_ahci
}, /* MCP77 */
555 { PCI_VDEVICE(NVIDIA
, 0x0adb), board_ahci
}, /* MCP77 */
556 { PCI_VDEVICE(NVIDIA
, 0x0ab4), board_ahci
}, /* MCP79 */
557 { PCI_VDEVICE(NVIDIA
, 0x0ab5), board_ahci
}, /* MCP79 */
558 { PCI_VDEVICE(NVIDIA
, 0x0ab6), board_ahci
}, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA
, 0x0ab7), board_ahci
}, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA
, 0x0ab8), board_ahci
}, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA
, 0x0ab9), board_ahci
}, /* MCP79 */
562 { PCI_VDEVICE(NVIDIA
, 0x0aba), board_ahci
}, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA
, 0x0abb), board_ahci
}, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA
, 0x0abc), board_ahci
}, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA
, 0x0abd), board_ahci
}, /* MCP79 */
566 { PCI_VDEVICE(NVIDIA
, 0x0abe), board_ahci
}, /* MCP79 */
567 { PCI_VDEVICE(NVIDIA
, 0x0abf), board_ahci
}, /* MCP79 */
568 { PCI_VDEVICE(NVIDIA
, 0x0bc8), board_ahci
}, /* MCP7B */
569 { PCI_VDEVICE(NVIDIA
, 0x0bc9), board_ahci
}, /* MCP7B */
570 { PCI_VDEVICE(NVIDIA
, 0x0bca), board_ahci
}, /* MCP7B */
571 { PCI_VDEVICE(NVIDIA
, 0x0bcb), board_ahci
}, /* MCP7B */
572 { PCI_VDEVICE(NVIDIA
, 0x0bcc), board_ahci
}, /* MCP7B */
573 { PCI_VDEVICE(NVIDIA
, 0x0bcd), board_ahci
}, /* MCP7B */
574 { PCI_VDEVICE(NVIDIA
, 0x0bce), board_ahci
}, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA
, 0x0bcf), board_ahci
}, /* MCP7B */
576 { PCI_VDEVICE(NVIDIA
, 0x0bd0), board_ahci
}, /* MCP7B */
577 { PCI_VDEVICE(NVIDIA
, 0x0bd1), board_ahci
}, /* MCP7B */
578 { PCI_VDEVICE(NVIDIA
, 0x0bd2), board_ahci
}, /* MCP7B */
579 { PCI_VDEVICE(NVIDIA
, 0x0bd3), board_ahci
}, /* MCP7B */
582 { PCI_VDEVICE(SI
, 0x1184), board_ahci
}, /* SiS 966 */
583 { PCI_VDEVICE(SI
, 0x1185), board_ahci
}, /* SiS 966 */
584 { PCI_VDEVICE(SI
, 0x0186), board_ahci
}, /* SiS 968 */
587 { PCI_VDEVICE(MARVELL
, 0x6145), board_ahci_mv
}, /* 6145 */
588 { PCI_VDEVICE(MARVELL
, 0x6121), board_ahci_mv
}, /* 6121 */
590 /* Generic, PCI class code for AHCI */
591 { PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
,
592 PCI_CLASS_STORAGE_SATA_AHCI
, 0xffffff, board_ahci
},
594 { } /* terminate list */
598 static struct pci_driver ahci_pci_driver
= {
600 .id_table
= ahci_pci_tbl
,
601 .probe
= ahci_init_one
,
602 .remove
= ata_pci_remove_one
,
604 .suspend
= ahci_pci_device_suspend
,
605 .resume
= ahci_pci_device_resume
,
610 static inline int ahci_nr_ports(u32 cap
)
612 return (cap
& 0x1f) + 1;
615 static inline void __iomem
*__ahci_port_base(struct ata_host
*host
,
616 unsigned int port_no
)
618 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
620 return mmio
+ 0x100 + (port_no
* 0x80);
623 static inline void __iomem
*ahci_port_base(struct ata_port
*ap
)
625 return __ahci_port_base(ap
->host
, ap
->port_no
);
628 static void ahci_enable_ahci(void __iomem
*mmio
)
632 /* turn on AHCI_EN */
633 tmp
= readl(mmio
+ HOST_CTL
);
634 if (!(tmp
& HOST_AHCI_EN
)) {
636 writel(tmp
, mmio
+ HOST_CTL
);
637 tmp
= readl(mmio
+ HOST_CTL
); /* flush && sanity check */
638 WARN_ON(!(tmp
& HOST_AHCI_EN
));
643 * ahci_save_initial_config - Save and fixup initial config values
644 * @pdev: target PCI device
645 * @hpriv: host private area to store config values
647 * Some registers containing configuration info might be setup by
648 * BIOS and might be cleared on reset. This function saves the
649 * initial values of those registers into @hpriv such that they
650 * can be restored after controller reset.
652 * If inconsistent, config values are fixed up by this function.
657 static void ahci_save_initial_config(struct pci_dev
*pdev
,
658 struct ahci_host_priv
*hpriv
)
660 void __iomem
*mmio
= pcim_iomap_table(pdev
)[AHCI_PCI_BAR
];
665 /* make sure AHCI mode is enabled before accessing CAP */
666 ahci_enable_ahci(mmio
);
668 /* Values prefixed with saved_ are written back to host after
669 * reset. Values without are used for driver operation.
671 hpriv
->saved_cap
= cap
= readl(mmio
+ HOST_CAP
);
672 hpriv
->saved_port_map
= port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
674 /* some chips have errata preventing 64bit use */
675 if ((cap
& HOST_CAP_64
) && (hpriv
->flags
& AHCI_HFLAG_32BIT_ONLY
)) {
676 dev_printk(KERN_INFO
, &pdev
->dev
,
677 "controller can't do 64bit DMA, forcing 32bit\n");
681 if ((cap
& HOST_CAP_NCQ
) && (hpriv
->flags
& AHCI_HFLAG_NO_NCQ
)) {
682 dev_printk(KERN_INFO
, &pdev
->dev
,
683 "controller can't do NCQ, turning off CAP_NCQ\n");
684 cap
&= ~HOST_CAP_NCQ
;
687 if ((cap
& HOST_CAP_PMP
) && (hpriv
->flags
& AHCI_HFLAG_NO_PMP
)) {
688 dev_printk(KERN_INFO
, &pdev
->dev
,
689 "controller can't do PMP, turning off CAP_PMP\n");
690 cap
&= ~HOST_CAP_PMP
;
694 * Temporary Marvell 6145 hack: PATA port presence
695 * is asserted through the standard AHCI port
696 * presence register, as bit 4 (counting from 0)
698 if (hpriv
->flags
& AHCI_HFLAG_MV_PATA
) {
699 if (pdev
->device
== 0x6121)
703 dev_printk(KERN_ERR
, &pdev
->dev
,
704 "MV_AHCI HACK: port_map %x -> %x\n",
711 /* cross check port_map and cap.n_ports */
715 for (i
= 0; i
< AHCI_MAX_PORTS
; i
++)
716 if (port_map
& (1 << i
))
719 /* If PI has more ports than n_ports, whine, clear
720 * port_map and let it be generated from n_ports.
722 if (map_ports
> ahci_nr_ports(cap
)) {
723 dev_printk(KERN_WARNING
, &pdev
->dev
,
724 "implemented port map (0x%x) contains more "
725 "ports than nr_ports (%u), using nr_ports\n",
726 port_map
, ahci_nr_ports(cap
));
731 /* fabricate port_map from cap.nr_ports */
733 port_map
= (1 << ahci_nr_ports(cap
)) - 1;
734 dev_printk(KERN_WARNING
, &pdev
->dev
,
735 "forcing PORTS_IMPL to 0x%x\n", port_map
);
737 /* write the fixed up value to the PI register */
738 hpriv
->saved_port_map
= port_map
;
741 /* record values to use during operation */
743 hpriv
->port_map
= port_map
;
747 * ahci_restore_initial_config - Restore initial config
748 * @host: target ATA host
750 * Restore initial config stored by ahci_save_initial_config().
755 static void ahci_restore_initial_config(struct ata_host
*host
)
757 struct ahci_host_priv
*hpriv
= host
->private_data
;
758 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
760 writel(hpriv
->saved_cap
, mmio
+ HOST_CAP
);
761 writel(hpriv
->saved_port_map
, mmio
+ HOST_PORTS_IMPL
);
762 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
765 static unsigned ahci_scr_offset(struct ata_port
*ap
, unsigned int sc_reg
)
767 static const int offset
[] = {
768 [SCR_STATUS
] = PORT_SCR_STAT
,
769 [SCR_CONTROL
] = PORT_SCR_CTL
,
770 [SCR_ERROR
] = PORT_SCR_ERR
,
771 [SCR_ACTIVE
] = PORT_SCR_ACT
,
772 [SCR_NOTIFICATION
] = PORT_SCR_NTF
,
774 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
776 if (sc_reg
< ARRAY_SIZE(offset
) &&
777 (sc_reg
!= SCR_NOTIFICATION
|| (hpriv
->cap
& HOST_CAP_SNTF
)))
778 return offset
[sc_reg
];
782 static int ahci_scr_read(struct ata_port
*ap
, unsigned int sc_reg
, u32
*val
)
784 void __iomem
*port_mmio
= ahci_port_base(ap
);
785 int offset
= ahci_scr_offset(ap
, sc_reg
);
788 *val
= readl(port_mmio
+ offset
);
794 static int ahci_scr_write(struct ata_port
*ap
, unsigned int sc_reg
, u32 val
)
796 void __iomem
*port_mmio
= ahci_port_base(ap
);
797 int offset
= ahci_scr_offset(ap
, sc_reg
);
800 writel(val
, port_mmio
+ offset
);
806 static void ahci_start_engine(struct ata_port
*ap
)
808 void __iomem
*port_mmio
= ahci_port_base(ap
);
812 tmp
= readl(port_mmio
+ PORT_CMD
);
813 tmp
|= PORT_CMD_START
;
814 writel(tmp
, port_mmio
+ PORT_CMD
);
815 readl(port_mmio
+ PORT_CMD
); /* flush */
818 static int ahci_stop_engine(struct ata_port
*ap
)
820 void __iomem
*port_mmio
= ahci_port_base(ap
);
823 tmp
= readl(port_mmio
+ PORT_CMD
);
825 /* check if the HBA is idle */
826 if ((tmp
& (PORT_CMD_START
| PORT_CMD_LIST_ON
)) == 0)
829 /* setting HBA to idle */
830 tmp
&= ~PORT_CMD_START
;
831 writel(tmp
, port_mmio
+ PORT_CMD
);
833 /* wait for engine to stop. This could be as long as 500 msec */
834 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
835 PORT_CMD_LIST_ON
, PORT_CMD_LIST_ON
, 1, 500);
836 if (tmp
& PORT_CMD_LIST_ON
)
842 static void ahci_start_fis_rx(struct ata_port
*ap
)
844 void __iomem
*port_mmio
= ahci_port_base(ap
);
845 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
846 struct ahci_port_priv
*pp
= ap
->private_data
;
849 /* set FIS registers */
850 if (hpriv
->cap
& HOST_CAP_64
)
851 writel((pp
->cmd_slot_dma
>> 16) >> 16,
852 port_mmio
+ PORT_LST_ADDR_HI
);
853 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
855 if (hpriv
->cap
& HOST_CAP_64
)
856 writel((pp
->rx_fis_dma
>> 16) >> 16,
857 port_mmio
+ PORT_FIS_ADDR_HI
);
858 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
860 /* enable FIS reception */
861 tmp
= readl(port_mmio
+ PORT_CMD
);
862 tmp
|= PORT_CMD_FIS_RX
;
863 writel(tmp
, port_mmio
+ PORT_CMD
);
866 readl(port_mmio
+ PORT_CMD
);
869 static int ahci_stop_fis_rx(struct ata_port
*ap
)
871 void __iomem
*port_mmio
= ahci_port_base(ap
);
874 /* disable FIS reception */
875 tmp
= readl(port_mmio
+ PORT_CMD
);
876 tmp
&= ~PORT_CMD_FIS_RX
;
877 writel(tmp
, port_mmio
+ PORT_CMD
);
879 /* wait for completion, spec says 500ms, give it 1000 */
880 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
, PORT_CMD_FIS_ON
,
881 PORT_CMD_FIS_ON
, 10, 1000);
882 if (tmp
& PORT_CMD_FIS_ON
)
888 static void ahci_power_up(struct ata_port
*ap
)
890 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
891 void __iomem
*port_mmio
= ahci_port_base(ap
);
894 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
897 if (hpriv
->cap
& HOST_CAP_SSS
) {
898 cmd
|= PORT_CMD_SPIN_UP
;
899 writel(cmd
, port_mmio
+ PORT_CMD
);
903 writel(cmd
| PORT_CMD_ICC_ACTIVE
, port_mmio
+ PORT_CMD
);
906 static void ahci_disable_alpm(struct ata_port
*ap
)
908 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
909 void __iomem
*port_mmio
= ahci_port_base(ap
);
911 struct ahci_port_priv
*pp
= ap
->private_data
;
913 /* IPM bits should be disabled by libata-core */
914 /* get the existing command bits */
915 cmd
= readl(port_mmio
+ PORT_CMD
);
917 /* disable ALPM and ASP */
918 cmd
&= ~PORT_CMD_ASP
;
919 cmd
&= ~PORT_CMD_ALPE
;
921 /* force the interface back to active */
922 cmd
|= PORT_CMD_ICC_ACTIVE
;
924 /* write out new cmd value */
925 writel(cmd
, port_mmio
+ PORT_CMD
);
926 cmd
= readl(port_mmio
+ PORT_CMD
);
928 /* wait 10ms to be sure we've come out of any low power state */
931 /* clear out any PhyRdy stuff from interrupt status */
932 writel(PORT_IRQ_PHYRDY
, port_mmio
+ PORT_IRQ_STAT
);
934 /* go ahead and clean out PhyRdy Change from Serror too */
935 ahci_scr_write(ap
, SCR_ERROR
, ((1 << 16) | (1 << 18)));
938 * Clear flag to indicate that we should ignore all PhyRdy
941 hpriv
->flags
&= ~AHCI_HFLAG_NO_HOTPLUG
;
944 * Enable interrupts on Phy Ready.
946 pp
->intr_mask
|= PORT_IRQ_PHYRDY
;
947 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
950 * don't change the link pm policy - we can be called
951 * just to turn of link pm temporarily
955 static int ahci_enable_alpm(struct ata_port
*ap
,
958 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
959 void __iomem
*port_mmio
= ahci_port_base(ap
);
961 struct ahci_port_priv
*pp
= ap
->private_data
;
964 /* Make sure the host is capable of link power management */
965 if (!(hpriv
->cap
& HOST_CAP_ALPM
))
969 case MAX_PERFORMANCE
:
972 * if we came here with NOT_AVAILABLE,
973 * it just means this is the first time we
974 * have tried to enable - default to max performance,
975 * and let the user go to lower power modes on request.
977 ahci_disable_alpm(ap
);
980 /* configure HBA to enter SLUMBER */
984 /* configure HBA to enter PARTIAL */
992 * Disable interrupts on Phy Ready. This keeps us from
993 * getting woken up due to spurious phy ready interrupts
994 * TBD - Hot plug should be done via polling now, is
995 * that even supported?
997 pp
->intr_mask
&= ~PORT_IRQ_PHYRDY
;
998 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
1001 * Set a flag to indicate that we should ignore all PhyRdy
1002 * state changes since these can happen now whenever we
1005 hpriv
->flags
|= AHCI_HFLAG_NO_HOTPLUG
;
1007 /* get the existing command bits */
1008 cmd
= readl(port_mmio
+ PORT_CMD
);
1011 * Set ASP based on Policy
1016 * Setting this bit will instruct the HBA to aggressively
1017 * enter a lower power link state when it's appropriate and
1018 * based on the value set above for ASP
1020 cmd
|= PORT_CMD_ALPE
;
1022 /* write out new cmd value */
1023 writel(cmd
, port_mmio
+ PORT_CMD
);
1024 cmd
= readl(port_mmio
+ PORT_CMD
);
1026 /* IPM bits should be set by libata-core */
1031 static void ahci_power_down(struct ata_port
*ap
)
1033 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1034 void __iomem
*port_mmio
= ahci_port_base(ap
);
1037 if (!(hpriv
->cap
& HOST_CAP_SSS
))
1040 /* put device into listen mode, first set PxSCTL.DET to 0 */
1041 scontrol
= readl(port_mmio
+ PORT_SCR_CTL
);
1043 writel(scontrol
, port_mmio
+ PORT_SCR_CTL
);
1045 /* then set PxCMD.SUD to 0 */
1046 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
1047 cmd
&= ~PORT_CMD_SPIN_UP
;
1048 writel(cmd
, port_mmio
+ PORT_CMD
);
1052 static void ahci_start_port(struct ata_port
*ap
)
1054 /* enable FIS reception */
1055 ahci_start_fis_rx(ap
);
1058 ahci_start_engine(ap
);
1061 static int ahci_deinit_port(struct ata_port
*ap
, const char **emsg
)
1066 rc
= ahci_stop_engine(ap
);
1068 *emsg
= "failed to stop engine";
1072 /* disable FIS reception */
1073 rc
= ahci_stop_fis_rx(ap
);
1075 *emsg
= "failed stop FIS RX";
1082 static int ahci_reset_controller(struct ata_host
*host
)
1084 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1085 struct ahci_host_priv
*hpriv
= host
->private_data
;
1086 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
1089 /* we must be in AHCI mode, before using anything
1090 * AHCI-specific, such as HOST_RESET.
1092 ahci_enable_ahci(mmio
);
1094 /* global controller reset */
1095 if (!ahci_skip_host_reset
) {
1096 tmp
= readl(mmio
+ HOST_CTL
);
1097 if ((tmp
& HOST_RESET
) == 0) {
1098 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
1099 readl(mmio
+ HOST_CTL
); /* flush */
1102 /* reset must complete within 1 second, or
1103 * the hardware should be considered fried.
1107 tmp
= readl(mmio
+ HOST_CTL
);
1108 if (tmp
& HOST_RESET
) {
1109 dev_printk(KERN_ERR
, host
->dev
,
1110 "controller reset failed (0x%x)\n", tmp
);
1114 /* turn on AHCI mode */
1115 ahci_enable_ahci(mmio
);
1117 /* Some registers might be cleared on reset. Restore
1120 ahci_restore_initial_config(host
);
1122 dev_printk(KERN_INFO
, host
->dev
,
1123 "skipping global host reset\n");
1125 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
) {
1129 pci_read_config_word(pdev
, 0x92, &tmp16
);
1130 if ((tmp16
& hpriv
->port_map
) != hpriv
->port_map
) {
1131 tmp16
|= hpriv
->port_map
;
1132 pci_write_config_word(pdev
, 0x92, tmp16
);
1139 static void ahci_port_init(struct pci_dev
*pdev
, struct ata_port
*ap
,
1140 int port_no
, void __iomem
*mmio
,
1141 void __iomem
*port_mmio
)
1143 const char *emsg
= NULL
;
1147 /* make sure port is not active */
1148 rc
= ahci_deinit_port(ap
, &emsg
);
1150 dev_printk(KERN_WARNING
, &pdev
->dev
,
1151 "%s (%d)\n", emsg
, rc
);
1154 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
1155 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
1156 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
1158 /* clear port IRQ */
1159 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1160 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
1162 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1164 writel(1 << port_no
, mmio
+ HOST_IRQ_STAT
);
1167 static void ahci_init_controller(struct ata_host
*host
)
1169 struct ahci_host_priv
*hpriv
= host
->private_data
;
1170 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1171 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
1173 void __iomem
*port_mmio
;
1177 if (hpriv
->flags
& AHCI_HFLAG_MV_PATA
) {
1178 if (pdev
->device
== 0x6121)
1182 port_mmio
= __ahci_port_base(host
, mv
);
1184 writel(0, port_mmio
+ PORT_IRQ_MASK
);
1186 /* clear port IRQ */
1187 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1188 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
1190 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1193 for (i
= 0; i
< host
->n_ports
; i
++) {
1194 struct ata_port
*ap
= host
->ports
[i
];
1196 port_mmio
= ahci_port_base(ap
);
1197 if (ata_port_is_dummy(ap
))
1200 ahci_port_init(pdev
, ap
, i
, mmio
, port_mmio
);
1203 tmp
= readl(mmio
+ HOST_CTL
);
1204 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1205 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
1206 tmp
= readl(mmio
+ HOST_CTL
);
1207 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1210 static void ahci_dev_config(struct ata_device
*dev
)
1212 struct ahci_host_priv
*hpriv
= dev
->link
->ap
->host
->private_data
;
1214 if (hpriv
->flags
& AHCI_HFLAG_SECT255
) {
1215 dev
->max_sectors
= 255;
1216 ata_dev_printk(dev
, KERN_INFO
,
1217 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1221 static unsigned int ahci_dev_classify(struct ata_port
*ap
)
1223 void __iomem
*port_mmio
= ahci_port_base(ap
);
1224 struct ata_taskfile tf
;
1227 tmp
= readl(port_mmio
+ PORT_SIG
);
1228 tf
.lbah
= (tmp
>> 24) & 0xff;
1229 tf
.lbam
= (tmp
>> 16) & 0xff;
1230 tf
.lbal
= (tmp
>> 8) & 0xff;
1231 tf
.nsect
= (tmp
) & 0xff;
1233 return ata_dev_classify(&tf
);
1236 static void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, unsigned int tag
,
1239 dma_addr_t cmd_tbl_dma
;
1241 cmd_tbl_dma
= pp
->cmd_tbl_dma
+ tag
* AHCI_CMD_TBL_SZ
;
1243 pp
->cmd_slot
[tag
].opts
= cpu_to_le32(opts
);
1244 pp
->cmd_slot
[tag
].status
= 0;
1245 pp
->cmd_slot
[tag
].tbl_addr
= cpu_to_le32(cmd_tbl_dma
& 0xffffffff);
1246 pp
->cmd_slot
[tag
].tbl_addr_hi
= cpu_to_le32((cmd_tbl_dma
>> 16) >> 16);
1249 static int ahci_kick_engine(struct ata_port
*ap
, int force_restart
)
1251 void __iomem
*port_mmio
= ap
->ioaddr
.cmd_addr
;
1252 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1256 /* do we need to kick the port? */
1257 busy
= ahci_check_status(ap
) & (ATA_BUSY
| ATA_DRQ
);
1258 if (!busy
&& !force_restart
)
1262 rc
= ahci_stop_engine(ap
);
1266 /* need to do CLO? */
1272 if (!(hpriv
->cap
& HOST_CAP_CLO
)) {
1278 tmp
= readl(port_mmio
+ PORT_CMD
);
1279 tmp
|= PORT_CMD_CLO
;
1280 writel(tmp
, port_mmio
+ PORT_CMD
);
1283 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
1284 PORT_CMD_CLO
, PORT_CMD_CLO
, 1, 500);
1285 if (tmp
& PORT_CMD_CLO
)
1288 /* restart engine */
1290 ahci_start_engine(ap
);
1294 static int ahci_exec_polled_cmd(struct ata_port
*ap
, int pmp
,
1295 struct ata_taskfile
*tf
, int is_cmd
, u16 flags
,
1296 unsigned long timeout_msec
)
1298 const u32 cmd_fis_len
= 5; /* five dwords */
1299 struct ahci_port_priv
*pp
= ap
->private_data
;
1300 void __iomem
*port_mmio
= ahci_port_base(ap
);
1301 u8
*fis
= pp
->cmd_tbl
;
1304 /* prep the command */
1305 ata_tf_to_fis(tf
, pmp
, is_cmd
, fis
);
1306 ahci_fill_cmd_slot(pp
, 0, cmd_fis_len
| flags
| (pmp
<< 12));
1309 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
1312 tmp
= ata_wait_register(port_mmio
+ PORT_CMD_ISSUE
, 0x1, 0x1,
1315 ahci_kick_engine(ap
, 1);
1319 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
1324 static int ahci_do_softreset(struct ata_link
*link
, unsigned int *class,
1325 int pmp
, unsigned long deadline
)
1327 struct ata_port
*ap
= link
->ap
;
1328 const char *reason
= NULL
;
1329 unsigned long now
, msecs
;
1330 struct ata_taskfile tf
;
1335 if (ata_link_offline(link
)) {
1336 DPRINTK("PHY reports no device\n");
1337 *class = ATA_DEV_NONE
;
1341 /* prepare for SRST (AHCI-1.1 10.4.1) */
1342 rc
= ahci_kick_engine(ap
, 1);
1343 if (rc
&& rc
!= -EOPNOTSUPP
)
1344 ata_link_printk(link
, KERN_WARNING
,
1345 "failed to reset engine (errno=%d)\n", rc
);
1347 ata_tf_init(link
->device
, &tf
);
1349 /* issue the first D2H Register FIS */
1352 if (time_after(now
, deadline
))
1353 msecs
= jiffies_to_msecs(deadline
- now
);
1356 if (ahci_exec_polled_cmd(ap
, pmp
, &tf
, 0,
1357 AHCI_CMD_RESET
| AHCI_CMD_CLR_BUSY
, msecs
)) {
1359 reason
= "1st FIS failed";
1363 /* spec says at least 5us, but be generous and sleep for 1ms */
1366 /* issue the second D2H Register FIS */
1367 tf
.ctl
&= ~ATA_SRST
;
1368 ahci_exec_polled_cmd(ap
, pmp
, &tf
, 0, 0, 0);
1370 /* wait a while before checking status */
1371 ata_wait_after_reset(ap
, deadline
);
1373 rc
= ata_wait_ready(ap
, deadline
);
1374 /* link occupied, -ENODEV too is an error */
1376 reason
= "device not ready";
1379 *class = ahci_dev_classify(ap
);
1381 DPRINTK("EXIT, class=%u\n", *class);
1385 ata_link_printk(link
, KERN_ERR
, "softreset failed (%s)\n", reason
);
1389 static int ahci_softreset(struct ata_link
*link
, unsigned int *class,
1390 unsigned long deadline
)
1394 if (link
->ap
->flags
& ATA_FLAG_PMP
)
1395 pmp
= SATA_PMP_CTRL_PORT
;
1397 return ahci_do_softreset(link
, class, pmp
, deadline
);
1400 static int ahci_hardreset(struct ata_link
*link
, unsigned int *class,
1401 unsigned long deadline
)
1403 struct ata_port
*ap
= link
->ap
;
1404 struct ahci_port_priv
*pp
= ap
->private_data
;
1405 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
1406 struct ata_taskfile tf
;
1411 ahci_stop_engine(ap
);
1413 /* clear D2H reception area to properly wait for D2H FIS */
1414 ata_tf_init(link
->device
, &tf
);
1416 ata_tf_to_fis(&tf
, 0, 0, d2h_fis
);
1418 rc
= sata_std_hardreset(link
, class, deadline
);
1420 ahci_start_engine(ap
);
1422 if (rc
== 0 && ata_link_online(link
))
1423 *class = ahci_dev_classify(ap
);
1424 if (rc
!= -EAGAIN
&& *class == ATA_DEV_UNKNOWN
)
1425 *class = ATA_DEV_NONE
;
1427 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
1431 static int ahci_vt8251_hardreset(struct ata_link
*link
, unsigned int *class,
1432 unsigned long deadline
)
1434 struct ata_port
*ap
= link
->ap
;
1440 ahci_stop_engine(ap
);
1442 rc
= sata_link_hardreset(link
, sata_ehc_deb_timing(&link
->eh_context
),
1445 /* vt8251 needs SError cleared for the port to operate */
1446 ahci_scr_read(ap
, SCR_ERROR
, &serror
);
1447 ahci_scr_write(ap
, SCR_ERROR
, serror
);
1449 ahci_start_engine(ap
);
1451 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
1453 /* vt8251 doesn't clear BSY on signature FIS reception,
1454 * request follow-up softreset.
1456 return rc
?: -EAGAIN
;
1459 static int ahci_p5wdh_hardreset(struct ata_link
*link
, unsigned int *class,
1460 unsigned long deadline
)
1462 struct ata_port
*ap
= link
->ap
;
1463 struct ahci_port_priv
*pp
= ap
->private_data
;
1464 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
1465 struct ata_taskfile tf
;
1468 ahci_stop_engine(ap
);
1470 /* clear D2H reception area to properly wait for D2H FIS */
1471 ata_tf_init(link
->device
, &tf
);
1473 ata_tf_to_fis(&tf
, 0, 0, d2h_fis
);
1475 rc
= sata_link_hardreset(link
, sata_ehc_deb_timing(&link
->eh_context
),
1478 ahci_start_engine(ap
);
1480 if (rc
|| ata_link_offline(link
))
1483 /* spec mandates ">= 2ms" before checking status */
1486 /* The pseudo configuration device on SIMG4726 attached to
1487 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1488 * hardreset if no device is attached to the first downstream
1489 * port && the pseudo device locks up on SRST w/ PMP==0. To
1490 * work around this, wait for !BSY only briefly. If BSY isn't
1491 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1492 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1494 * Wait for two seconds. Devices attached to downstream port
1495 * which can't process the following IDENTIFY after this will
1496 * have to be reset again. For most cases, this should
1497 * suffice while making probing snappish enough.
1499 rc
= ata_wait_ready(ap
, jiffies
+ 2 * HZ
);
1501 ahci_kick_engine(ap
, 0);
1506 static void ahci_postreset(struct ata_link
*link
, unsigned int *class)
1508 struct ata_port
*ap
= link
->ap
;
1509 void __iomem
*port_mmio
= ahci_port_base(ap
);
1512 ata_std_postreset(link
, class);
1514 /* Make sure port's ATAPI bit is set appropriately */
1515 new_tmp
= tmp
= readl(port_mmio
+ PORT_CMD
);
1516 if (*class == ATA_DEV_ATAPI
)
1517 new_tmp
|= PORT_CMD_ATAPI
;
1519 new_tmp
&= ~PORT_CMD_ATAPI
;
1520 if (new_tmp
!= tmp
) {
1521 writel(new_tmp
, port_mmio
+ PORT_CMD
);
1522 readl(port_mmio
+ PORT_CMD
); /* flush */
1526 static int ahci_pmp_softreset(struct ata_link
*link
, unsigned int *class,
1527 unsigned long deadline
)
1529 return ahci_do_softreset(link
, class, link
->pmp
, deadline
);
1532 static u8
ahci_check_status(struct ata_port
*ap
)
1534 void __iomem
*mmio
= ap
->ioaddr
.cmd_addr
;
1536 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
1539 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
1541 struct ahci_port_priv
*pp
= ap
->private_data
;
1542 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
1544 ata_tf_from_fis(d2h_fis
, tf
);
1547 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_tbl
)
1549 struct scatterlist
*sg
;
1550 struct ahci_sg
*ahci_sg
= cmd_tbl
+ AHCI_CMD_TBL_HDR_SZ
;
1556 * Next, the S/G list.
1558 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
1559 dma_addr_t addr
= sg_dma_address(sg
);
1560 u32 sg_len
= sg_dma_len(sg
);
1562 ahci_sg
[si
].addr
= cpu_to_le32(addr
& 0xffffffff);
1563 ahci_sg
[si
].addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
1564 ahci_sg
[si
].flags_size
= cpu_to_le32(sg_len
- 1);
1570 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
1572 struct ata_port
*ap
= qc
->ap
;
1573 struct ahci_port_priv
*pp
= ap
->private_data
;
1574 int is_atapi
= ata_is_atapi(qc
->tf
.protocol
);
1577 const u32 cmd_fis_len
= 5; /* five dwords */
1578 unsigned int n_elem
;
1581 * Fill in command table information. First, the header,
1582 * a SATA Register - Host to Device command FIS.
1584 cmd_tbl
= pp
->cmd_tbl
+ qc
->tag
* AHCI_CMD_TBL_SZ
;
1586 ata_tf_to_fis(&qc
->tf
, qc
->dev
->link
->pmp
, 1, cmd_tbl
);
1588 memset(cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
1589 memcpy(cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, qc
->dev
->cdb_len
);
1593 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
1594 n_elem
= ahci_fill_sg(qc
, cmd_tbl
);
1597 * Fill in command slot information.
1599 opts
= cmd_fis_len
| n_elem
<< 16 | (qc
->dev
->link
->pmp
<< 12);
1600 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
1601 opts
|= AHCI_CMD_WRITE
;
1603 opts
|= AHCI_CMD_ATAPI
| AHCI_CMD_PREFETCH
;
1605 ahci_fill_cmd_slot(pp
, qc
->tag
, opts
);
1608 static void ahci_error_intr(struct ata_port
*ap
, u32 irq_stat
)
1610 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1611 struct ahci_port_priv
*pp
= ap
->private_data
;
1612 struct ata_eh_info
*host_ehi
= &ap
->link
.eh_info
;
1613 struct ata_link
*link
= NULL
;
1614 struct ata_queued_cmd
*active_qc
;
1615 struct ata_eh_info
*active_ehi
;
1618 /* determine active link */
1619 ata_port_for_each_link(link
, ap
)
1620 if (ata_link_active(link
))
1625 active_qc
= ata_qc_from_tag(ap
, link
->active_tag
);
1626 active_ehi
= &link
->eh_info
;
1628 /* record irq stat */
1629 ata_ehi_clear_desc(host_ehi
);
1630 ata_ehi_push_desc(host_ehi
, "irq_stat 0x%08x", irq_stat
);
1632 /* AHCI needs SError cleared; otherwise, it might lock up */
1633 ahci_scr_read(ap
, SCR_ERROR
, &serror
);
1634 ahci_scr_write(ap
, SCR_ERROR
, serror
);
1635 host_ehi
->serror
|= serror
;
1637 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1638 if (hpriv
->flags
& AHCI_HFLAG_IGN_IRQ_IF_ERR
)
1639 irq_stat
&= ~PORT_IRQ_IF_ERR
;
1641 if (irq_stat
& PORT_IRQ_TF_ERR
) {
1642 /* If qc is active, charge it; otherwise, the active
1643 * link. There's no active qc on NCQ errors. It will
1644 * be determined by EH by reading log page 10h.
1647 active_qc
->err_mask
|= AC_ERR_DEV
;
1649 active_ehi
->err_mask
|= AC_ERR_DEV
;
1651 if (hpriv
->flags
& AHCI_HFLAG_IGN_SERR_INTERNAL
)
1652 host_ehi
->serror
&= ~SERR_INTERNAL
;
1655 if (irq_stat
& PORT_IRQ_UNK_FIS
) {
1656 u32
*unk
= (u32
*)(pp
->rx_fis
+ RX_FIS_UNK
);
1658 active_ehi
->err_mask
|= AC_ERR_HSM
;
1659 active_ehi
->action
|= ATA_EH_RESET
;
1660 ata_ehi_push_desc(active_ehi
,
1661 "unknown FIS %08x %08x %08x %08x" ,
1662 unk
[0], unk
[1], unk
[2], unk
[3]);
1665 if (ap
->nr_pmp_links
&& (irq_stat
& PORT_IRQ_BAD_PMP
)) {
1666 active_ehi
->err_mask
|= AC_ERR_HSM
;
1667 active_ehi
->action
|= ATA_EH_RESET
;
1668 ata_ehi_push_desc(active_ehi
, "incorrect PMP");
1671 if (irq_stat
& (PORT_IRQ_HBUS_ERR
| PORT_IRQ_HBUS_DATA_ERR
)) {
1672 host_ehi
->err_mask
|= AC_ERR_HOST_BUS
;
1673 host_ehi
->action
|= ATA_EH_RESET
;
1674 ata_ehi_push_desc(host_ehi
, "host bus error");
1677 if (irq_stat
& PORT_IRQ_IF_ERR
) {
1678 host_ehi
->err_mask
|= AC_ERR_ATA_BUS
;
1679 host_ehi
->action
|= ATA_EH_RESET
;
1680 ata_ehi_push_desc(host_ehi
, "interface fatal error");
1683 if (irq_stat
& (PORT_IRQ_CONNECT
| PORT_IRQ_PHYRDY
)) {
1684 ata_ehi_hotplugged(host_ehi
);
1685 ata_ehi_push_desc(host_ehi
, "%s",
1686 irq_stat
& PORT_IRQ_CONNECT
?
1687 "connection status changed" : "PHY RDY changed");
1690 /* okay, let's hand over to EH */
1692 if (irq_stat
& PORT_IRQ_FREEZE
)
1693 ata_port_freeze(ap
);
1698 static void ahci_port_intr(struct ata_port
*ap
)
1700 void __iomem
*port_mmio
= ap
->ioaddr
.cmd_addr
;
1701 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
1702 struct ahci_port_priv
*pp
= ap
->private_data
;
1703 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1704 int resetting
= !!(ap
->pflags
& ATA_PFLAG_RESETTING
);
1705 u32 status
, qc_active
;
1708 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
1709 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
1711 /* ignore BAD_PMP while resetting */
1712 if (unlikely(resetting
))
1713 status
&= ~PORT_IRQ_BAD_PMP
;
1715 /* If we are getting PhyRdy, this is
1716 * just a power state change, we should
1717 * clear out this, plus the PhyRdy/Comm
1718 * Wake bits from Serror
1720 if ((hpriv
->flags
& AHCI_HFLAG_NO_HOTPLUG
) &&
1721 (status
& PORT_IRQ_PHYRDY
)) {
1722 status
&= ~PORT_IRQ_PHYRDY
;
1723 ahci_scr_write(ap
, SCR_ERROR
, ((1 << 16) | (1 << 18)));
1726 if (unlikely(status
& PORT_IRQ_ERROR
)) {
1727 ahci_error_intr(ap
, status
);
1731 if (status
& PORT_IRQ_SDB_FIS
) {
1732 /* If SNotification is available, leave notification
1733 * handling to sata_async_notification(). If not,
1734 * emulate it by snooping SDB FIS RX area.
1736 * Snooping FIS RX area is probably cheaper than
1737 * poking SNotification but some constrollers which
1738 * implement SNotification, ICH9 for example, don't
1739 * store AN SDB FIS into receive area.
1741 if (hpriv
->cap
& HOST_CAP_SNTF
)
1742 sata_async_notification(ap
);
1744 /* If the 'N' bit in word 0 of the FIS is set,
1745 * we just received asynchronous notification.
1746 * Tell libata about it.
1748 const __le32
*f
= pp
->rx_fis
+ RX_FIS_SDB
;
1749 u32 f0
= le32_to_cpu(f
[0]);
1752 sata_async_notification(ap
);
1756 /* pp->active_link is valid iff any command is in flight */
1757 if (ap
->qc_active
&& pp
->active_link
->sactive
)
1758 qc_active
= readl(port_mmio
+ PORT_SCR_ACT
);
1760 qc_active
= readl(port_mmio
+ PORT_CMD_ISSUE
);
1762 rc
= ata_qc_complete_multiple(ap
, qc_active
, NULL
);
1764 /* while resetting, invalid completions are expected */
1765 if (unlikely(rc
< 0 && !resetting
)) {
1766 ehi
->err_mask
|= AC_ERR_HSM
;
1767 ehi
->action
|= ATA_EH_RESET
;
1768 ata_port_freeze(ap
);
1772 static void ahci_irq_clear(struct ata_port
*ap
)
1777 static irqreturn_t
ahci_interrupt(int irq
, void *dev_instance
)
1779 struct ata_host
*host
= dev_instance
;
1780 struct ahci_host_priv
*hpriv
;
1781 unsigned int i
, handled
= 0;
1783 u32 irq_stat
, irq_ack
= 0;
1787 hpriv
= host
->private_data
;
1788 mmio
= host
->iomap
[AHCI_PCI_BAR
];
1790 /* sigh. 0xffffffff is a valid return from h/w */
1791 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
1792 irq_stat
&= hpriv
->port_map
;
1796 spin_lock(&host
->lock
);
1798 for (i
= 0; i
< host
->n_ports
; i
++) {
1799 struct ata_port
*ap
;
1801 if (!(irq_stat
& (1 << i
)))
1804 ap
= host
->ports
[i
];
1807 VPRINTK("port %u\n", i
);
1809 VPRINTK("port %u (no irq)\n", i
);
1810 if (ata_ratelimit())
1811 dev_printk(KERN_WARNING
, host
->dev
,
1812 "interrupt on disabled port %u\n", i
);
1815 irq_ack
|= (1 << i
);
1819 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
1823 spin_unlock(&host
->lock
);
1827 return IRQ_RETVAL(handled
);
1830 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
)
1832 struct ata_port
*ap
= qc
->ap
;
1833 void __iomem
*port_mmio
= ahci_port_base(ap
);
1834 struct ahci_port_priv
*pp
= ap
->private_data
;
1836 /* Keep track of the currently active link. It will be used
1837 * in completion path to determine whether NCQ phase is in
1840 pp
->active_link
= qc
->dev
->link
;
1842 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
1843 writel(1 << qc
->tag
, port_mmio
+ PORT_SCR_ACT
);
1844 writel(1 << qc
->tag
, port_mmio
+ PORT_CMD_ISSUE
);
1845 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
1850 static void ahci_freeze(struct ata_port
*ap
)
1852 void __iomem
*port_mmio
= ahci_port_base(ap
);
1855 writel(0, port_mmio
+ PORT_IRQ_MASK
);
1858 static void ahci_thaw(struct ata_port
*ap
)
1860 void __iomem
*mmio
= ap
->host
->iomap
[AHCI_PCI_BAR
];
1861 void __iomem
*port_mmio
= ahci_port_base(ap
);
1863 struct ahci_port_priv
*pp
= ap
->private_data
;
1866 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1867 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1868 writel(1 << ap
->port_no
, mmio
+ HOST_IRQ_STAT
);
1870 /* turn IRQ back on */
1871 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
1874 static void ahci_error_handler(struct ata_port
*ap
)
1876 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
1877 /* restart engine */
1878 ahci_stop_engine(ap
);
1879 ahci_start_engine(ap
);
1882 /* perform recovery */
1883 sata_pmp_do_eh(ap
, ata_std_prereset
, ahci_softreset
,
1884 ahci_hardreset
, ahci_postreset
,
1885 sata_pmp_std_prereset
, ahci_pmp_softreset
,
1886 sata_pmp_std_hardreset
, sata_pmp_std_postreset
);
1889 static void ahci_vt8251_error_handler(struct ata_port
*ap
)
1891 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
1892 /* restart engine */
1893 ahci_stop_engine(ap
);
1894 ahci_start_engine(ap
);
1897 /* perform recovery */
1898 ata_do_eh(ap
, ata_std_prereset
, ahci_softreset
, ahci_vt8251_hardreset
,
1902 static void ahci_p5wdh_error_handler(struct ata_port
*ap
)
1904 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
1905 /* restart engine */
1906 ahci_stop_engine(ap
);
1907 ahci_start_engine(ap
);
1910 /* perform recovery */
1911 ata_do_eh(ap
, ata_std_prereset
, ahci_softreset
, ahci_p5wdh_hardreset
,
1915 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
)
1917 struct ata_port
*ap
= qc
->ap
;
1919 /* make DMA engine forget about the failed command */
1920 if (qc
->flags
& ATA_QCFLAG_FAILED
)
1921 ahci_kick_engine(ap
, 1);
1924 static void ahci_pmp_attach(struct ata_port
*ap
)
1926 void __iomem
*port_mmio
= ahci_port_base(ap
);
1927 struct ahci_port_priv
*pp
= ap
->private_data
;
1930 cmd
= readl(port_mmio
+ PORT_CMD
);
1931 cmd
|= PORT_CMD_PMP
;
1932 writel(cmd
, port_mmio
+ PORT_CMD
);
1934 pp
->intr_mask
|= PORT_IRQ_BAD_PMP
;
1935 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
1938 static void ahci_pmp_detach(struct ata_port
*ap
)
1940 void __iomem
*port_mmio
= ahci_port_base(ap
);
1941 struct ahci_port_priv
*pp
= ap
->private_data
;
1944 cmd
= readl(port_mmio
+ PORT_CMD
);
1945 cmd
&= ~PORT_CMD_PMP
;
1946 writel(cmd
, port_mmio
+ PORT_CMD
);
1948 pp
->intr_mask
&= ~PORT_IRQ_BAD_PMP
;
1949 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
1952 static int ahci_port_resume(struct ata_port
*ap
)
1955 ahci_start_port(ap
);
1957 if (ap
->nr_pmp_links
)
1958 ahci_pmp_attach(ap
);
1960 ahci_pmp_detach(ap
);
1966 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
)
1968 const char *emsg
= NULL
;
1971 rc
= ahci_deinit_port(ap
, &emsg
);
1973 ahci_power_down(ap
);
1975 ata_port_printk(ap
, KERN_ERR
, "%s (%d)\n", emsg
, rc
);
1976 ahci_start_port(ap
);
1982 static int ahci_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1984 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1985 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
1988 if (mesg
.event
& PM_EVENT_SLEEP
) {
1989 /* AHCI spec rev1.1 section 8.3.3:
1990 * Software must disable interrupts prior to requesting a
1991 * transition of the HBA to D3 state.
1993 ctl
= readl(mmio
+ HOST_CTL
);
1994 ctl
&= ~HOST_IRQ_EN
;
1995 writel(ctl
, mmio
+ HOST_CTL
);
1996 readl(mmio
+ HOST_CTL
); /* flush */
1999 return ata_pci_device_suspend(pdev
, mesg
);
2002 static int ahci_pci_device_resume(struct pci_dev
*pdev
)
2004 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
2007 rc
= ata_pci_device_do_resume(pdev
);
2011 if (pdev
->dev
.power
.power_state
.event
== PM_EVENT_SUSPEND
) {
2012 rc
= ahci_reset_controller(host
);
2016 ahci_init_controller(host
);
2019 ata_host_resume(host
);
2025 static int ahci_port_start(struct ata_port
*ap
)
2027 struct device
*dev
= ap
->host
->dev
;
2028 struct ahci_port_priv
*pp
;
2032 pp
= devm_kzalloc(dev
, sizeof(*pp
), GFP_KERNEL
);
2036 mem
= dmam_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
,
2040 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
2043 * First item in chunk of DMA memory: 32-slot command table,
2044 * 32 bytes each in size
2047 pp
->cmd_slot_dma
= mem_dma
;
2049 mem
+= AHCI_CMD_SLOT_SZ
;
2050 mem_dma
+= AHCI_CMD_SLOT_SZ
;
2053 * Second item: Received-FIS area
2056 pp
->rx_fis_dma
= mem_dma
;
2058 mem
+= AHCI_RX_FIS_SZ
;
2059 mem_dma
+= AHCI_RX_FIS_SZ
;
2062 * Third item: data area for storing a single command
2063 * and its scatter-gather table
2066 pp
->cmd_tbl_dma
= mem_dma
;
2069 * Save off initial list of interrupts to be enabled.
2070 * This could be changed later
2072 pp
->intr_mask
= DEF_PORT_IRQ
;
2074 ap
->private_data
= pp
;
2076 /* engage engines, captain */
2077 return ahci_port_resume(ap
);
2080 static void ahci_port_stop(struct ata_port
*ap
)
2082 const char *emsg
= NULL
;
2085 /* de-initialize port */
2086 rc
= ahci_deinit_port(ap
, &emsg
);
2088 ata_port_printk(ap
, KERN_WARNING
, "%s (%d)\n", emsg
, rc
);
2091 static int ahci_configure_dma_masks(struct pci_dev
*pdev
, int using_dac
)
2096 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
2097 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
2099 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
2101 dev_printk(KERN_ERR
, &pdev
->dev
,
2102 "64-bit DMA enable failed\n");
2107 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
2109 dev_printk(KERN_ERR
, &pdev
->dev
,
2110 "32-bit DMA enable failed\n");
2113 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
2115 dev_printk(KERN_ERR
, &pdev
->dev
,
2116 "32-bit consistent DMA enable failed\n");
2123 static void ahci_print_info(struct ata_host
*host
)
2125 struct ahci_host_priv
*hpriv
= host
->private_data
;
2126 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
2127 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
2128 u32 vers
, cap
, impl
, speed
;
2129 const char *speed_s
;
2133 vers
= readl(mmio
+ HOST_VERSION
);
2135 impl
= hpriv
->port_map
;
2137 speed
= (cap
>> 20) & 0xf;
2140 else if (speed
== 2)
2145 pci_read_config_word(pdev
, 0x0a, &cc
);
2146 if (cc
== PCI_CLASS_STORAGE_IDE
)
2148 else if (cc
== PCI_CLASS_STORAGE_SATA
)
2150 else if (cc
== PCI_CLASS_STORAGE_RAID
)
2155 dev_printk(KERN_INFO
, &pdev
->dev
,
2156 "AHCI %02x%02x.%02x%02x "
2157 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2160 (vers
>> 24) & 0xff,
2161 (vers
>> 16) & 0xff,
2165 ((cap
>> 8) & 0x1f) + 1,
2171 dev_printk(KERN_INFO
, &pdev
->dev
,
2177 cap
& (1 << 31) ? "64bit " : "",
2178 cap
& (1 << 30) ? "ncq " : "",
2179 cap
& (1 << 29) ? "sntf " : "",
2180 cap
& (1 << 28) ? "ilck " : "",
2181 cap
& (1 << 27) ? "stag " : "",
2182 cap
& (1 << 26) ? "pm " : "",
2183 cap
& (1 << 25) ? "led " : "",
2185 cap
& (1 << 24) ? "clo " : "",
2186 cap
& (1 << 19) ? "nz " : "",
2187 cap
& (1 << 18) ? "only " : "",
2188 cap
& (1 << 17) ? "pmp " : "",
2189 cap
& (1 << 15) ? "pio " : "",
2190 cap
& (1 << 14) ? "slum " : "",
2191 cap
& (1 << 13) ? "part " : ""
2195 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2196 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2197 * support PMP and the 4726 either directly exports the device
2198 * attached to the first downstream port or acts as a hardware storage
2199 * controller and emulate a single ATA device (can be RAID 0/1 or some
2200 * other configuration).
2202 * When there's no device attached to the first downstream port of the
2203 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2204 * configure the 4726. However, ATA emulation of the device is very
2205 * lame. It doesn't send signature D2H Reg FIS after the initial
2206 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2208 * The following function works around the problem by always using
2209 * hardreset on the port and not depending on receiving signature FIS
2210 * afterward. If signature FIS isn't received soon, ATA class is
2211 * assumed without follow-up softreset.
2213 static void ahci_p5wdh_workaround(struct ata_host
*host
)
2215 static struct dmi_system_id sysids
[] = {
2217 .ident
= "P5W DH Deluxe",
2219 DMI_MATCH(DMI_SYS_VENDOR
,
2220 "ASUSTEK COMPUTER INC"),
2221 DMI_MATCH(DMI_PRODUCT_NAME
, "P5W DH Deluxe"),
2226 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
2228 if (pdev
->bus
->number
== 0 && pdev
->devfn
== PCI_DEVFN(0x1f, 2) &&
2229 dmi_check_system(sysids
)) {
2230 struct ata_port
*ap
= host
->ports
[1];
2232 dev_printk(KERN_INFO
, &pdev
->dev
, "enabling ASUS P5W DH "
2233 "Deluxe on-board SIMG4726 workaround\n");
2235 ap
->ops
= &ahci_p5wdh_ops
;
2236 ap
->link
.flags
|= ATA_LFLAG_NO_SRST
| ATA_LFLAG_ASSUME_ATA
;
2240 static int ahci_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2242 static int printed_version
;
2243 struct ata_port_info pi
= ahci_port_info
[ent
->driver_data
];
2244 const struct ata_port_info
*ppi
[] = { &pi
, NULL
};
2245 struct device
*dev
= &pdev
->dev
;
2246 struct ahci_host_priv
*hpriv
;
2247 struct ata_host
*host
;
2252 WARN_ON(ATA_MAX_QUEUE
> AHCI_MAX_CMDS
);
2254 if (!printed_version
++)
2255 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
2257 /* acquire resources */
2258 rc
= pcim_enable_device(pdev
);
2262 /* AHCI controllers often implement SFF compatible interface.
2263 * Grab all PCI BARs just in case.
2265 rc
= pcim_iomap_regions_request_all(pdev
, 1 << AHCI_PCI_BAR
, DRV_NAME
);
2267 pcim_pin_device(pdev
);
2271 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
&&
2272 (pdev
->device
== 0x2652 || pdev
->device
== 0x2653)) {
2275 /* ICH6s share the same PCI ID for both piix and ahci
2276 * modes. Enabling ahci mode while MAP indicates
2277 * combined mode is a bad idea. Yield to ata_piix.
2279 pci_read_config_byte(pdev
, ICH_MAP
, &map
);
2281 dev_printk(KERN_INFO
, &pdev
->dev
, "controller is in "
2282 "combined mode, can't enable AHCI mode\n");
2287 hpriv
= devm_kzalloc(dev
, sizeof(*hpriv
), GFP_KERNEL
);
2290 hpriv
->flags
|= (unsigned long)pi
.private_data
;
2292 if ((hpriv
->flags
& AHCI_HFLAG_NO_MSI
) || pci_enable_msi(pdev
))
2295 /* save initial config */
2296 ahci_save_initial_config(pdev
, hpriv
);
2299 if (hpriv
->cap
& HOST_CAP_NCQ
)
2300 pi
.flags
|= ATA_FLAG_NCQ
;
2302 if (hpriv
->cap
& HOST_CAP_PMP
)
2303 pi
.flags
|= ATA_FLAG_PMP
;
2305 /* CAP.NP sometimes indicate the index of the last enabled
2306 * port, at other times, that of the last possible port, so
2307 * determining the maximum port number requires looking at
2308 * both CAP.NP and port_map.
2310 n_ports
= max(ahci_nr_ports(hpriv
->cap
), fls(hpriv
->port_map
));
2312 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, n_ports
);
2315 host
->iomap
= pcim_iomap_table(pdev
);
2316 host
->private_data
= hpriv
;
2318 for (i
= 0; i
< host
->n_ports
; i
++) {
2319 struct ata_port
*ap
= host
->ports
[i
];
2320 void __iomem
*port_mmio
= ahci_port_base(ap
);
2322 ata_port_pbar_desc(ap
, AHCI_PCI_BAR
, -1, "abar");
2323 ata_port_pbar_desc(ap
, AHCI_PCI_BAR
,
2324 0x100 + ap
->port_no
* 0x80, "port");
2326 /* set initial link pm policy */
2327 ap
->pm_policy
= NOT_AVAILABLE
;
2329 /* standard SATA port setup */
2330 if (hpriv
->port_map
& (1 << i
))
2331 ap
->ioaddr
.cmd_addr
= port_mmio
;
2333 /* disabled/not-implemented port */
2335 ap
->ops
= &ata_dummy_port_ops
;
2338 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2339 ahci_p5wdh_workaround(host
);
2341 /* initialize adapter */
2342 rc
= ahci_configure_dma_masks(pdev
, hpriv
->cap
& HOST_CAP_64
);
2346 rc
= ahci_reset_controller(host
);
2350 ahci_init_controller(host
);
2351 ahci_print_info(host
);
2353 pci_set_master(pdev
);
2354 return ata_host_activate(host
, pdev
->irq
, ahci_interrupt
, IRQF_SHARED
,
2358 static int __init
ahci_init(void)
2360 return pci_register_driver(&ahci_pci_driver
);
2363 static void __exit
ahci_exit(void)
2365 pci_unregister_driver(&ahci_pci_driver
);
2369 MODULE_AUTHOR("Jeff Garzik");
2370 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2371 MODULE_LICENSE("GPL");
2372 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
2373 MODULE_VERSION(DRV_VERSION
);
2375 module_init(ahci_init
);
2376 module_exit(ahci_exit
);