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[mirror_ubuntu-eoan-kernel.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include <linux/ahci-remap.h>
50 #include <linux/io-64-nonatomic-lo-hi.h>
51 #include "ahci.h"
52
53 #define DRV_NAME "ahci"
54 #define DRV_VERSION "3.0"
55
56 enum {
57 AHCI_PCI_BAR_STA2X11 = 0,
58 AHCI_PCI_BAR_CAVIUM = 0,
59 AHCI_PCI_BAR_ENMOTUS = 2,
60 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
61 AHCI_PCI_BAR_STANDARD = 5,
62 };
63
64 enum board_ids {
65 /* board IDs by feature in alphabetical order */
66 board_ahci,
67 board_ahci_ign_iferr,
68 board_ahci_mobile,
69 board_ahci_nomsi,
70 board_ahci_noncq,
71 board_ahci_nosntf,
72 board_ahci_yes_fbs,
73
74 /* board IDs for specific chipsets in alphabetical order */
75 board_ahci_avn,
76 board_ahci_mcp65,
77 board_ahci_mcp77,
78 board_ahci_mcp89,
79 board_ahci_mv,
80 board_ahci_sb600,
81 board_ahci_sb700, /* for SB700 and SB800 */
82 board_ahci_vt8251,
83
84 /* aliases */
85 board_ahci_mcp_linux = board_ahci_mcp65,
86 board_ahci_mcp67 = board_ahci_mcp65,
87 board_ahci_mcp73 = board_ahci_mcp65,
88 board_ahci_mcp79 = board_ahci_mcp77,
89 };
90
91 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
92 static void ahci_remove_one(struct pci_dev *dev);
93 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
95 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
96 unsigned long deadline);
97 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
98 static bool is_mcp89_apple(struct pci_dev *pdev);
99 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
100 unsigned long deadline);
101 #ifdef CONFIG_PM
102 static int ahci_pci_device_runtime_suspend(struct device *dev);
103 static int ahci_pci_device_runtime_resume(struct device *dev);
104 #ifdef CONFIG_PM_SLEEP
105 static int ahci_pci_device_suspend(struct device *dev);
106 static int ahci_pci_device_resume(struct device *dev);
107 #endif
108 #endif /* CONFIG_PM */
109
110 static struct scsi_host_template ahci_sht = {
111 AHCI_SHT("ahci"),
112 };
113
114 static struct ata_port_operations ahci_vt8251_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_vt8251_hardreset,
117 };
118
119 static struct ata_port_operations ahci_p5wdh_ops = {
120 .inherits = &ahci_ops,
121 .hardreset = ahci_p5wdh_hardreset,
122 };
123
124 static struct ata_port_operations ahci_avn_ops = {
125 .inherits = &ahci_ops,
126 .hardreset = ahci_avn_hardreset,
127 };
128
129 static const struct ata_port_info ahci_port_info[] = {
130 /* by features */
131 [board_ahci] = {
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
136 },
137 [board_ahci_ign_iferr] = {
138 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
144 [board_ahci_mobile] = {
145 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
151 [board_ahci_nomsi] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_noncq] = {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_nosntf] = {
166 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
172 [board_ahci_yes_fbs] = {
173 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
174 .flags = AHCI_FLAG_COMMON,
175 .pio_mask = ATA_PIO4,
176 .udma_mask = ATA_UDMA6,
177 .port_ops = &ahci_ops,
178 },
179 /* by chipsets */
180 [board_ahci_avn] = {
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_avn_ops,
185 },
186 [board_ahci_mcp65] = {
187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 AHCI_HFLAG_YES_NCQ),
189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_ops,
193 },
194 [board_ahci_mcp77] = {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
201 [board_ahci_mcp89] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
208 [board_ahci_mv] = {
209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
216 [board_ahci_sb600] = {
217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
219 AHCI_HFLAG_32BIT_ONLY),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
224 },
225 [board_ahci_sb700] = { /* for SB700 and SB800 */
226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_pmp_retry_srst_ops,
231 },
232 [board_ahci_vt8251] = {
233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
237 .port_ops = &ahci_vt8251_ops,
238 },
239 };
240
241 static const struct pci_device_id ahci_pci_tbl[] = {
242 /* Intel */
243 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
244 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
245 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
246 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
247 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
248 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
249 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
250 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
251 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
252 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
253 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
254 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
255 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
256 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
257 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
258 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
259 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
260 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
261 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
262 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
263 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
264 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
265 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
266 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
267 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
268 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
269 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
270 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
271 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
272 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
273 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
274 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
275 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
276 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
277 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
278 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
279 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
280 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
281 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
282 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
283 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
304 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
305 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
306 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
307 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
308 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
309 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
310 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
311 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
312 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
313 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
314 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
315 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
316 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
317 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
318 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
319 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
320 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
321 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
322 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
323 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
324 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
325 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
326 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
327 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
328 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
329 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
330 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
331 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
332 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
333 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
334 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
335 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
336 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
337 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
338 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
339 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
344 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
345 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
347 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
352 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
353 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
354 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
355 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
356 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
357 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
358 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
359 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
360 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
361 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
362 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
363 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
364 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
365 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
366 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
367 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
368 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
369 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
370 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
371 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
372 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
373 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
374 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
375 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
376 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
377 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
378 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
379 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
380 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
381 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
382 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
383 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
384 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
385 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
386 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
387 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
388 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
389 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
390 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
391 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
392 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
393 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
394 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
395 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
396 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
397 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
398 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
399 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
400 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
401 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
402
403 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
404 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
405 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
406 /* JMicron 362B and 362C have an AHCI function with IDE class code */
407 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
408 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
409 /* May need to update quirk_jmicron_async_suspend() for additions */
410
411 /* ATI */
412 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
413 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
414 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
415 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
416 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
417 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
418 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
419
420 /* AMD */
421 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
422 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
423 /* AMD is using RAID class only for ahci controllers */
424 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
425 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
426
427 /* VIA */
428 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
429 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
430
431 /* NVIDIA */
432 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
433 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
434 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
435 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
436 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
437 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
438 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
439 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
440 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
445 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
446 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
447 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
448 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
449 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
450 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
451 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
452 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
456 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
457 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
458 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
459 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
460 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
461 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
462 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
463 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
464 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
465 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
466 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
467 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
468 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
476 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
477 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
478 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
479 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
487 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
488 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
489 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
490 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
491 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
492 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
497 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
498 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
499 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
500 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
501 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
502 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
503 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
504 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
505 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
506 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
507 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
508 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
509 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
510 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
511 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
512 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
513 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
514 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
515 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
516
517 /* SiS */
518 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
519 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
520 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
521
522 /* ST Microelectronics */
523 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
524
525 /* Marvell */
526 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
527 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
528 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
529 .class = PCI_CLASS_STORAGE_SATA_AHCI,
530 .class_mask = 0xffffff,
531 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
532 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
533 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
534 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
535 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
536 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
538 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
539 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
540 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
541 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
542 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
543 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
544 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
545 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
546 .driver_data = board_ahci_yes_fbs },
547 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
548 .driver_data = board_ahci_yes_fbs },
549 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
550 .driver_data = board_ahci_yes_fbs },
551 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
552 .driver_data = board_ahci_yes_fbs },
553 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
554 .driver_data = board_ahci_yes_fbs },
555 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
556 .driver_data = board_ahci_yes_fbs },
557
558 /* Promise */
559 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
560 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
561
562 /* Asmedia */
563 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
564 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
565 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
566 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
567 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
568 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
569
570 /*
571 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
572 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
573 */
574 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
575 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
576
577 /* Enmotus */
578 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
579
580 /* Generic, PCI class code for AHCI */
581 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
582 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
583
584 { } /* terminate list */
585 };
586
587 static const struct dev_pm_ops ahci_pci_pm_ops = {
588 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
589 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
590 ahci_pci_device_runtime_resume, NULL)
591 };
592
593 static struct pci_driver ahci_pci_driver = {
594 .name = DRV_NAME,
595 .id_table = ahci_pci_tbl,
596 .probe = ahci_init_one,
597 .remove = ahci_remove_one,
598 .driver = {
599 .pm = &ahci_pci_pm_ops,
600 },
601 };
602
603 #if IS_ENABLED(CONFIG_PATA_MARVELL)
604 static int marvell_enable;
605 #else
606 static int marvell_enable = 1;
607 #endif
608 module_param(marvell_enable, int, 0644);
609 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
610
611 static int mobile_lpm_policy = CONFIG_SATA_MOBILE_LPM_POLICY;
612 module_param(mobile_lpm_policy, int, 0644);
613 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
614
615 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
616 struct ahci_host_priv *hpriv)
617 {
618 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
619 dev_info(&pdev->dev, "JMB361 has only one port\n");
620 hpriv->force_port_map = 1;
621 }
622
623 /*
624 * Temporary Marvell 6145 hack: PATA port presence
625 * is asserted through the standard AHCI port
626 * presence register, as bit 4 (counting from 0)
627 */
628 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
629 if (pdev->device == 0x6121)
630 hpriv->mask_port_map = 0x3;
631 else
632 hpriv->mask_port_map = 0xf;
633 dev_info(&pdev->dev,
634 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
635 }
636
637 ahci_save_initial_config(&pdev->dev, hpriv);
638 }
639
640 static int ahci_pci_reset_controller(struct ata_host *host)
641 {
642 struct pci_dev *pdev = to_pci_dev(host->dev);
643 int rc;
644
645 rc = ahci_reset_controller(host);
646 if (rc)
647 return rc;
648
649 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
650 struct ahci_host_priv *hpriv = host->private_data;
651 u16 tmp16;
652
653 /* configure PCS */
654 pci_read_config_word(pdev, 0x92, &tmp16);
655 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
656 tmp16 |= hpriv->port_map;
657 pci_write_config_word(pdev, 0x92, tmp16);
658 }
659 }
660
661 return 0;
662 }
663
664 static void ahci_pci_init_controller(struct ata_host *host)
665 {
666 struct ahci_host_priv *hpriv = host->private_data;
667 struct pci_dev *pdev = to_pci_dev(host->dev);
668 void __iomem *port_mmio;
669 u32 tmp;
670 int mv;
671
672 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
673 if (pdev->device == 0x6121)
674 mv = 2;
675 else
676 mv = 4;
677 port_mmio = __ahci_port_base(host, mv);
678
679 writel(0, port_mmio + PORT_IRQ_MASK);
680
681 /* clear port IRQ */
682 tmp = readl(port_mmio + PORT_IRQ_STAT);
683 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
684 if (tmp)
685 writel(tmp, port_mmio + PORT_IRQ_STAT);
686 }
687
688 ahci_init_controller(host);
689 }
690
691 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
692 unsigned long deadline)
693 {
694 struct ata_port *ap = link->ap;
695 struct ahci_host_priv *hpriv = ap->host->private_data;
696 bool online;
697 int rc;
698
699 DPRINTK("ENTER\n");
700
701 ahci_stop_engine(ap);
702
703 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
704 deadline, &online, NULL);
705
706 hpriv->start_engine(ap);
707
708 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
709
710 /* vt8251 doesn't clear BSY on signature FIS reception,
711 * request follow-up softreset.
712 */
713 return online ? -EAGAIN : rc;
714 }
715
716 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
717 unsigned long deadline)
718 {
719 struct ata_port *ap = link->ap;
720 struct ahci_port_priv *pp = ap->private_data;
721 struct ahci_host_priv *hpriv = ap->host->private_data;
722 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
723 struct ata_taskfile tf;
724 bool online;
725 int rc;
726
727 ahci_stop_engine(ap);
728
729 /* clear D2H reception area to properly wait for D2H FIS */
730 ata_tf_init(link->device, &tf);
731 tf.command = ATA_BUSY;
732 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
733
734 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
735 deadline, &online, NULL);
736
737 hpriv->start_engine(ap);
738
739 /* The pseudo configuration device on SIMG4726 attached to
740 * ASUS P5W-DH Deluxe doesn't send signature FIS after
741 * hardreset if no device is attached to the first downstream
742 * port && the pseudo device locks up on SRST w/ PMP==0. To
743 * work around this, wait for !BSY only briefly. If BSY isn't
744 * cleared, perform CLO and proceed to IDENTIFY (achieved by
745 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
746 *
747 * Wait for two seconds. Devices attached to downstream port
748 * which can't process the following IDENTIFY after this will
749 * have to be reset again. For most cases, this should
750 * suffice while making probing snappish enough.
751 */
752 if (online) {
753 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
754 ahci_check_ready);
755 if (rc)
756 ahci_kick_engine(ap);
757 }
758 return rc;
759 }
760
761 /*
762 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
763 *
764 * It has been observed with some SSDs that the timing of events in the
765 * link synchronization phase can leave the port in a state that can not
766 * be recovered by a SATA-hard-reset alone. The failing signature is
767 * SStatus.DET stuck at 1 ("Device presence detected but Phy
768 * communication not established"). It was found that unloading and
769 * reloading the driver when this problem occurs allows the drive
770 * connection to be recovered (DET advanced to 0x3). The critical
771 * component of reloading the driver is that the port state machines are
772 * reset by bouncing "port enable" in the AHCI PCS configuration
773 * register. So, reproduce that effect by bouncing a port whenever we
774 * see DET==1 after a reset.
775 */
776 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
777 unsigned long deadline)
778 {
779 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
780 struct ata_port *ap = link->ap;
781 struct ahci_port_priv *pp = ap->private_data;
782 struct ahci_host_priv *hpriv = ap->host->private_data;
783 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
784 unsigned long tmo = deadline - jiffies;
785 struct ata_taskfile tf;
786 bool online;
787 int rc, i;
788
789 DPRINTK("ENTER\n");
790
791 ahci_stop_engine(ap);
792
793 for (i = 0; i < 2; i++) {
794 u16 val;
795 u32 sstatus;
796 int port = ap->port_no;
797 struct ata_host *host = ap->host;
798 struct pci_dev *pdev = to_pci_dev(host->dev);
799
800 /* clear D2H reception area to properly wait for D2H FIS */
801 ata_tf_init(link->device, &tf);
802 tf.command = ATA_BUSY;
803 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
804
805 rc = sata_link_hardreset(link, timing, deadline, &online,
806 ahci_check_ready);
807
808 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
809 (sstatus & 0xf) != 1)
810 break;
811
812 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
813 port);
814
815 pci_read_config_word(pdev, 0x92, &val);
816 val &= ~(1 << port);
817 pci_write_config_word(pdev, 0x92, val);
818 ata_msleep(ap, 1000);
819 val |= 1 << port;
820 pci_write_config_word(pdev, 0x92, val);
821 deadline += tmo;
822 }
823
824 hpriv->start_engine(ap);
825
826 if (online)
827 *class = ahci_dev_classify(ap);
828
829 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
830 return rc;
831 }
832
833
834 #ifdef CONFIG_PM
835 static void ahci_pci_disable_interrupts(struct ata_host *host)
836 {
837 struct ahci_host_priv *hpriv = host->private_data;
838 void __iomem *mmio = hpriv->mmio;
839 u32 ctl;
840
841 /* AHCI spec rev1.1 section 8.3.3:
842 * Software must disable interrupts prior to requesting a
843 * transition of the HBA to D3 state.
844 */
845 ctl = readl(mmio + HOST_CTL);
846 ctl &= ~HOST_IRQ_EN;
847 writel(ctl, mmio + HOST_CTL);
848 readl(mmio + HOST_CTL); /* flush */
849 }
850
851 static int ahci_pci_device_runtime_suspend(struct device *dev)
852 {
853 struct pci_dev *pdev = to_pci_dev(dev);
854 struct ata_host *host = pci_get_drvdata(pdev);
855
856 ahci_pci_disable_interrupts(host);
857 return 0;
858 }
859
860 static int ahci_pci_device_runtime_resume(struct device *dev)
861 {
862 struct pci_dev *pdev = to_pci_dev(dev);
863 struct ata_host *host = pci_get_drvdata(pdev);
864 int rc;
865
866 rc = ahci_pci_reset_controller(host);
867 if (rc)
868 return rc;
869 ahci_pci_init_controller(host);
870 return 0;
871 }
872
873 #ifdef CONFIG_PM_SLEEP
874 static int ahci_pci_device_suspend(struct device *dev)
875 {
876 struct pci_dev *pdev = to_pci_dev(dev);
877 struct ata_host *host = pci_get_drvdata(pdev);
878 struct ahci_host_priv *hpriv = host->private_data;
879
880 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
881 dev_err(&pdev->dev,
882 "BIOS update required for suspend/resume\n");
883 return -EIO;
884 }
885
886 ahci_pci_disable_interrupts(host);
887 return ata_host_suspend(host, PMSG_SUSPEND);
888 }
889
890 static int ahci_pci_device_resume(struct device *dev)
891 {
892 struct pci_dev *pdev = to_pci_dev(dev);
893 struct ata_host *host = pci_get_drvdata(pdev);
894 int rc;
895
896 /* Apple BIOS helpfully mangles the registers on resume */
897 if (is_mcp89_apple(pdev))
898 ahci_mcp89_apple_enable(pdev);
899
900 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
901 rc = ahci_pci_reset_controller(host);
902 if (rc)
903 return rc;
904
905 ahci_pci_init_controller(host);
906 }
907
908 ata_host_resume(host);
909
910 return 0;
911 }
912 #endif
913
914 #endif /* CONFIG_PM */
915
916 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
917 {
918 int rc;
919
920 /*
921 * If the device fixup already set the dma_mask to some non-standard
922 * value, don't extend it here. This happens on STA2X11, for example.
923 */
924 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
925 return 0;
926
927 if (using_dac &&
928 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
929 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
930 if (rc) {
931 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
932 if (rc) {
933 dev_err(&pdev->dev,
934 "64-bit DMA enable failed\n");
935 return rc;
936 }
937 }
938 } else {
939 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
940 if (rc) {
941 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
942 return rc;
943 }
944 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
945 if (rc) {
946 dev_err(&pdev->dev,
947 "32-bit consistent DMA enable failed\n");
948 return rc;
949 }
950 }
951 return 0;
952 }
953
954 static void ahci_pci_print_info(struct ata_host *host)
955 {
956 struct pci_dev *pdev = to_pci_dev(host->dev);
957 u16 cc;
958 const char *scc_s;
959
960 pci_read_config_word(pdev, 0x0a, &cc);
961 if (cc == PCI_CLASS_STORAGE_IDE)
962 scc_s = "IDE";
963 else if (cc == PCI_CLASS_STORAGE_SATA)
964 scc_s = "SATA";
965 else if (cc == PCI_CLASS_STORAGE_RAID)
966 scc_s = "RAID";
967 else
968 scc_s = "unknown";
969
970 ahci_print_info(host, scc_s);
971 }
972
973 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
974 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
975 * support PMP and the 4726 either directly exports the device
976 * attached to the first downstream port or acts as a hardware storage
977 * controller and emulate a single ATA device (can be RAID 0/1 or some
978 * other configuration).
979 *
980 * When there's no device attached to the first downstream port of the
981 * 4726, "Config Disk" appears, which is a pseudo ATA device to
982 * configure the 4726. However, ATA emulation of the device is very
983 * lame. It doesn't send signature D2H Reg FIS after the initial
984 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
985 *
986 * The following function works around the problem by always using
987 * hardreset on the port and not depending on receiving signature FIS
988 * afterward. If signature FIS isn't received soon, ATA class is
989 * assumed without follow-up softreset.
990 */
991 static void ahci_p5wdh_workaround(struct ata_host *host)
992 {
993 static const struct dmi_system_id sysids[] = {
994 {
995 .ident = "P5W DH Deluxe",
996 .matches = {
997 DMI_MATCH(DMI_SYS_VENDOR,
998 "ASUSTEK COMPUTER INC"),
999 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1000 },
1001 },
1002 { }
1003 };
1004 struct pci_dev *pdev = to_pci_dev(host->dev);
1005
1006 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1007 dmi_check_system(sysids)) {
1008 struct ata_port *ap = host->ports[1];
1009
1010 dev_info(&pdev->dev,
1011 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1012
1013 ap->ops = &ahci_p5wdh_ops;
1014 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1015 }
1016 }
1017
1018 /*
1019 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1020 * booting in BIOS compatibility mode. We restore the registers but not ID.
1021 */
1022 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1023 {
1024 u32 val;
1025
1026 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1027
1028 pci_read_config_dword(pdev, 0xf8, &val);
1029 val |= 1 << 0x1b;
1030 /* the following changes the device ID, but appears not to affect function */
1031 /* val = (val & ~0xf0000000) | 0x80000000; */
1032 pci_write_config_dword(pdev, 0xf8, val);
1033
1034 pci_read_config_dword(pdev, 0x54c, &val);
1035 val |= 1 << 0xc;
1036 pci_write_config_dword(pdev, 0x54c, val);
1037
1038 pci_read_config_dword(pdev, 0x4a4, &val);
1039 val &= 0xff;
1040 val |= 0x01060100;
1041 pci_write_config_dword(pdev, 0x4a4, val);
1042
1043 pci_read_config_dword(pdev, 0x54c, &val);
1044 val &= ~(1 << 0xc);
1045 pci_write_config_dword(pdev, 0x54c, val);
1046
1047 pci_read_config_dword(pdev, 0xf8, &val);
1048 val &= ~(1 << 0x1b);
1049 pci_write_config_dword(pdev, 0xf8, val);
1050 }
1051
1052 static bool is_mcp89_apple(struct pci_dev *pdev)
1053 {
1054 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1055 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1056 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1057 pdev->subsystem_device == 0xcb89;
1058 }
1059
1060 /* only some SB600 ahci controllers can do 64bit DMA */
1061 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1062 {
1063 static const struct dmi_system_id sysids[] = {
1064 /*
1065 * The oldest version known to be broken is 0901 and
1066 * working is 1501 which was released on 2007-10-26.
1067 * Enable 64bit DMA on 1501 and anything newer.
1068 *
1069 * Please read bko#9412 for more info.
1070 */
1071 {
1072 .ident = "ASUS M2A-VM",
1073 .matches = {
1074 DMI_MATCH(DMI_BOARD_VENDOR,
1075 "ASUSTeK Computer INC."),
1076 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1077 },
1078 .driver_data = "20071026", /* yyyymmdd */
1079 },
1080 /*
1081 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1082 * support 64bit DMA.
1083 *
1084 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1085 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1086 * This spelling mistake was fixed in BIOS version 1.5, so
1087 * 1.5 and later have the Manufacturer as
1088 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1089 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1090 *
1091 * BIOS versions earlier than 1.9 had a Board Product Name
1092 * DMI field of "MS-7376". This was changed to be
1093 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1094 * match on DMI_BOARD_NAME of "MS-7376".
1095 */
1096 {
1097 .ident = "MSI K9A2 Platinum",
1098 .matches = {
1099 DMI_MATCH(DMI_BOARD_VENDOR,
1100 "MICRO-STAR INTER"),
1101 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1102 },
1103 },
1104 /*
1105 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1106 * 64bit DMA.
1107 *
1108 * This board also had the typo mentioned above in the
1109 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1110 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1111 */
1112 {
1113 .ident = "MSI K9AGM2",
1114 .matches = {
1115 DMI_MATCH(DMI_BOARD_VENDOR,
1116 "MICRO-STAR INTER"),
1117 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1118 },
1119 },
1120 /*
1121 * All BIOS versions for the Asus M3A support 64bit DMA.
1122 * (all release versions from 0301 to 1206 were tested)
1123 */
1124 {
1125 .ident = "ASUS M3A",
1126 .matches = {
1127 DMI_MATCH(DMI_BOARD_VENDOR,
1128 "ASUSTeK Computer INC."),
1129 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1130 },
1131 },
1132 { }
1133 };
1134 const struct dmi_system_id *match;
1135 int year, month, date;
1136 char buf[9];
1137
1138 match = dmi_first_match(sysids);
1139 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1140 !match)
1141 return false;
1142
1143 if (!match->driver_data)
1144 goto enable_64bit;
1145
1146 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1147 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1148
1149 if (strcmp(buf, match->driver_data) >= 0)
1150 goto enable_64bit;
1151 else {
1152 dev_warn(&pdev->dev,
1153 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1154 match->ident);
1155 return false;
1156 }
1157
1158 enable_64bit:
1159 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1160 return true;
1161 }
1162
1163 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1164 {
1165 static const struct dmi_system_id broken_systems[] = {
1166 {
1167 .ident = "HP Compaq nx6310",
1168 .matches = {
1169 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1170 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1171 },
1172 /* PCI slot number of the controller */
1173 .driver_data = (void *)0x1FUL,
1174 },
1175 {
1176 .ident = "HP Compaq 6720s",
1177 .matches = {
1178 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1179 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1180 },
1181 /* PCI slot number of the controller */
1182 .driver_data = (void *)0x1FUL,
1183 },
1184
1185 { } /* terminate list */
1186 };
1187 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1188
1189 if (dmi) {
1190 unsigned long slot = (unsigned long)dmi->driver_data;
1191 /* apply the quirk only to on-board controllers */
1192 return slot == PCI_SLOT(pdev->devfn);
1193 }
1194
1195 return false;
1196 }
1197
1198 static bool ahci_broken_suspend(struct pci_dev *pdev)
1199 {
1200 static const struct dmi_system_id sysids[] = {
1201 /*
1202 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1203 * to the harddisk doesn't become online after
1204 * resuming from STR. Warn and fail suspend.
1205 *
1206 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1207 *
1208 * Use dates instead of versions to match as HP is
1209 * apparently recycling both product and version
1210 * strings.
1211 *
1212 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1213 */
1214 {
1215 .ident = "dv4",
1216 .matches = {
1217 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1218 DMI_MATCH(DMI_PRODUCT_NAME,
1219 "HP Pavilion dv4 Notebook PC"),
1220 },
1221 .driver_data = "20090105", /* F.30 */
1222 },
1223 {
1224 .ident = "dv5",
1225 .matches = {
1226 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1227 DMI_MATCH(DMI_PRODUCT_NAME,
1228 "HP Pavilion dv5 Notebook PC"),
1229 },
1230 .driver_data = "20090506", /* F.16 */
1231 },
1232 {
1233 .ident = "dv6",
1234 .matches = {
1235 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1236 DMI_MATCH(DMI_PRODUCT_NAME,
1237 "HP Pavilion dv6 Notebook PC"),
1238 },
1239 .driver_data = "20090423", /* F.21 */
1240 },
1241 {
1242 .ident = "HDX18",
1243 .matches = {
1244 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1245 DMI_MATCH(DMI_PRODUCT_NAME,
1246 "HP HDX18 Notebook PC"),
1247 },
1248 .driver_data = "20090430", /* F.23 */
1249 },
1250 /*
1251 * Acer eMachines G725 has the same problem. BIOS
1252 * V1.03 is known to be broken. V3.04 is known to
1253 * work. Between, there are V1.06, V2.06 and V3.03
1254 * that we don't have much idea about. For now,
1255 * blacklist anything older than V3.04.
1256 *
1257 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1258 */
1259 {
1260 .ident = "G725",
1261 .matches = {
1262 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1263 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1264 },
1265 .driver_data = "20091216", /* V3.04 */
1266 },
1267 { } /* terminate list */
1268 };
1269 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1270 int year, month, date;
1271 char buf[9];
1272
1273 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1274 return false;
1275
1276 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1277 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1278
1279 return strcmp(buf, dmi->driver_data) < 0;
1280 }
1281
1282 static bool ahci_broken_online(struct pci_dev *pdev)
1283 {
1284 #define ENCODE_BUSDEVFN(bus, slot, func) \
1285 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1286 static const struct dmi_system_id sysids[] = {
1287 /*
1288 * There are several gigabyte boards which use
1289 * SIMG5723s configured as hardware RAID. Certain
1290 * 5723 firmware revisions shipped there keep the link
1291 * online but fail to answer properly to SRST or
1292 * IDENTIFY when no device is attached downstream
1293 * causing libata to retry quite a few times leading
1294 * to excessive detection delay.
1295 *
1296 * As these firmwares respond to the second reset try
1297 * with invalid device signature, considering unknown
1298 * sig as offline works around the problem acceptably.
1299 */
1300 {
1301 .ident = "EP45-DQ6",
1302 .matches = {
1303 DMI_MATCH(DMI_BOARD_VENDOR,
1304 "Gigabyte Technology Co., Ltd."),
1305 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1306 },
1307 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1308 },
1309 {
1310 .ident = "EP45-DS5",
1311 .matches = {
1312 DMI_MATCH(DMI_BOARD_VENDOR,
1313 "Gigabyte Technology Co., Ltd."),
1314 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1315 },
1316 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1317 },
1318 { } /* terminate list */
1319 };
1320 #undef ENCODE_BUSDEVFN
1321 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1322 unsigned int val;
1323
1324 if (!dmi)
1325 return false;
1326
1327 val = (unsigned long)dmi->driver_data;
1328
1329 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1330 }
1331
1332 static bool ahci_broken_devslp(struct pci_dev *pdev)
1333 {
1334 /* device with broken DEVSLP but still showing SDS capability */
1335 static const struct pci_device_id ids[] = {
1336 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1337 {}
1338 };
1339
1340 return pci_match_id(ids, pdev);
1341 }
1342
1343 #ifdef CONFIG_ATA_ACPI
1344 static void ahci_gtf_filter_workaround(struct ata_host *host)
1345 {
1346 static const struct dmi_system_id sysids[] = {
1347 /*
1348 * Aspire 3810T issues a bunch of SATA enable commands
1349 * via _GTF including an invalid one and one which is
1350 * rejected by the device. Among the successful ones
1351 * is FPDMA non-zero offset enable which when enabled
1352 * only on the drive side leads to NCQ command
1353 * failures. Filter it out.
1354 */
1355 {
1356 .ident = "Aspire 3810T",
1357 .matches = {
1358 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1359 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1360 },
1361 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1362 },
1363 { }
1364 };
1365 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1366 unsigned int filter;
1367 int i;
1368
1369 if (!dmi)
1370 return;
1371
1372 filter = (unsigned long)dmi->driver_data;
1373 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1374 filter, dmi->ident);
1375
1376 for (i = 0; i < host->n_ports; i++) {
1377 struct ata_port *ap = host->ports[i];
1378 struct ata_link *link;
1379 struct ata_device *dev;
1380
1381 ata_for_each_link(link, ap, EDGE)
1382 ata_for_each_dev(dev, link, ALL)
1383 dev->gtf_filter |= filter;
1384 }
1385 }
1386 #else
1387 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1388 {}
1389 #endif
1390
1391 /*
1392 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1393 * as DUMMY, or detected but eventually get a "link down" and never get up
1394 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1395 * port_map may hold a value of 0x00.
1396 *
1397 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1398 * and can significantly reduce the occurrence of the problem.
1399 *
1400 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1401 */
1402 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1403 struct pci_dev *pdev)
1404 {
1405 static const struct dmi_system_id sysids[] = {
1406 {
1407 .ident = "Acer Switch Alpha 12",
1408 .matches = {
1409 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1410 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1411 },
1412 },
1413 { }
1414 };
1415
1416 if (dmi_check_system(sysids)) {
1417 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1418 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1419 hpriv->port_map = 0x7;
1420 hpriv->cap = 0xC734FF02;
1421 }
1422 }
1423 }
1424
1425 #ifdef CONFIG_ARM64
1426 /*
1427 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1428 * Workaround is to make sure all pending IRQs are served before leaving
1429 * handler.
1430 */
1431 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1432 {
1433 struct ata_host *host = dev_instance;
1434 struct ahci_host_priv *hpriv;
1435 unsigned int rc = 0;
1436 void __iomem *mmio;
1437 u32 irq_stat, irq_masked;
1438 unsigned int handled = 1;
1439
1440 VPRINTK("ENTER\n");
1441 hpriv = host->private_data;
1442 mmio = hpriv->mmio;
1443 irq_stat = readl(mmio + HOST_IRQ_STAT);
1444 if (!irq_stat)
1445 return IRQ_NONE;
1446
1447 do {
1448 irq_masked = irq_stat & hpriv->port_map;
1449 spin_lock(&host->lock);
1450 rc = ahci_handle_port_intr(host, irq_masked);
1451 if (!rc)
1452 handled = 0;
1453 writel(irq_stat, mmio + HOST_IRQ_STAT);
1454 irq_stat = readl(mmio + HOST_IRQ_STAT);
1455 spin_unlock(&host->lock);
1456 } while (irq_stat);
1457 VPRINTK("EXIT\n");
1458
1459 return IRQ_RETVAL(handled);
1460 }
1461 #endif
1462
1463 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1464 struct ahci_host_priv *hpriv)
1465 {
1466 int i, count = 0;
1467 u32 cap;
1468
1469 /*
1470 * Check if this device might have remapped nvme devices.
1471 */
1472 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1473 pci_resource_len(pdev, bar) < SZ_512K ||
1474 bar != AHCI_PCI_BAR_STANDARD ||
1475 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1476 return;
1477
1478 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1479 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1480 if ((cap & (1 << i)) == 0)
1481 continue;
1482 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1483 != PCI_CLASS_STORAGE_EXPRESS)
1484 continue;
1485
1486 /* We've found a remapped device */
1487 count++;
1488 }
1489
1490 if (!count)
1491 return;
1492
1493 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1494 dev_warn(&pdev->dev,
1495 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1496
1497 /*
1498 * Don't rely on the msi-x capability in the remap case,
1499 * share the legacy interrupt across ahci and remapped devices.
1500 */
1501 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1502 }
1503
1504 static int ahci_get_irq_vector(struct ata_host *host, int port)
1505 {
1506 return pci_irq_vector(to_pci_dev(host->dev), port);
1507 }
1508
1509 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1510 struct ahci_host_priv *hpriv)
1511 {
1512 int nvec;
1513
1514 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1515 return -ENODEV;
1516
1517 /*
1518 * If number of MSIs is less than number of ports then Sharing Last
1519 * Message mode could be enforced. In this case assume that advantage
1520 * of multipe MSIs is negated and use single MSI mode instead.
1521 */
1522 if (n_ports > 1) {
1523 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1524 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1525 if (nvec > 0) {
1526 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1527 hpriv->get_irq_vector = ahci_get_irq_vector;
1528 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1529 return nvec;
1530 }
1531
1532 /*
1533 * Fallback to single MSI mode if the controller
1534 * enforced MRSM mode.
1535 */
1536 printk(KERN_INFO
1537 "ahci: MRSM is on, fallback to single MSI\n");
1538 pci_free_irq_vectors(pdev);
1539 }
1540 }
1541
1542 /*
1543 * If the host is not capable of supporting per-port vectors, fall
1544 * back to single MSI before finally attempting single MSI-X.
1545 */
1546 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1547 if (nvec == 1)
1548 return nvec;
1549 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1550 }
1551
1552 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1553 {
1554 unsigned int board_id = ent->driver_data;
1555 struct ata_port_info pi = ahci_port_info[board_id];
1556 const struct ata_port_info *ppi[] = { &pi, NULL };
1557 struct device *dev = &pdev->dev;
1558 struct ahci_host_priv *hpriv;
1559 struct ata_host *host;
1560 int n_ports, i, rc;
1561 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1562
1563 VPRINTK("ENTER\n");
1564
1565 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1566
1567 ata_print_version_once(&pdev->dev, DRV_VERSION);
1568
1569 /* The AHCI driver can only drive the SATA ports, the PATA driver
1570 can drive them all so if both drivers are selected make sure
1571 AHCI stays out of the way */
1572 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1573 return -ENODEV;
1574
1575 /* Apple BIOS on MCP89 prevents us using AHCI */
1576 if (is_mcp89_apple(pdev))
1577 ahci_mcp89_apple_enable(pdev);
1578
1579 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1580 * At the moment, we can only use the AHCI mode. Let the users know
1581 * that for SAS drives they're out of luck.
1582 */
1583 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1584 dev_info(&pdev->dev,
1585 "PDC42819 can only drive SATA devices with this driver\n");
1586
1587 /* Some devices use non-standard BARs */
1588 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1589 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1590 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1591 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1592 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1593 if (pdev->device == 0xa01c)
1594 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1595 if (pdev->device == 0xa084)
1596 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1597 }
1598
1599 /* acquire resources */
1600 rc = pcim_enable_device(pdev);
1601 if (rc)
1602 return rc;
1603
1604 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1605 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1606 u8 map;
1607
1608 /* ICH6s share the same PCI ID for both piix and ahci
1609 * modes. Enabling ahci mode while MAP indicates
1610 * combined mode is a bad idea. Yield to ata_piix.
1611 */
1612 pci_read_config_byte(pdev, ICH_MAP, &map);
1613 if (map & 0x3) {
1614 dev_info(&pdev->dev,
1615 "controller is in combined mode, can't enable AHCI mode\n");
1616 return -ENODEV;
1617 }
1618 }
1619
1620 /* AHCI controllers often implement SFF compatible interface.
1621 * Grab all PCI BARs just in case.
1622 */
1623 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1624 if (rc == -EBUSY)
1625 pcim_pin_device(pdev);
1626 if (rc)
1627 return rc;
1628
1629 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1630 if (!hpriv)
1631 return -ENOMEM;
1632 hpriv->flags |= (unsigned long)pi.private_data;
1633
1634 /* MCP65 revision A1 and A2 can't do MSI */
1635 if (board_id == board_ahci_mcp65 &&
1636 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1637 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1638
1639 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1640 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1641 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1642
1643 /* only some SB600s can do 64bit DMA */
1644 if (ahci_sb600_enable_64bit(pdev))
1645 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1646
1647 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1648
1649 /* detect remapped nvme devices */
1650 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1651
1652 /* must set flag prior to save config in order to take effect */
1653 if (ahci_broken_devslp(pdev))
1654 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1655
1656 #ifdef CONFIG_ARM64
1657 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1658 hpriv->irq_handler = ahci_thunderx_irq_handler;
1659 #endif
1660
1661 /* save initial config */
1662 ahci_pci_save_initial_config(pdev, hpriv);
1663
1664 /* prepare host */
1665 if (hpriv->cap & HOST_CAP_NCQ) {
1666 pi.flags |= ATA_FLAG_NCQ;
1667 /*
1668 * Auto-activate optimization is supposed to be
1669 * supported on all AHCI controllers indicating NCQ
1670 * capability, but it seems to be broken on some
1671 * chipsets including NVIDIAs.
1672 */
1673 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1674 pi.flags |= ATA_FLAG_FPDMA_AA;
1675
1676 /*
1677 * All AHCI controllers should be forward-compatible
1678 * with the new auxiliary field. This code should be
1679 * conditionalized if any buggy AHCI controllers are
1680 * encountered.
1681 */
1682 pi.flags |= ATA_FLAG_FPDMA_AUX;
1683 }
1684
1685 if (hpriv->cap & HOST_CAP_PMP)
1686 pi.flags |= ATA_FLAG_PMP;
1687
1688 ahci_set_em_messages(hpriv, &pi);
1689
1690 if (ahci_broken_system_poweroff(pdev)) {
1691 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1692 dev_info(&pdev->dev,
1693 "quirky BIOS, skipping spindown on poweroff\n");
1694 }
1695
1696 if (ahci_broken_suspend(pdev)) {
1697 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1698 dev_warn(&pdev->dev,
1699 "BIOS update required for suspend/resume\n");
1700 }
1701
1702 if (ahci_broken_online(pdev)) {
1703 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1704 dev_info(&pdev->dev,
1705 "online status unreliable, applying workaround\n");
1706 }
1707
1708
1709 /* Acer SA5-271 workaround modifies private_data */
1710 acer_sa5_271_workaround(hpriv, pdev);
1711
1712 /* CAP.NP sometimes indicate the index of the last enabled
1713 * port, at other times, that of the last possible port, so
1714 * determining the maximum port number requires looking at
1715 * both CAP.NP and port_map.
1716 */
1717 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1718
1719 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1720 if (!host)
1721 return -ENOMEM;
1722 host->private_data = hpriv;
1723
1724 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1725 /* legacy intx interrupts */
1726 pci_intx(pdev, 1);
1727 }
1728 hpriv->irq = pci_irq_vector(pdev, 0);
1729
1730 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1731 host->flags |= ATA_HOST_PARALLEL_SCAN;
1732 else
1733 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1734
1735 if (pi.flags & ATA_FLAG_EM)
1736 ahci_reset_em(host);
1737
1738 for (i = 0; i < host->n_ports; i++) {
1739 struct ata_port *ap = host->ports[i];
1740
1741 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1742 ata_port_pbar_desc(ap, ahci_pci_bar,
1743 0x100 + ap->port_no * 0x80, "port");
1744
1745 /* set enclosure management message type */
1746 if (ap->flags & ATA_FLAG_EM)
1747 ap->em_message_type = hpriv->em_msg_type;
1748
1749 if ((hpriv->flags & AHCI_HFLAG_IS_MOBILE) &&
1750 mobile_lpm_policy >= ATA_LPM_UNKNOWN &&
1751 mobile_lpm_policy <= ATA_LPM_MIN_POWER)
1752 ap->target_lpm_policy = mobile_lpm_policy;
1753
1754 /* disabled/not-implemented port */
1755 if (!(hpriv->port_map & (1 << i)))
1756 ap->ops = &ata_dummy_port_ops;
1757 }
1758
1759 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1760 ahci_p5wdh_workaround(host);
1761
1762 /* apply gtf filter quirk */
1763 ahci_gtf_filter_workaround(host);
1764
1765 /* initialize adapter */
1766 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1767 if (rc)
1768 return rc;
1769
1770 rc = ahci_pci_reset_controller(host);
1771 if (rc)
1772 return rc;
1773
1774 ahci_pci_init_controller(host);
1775 ahci_pci_print_info(host);
1776
1777 pci_set_master(pdev);
1778
1779 rc = ahci_host_activate(host, &ahci_sht);
1780 if (rc)
1781 return rc;
1782
1783 pm_runtime_put_noidle(&pdev->dev);
1784 return 0;
1785 }
1786
1787 static void ahci_remove_one(struct pci_dev *pdev)
1788 {
1789 pm_runtime_get_noresume(&pdev->dev);
1790 ata_pci_remove_one(pdev);
1791 }
1792
1793 module_pci_driver(ahci_pci_driver);
1794
1795 MODULE_AUTHOR("Jeff Garzik");
1796 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1797 MODULE_LICENSE("GPL");
1798 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1799 MODULE_VERSION(DRV_VERSION);
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