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spi: sh-msiof: Fix timeout failures for TX-only DMA transfers
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include <linux/ahci-remap.h>
50 #include <linux/io-64-nonatomic-lo-hi.h>
51 #include "ahci.h"
52
53 #define DRV_NAME "ahci"
54 #define DRV_VERSION "3.0"
55
56 enum {
57 AHCI_PCI_BAR_STA2X11 = 0,
58 AHCI_PCI_BAR_CAVIUM = 0,
59 AHCI_PCI_BAR_ENMOTUS = 2,
60 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
61 AHCI_PCI_BAR_STANDARD = 5,
62 };
63
64 enum board_ids {
65 /* board IDs by feature in alphabetical order */
66 board_ahci,
67 board_ahci_ign_iferr,
68 board_ahci_nomsi,
69 board_ahci_noncq,
70 board_ahci_nosntf,
71 board_ahci_yes_fbs,
72
73 /* board IDs for specific chipsets in alphabetical order */
74 board_ahci_avn,
75 board_ahci_mcp65,
76 board_ahci_mcp77,
77 board_ahci_mcp89,
78 board_ahci_mv,
79 board_ahci_sb600,
80 board_ahci_sb700, /* for SB700 and SB800 */
81 board_ahci_vt8251,
82
83 /* aliases */
84 board_ahci_mcp_linux = board_ahci_mcp65,
85 board_ahci_mcp67 = board_ahci_mcp65,
86 board_ahci_mcp73 = board_ahci_mcp65,
87 board_ahci_mcp79 = board_ahci_mcp77,
88 };
89
90 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
91 static void ahci_remove_one(struct pci_dev *dev);
92 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
96 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
97 static bool is_mcp89_apple(struct pci_dev *pdev);
98 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
99 unsigned long deadline);
100 #ifdef CONFIG_PM
101 static int ahci_pci_device_runtime_suspend(struct device *dev);
102 static int ahci_pci_device_runtime_resume(struct device *dev);
103 #ifdef CONFIG_PM_SLEEP
104 static int ahci_pci_device_suspend(struct device *dev);
105 static int ahci_pci_device_resume(struct device *dev);
106 #endif
107 #endif /* CONFIG_PM */
108
109 static struct scsi_host_template ahci_sht = {
110 AHCI_SHT("ahci"),
111 };
112
113 static struct ata_port_operations ahci_vt8251_ops = {
114 .inherits = &ahci_ops,
115 .hardreset = ahci_vt8251_hardreset,
116 };
117
118 static struct ata_port_operations ahci_p5wdh_ops = {
119 .inherits = &ahci_ops,
120 .hardreset = ahci_p5wdh_hardreset,
121 };
122
123 static struct ata_port_operations ahci_avn_ops = {
124 .inherits = &ahci_ops,
125 .hardreset = ahci_avn_hardreset,
126 };
127
128 static const struct ata_port_info ahci_port_info[] = {
129 /* by features */
130 [board_ahci] = {
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
135 },
136 [board_ahci_ign_iferr] = {
137 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
138 .flags = AHCI_FLAG_COMMON,
139 .pio_mask = ATA_PIO4,
140 .udma_mask = ATA_UDMA6,
141 .port_ops = &ahci_ops,
142 },
143 [board_ahci_nomsi] = {
144 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
149 },
150 [board_ahci_noncq] = {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
156 },
157 [board_ahci_nosntf] = {
158 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
159 .flags = AHCI_FLAG_COMMON,
160 .pio_mask = ATA_PIO4,
161 .udma_mask = ATA_UDMA6,
162 .port_ops = &ahci_ops,
163 },
164 [board_ahci_yes_fbs] = {
165 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
166 .flags = AHCI_FLAG_COMMON,
167 .pio_mask = ATA_PIO4,
168 .udma_mask = ATA_UDMA6,
169 .port_ops = &ahci_ops,
170 },
171 /* by chipsets */
172 [board_ahci_avn] = {
173 .flags = AHCI_FLAG_COMMON,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_avn_ops,
177 },
178 [board_ahci_mcp65] = {
179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
180 AHCI_HFLAG_YES_NCQ),
181 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_ops,
185 },
186 [board_ahci_mcp77] = {
187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_ops,
192 },
193 [board_ahci_mcp89] = {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
199 },
200 [board_ahci_mv] = {
201 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
202 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
203 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
208 [board_ahci_sb600] = {
209 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
210 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
211 AHCI_HFLAG_32BIT_ONLY),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_pmp_retry_srst_ops,
216 },
217 [board_ahci_sb700] = { /* for SB700 and SB800 */
218 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
219 .flags = AHCI_FLAG_COMMON,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_pmp_retry_srst_ops,
223 },
224 [board_ahci_vt8251] = {
225 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
226 .flags = AHCI_FLAG_COMMON,
227 .pio_mask = ATA_PIO4,
228 .udma_mask = ATA_UDMA6,
229 .port_ops = &ahci_vt8251_ops,
230 },
231 };
232
233 static const struct pci_device_id ahci_pci_tbl[] = {
234 /* Intel */
235 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
236 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
237 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
238 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
239 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
240 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
241 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
242 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
243 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
244 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
245 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
246 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
247 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
248 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
249 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
250 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
252 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
255 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
256 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
257 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
260 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
261 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
262 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
263 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
264 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
265 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
266 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
267 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
268 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
269 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
270 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
271 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH M AHCI */
272 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
273 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH M RAID */
274 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
275 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
296 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT M AHCI */
297 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
298 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT M RAID */
299 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
300 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
301 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
302 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
303 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
304 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
305 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
306 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
307 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point M AHCI */
308 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
309 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
310 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
311 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point M RAID */
312 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
313 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
314 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point M AHCI */
315 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
316 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point M RAID */
317 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
318 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point M RAID */
319 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
320 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point M RAID */
321 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
322 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
323 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
324 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
328 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
329 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
331 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
338 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
339 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
344 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
345 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
347 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
348 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
349 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
350 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
351 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
352 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
354 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
355 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
356 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
357 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
359 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
360 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
361 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series M AHCI */
362 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
363 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series M RAID */
364 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
365 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series M RAID */
366 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
367 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series M RAID */
368 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
369 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
370 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
371 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
372 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H M AHCI */
373 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
374 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
375 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H M RAID */
376 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
377 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
378 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
379 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
380 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
381 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
382 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
384 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
385 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
386 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
387 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
388 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
389 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
390 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci }, /* Bay Trail AHCI */
391 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci }, /* Bay Trail AHCI */
392 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci }, /* Cherry Trail AHCI */
393 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci }, /* Apollo Lake AHCI */
394
395 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
396 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
397 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
398 /* JMicron 362B and 362C have an AHCI function with IDE class code */
399 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
400 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
401 /* May need to update quirk_jmicron_async_suspend() for additions */
402
403 /* ATI */
404 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
405 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
406 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
407 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
408 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
409 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
410 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
411
412 /* AMD */
413 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
414 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
415 /* AMD is using RAID class only for ahci controllers */
416 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
417 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
418
419 /* VIA */
420 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
421 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
422
423 /* NVIDIA */
424 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
431 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
432 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
456 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
457 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
458 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
459 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
460 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
502 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
503 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
504 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
505 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
506 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
507 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
508
509 /* SiS */
510 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
511 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
512 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
513
514 /* ST Microelectronics */
515 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
516
517 /* Marvell */
518 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
519 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
520 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
521 .class = PCI_CLASS_STORAGE_SATA_AHCI,
522 .class_mask = 0xffffff,
523 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
524 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
525 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
526 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
527 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
528 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
530 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
531 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
532 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
534 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
536 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
538 .driver_data = board_ahci_yes_fbs },
539 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
540 .driver_data = board_ahci_yes_fbs },
541 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
542 .driver_data = board_ahci_yes_fbs },
543 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
544 .driver_data = board_ahci_yes_fbs },
545 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
546 .driver_data = board_ahci_yes_fbs },
547 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
548 .driver_data = board_ahci_yes_fbs },
549
550 /* Promise */
551 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
552 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
553
554 /* Asmedia */
555 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
556 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
557 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
558 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
559 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
560 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
561
562 /*
563 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
564 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
565 */
566 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
567 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
568
569 /* Enmotus */
570 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
571
572 /* Generic, PCI class code for AHCI */
573 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
574 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
575
576 { } /* terminate list */
577 };
578
579 static const struct dev_pm_ops ahci_pci_pm_ops = {
580 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
581 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
582 ahci_pci_device_runtime_resume, NULL)
583 };
584
585 static struct pci_driver ahci_pci_driver = {
586 .name = DRV_NAME,
587 .id_table = ahci_pci_tbl,
588 .probe = ahci_init_one,
589 .remove = ahci_remove_one,
590 .driver = {
591 .pm = &ahci_pci_pm_ops,
592 },
593 };
594
595 #if IS_ENABLED(CONFIG_PATA_MARVELL)
596 static int marvell_enable;
597 #else
598 static int marvell_enable = 1;
599 #endif
600 module_param(marvell_enable, int, 0644);
601 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
602
603
604 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
605 struct ahci_host_priv *hpriv)
606 {
607 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
608 dev_info(&pdev->dev, "JMB361 has only one port\n");
609 hpriv->force_port_map = 1;
610 }
611
612 /*
613 * Temporary Marvell 6145 hack: PATA port presence
614 * is asserted through the standard AHCI port
615 * presence register, as bit 4 (counting from 0)
616 */
617 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
618 if (pdev->device == 0x6121)
619 hpriv->mask_port_map = 0x3;
620 else
621 hpriv->mask_port_map = 0xf;
622 dev_info(&pdev->dev,
623 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
624 }
625
626 ahci_save_initial_config(&pdev->dev, hpriv);
627 }
628
629 static int ahci_pci_reset_controller(struct ata_host *host)
630 {
631 struct pci_dev *pdev = to_pci_dev(host->dev);
632 int rc;
633
634 rc = ahci_reset_controller(host);
635 if (rc)
636 return rc;
637
638 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
639 struct ahci_host_priv *hpriv = host->private_data;
640 u16 tmp16;
641
642 /* configure PCS */
643 pci_read_config_word(pdev, 0x92, &tmp16);
644 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
645 tmp16 |= hpriv->port_map;
646 pci_write_config_word(pdev, 0x92, tmp16);
647 }
648 }
649
650 return 0;
651 }
652
653 static void ahci_pci_init_controller(struct ata_host *host)
654 {
655 struct ahci_host_priv *hpriv = host->private_data;
656 struct pci_dev *pdev = to_pci_dev(host->dev);
657 void __iomem *port_mmio;
658 u32 tmp;
659 int mv;
660
661 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
662 if (pdev->device == 0x6121)
663 mv = 2;
664 else
665 mv = 4;
666 port_mmio = __ahci_port_base(host, mv);
667
668 writel(0, port_mmio + PORT_IRQ_MASK);
669
670 /* clear port IRQ */
671 tmp = readl(port_mmio + PORT_IRQ_STAT);
672 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
673 if (tmp)
674 writel(tmp, port_mmio + PORT_IRQ_STAT);
675 }
676
677 ahci_init_controller(host);
678 }
679
680 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
681 unsigned long deadline)
682 {
683 struct ata_port *ap = link->ap;
684 struct ahci_host_priv *hpriv = ap->host->private_data;
685 bool online;
686 int rc;
687
688 DPRINTK("ENTER\n");
689
690 ahci_stop_engine(ap);
691
692 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
693 deadline, &online, NULL);
694
695 hpriv->start_engine(ap);
696
697 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
698
699 /* vt8251 doesn't clear BSY on signature FIS reception,
700 * request follow-up softreset.
701 */
702 return online ? -EAGAIN : rc;
703 }
704
705 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
706 unsigned long deadline)
707 {
708 struct ata_port *ap = link->ap;
709 struct ahci_port_priv *pp = ap->private_data;
710 struct ahci_host_priv *hpriv = ap->host->private_data;
711 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
712 struct ata_taskfile tf;
713 bool online;
714 int rc;
715
716 ahci_stop_engine(ap);
717
718 /* clear D2H reception area to properly wait for D2H FIS */
719 ata_tf_init(link->device, &tf);
720 tf.command = ATA_BUSY;
721 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
722
723 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
724 deadline, &online, NULL);
725
726 hpriv->start_engine(ap);
727
728 /* The pseudo configuration device on SIMG4726 attached to
729 * ASUS P5W-DH Deluxe doesn't send signature FIS after
730 * hardreset if no device is attached to the first downstream
731 * port && the pseudo device locks up on SRST w/ PMP==0. To
732 * work around this, wait for !BSY only briefly. If BSY isn't
733 * cleared, perform CLO and proceed to IDENTIFY (achieved by
734 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
735 *
736 * Wait for two seconds. Devices attached to downstream port
737 * which can't process the following IDENTIFY after this will
738 * have to be reset again. For most cases, this should
739 * suffice while making probing snappish enough.
740 */
741 if (online) {
742 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
743 ahci_check_ready);
744 if (rc)
745 ahci_kick_engine(ap);
746 }
747 return rc;
748 }
749
750 /*
751 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
752 *
753 * It has been observed with some SSDs that the timing of events in the
754 * link synchronization phase can leave the port in a state that can not
755 * be recovered by a SATA-hard-reset alone. The failing signature is
756 * SStatus.DET stuck at 1 ("Device presence detected but Phy
757 * communication not established"). It was found that unloading and
758 * reloading the driver when this problem occurs allows the drive
759 * connection to be recovered (DET advanced to 0x3). The critical
760 * component of reloading the driver is that the port state machines are
761 * reset by bouncing "port enable" in the AHCI PCS configuration
762 * register. So, reproduce that effect by bouncing a port whenever we
763 * see DET==1 after a reset.
764 */
765 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
766 unsigned long deadline)
767 {
768 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
769 struct ata_port *ap = link->ap;
770 struct ahci_port_priv *pp = ap->private_data;
771 struct ahci_host_priv *hpriv = ap->host->private_data;
772 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
773 unsigned long tmo = deadline - jiffies;
774 struct ata_taskfile tf;
775 bool online;
776 int rc, i;
777
778 DPRINTK("ENTER\n");
779
780 ahci_stop_engine(ap);
781
782 for (i = 0; i < 2; i++) {
783 u16 val;
784 u32 sstatus;
785 int port = ap->port_no;
786 struct ata_host *host = ap->host;
787 struct pci_dev *pdev = to_pci_dev(host->dev);
788
789 /* clear D2H reception area to properly wait for D2H FIS */
790 ata_tf_init(link->device, &tf);
791 tf.command = ATA_BUSY;
792 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
793
794 rc = sata_link_hardreset(link, timing, deadline, &online,
795 ahci_check_ready);
796
797 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
798 (sstatus & 0xf) != 1)
799 break;
800
801 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
802 port);
803
804 pci_read_config_word(pdev, 0x92, &val);
805 val &= ~(1 << port);
806 pci_write_config_word(pdev, 0x92, val);
807 ata_msleep(ap, 1000);
808 val |= 1 << port;
809 pci_write_config_word(pdev, 0x92, val);
810 deadline += tmo;
811 }
812
813 hpriv->start_engine(ap);
814
815 if (online)
816 *class = ahci_dev_classify(ap);
817
818 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
819 return rc;
820 }
821
822
823 #ifdef CONFIG_PM
824 static void ahci_pci_disable_interrupts(struct ata_host *host)
825 {
826 struct ahci_host_priv *hpriv = host->private_data;
827 void __iomem *mmio = hpriv->mmio;
828 u32 ctl;
829
830 /* AHCI spec rev1.1 section 8.3.3:
831 * Software must disable interrupts prior to requesting a
832 * transition of the HBA to D3 state.
833 */
834 ctl = readl(mmio + HOST_CTL);
835 ctl &= ~HOST_IRQ_EN;
836 writel(ctl, mmio + HOST_CTL);
837 readl(mmio + HOST_CTL); /* flush */
838 }
839
840 static int ahci_pci_device_runtime_suspend(struct device *dev)
841 {
842 struct pci_dev *pdev = to_pci_dev(dev);
843 struct ata_host *host = pci_get_drvdata(pdev);
844
845 ahci_pci_disable_interrupts(host);
846 return 0;
847 }
848
849 static int ahci_pci_device_runtime_resume(struct device *dev)
850 {
851 struct pci_dev *pdev = to_pci_dev(dev);
852 struct ata_host *host = pci_get_drvdata(pdev);
853 int rc;
854
855 rc = ahci_pci_reset_controller(host);
856 if (rc)
857 return rc;
858 ahci_pci_init_controller(host);
859 return 0;
860 }
861
862 #ifdef CONFIG_PM_SLEEP
863 static int ahci_pci_device_suspend(struct device *dev)
864 {
865 struct pci_dev *pdev = to_pci_dev(dev);
866 struct ata_host *host = pci_get_drvdata(pdev);
867 struct ahci_host_priv *hpriv = host->private_data;
868
869 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
870 dev_err(&pdev->dev,
871 "BIOS update required for suspend/resume\n");
872 return -EIO;
873 }
874
875 ahci_pci_disable_interrupts(host);
876 return ata_host_suspend(host, PMSG_SUSPEND);
877 }
878
879 static int ahci_pci_device_resume(struct device *dev)
880 {
881 struct pci_dev *pdev = to_pci_dev(dev);
882 struct ata_host *host = pci_get_drvdata(pdev);
883 int rc;
884
885 /* Apple BIOS helpfully mangles the registers on resume */
886 if (is_mcp89_apple(pdev))
887 ahci_mcp89_apple_enable(pdev);
888
889 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
890 rc = ahci_pci_reset_controller(host);
891 if (rc)
892 return rc;
893
894 ahci_pci_init_controller(host);
895 }
896
897 ata_host_resume(host);
898
899 return 0;
900 }
901 #endif
902
903 #endif /* CONFIG_PM */
904
905 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
906 {
907 int rc;
908
909 /*
910 * If the device fixup already set the dma_mask to some non-standard
911 * value, don't extend it here. This happens on STA2X11, for example.
912 */
913 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
914 return 0;
915
916 if (using_dac &&
917 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
918 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
919 if (rc) {
920 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
921 if (rc) {
922 dev_err(&pdev->dev,
923 "64-bit DMA enable failed\n");
924 return rc;
925 }
926 }
927 } else {
928 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
929 if (rc) {
930 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
931 return rc;
932 }
933 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
934 if (rc) {
935 dev_err(&pdev->dev,
936 "32-bit consistent DMA enable failed\n");
937 return rc;
938 }
939 }
940 return 0;
941 }
942
943 static void ahci_pci_print_info(struct ata_host *host)
944 {
945 struct pci_dev *pdev = to_pci_dev(host->dev);
946 u16 cc;
947 const char *scc_s;
948
949 pci_read_config_word(pdev, 0x0a, &cc);
950 if (cc == PCI_CLASS_STORAGE_IDE)
951 scc_s = "IDE";
952 else if (cc == PCI_CLASS_STORAGE_SATA)
953 scc_s = "SATA";
954 else if (cc == PCI_CLASS_STORAGE_RAID)
955 scc_s = "RAID";
956 else
957 scc_s = "unknown";
958
959 ahci_print_info(host, scc_s);
960 }
961
962 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
963 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
964 * support PMP and the 4726 either directly exports the device
965 * attached to the first downstream port or acts as a hardware storage
966 * controller and emulate a single ATA device (can be RAID 0/1 or some
967 * other configuration).
968 *
969 * When there's no device attached to the first downstream port of the
970 * 4726, "Config Disk" appears, which is a pseudo ATA device to
971 * configure the 4726. However, ATA emulation of the device is very
972 * lame. It doesn't send signature D2H Reg FIS after the initial
973 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
974 *
975 * The following function works around the problem by always using
976 * hardreset on the port and not depending on receiving signature FIS
977 * afterward. If signature FIS isn't received soon, ATA class is
978 * assumed without follow-up softreset.
979 */
980 static void ahci_p5wdh_workaround(struct ata_host *host)
981 {
982 static const struct dmi_system_id sysids[] = {
983 {
984 .ident = "P5W DH Deluxe",
985 .matches = {
986 DMI_MATCH(DMI_SYS_VENDOR,
987 "ASUSTEK COMPUTER INC"),
988 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
989 },
990 },
991 { }
992 };
993 struct pci_dev *pdev = to_pci_dev(host->dev);
994
995 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
996 dmi_check_system(sysids)) {
997 struct ata_port *ap = host->ports[1];
998
999 dev_info(&pdev->dev,
1000 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1001
1002 ap->ops = &ahci_p5wdh_ops;
1003 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1004 }
1005 }
1006
1007 /*
1008 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1009 * booting in BIOS compatibility mode. We restore the registers but not ID.
1010 */
1011 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1012 {
1013 u32 val;
1014
1015 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1016
1017 pci_read_config_dword(pdev, 0xf8, &val);
1018 val |= 1 << 0x1b;
1019 /* the following changes the device ID, but appears not to affect function */
1020 /* val = (val & ~0xf0000000) | 0x80000000; */
1021 pci_write_config_dword(pdev, 0xf8, val);
1022
1023 pci_read_config_dword(pdev, 0x54c, &val);
1024 val |= 1 << 0xc;
1025 pci_write_config_dword(pdev, 0x54c, val);
1026
1027 pci_read_config_dword(pdev, 0x4a4, &val);
1028 val &= 0xff;
1029 val |= 0x01060100;
1030 pci_write_config_dword(pdev, 0x4a4, val);
1031
1032 pci_read_config_dword(pdev, 0x54c, &val);
1033 val &= ~(1 << 0xc);
1034 pci_write_config_dword(pdev, 0x54c, val);
1035
1036 pci_read_config_dword(pdev, 0xf8, &val);
1037 val &= ~(1 << 0x1b);
1038 pci_write_config_dword(pdev, 0xf8, val);
1039 }
1040
1041 static bool is_mcp89_apple(struct pci_dev *pdev)
1042 {
1043 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1044 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1045 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1046 pdev->subsystem_device == 0xcb89;
1047 }
1048
1049 /* only some SB600 ahci controllers can do 64bit DMA */
1050 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1051 {
1052 static const struct dmi_system_id sysids[] = {
1053 /*
1054 * The oldest version known to be broken is 0901 and
1055 * working is 1501 which was released on 2007-10-26.
1056 * Enable 64bit DMA on 1501 and anything newer.
1057 *
1058 * Please read bko#9412 for more info.
1059 */
1060 {
1061 .ident = "ASUS M2A-VM",
1062 .matches = {
1063 DMI_MATCH(DMI_BOARD_VENDOR,
1064 "ASUSTeK Computer INC."),
1065 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1066 },
1067 .driver_data = "20071026", /* yyyymmdd */
1068 },
1069 /*
1070 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1071 * support 64bit DMA.
1072 *
1073 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1074 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1075 * This spelling mistake was fixed in BIOS version 1.5, so
1076 * 1.5 and later have the Manufacturer as
1077 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1078 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1079 *
1080 * BIOS versions earlier than 1.9 had a Board Product Name
1081 * DMI field of "MS-7376". This was changed to be
1082 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1083 * match on DMI_BOARD_NAME of "MS-7376".
1084 */
1085 {
1086 .ident = "MSI K9A2 Platinum",
1087 .matches = {
1088 DMI_MATCH(DMI_BOARD_VENDOR,
1089 "MICRO-STAR INTER"),
1090 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1091 },
1092 },
1093 /*
1094 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1095 * 64bit DMA.
1096 *
1097 * This board also had the typo mentioned above in the
1098 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1099 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1100 */
1101 {
1102 .ident = "MSI K9AGM2",
1103 .matches = {
1104 DMI_MATCH(DMI_BOARD_VENDOR,
1105 "MICRO-STAR INTER"),
1106 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1107 },
1108 },
1109 /*
1110 * All BIOS versions for the Asus M3A support 64bit DMA.
1111 * (all release versions from 0301 to 1206 were tested)
1112 */
1113 {
1114 .ident = "ASUS M3A",
1115 .matches = {
1116 DMI_MATCH(DMI_BOARD_VENDOR,
1117 "ASUSTeK Computer INC."),
1118 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1119 },
1120 },
1121 { }
1122 };
1123 const struct dmi_system_id *match;
1124 int year, month, date;
1125 char buf[9];
1126
1127 match = dmi_first_match(sysids);
1128 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1129 !match)
1130 return false;
1131
1132 if (!match->driver_data)
1133 goto enable_64bit;
1134
1135 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1136 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1137
1138 if (strcmp(buf, match->driver_data) >= 0)
1139 goto enable_64bit;
1140 else {
1141 dev_warn(&pdev->dev,
1142 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1143 match->ident);
1144 return false;
1145 }
1146
1147 enable_64bit:
1148 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1149 return true;
1150 }
1151
1152 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1153 {
1154 static const struct dmi_system_id broken_systems[] = {
1155 {
1156 .ident = "HP Compaq nx6310",
1157 .matches = {
1158 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1159 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1160 },
1161 /* PCI slot number of the controller */
1162 .driver_data = (void *)0x1FUL,
1163 },
1164 {
1165 .ident = "HP Compaq 6720s",
1166 .matches = {
1167 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1168 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1169 },
1170 /* PCI slot number of the controller */
1171 .driver_data = (void *)0x1FUL,
1172 },
1173
1174 { } /* terminate list */
1175 };
1176 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1177
1178 if (dmi) {
1179 unsigned long slot = (unsigned long)dmi->driver_data;
1180 /* apply the quirk only to on-board controllers */
1181 return slot == PCI_SLOT(pdev->devfn);
1182 }
1183
1184 return false;
1185 }
1186
1187 static bool ahci_broken_suspend(struct pci_dev *pdev)
1188 {
1189 static const struct dmi_system_id sysids[] = {
1190 /*
1191 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1192 * to the harddisk doesn't become online after
1193 * resuming from STR. Warn and fail suspend.
1194 *
1195 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1196 *
1197 * Use dates instead of versions to match as HP is
1198 * apparently recycling both product and version
1199 * strings.
1200 *
1201 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1202 */
1203 {
1204 .ident = "dv4",
1205 .matches = {
1206 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1207 DMI_MATCH(DMI_PRODUCT_NAME,
1208 "HP Pavilion dv4 Notebook PC"),
1209 },
1210 .driver_data = "20090105", /* F.30 */
1211 },
1212 {
1213 .ident = "dv5",
1214 .matches = {
1215 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1216 DMI_MATCH(DMI_PRODUCT_NAME,
1217 "HP Pavilion dv5 Notebook PC"),
1218 },
1219 .driver_data = "20090506", /* F.16 */
1220 },
1221 {
1222 .ident = "dv6",
1223 .matches = {
1224 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1225 DMI_MATCH(DMI_PRODUCT_NAME,
1226 "HP Pavilion dv6 Notebook PC"),
1227 },
1228 .driver_data = "20090423", /* F.21 */
1229 },
1230 {
1231 .ident = "HDX18",
1232 .matches = {
1233 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1234 DMI_MATCH(DMI_PRODUCT_NAME,
1235 "HP HDX18 Notebook PC"),
1236 },
1237 .driver_data = "20090430", /* F.23 */
1238 },
1239 /*
1240 * Acer eMachines G725 has the same problem. BIOS
1241 * V1.03 is known to be broken. V3.04 is known to
1242 * work. Between, there are V1.06, V2.06 and V3.03
1243 * that we don't have much idea about. For now,
1244 * blacklist anything older than V3.04.
1245 *
1246 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1247 */
1248 {
1249 .ident = "G725",
1250 .matches = {
1251 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1252 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1253 },
1254 .driver_data = "20091216", /* V3.04 */
1255 },
1256 { } /* terminate list */
1257 };
1258 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1259 int year, month, date;
1260 char buf[9];
1261
1262 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1263 return false;
1264
1265 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1266 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1267
1268 return strcmp(buf, dmi->driver_data) < 0;
1269 }
1270
1271 static bool ahci_broken_online(struct pci_dev *pdev)
1272 {
1273 #define ENCODE_BUSDEVFN(bus, slot, func) \
1274 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1275 static const struct dmi_system_id sysids[] = {
1276 /*
1277 * There are several gigabyte boards which use
1278 * SIMG5723s configured as hardware RAID. Certain
1279 * 5723 firmware revisions shipped there keep the link
1280 * online but fail to answer properly to SRST or
1281 * IDENTIFY when no device is attached downstream
1282 * causing libata to retry quite a few times leading
1283 * to excessive detection delay.
1284 *
1285 * As these firmwares respond to the second reset try
1286 * with invalid device signature, considering unknown
1287 * sig as offline works around the problem acceptably.
1288 */
1289 {
1290 .ident = "EP45-DQ6",
1291 .matches = {
1292 DMI_MATCH(DMI_BOARD_VENDOR,
1293 "Gigabyte Technology Co., Ltd."),
1294 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1295 },
1296 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1297 },
1298 {
1299 .ident = "EP45-DS5",
1300 .matches = {
1301 DMI_MATCH(DMI_BOARD_VENDOR,
1302 "Gigabyte Technology Co., Ltd."),
1303 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1304 },
1305 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1306 },
1307 { } /* terminate list */
1308 };
1309 #undef ENCODE_BUSDEVFN
1310 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1311 unsigned int val;
1312
1313 if (!dmi)
1314 return false;
1315
1316 val = (unsigned long)dmi->driver_data;
1317
1318 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1319 }
1320
1321 static bool ahci_broken_devslp(struct pci_dev *pdev)
1322 {
1323 /* device with broken DEVSLP but still showing SDS capability */
1324 static const struct pci_device_id ids[] = {
1325 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1326 {}
1327 };
1328
1329 return pci_match_id(ids, pdev);
1330 }
1331
1332 #ifdef CONFIG_ATA_ACPI
1333 static void ahci_gtf_filter_workaround(struct ata_host *host)
1334 {
1335 static const struct dmi_system_id sysids[] = {
1336 /*
1337 * Aspire 3810T issues a bunch of SATA enable commands
1338 * via _GTF including an invalid one and one which is
1339 * rejected by the device. Among the successful ones
1340 * is FPDMA non-zero offset enable which when enabled
1341 * only on the drive side leads to NCQ command
1342 * failures. Filter it out.
1343 */
1344 {
1345 .ident = "Aspire 3810T",
1346 .matches = {
1347 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1348 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1349 },
1350 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1351 },
1352 { }
1353 };
1354 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1355 unsigned int filter;
1356 int i;
1357
1358 if (!dmi)
1359 return;
1360
1361 filter = (unsigned long)dmi->driver_data;
1362 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1363 filter, dmi->ident);
1364
1365 for (i = 0; i < host->n_ports; i++) {
1366 struct ata_port *ap = host->ports[i];
1367 struct ata_link *link;
1368 struct ata_device *dev;
1369
1370 ata_for_each_link(link, ap, EDGE)
1371 ata_for_each_dev(dev, link, ALL)
1372 dev->gtf_filter |= filter;
1373 }
1374 }
1375 #else
1376 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1377 {}
1378 #endif
1379
1380 /*
1381 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1382 * as DUMMY, or detected but eventually get a "link down" and never get up
1383 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1384 * port_map may hold a value of 0x00.
1385 *
1386 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1387 * and can significantly reduce the occurrence of the problem.
1388 *
1389 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1390 */
1391 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1392 struct pci_dev *pdev)
1393 {
1394 static const struct dmi_system_id sysids[] = {
1395 {
1396 .ident = "Acer Switch Alpha 12",
1397 .matches = {
1398 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1399 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1400 },
1401 },
1402 { }
1403 };
1404
1405 if (dmi_check_system(sysids)) {
1406 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1407 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1408 hpriv->port_map = 0x7;
1409 hpriv->cap = 0xC734FF02;
1410 }
1411 }
1412 }
1413
1414 #ifdef CONFIG_ARM64
1415 /*
1416 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1417 * Workaround is to make sure all pending IRQs are served before leaving
1418 * handler.
1419 */
1420 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1421 {
1422 struct ata_host *host = dev_instance;
1423 struct ahci_host_priv *hpriv;
1424 unsigned int rc = 0;
1425 void __iomem *mmio;
1426 u32 irq_stat, irq_masked;
1427 unsigned int handled = 1;
1428
1429 VPRINTK("ENTER\n");
1430 hpriv = host->private_data;
1431 mmio = hpriv->mmio;
1432 irq_stat = readl(mmio + HOST_IRQ_STAT);
1433 if (!irq_stat)
1434 return IRQ_NONE;
1435
1436 do {
1437 irq_masked = irq_stat & hpriv->port_map;
1438 spin_lock(&host->lock);
1439 rc = ahci_handle_port_intr(host, irq_masked);
1440 if (!rc)
1441 handled = 0;
1442 writel(irq_stat, mmio + HOST_IRQ_STAT);
1443 irq_stat = readl(mmio + HOST_IRQ_STAT);
1444 spin_unlock(&host->lock);
1445 } while (irq_stat);
1446 VPRINTK("EXIT\n");
1447
1448 return IRQ_RETVAL(handled);
1449 }
1450 #endif
1451
1452 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1453 struct ahci_host_priv *hpriv)
1454 {
1455 int i, count = 0;
1456 u32 cap;
1457
1458 /*
1459 * Check if this device might have remapped nvme devices.
1460 */
1461 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1462 pci_resource_len(pdev, bar) < SZ_512K ||
1463 bar != AHCI_PCI_BAR_STANDARD ||
1464 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1465 return;
1466
1467 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1468 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1469 if ((cap & (1 << i)) == 0)
1470 continue;
1471 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1472 != PCI_CLASS_STORAGE_EXPRESS)
1473 continue;
1474
1475 /* We've found a remapped device */
1476 count++;
1477 }
1478
1479 if (!count)
1480 return;
1481
1482 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1483 dev_warn(&pdev->dev,
1484 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1485
1486 /*
1487 * Don't rely on the msi-x capability in the remap case,
1488 * share the legacy interrupt across ahci and remapped devices.
1489 */
1490 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1491 }
1492
1493 static int ahci_get_irq_vector(struct ata_host *host, int port)
1494 {
1495 return pci_irq_vector(to_pci_dev(host->dev), port);
1496 }
1497
1498 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1499 struct ahci_host_priv *hpriv)
1500 {
1501 int nvec;
1502
1503 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1504 return -ENODEV;
1505
1506 /*
1507 * If number of MSIs is less than number of ports then Sharing Last
1508 * Message mode could be enforced. In this case assume that advantage
1509 * of multipe MSIs is negated and use single MSI mode instead.
1510 */
1511 if (n_ports > 1) {
1512 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1513 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1514 if (nvec > 0) {
1515 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1516 hpriv->get_irq_vector = ahci_get_irq_vector;
1517 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1518 return nvec;
1519 }
1520
1521 /*
1522 * Fallback to single MSI mode if the controller
1523 * enforced MRSM mode.
1524 */
1525 printk(KERN_INFO
1526 "ahci: MRSM is on, fallback to single MSI\n");
1527 pci_free_irq_vectors(pdev);
1528 }
1529 }
1530
1531 /*
1532 * If the host is not capable of supporting per-port vectors, fall
1533 * back to single MSI before finally attempting single MSI-X.
1534 */
1535 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1536 if (nvec == 1)
1537 return nvec;
1538 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1539 }
1540
1541 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1542 {
1543 unsigned int board_id = ent->driver_data;
1544 struct ata_port_info pi = ahci_port_info[board_id];
1545 const struct ata_port_info *ppi[] = { &pi, NULL };
1546 struct device *dev = &pdev->dev;
1547 struct ahci_host_priv *hpriv;
1548 struct ata_host *host;
1549 int n_ports, i, rc;
1550 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1551
1552 VPRINTK("ENTER\n");
1553
1554 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1555
1556 ata_print_version_once(&pdev->dev, DRV_VERSION);
1557
1558 /* The AHCI driver can only drive the SATA ports, the PATA driver
1559 can drive them all so if both drivers are selected make sure
1560 AHCI stays out of the way */
1561 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1562 return -ENODEV;
1563
1564 /* Apple BIOS on MCP89 prevents us using AHCI */
1565 if (is_mcp89_apple(pdev))
1566 ahci_mcp89_apple_enable(pdev);
1567
1568 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1569 * At the moment, we can only use the AHCI mode. Let the users know
1570 * that for SAS drives they're out of luck.
1571 */
1572 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1573 dev_info(&pdev->dev,
1574 "PDC42819 can only drive SATA devices with this driver\n");
1575
1576 /* Some devices use non-standard BARs */
1577 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1578 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1579 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1580 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1581 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1582 if (pdev->device == 0xa01c)
1583 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1584 if (pdev->device == 0xa084)
1585 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1586 }
1587
1588 /* acquire resources */
1589 rc = pcim_enable_device(pdev);
1590 if (rc)
1591 return rc;
1592
1593 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1594 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1595 u8 map;
1596
1597 /* ICH6s share the same PCI ID for both piix and ahci
1598 * modes. Enabling ahci mode while MAP indicates
1599 * combined mode is a bad idea. Yield to ata_piix.
1600 */
1601 pci_read_config_byte(pdev, ICH_MAP, &map);
1602 if (map & 0x3) {
1603 dev_info(&pdev->dev,
1604 "controller is in combined mode, can't enable AHCI mode\n");
1605 return -ENODEV;
1606 }
1607 }
1608
1609 /* AHCI controllers often implement SFF compatible interface.
1610 * Grab all PCI BARs just in case.
1611 */
1612 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1613 if (rc == -EBUSY)
1614 pcim_pin_device(pdev);
1615 if (rc)
1616 return rc;
1617
1618 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1619 if (!hpriv)
1620 return -ENOMEM;
1621 hpriv->flags |= (unsigned long)pi.private_data;
1622
1623 /* MCP65 revision A1 and A2 can't do MSI */
1624 if (board_id == board_ahci_mcp65 &&
1625 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1626 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1627
1628 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1629 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1630 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1631
1632 /* only some SB600s can do 64bit DMA */
1633 if (ahci_sb600_enable_64bit(pdev))
1634 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1635
1636 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1637
1638 /* detect remapped nvme devices */
1639 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1640
1641 /* must set flag prior to save config in order to take effect */
1642 if (ahci_broken_devslp(pdev))
1643 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1644
1645 #ifdef CONFIG_ARM64
1646 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1647 hpriv->irq_handler = ahci_thunderx_irq_handler;
1648 #endif
1649
1650 /* save initial config */
1651 ahci_pci_save_initial_config(pdev, hpriv);
1652
1653 /* prepare host */
1654 if (hpriv->cap & HOST_CAP_NCQ) {
1655 pi.flags |= ATA_FLAG_NCQ;
1656 /*
1657 * Auto-activate optimization is supposed to be
1658 * supported on all AHCI controllers indicating NCQ
1659 * capability, but it seems to be broken on some
1660 * chipsets including NVIDIAs.
1661 */
1662 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1663 pi.flags |= ATA_FLAG_FPDMA_AA;
1664
1665 /*
1666 * All AHCI controllers should be forward-compatible
1667 * with the new auxiliary field. This code should be
1668 * conditionalized if any buggy AHCI controllers are
1669 * encountered.
1670 */
1671 pi.flags |= ATA_FLAG_FPDMA_AUX;
1672 }
1673
1674 if (hpriv->cap & HOST_CAP_PMP)
1675 pi.flags |= ATA_FLAG_PMP;
1676
1677 ahci_set_em_messages(hpriv, &pi);
1678
1679 if (ahci_broken_system_poweroff(pdev)) {
1680 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1681 dev_info(&pdev->dev,
1682 "quirky BIOS, skipping spindown on poweroff\n");
1683 }
1684
1685 if (ahci_broken_suspend(pdev)) {
1686 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1687 dev_warn(&pdev->dev,
1688 "BIOS update required for suspend/resume\n");
1689 }
1690
1691 if (ahci_broken_online(pdev)) {
1692 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1693 dev_info(&pdev->dev,
1694 "online status unreliable, applying workaround\n");
1695 }
1696
1697
1698 /* Acer SA5-271 workaround modifies private_data */
1699 acer_sa5_271_workaround(hpriv, pdev);
1700
1701 /* CAP.NP sometimes indicate the index of the last enabled
1702 * port, at other times, that of the last possible port, so
1703 * determining the maximum port number requires looking at
1704 * both CAP.NP and port_map.
1705 */
1706 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1707
1708 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1709 if (!host)
1710 return -ENOMEM;
1711 host->private_data = hpriv;
1712
1713 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1714 /* legacy intx interrupts */
1715 pci_intx(pdev, 1);
1716 }
1717 hpriv->irq = pci_irq_vector(pdev, 0);
1718
1719 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1720 host->flags |= ATA_HOST_PARALLEL_SCAN;
1721 else
1722 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1723
1724 if (pi.flags & ATA_FLAG_EM)
1725 ahci_reset_em(host);
1726
1727 for (i = 0; i < host->n_ports; i++) {
1728 struct ata_port *ap = host->ports[i];
1729
1730 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1731 ata_port_pbar_desc(ap, ahci_pci_bar,
1732 0x100 + ap->port_no * 0x80, "port");
1733
1734 /* set enclosure management message type */
1735 if (ap->flags & ATA_FLAG_EM)
1736 ap->em_message_type = hpriv->em_msg_type;
1737
1738
1739 /* disabled/not-implemented port */
1740 if (!(hpriv->port_map & (1 << i)))
1741 ap->ops = &ata_dummy_port_ops;
1742 }
1743
1744 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1745 ahci_p5wdh_workaround(host);
1746
1747 /* apply gtf filter quirk */
1748 ahci_gtf_filter_workaround(host);
1749
1750 /* initialize adapter */
1751 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1752 if (rc)
1753 return rc;
1754
1755 rc = ahci_pci_reset_controller(host);
1756 if (rc)
1757 return rc;
1758
1759 ahci_pci_init_controller(host);
1760 ahci_pci_print_info(host);
1761
1762 pci_set_master(pdev);
1763
1764 rc = ahci_host_activate(host, &ahci_sht);
1765 if (rc)
1766 return rc;
1767
1768 pm_runtime_put_noidle(&pdev->dev);
1769 return 0;
1770 }
1771
1772 static void ahci_remove_one(struct pci_dev *pdev)
1773 {
1774 pm_runtime_get_noresume(&pdev->dev);
1775 ata_pci_remove_one(pdev);
1776 }
1777
1778 module_pci_driver(ahci_pci_driver);
1779
1780 MODULE_AUTHOR("Jeff Garzik");
1781 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1782 MODULE_LICENSE("GPL");
1783 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1784 MODULE_VERSION(DRV_VERSION);
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