]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - drivers/ata/ahci.c
projects / mirror_ubuntu-eoan-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
libata: restructure SFF post-reset readiness waits
[mirror_ubuntu-eoan-kernel.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58 static void ahci_disable_alpm(struct ata_port *ap);
59
60 enum {
61 AHCI_PCI_BAR = 5,
62 AHCI_MAX_PORTS = 32,
63 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
65 AHCI_MAX_CMDS = 32,
66 AHCI_CMD_SZ = 32,
67 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
68 AHCI_RX_FIS_SZ = 256,
69 AHCI_CMD_TBL_CDB = 0x40,
70 AHCI_CMD_TBL_HDR_SZ = 0x80,
71 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
72 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
73 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
74 AHCI_RX_FIS_SZ,
75 AHCI_IRQ_ON_SG = (1 << 31),
76 AHCI_CMD_ATAPI = (1 << 5),
77 AHCI_CMD_WRITE = (1 << 6),
78 AHCI_CMD_PREFETCH = (1 << 7),
79 AHCI_CMD_RESET = (1 << 8),
80 AHCI_CMD_CLR_BUSY = (1 << 10),
81
82 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
83 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
84 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
85
86 board_ahci = 0,
87 board_ahci_vt8251 = 1,
88 board_ahci_ign_iferr = 2,
89 board_ahci_sb600 = 3,
90 board_ahci_mv = 4,
91 board_ahci_sb700 = 5,
92
93 /* global controller registers */
94 HOST_CAP = 0x00, /* host capabilities */
95 HOST_CTL = 0x04, /* global host control */
96 HOST_IRQ_STAT = 0x08, /* interrupt status */
97 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
98 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
99
100 /* HOST_CTL bits */
101 HOST_RESET = (1 << 0), /* reset controller; self-clear */
102 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
103 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
104
105 /* HOST_CAP bits */
106 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
107 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
108 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
109 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
110 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
111 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
112 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
113 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
114
115 /* registers for each SATA port */
116 PORT_LST_ADDR = 0x00, /* command list DMA addr */
117 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
118 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
119 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
120 PORT_IRQ_STAT = 0x10, /* interrupt status */
121 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
122 PORT_CMD = 0x18, /* port command */
123 PORT_TFDATA = 0x20, /* taskfile data */
124 PORT_SIG = 0x24, /* device TF signature */
125 PORT_CMD_ISSUE = 0x38, /* command issue */
126 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
127 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
128 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
129 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
130 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
131
132 /* PORT_IRQ_{STAT,MASK} bits */
133 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
134 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
135 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
136 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
137 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
138 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
139 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
140 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
141
142 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
143 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
144 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
145 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
146 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
147 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
148 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
149 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
150 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
151
152 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
153 PORT_IRQ_IF_ERR |
154 PORT_IRQ_CONNECT |
155 PORT_IRQ_PHYRDY |
156 PORT_IRQ_UNK_FIS |
157 PORT_IRQ_BAD_PMP,
158 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
159 PORT_IRQ_TF_ERR |
160 PORT_IRQ_HBUS_DATA_ERR,
161 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
162 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
163 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
164
165 /* PORT_CMD bits */
166 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
167 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
168 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
169 PORT_CMD_PMP = (1 << 17), /* PMP attached */
170 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
171 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
172 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
173 PORT_CMD_CLO = (1 << 3), /* Command list override */
174 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
175 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
176 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
177
178 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
179 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
180 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
181 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
182
183 /* hpriv->flags bits */
184 AHCI_HFLAG_NO_NCQ = (1 << 0),
185 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
186 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
187 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
188 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
189 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
190 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
191 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
192 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
193
194 /* ap->flags bits */
195
196 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
197 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
198 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
199 ATA_FLAG_IPM,
200
201 ICH_MAP = 0x90, /* ICH MAP register */
202 };
203
204 struct ahci_cmd_hdr {
205 __le32 opts;
206 __le32 status;
207 __le32 tbl_addr;
208 __le32 tbl_addr_hi;
209 __le32 reserved[4];
210 };
211
212 struct ahci_sg {
213 __le32 addr;
214 __le32 addr_hi;
215 __le32 reserved;
216 __le32 flags_size;
217 };
218
219 struct ahci_host_priv {
220 unsigned int flags; /* AHCI_HFLAG_* */
221 u32 cap; /* cap to use */
222 u32 port_map; /* port map to use */
223 u32 saved_cap; /* saved initial cap */
224 u32 saved_port_map; /* saved initial port_map */
225 };
226
227 struct ahci_port_priv {
228 struct ata_link *active_link;
229 struct ahci_cmd_hdr *cmd_slot;
230 dma_addr_t cmd_slot_dma;
231 void *cmd_tbl;
232 dma_addr_t cmd_tbl_dma;
233 void *rx_fis;
234 dma_addr_t rx_fis_dma;
235 /* for NCQ spurious interrupt analysis */
236 unsigned int ncq_saw_d2h:1;
237 unsigned int ncq_saw_dmas:1;
238 unsigned int ncq_saw_sdb:1;
239 u32 intr_mask; /* interrupts to enable */
240 };
241
242 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
243 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
244 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
245 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
246 static int ahci_port_start(struct ata_port *ap);
247 static void ahci_port_stop(struct ata_port *ap);
248 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
249 static void ahci_qc_prep(struct ata_queued_cmd *qc);
250 static u8 ahci_check_status(struct ata_port *ap);
251 static void ahci_freeze(struct ata_port *ap);
252 static void ahci_thaw(struct ata_port *ap);
253 static void ahci_pmp_attach(struct ata_port *ap);
254 static void ahci_pmp_detach(struct ata_port *ap);
255 static int ahci_softreset(struct ata_link *link, unsigned int *class,
256 unsigned long deadline);
257 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
258 unsigned long deadline);
259 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
260 unsigned long deadline);
261 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
262 unsigned long deadline);
263 static void ahci_postreset(struct ata_link *link, unsigned int *class);
264 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
265 unsigned long deadline);
266 static void ahci_error_handler(struct ata_port *ap);
267 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
268 static int ahci_port_resume(struct ata_port *ap);
269 static void ahci_dev_config(struct ata_device *dev);
270 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
271 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
272 u32 opts);
273 #ifdef CONFIG_PM
274 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
275 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
276 static int ahci_pci_device_resume(struct pci_dev *pdev);
277 #endif
278
279 static struct class_device_attribute *ahci_shost_attrs[] = {
280 &class_device_attr_link_power_management_policy,
281 NULL
282 };
283
284 static struct scsi_host_template ahci_sht = {
285 ATA_NCQ_SHT(DRV_NAME),
286 .can_queue = AHCI_MAX_CMDS - 1,
287 .sg_tablesize = AHCI_MAX_SG,
288 .dma_boundary = AHCI_DMA_BOUNDARY,
289 .shost_attrs = ahci_shost_attrs,
290 };
291
292 static struct ata_port_operations ahci_ops = {
293 .inherits = &sata_pmp_port_ops,
294
295 .sff_check_status = ahci_check_status,
296 .sff_check_altstatus = ahci_check_status,
297
298 .sff_tf_read = ahci_tf_read,
299 .qc_defer = sata_pmp_qc_defer_cmd_switch,
300 .qc_prep = ahci_qc_prep,
301 .qc_issue = ahci_qc_issue,
302
303 .freeze = ahci_freeze,
304 .thaw = ahci_thaw,
305 .softreset = ahci_softreset,
306 .hardreset = ahci_hardreset,
307 .postreset = ahci_postreset,
308 .pmp_softreset = ahci_pmp_softreset,
309 .error_handler = ahci_error_handler,
310 .post_internal_cmd = ahci_post_internal_cmd,
311 .dev_config = ahci_dev_config,
312
313 .scr_read = ahci_scr_read,
314 .scr_write = ahci_scr_write,
315 .pmp_attach = ahci_pmp_attach,
316 .pmp_detach = ahci_pmp_detach,
317
318 .enable_pm = ahci_enable_alpm,
319 .disable_pm = ahci_disable_alpm,
320 #ifdef CONFIG_PM
321 .port_suspend = ahci_port_suspend,
322 .port_resume = ahci_port_resume,
323 #endif
324 .port_start = ahci_port_start,
325 .port_stop = ahci_port_stop,
326 };
327
328 static struct ata_port_operations ahci_vt8251_ops = {
329 .inherits = &ahci_ops,
330 .hardreset = ahci_vt8251_hardreset,
331 };
332
333 static struct ata_port_operations ahci_p5wdh_ops = {
334 .inherits = &ahci_ops,
335 .hardreset = ahci_p5wdh_hardreset,
336 };
337
338 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
339
340 static const struct ata_port_info ahci_port_info[] = {
341 /* board_ahci */
342 {
343 .flags = AHCI_FLAG_COMMON,
344 .pio_mask = 0x1f, /* pio0-4 */
345 .udma_mask = ATA_UDMA6,
346 .port_ops = &ahci_ops,
347 },
348 /* board_ahci_vt8251 */
349 {
350 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
351 .flags = AHCI_FLAG_COMMON,
352 .pio_mask = 0x1f, /* pio0-4 */
353 .udma_mask = ATA_UDMA6,
354 .port_ops = &ahci_vt8251_ops,
355 },
356 /* board_ahci_ign_iferr */
357 {
358 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
359 .flags = AHCI_FLAG_COMMON,
360 .pio_mask = 0x1f, /* pio0-4 */
361 .udma_mask = ATA_UDMA6,
362 .port_ops = &ahci_ops,
363 },
364 /* board_ahci_sb600 */
365 {
366 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
367 AHCI_HFLAG_32BIT_ONLY |
368 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
369 .flags = AHCI_FLAG_COMMON,
370 .pio_mask = 0x1f, /* pio0-4 */
371 .udma_mask = ATA_UDMA6,
372 .port_ops = &ahci_ops,
373 },
374 /* board_ahci_mv */
375 {
376 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
377 AHCI_HFLAG_MV_PATA),
378 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
379 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
380 .pio_mask = 0x1f, /* pio0-4 */
381 .udma_mask = ATA_UDMA6,
382 .port_ops = &ahci_ops,
383 },
384 /* board_ahci_sb700 */
385 {
386 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
387 AHCI_HFLAG_NO_PMP),
388 .flags = AHCI_FLAG_COMMON,
389 .pio_mask = 0x1f, /* pio0-4 */
390 .udma_mask = ATA_UDMA6,
391 .port_ops = &ahci_ops,
392 },
393 };
394
395 static const struct pci_device_id ahci_pci_tbl[] = {
396 /* Intel */
397 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
398 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
399 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
400 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
401 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
402 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
403 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
404 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
405 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
406 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
407 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
408 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
409 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
410 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
411 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
412 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
413 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
414 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
415 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
416 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
417 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
418 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
419 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
420 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
421 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
422 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
423 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
424 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
425 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
426 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
427 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
428
429 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
430 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
431 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
432
433 /* ATI */
434 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
435 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
436 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
437 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
438 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
439 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
440 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
441
442 /* VIA */
443 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
444 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
445
446 /* NVIDIA */
447 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
448 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
453 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
454 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
455 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
456 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
476 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
477 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
478 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
487 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
488 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
489 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
490 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
491 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
497 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
498 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
499 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
500 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
501 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
502 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
503 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
504 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
505 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
506 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
507 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
508 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
509 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
510 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
511 { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */
512 { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */
513 { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */
514 { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */
515
516 /* SiS */
517 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
518 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
519 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
520
521 /* Marvell */
522 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
523 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
524
525 /* Generic, PCI class code for AHCI */
526 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
527 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
528
529 { } /* terminate list */
530 };
531
532
533 static struct pci_driver ahci_pci_driver = {
534 .name = DRV_NAME,
535 .id_table = ahci_pci_tbl,
536 .probe = ahci_init_one,
537 .remove = ata_pci_remove_one,
538 #ifdef CONFIG_PM
539 .suspend = ahci_pci_device_suspend,
540 .resume = ahci_pci_device_resume,
541 #endif
542 };
543
544
545 static inline int ahci_nr_ports(u32 cap)
546 {
547 return (cap & 0x1f) + 1;
548 }
549
550 static inline void __iomem *__ahci_port_base(struct ata_host *host,
551 unsigned int port_no)
552 {
553 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
554
555 return mmio + 0x100 + (port_no * 0x80);
556 }
557
558 static inline void __iomem *ahci_port_base(struct ata_port *ap)
559 {
560 return __ahci_port_base(ap->host, ap->port_no);
561 }
562
563 static void ahci_enable_ahci(void __iomem *mmio)
564 {
565 u32 tmp;
566
567 /* turn on AHCI_EN */
568 tmp = readl(mmio + HOST_CTL);
569 if (!(tmp & HOST_AHCI_EN)) {
570 tmp |= HOST_AHCI_EN;
571 writel(tmp, mmio + HOST_CTL);
572 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
573 WARN_ON(!(tmp & HOST_AHCI_EN));
574 }
575 }
576
577 /**
578 * ahci_save_initial_config - Save and fixup initial config values
579 * @pdev: target PCI device
580 * @hpriv: host private area to store config values
581 *
582 * Some registers containing configuration info might be setup by
583 * BIOS and might be cleared on reset. This function saves the
584 * initial values of those registers into @hpriv such that they
585 * can be restored after controller reset.
586 *
587 * If inconsistent, config values are fixed up by this function.
588 *
589 * LOCKING:
590 * None.
591 */
592 static void ahci_save_initial_config(struct pci_dev *pdev,
593 struct ahci_host_priv *hpriv)
594 {
595 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
596 u32 cap, port_map;
597 int i;
598 int mv;
599
600 /* make sure AHCI mode is enabled before accessing CAP */
601 ahci_enable_ahci(mmio);
602
603 /* Values prefixed with saved_ are written back to host after
604 * reset. Values without are used for driver operation.
605 */
606 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
607 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
608
609 /* some chips have errata preventing 64bit use */
610 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
611 dev_printk(KERN_INFO, &pdev->dev,
612 "controller can't do 64bit DMA, forcing 32bit\n");
613 cap &= ~HOST_CAP_64;
614 }
615
616 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
617 dev_printk(KERN_INFO, &pdev->dev,
618 "controller can't do NCQ, turning off CAP_NCQ\n");
619 cap &= ~HOST_CAP_NCQ;
620 }
621
622 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
623 dev_printk(KERN_INFO, &pdev->dev,
624 "controller can't do PMP, turning off CAP_PMP\n");
625 cap &= ~HOST_CAP_PMP;
626 }
627
628 /*
629 * Temporary Marvell 6145 hack: PATA port presence
630 * is asserted through the standard AHCI port
631 * presence register, as bit 4 (counting from 0)
632 */
633 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
634 if (pdev->device == 0x6121)
635 mv = 0x3;
636 else
637 mv = 0xf;
638 dev_printk(KERN_ERR, &pdev->dev,
639 "MV_AHCI HACK: port_map %x -> %x\n",
640 port_map,
641 port_map & mv);
642
643 port_map &= mv;
644 }
645
646 /* cross check port_map and cap.n_ports */
647 if (port_map) {
648 int map_ports = 0;
649
650 for (i = 0; i < AHCI_MAX_PORTS; i++)
651 if (port_map & (1 << i))
652 map_ports++;
653
654 /* If PI has more ports than n_ports, whine, clear
655 * port_map and let it be generated from n_ports.
656 */
657 if (map_ports > ahci_nr_ports(cap)) {
658 dev_printk(KERN_WARNING, &pdev->dev,
659 "implemented port map (0x%x) contains more "
660 "ports than nr_ports (%u), using nr_ports\n",
661 port_map, ahci_nr_ports(cap));
662 port_map = 0;
663 }
664 }
665
666 /* fabricate port_map from cap.nr_ports */
667 if (!port_map) {
668 port_map = (1 << ahci_nr_ports(cap)) - 1;
669 dev_printk(KERN_WARNING, &pdev->dev,
670 "forcing PORTS_IMPL to 0x%x\n", port_map);
671
672 /* write the fixed up value to the PI register */
673 hpriv->saved_port_map = port_map;
674 }
675
676 /* record values to use during operation */
677 hpriv->cap = cap;
678 hpriv->port_map = port_map;
679 }
680
681 /**
682 * ahci_restore_initial_config - Restore initial config
683 * @host: target ATA host
684 *
685 * Restore initial config stored by ahci_save_initial_config().
686 *
687 * LOCKING:
688 * None.
689 */
690 static void ahci_restore_initial_config(struct ata_host *host)
691 {
692 struct ahci_host_priv *hpriv = host->private_data;
693 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
694
695 writel(hpriv->saved_cap, mmio + HOST_CAP);
696 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
697 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
698 }
699
700 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
701 {
702 static const int offset[] = {
703 [SCR_STATUS] = PORT_SCR_STAT,
704 [SCR_CONTROL] = PORT_SCR_CTL,
705 [SCR_ERROR] = PORT_SCR_ERR,
706 [SCR_ACTIVE] = PORT_SCR_ACT,
707 [SCR_NOTIFICATION] = PORT_SCR_NTF,
708 };
709 struct ahci_host_priv *hpriv = ap->host->private_data;
710
711 if (sc_reg < ARRAY_SIZE(offset) &&
712 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
713 return offset[sc_reg];
714 return 0;
715 }
716
717 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
718 {
719 void __iomem *port_mmio = ahci_port_base(ap);
720 int offset = ahci_scr_offset(ap, sc_reg);
721
722 if (offset) {
723 *val = readl(port_mmio + offset);
724 return 0;
725 }
726 return -EINVAL;
727 }
728
729 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
730 {
731 void __iomem *port_mmio = ahci_port_base(ap);
732 int offset = ahci_scr_offset(ap, sc_reg);
733
734 if (offset) {
735 writel(val, port_mmio + offset);
736 return 0;
737 }
738 return -EINVAL;
739 }
740
741 static void ahci_start_engine(struct ata_port *ap)
742 {
743 void __iomem *port_mmio = ahci_port_base(ap);
744 u32 tmp;
745
746 /* start DMA */
747 tmp = readl(port_mmio + PORT_CMD);
748 tmp |= PORT_CMD_START;
749 writel(tmp, port_mmio + PORT_CMD);
750 readl(port_mmio + PORT_CMD); /* flush */
751 }
752
753 static int ahci_stop_engine(struct ata_port *ap)
754 {
755 void __iomem *port_mmio = ahci_port_base(ap);
756 u32 tmp;
757
758 tmp = readl(port_mmio + PORT_CMD);
759
760 /* check if the HBA is idle */
761 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
762 return 0;
763
764 /* setting HBA to idle */
765 tmp &= ~PORT_CMD_START;
766 writel(tmp, port_mmio + PORT_CMD);
767
768 /* wait for engine to stop. This could be as long as 500 msec */
769 tmp = ata_wait_register(port_mmio + PORT_CMD,
770 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
771 if (tmp & PORT_CMD_LIST_ON)
772 return -EIO;
773
774 return 0;
775 }
776
777 static void ahci_start_fis_rx(struct ata_port *ap)
778 {
779 void __iomem *port_mmio = ahci_port_base(ap);
780 struct ahci_host_priv *hpriv = ap->host->private_data;
781 struct ahci_port_priv *pp = ap->private_data;
782 u32 tmp;
783
784 /* set FIS registers */
785 if (hpriv->cap & HOST_CAP_64)
786 writel((pp->cmd_slot_dma >> 16) >> 16,
787 port_mmio + PORT_LST_ADDR_HI);
788 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
789
790 if (hpriv->cap & HOST_CAP_64)
791 writel((pp->rx_fis_dma >> 16) >> 16,
792 port_mmio + PORT_FIS_ADDR_HI);
793 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
794
795 /* enable FIS reception */
796 tmp = readl(port_mmio + PORT_CMD);
797 tmp |= PORT_CMD_FIS_RX;
798 writel(tmp, port_mmio + PORT_CMD);
799
800 /* flush */
801 readl(port_mmio + PORT_CMD);
802 }
803
804 static int ahci_stop_fis_rx(struct ata_port *ap)
805 {
806 void __iomem *port_mmio = ahci_port_base(ap);
807 u32 tmp;
808
809 /* disable FIS reception */
810 tmp = readl(port_mmio + PORT_CMD);
811 tmp &= ~PORT_CMD_FIS_RX;
812 writel(tmp, port_mmio + PORT_CMD);
813
814 /* wait for completion, spec says 500ms, give it 1000 */
815 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
816 PORT_CMD_FIS_ON, 10, 1000);
817 if (tmp & PORT_CMD_FIS_ON)
818 return -EBUSY;
819
820 return 0;
821 }
822
823 static void ahci_power_up(struct ata_port *ap)
824 {
825 struct ahci_host_priv *hpriv = ap->host->private_data;
826 void __iomem *port_mmio = ahci_port_base(ap);
827 u32 cmd;
828
829 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
830
831 /* spin up device */
832 if (hpriv->cap & HOST_CAP_SSS) {
833 cmd |= PORT_CMD_SPIN_UP;
834 writel(cmd, port_mmio + PORT_CMD);
835 }
836
837 /* wake up link */
838 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
839 }
840
841 static void ahci_disable_alpm(struct ata_port *ap)
842 {
843 struct ahci_host_priv *hpriv = ap->host->private_data;
844 void __iomem *port_mmio = ahci_port_base(ap);
845 u32 cmd;
846 struct ahci_port_priv *pp = ap->private_data;
847
848 /* IPM bits should be disabled by libata-core */
849 /* get the existing command bits */
850 cmd = readl(port_mmio + PORT_CMD);
851
852 /* disable ALPM and ASP */
853 cmd &= ~PORT_CMD_ASP;
854 cmd &= ~PORT_CMD_ALPE;
855
856 /* force the interface back to active */
857 cmd |= PORT_CMD_ICC_ACTIVE;
858
859 /* write out new cmd value */
860 writel(cmd, port_mmio + PORT_CMD);
861 cmd = readl(port_mmio + PORT_CMD);
862
863 /* wait 10ms to be sure we've come out of any low power state */
864 msleep(10);
865
866 /* clear out any PhyRdy stuff from interrupt status */
867 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
868
869 /* go ahead and clean out PhyRdy Change from Serror too */
870 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
871
872 /*
873 * Clear flag to indicate that we should ignore all PhyRdy
874 * state changes
875 */
876 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
877
878 /*
879 * Enable interrupts on Phy Ready.
880 */
881 pp->intr_mask |= PORT_IRQ_PHYRDY;
882 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
883
884 /*
885 * don't change the link pm policy - we can be called
886 * just to turn of link pm temporarily
887 */
888 }
889
890 static int ahci_enable_alpm(struct ata_port *ap,
891 enum link_pm policy)
892 {
893 struct ahci_host_priv *hpriv = ap->host->private_data;
894 void __iomem *port_mmio = ahci_port_base(ap);
895 u32 cmd;
896 struct ahci_port_priv *pp = ap->private_data;
897 u32 asp;
898
899 /* Make sure the host is capable of link power management */
900 if (!(hpriv->cap & HOST_CAP_ALPM))
901 return -EINVAL;
902
903 switch (policy) {
904 case MAX_PERFORMANCE:
905 case NOT_AVAILABLE:
906 /*
907 * if we came here with NOT_AVAILABLE,
908 * it just means this is the first time we
909 * have tried to enable - default to max performance,
910 * and let the user go to lower power modes on request.
911 */
912 ahci_disable_alpm(ap);
913 return 0;
914 case MIN_POWER:
915 /* configure HBA to enter SLUMBER */
916 asp = PORT_CMD_ASP;
917 break;
918 case MEDIUM_POWER:
919 /* configure HBA to enter PARTIAL */
920 asp = 0;
921 break;
922 default:
923 return -EINVAL;
924 }
925
926 /*
927 * Disable interrupts on Phy Ready. This keeps us from
928 * getting woken up due to spurious phy ready interrupts
929 * TBD - Hot plug should be done via polling now, is
930 * that even supported?
931 */
932 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
933 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
934
935 /*
936 * Set a flag to indicate that we should ignore all PhyRdy
937 * state changes since these can happen now whenever we
938 * change link state
939 */
940 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
941
942 /* get the existing command bits */
943 cmd = readl(port_mmio + PORT_CMD);
944
945 /*
946 * Set ASP based on Policy
947 */
948 cmd |= asp;
949
950 /*
951 * Setting this bit will instruct the HBA to aggressively
952 * enter a lower power link state when it's appropriate and
953 * based on the value set above for ASP
954 */
955 cmd |= PORT_CMD_ALPE;
956
957 /* write out new cmd value */
958 writel(cmd, port_mmio + PORT_CMD);
959 cmd = readl(port_mmio + PORT_CMD);
960
961 /* IPM bits should be set by libata-core */
962 return 0;
963 }
964
965 #ifdef CONFIG_PM
966 static void ahci_power_down(struct ata_port *ap)
967 {
968 struct ahci_host_priv *hpriv = ap->host->private_data;
969 void __iomem *port_mmio = ahci_port_base(ap);
970 u32 cmd, scontrol;
971
972 if (!(hpriv->cap & HOST_CAP_SSS))
973 return;
974
975 /* put device into listen mode, first set PxSCTL.DET to 0 */
976 scontrol = readl(port_mmio + PORT_SCR_CTL);
977 scontrol &= ~0xf;
978 writel(scontrol, port_mmio + PORT_SCR_CTL);
979
980 /* then set PxCMD.SUD to 0 */
981 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
982 cmd &= ~PORT_CMD_SPIN_UP;
983 writel(cmd, port_mmio + PORT_CMD);
984 }
985 #endif
986
987 static void ahci_start_port(struct ata_port *ap)
988 {
989 /* enable FIS reception */
990 ahci_start_fis_rx(ap);
991
992 /* enable DMA */
993 ahci_start_engine(ap);
994 }
995
996 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
997 {
998 int rc;
999
1000 /* disable DMA */
1001 rc = ahci_stop_engine(ap);
1002 if (rc) {
1003 *emsg = "failed to stop engine";
1004 return rc;
1005 }
1006
1007 /* disable FIS reception */
1008 rc = ahci_stop_fis_rx(ap);
1009 if (rc) {
1010 *emsg = "failed stop FIS RX";
1011 return rc;
1012 }
1013
1014 return 0;
1015 }
1016
1017 static int ahci_reset_controller(struct ata_host *host)
1018 {
1019 struct pci_dev *pdev = to_pci_dev(host->dev);
1020 struct ahci_host_priv *hpriv = host->private_data;
1021 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1022 u32 tmp;
1023
1024 /* we must be in AHCI mode, before using anything
1025 * AHCI-specific, such as HOST_RESET.
1026 */
1027 ahci_enable_ahci(mmio);
1028
1029 /* global controller reset */
1030 if (!ahci_skip_host_reset) {
1031 tmp = readl(mmio + HOST_CTL);
1032 if ((tmp & HOST_RESET) == 0) {
1033 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1034 readl(mmio + HOST_CTL); /* flush */
1035 }
1036
1037 /* reset must complete within 1 second, or
1038 * the hardware should be considered fried.
1039 */
1040 ssleep(1);
1041
1042 tmp = readl(mmio + HOST_CTL);
1043 if (tmp & HOST_RESET) {
1044 dev_printk(KERN_ERR, host->dev,
1045 "controller reset failed (0x%x)\n", tmp);
1046 return -EIO;
1047 }
1048
1049 /* turn on AHCI mode */
1050 ahci_enable_ahci(mmio);
1051
1052 /* Some registers might be cleared on reset. Restore
1053 * initial values.
1054 */
1055 ahci_restore_initial_config(host);
1056 } else
1057 dev_printk(KERN_INFO, host->dev,
1058 "skipping global host reset\n");
1059
1060 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1061 u16 tmp16;
1062
1063 /* configure PCS */
1064 pci_read_config_word(pdev, 0x92, &tmp16);
1065 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1066 tmp16 |= hpriv->port_map;
1067 pci_write_config_word(pdev, 0x92, tmp16);
1068 }
1069 }
1070
1071 return 0;
1072 }
1073
1074 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1075 int port_no, void __iomem *mmio,
1076 void __iomem *port_mmio)
1077 {
1078 const char *emsg = NULL;
1079 int rc;
1080 u32 tmp;
1081
1082 /* make sure port is not active */
1083 rc = ahci_deinit_port(ap, &emsg);
1084 if (rc)
1085 dev_printk(KERN_WARNING, &pdev->dev,
1086 "%s (%d)\n", emsg, rc);
1087
1088 /* clear SError */
1089 tmp = readl(port_mmio + PORT_SCR_ERR);
1090 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1091 writel(tmp, port_mmio + PORT_SCR_ERR);
1092
1093 /* clear port IRQ */
1094 tmp = readl(port_mmio + PORT_IRQ_STAT);
1095 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1096 if (tmp)
1097 writel(tmp, port_mmio + PORT_IRQ_STAT);
1098
1099 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1100 }
1101
1102 static void ahci_init_controller(struct ata_host *host)
1103 {
1104 struct ahci_host_priv *hpriv = host->private_data;
1105 struct pci_dev *pdev = to_pci_dev(host->dev);
1106 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1107 int i;
1108 void __iomem *port_mmio;
1109 u32 tmp;
1110 int mv;
1111
1112 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1113 if (pdev->device == 0x6121)
1114 mv = 2;
1115 else
1116 mv = 4;
1117 port_mmio = __ahci_port_base(host, mv);
1118
1119 writel(0, port_mmio + PORT_IRQ_MASK);
1120
1121 /* clear port IRQ */
1122 tmp = readl(port_mmio + PORT_IRQ_STAT);
1123 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1124 if (tmp)
1125 writel(tmp, port_mmio + PORT_IRQ_STAT);
1126 }
1127
1128 for (i = 0; i < host->n_ports; i++) {
1129 struct ata_port *ap = host->ports[i];
1130
1131 port_mmio = ahci_port_base(ap);
1132 if (ata_port_is_dummy(ap))
1133 continue;
1134
1135 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1136 }
1137
1138 tmp = readl(mmio + HOST_CTL);
1139 VPRINTK("HOST_CTL 0x%x\n", tmp);
1140 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1141 tmp = readl(mmio + HOST_CTL);
1142 VPRINTK("HOST_CTL 0x%x\n", tmp);
1143 }
1144
1145 static void ahci_dev_config(struct ata_device *dev)
1146 {
1147 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1148
1149 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1150 dev->max_sectors = 255;
1151 ata_dev_printk(dev, KERN_INFO,
1152 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1153 }
1154 }
1155
1156 static unsigned int ahci_dev_classify(struct ata_port *ap)
1157 {
1158 void __iomem *port_mmio = ahci_port_base(ap);
1159 struct ata_taskfile tf;
1160 u32 tmp;
1161
1162 tmp = readl(port_mmio + PORT_SIG);
1163 tf.lbah = (tmp >> 24) & 0xff;
1164 tf.lbam = (tmp >> 16) & 0xff;
1165 tf.lbal = (tmp >> 8) & 0xff;
1166 tf.nsect = (tmp) & 0xff;
1167
1168 return ata_dev_classify(&tf);
1169 }
1170
1171 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1172 u32 opts)
1173 {
1174 dma_addr_t cmd_tbl_dma;
1175
1176 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1177
1178 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1179 pp->cmd_slot[tag].status = 0;
1180 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1181 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1182 }
1183
1184 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1185 {
1186 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1187 struct ahci_host_priv *hpriv = ap->host->private_data;
1188 u32 tmp;
1189 int busy, rc;
1190
1191 /* do we need to kick the port? */
1192 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1193 if (!busy && !force_restart)
1194 return 0;
1195
1196 /* stop engine */
1197 rc = ahci_stop_engine(ap);
1198 if (rc)
1199 goto out_restart;
1200
1201 /* need to do CLO? */
1202 if (!busy) {
1203 rc = 0;
1204 goto out_restart;
1205 }
1206
1207 if (!(hpriv->cap & HOST_CAP_CLO)) {
1208 rc = -EOPNOTSUPP;
1209 goto out_restart;
1210 }
1211
1212 /* perform CLO */
1213 tmp = readl(port_mmio + PORT_CMD);
1214 tmp |= PORT_CMD_CLO;
1215 writel(tmp, port_mmio + PORT_CMD);
1216
1217 rc = 0;
1218 tmp = ata_wait_register(port_mmio + PORT_CMD,
1219 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1220 if (tmp & PORT_CMD_CLO)
1221 rc = -EIO;
1222
1223 /* restart engine */
1224 out_restart:
1225 ahci_start_engine(ap);
1226 return rc;
1227 }
1228
1229 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1230 struct ata_taskfile *tf, int is_cmd, u16 flags,
1231 unsigned long timeout_msec)
1232 {
1233 const u32 cmd_fis_len = 5; /* five dwords */
1234 struct ahci_port_priv *pp = ap->private_data;
1235 void __iomem *port_mmio = ahci_port_base(ap);
1236 u8 *fis = pp->cmd_tbl;
1237 u32 tmp;
1238
1239 /* prep the command */
1240 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1241 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1242
1243 /* issue & wait */
1244 writel(1, port_mmio + PORT_CMD_ISSUE);
1245
1246 if (timeout_msec) {
1247 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1248 1, timeout_msec);
1249 if (tmp & 0x1) {
1250 ahci_kick_engine(ap, 1);
1251 return -EBUSY;
1252 }
1253 } else
1254 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1255
1256 return 0;
1257 }
1258
1259 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1260 int pmp, unsigned long deadline)
1261 {
1262 struct ata_port *ap = link->ap;
1263 const char *reason = NULL;
1264 unsigned long now, msecs;
1265 struct ata_taskfile tf;
1266 int rc;
1267
1268 DPRINTK("ENTER\n");
1269
1270 if (ata_link_offline(link)) {
1271 DPRINTK("PHY reports no device\n");
1272 *class = ATA_DEV_NONE;
1273 return 0;
1274 }
1275
1276 /* prepare for SRST (AHCI-1.1 10.4.1) */
1277 rc = ahci_kick_engine(ap, 1);
1278 if (rc && rc != -EOPNOTSUPP)
1279 ata_link_printk(link, KERN_WARNING,
1280 "failed to reset engine (errno=%d)\n", rc);
1281
1282 ata_tf_init(link->device, &tf);
1283
1284 /* issue the first D2H Register FIS */
1285 msecs = 0;
1286 now = jiffies;
1287 if (time_after(now, deadline))
1288 msecs = jiffies_to_msecs(deadline - now);
1289
1290 tf.ctl |= ATA_SRST;
1291 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1292 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1293 rc = -EIO;
1294 reason = "1st FIS failed";
1295 goto fail;
1296 }
1297
1298 /* spec says at least 5us, but be generous and sleep for 1ms */
1299 msleep(1);
1300
1301 /* issue the second D2H Register FIS */
1302 tf.ctl &= ~ATA_SRST;
1303 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1304
1305 /* wait for link to become ready */
1306 rc = ata_sff_wait_after_reset(link, 1, deadline);
1307 /* link occupied, -ENODEV too is an error */
1308 if (rc) {
1309 reason = "device not ready";
1310 goto fail;
1311 }
1312 *class = ahci_dev_classify(ap);
1313
1314 DPRINTK("EXIT, class=%u\n", *class);
1315 return 0;
1316
1317 fail:
1318 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1319 return rc;
1320 }
1321
1322 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1323 unsigned long deadline)
1324 {
1325 int pmp = 0;
1326
1327 if (link->ap->flags & ATA_FLAG_PMP)
1328 pmp = SATA_PMP_CTRL_PORT;
1329
1330 return ahci_do_softreset(link, class, pmp, deadline);
1331 }
1332
1333 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1334 unsigned long deadline)
1335 {
1336 struct ata_port *ap = link->ap;
1337 struct ahci_port_priv *pp = ap->private_data;
1338 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1339 struct ata_taskfile tf;
1340 int rc;
1341
1342 DPRINTK("ENTER\n");
1343
1344 ahci_stop_engine(ap);
1345
1346 /* clear D2H reception area to properly wait for D2H FIS */
1347 ata_tf_init(link->device, &tf);
1348 tf.command = 0x80;
1349 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1350
1351 rc = sata_sff_hardreset(link, class, deadline);
1352
1353 ahci_start_engine(ap);
1354
1355 if (rc == 0 && ata_link_online(link))
1356 *class = ahci_dev_classify(ap);
1357 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1358 *class = ATA_DEV_NONE;
1359
1360 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1361 return rc;
1362 }
1363
1364 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1365 unsigned long deadline)
1366 {
1367 struct ata_port *ap = link->ap;
1368 u32 serror;
1369 int rc;
1370
1371 DPRINTK("ENTER\n");
1372
1373 ahci_stop_engine(ap);
1374
1375 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1376 deadline);
1377
1378 /* vt8251 needs SError cleared for the port to operate */
1379 ahci_scr_read(ap, SCR_ERROR, &serror);
1380 ahci_scr_write(ap, SCR_ERROR, serror);
1381
1382 ahci_start_engine(ap);
1383
1384 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1385
1386 /* vt8251 doesn't clear BSY on signature FIS reception,
1387 * request follow-up softreset.
1388 */
1389 return rc ?: -EAGAIN;
1390 }
1391
1392 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1393 unsigned long deadline)
1394 {
1395 struct ata_port *ap = link->ap;
1396 struct ahci_port_priv *pp = ap->private_data;
1397 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1398 struct ata_taskfile tf;
1399 int rc;
1400
1401 ahci_stop_engine(ap);
1402
1403 /* clear D2H reception area to properly wait for D2H FIS */
1404 ata_tf_init(link->device, &tf);
1405 tf.command = 0x80;
1406 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1407
1408 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1409 deadline);
1410
1411 ahci_start_engine(ap);
1412
1413 if (rc || ata_link_offline(link))
1414 return rc;
1415
1416 /* The pseudo configuration device on SIMG4726 attached to
1417 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1418 * hardreset if no device is attached to the first downstream
1419 * port && the pseudo device locks up on SRST w/ PMP==0. To
1420 * work around this, wait for !BSY only briefly. If BSY isn't
1421 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1422 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1423 *
1424 * Wait for two seconds. Devices attached to downstream port
1425 * which can't process the following IDENTIFY after this will
1426 * have to be reset again. For most cases, this should
1427 * suffice while making probing snappish enough.
1428 */
1429 rc = ata_sff_wait_after_reset(link, 1, jiffies + 2 * HZ);
1430 if (rc)
1431 ahci_kick_engine(ap, 0);
1432
1433 return 0;
1434 }
1435
1436 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1437 {
1438 struct ata_port *ap = link->ap;
1439 void __iomem *port_mmio = ahci_port_base(ap);
1440 u32 new_tmp, tmp;
1441
1442 ata_std_postreset(link, class);
1443
1444 /* Make sure port's ATAPI bit is set appropriately */
1445 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1446 if (*class == ATA_DEV_ATAPI)
1447 new_tmp |= PORT_CMD_ATAPI;
1448 else
1449 new_tmp &= ~PORT_CMD_ATAPI;
1450 if (new_tmp != tmp) {
1451 writel(new_tmp, port_mmio + PORT_CMD);
1452 readl(port_mmio + PORT_CMD); /* flush */
1453 }
1454 }
1455
1456 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1457 unsigned long deadline)
1458 {
1459 return ahci_do_softreset(link, class, link->pmp, deadline);
1460 }
1461
1462 static u8 ahci_check_status(struct ata_port *ap)
1463 {
1464 void __iomem *mmio = ap->ioaddr.cmd_addr;
1465
1466 return readl(mmio + PORT_TFDATA) & 0xFF;
1467 }
1468
1469 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1470 {
1471 struct ahci_port_priv *pp = ap->private_data;
1472 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1473
1474 ata_tf_from_fis(d2h_fis, tf);
1475 }
1476
1477 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1478 {
1479 struct scatterlist *sg;
1480 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1481 unsigned int si;
1482
1483 VPRINTK("ENTER\n");
1484
1485 /*
1486 * Next, the S/G list.
1487 */
1488 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1489 dma_addr_t addr = sg_dma_address(sg);
1490 u32 sg_len = sg_dma_len(sg);
1491
1492 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1493 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1494 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1495 }
1496
1497 return si;
1498 }
1499
1500 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1501 {
1502 struct ata_port *ap = qc->ap;
1503 struct ahci_port_priv *pp = ap->private_data;
1504 int is_atapi = ata_is_atapi(qc->tf.protocol);
1505 void *cmd_tbl;
1506 u32 opts;
1507 const u32 cmd_fis_len = 5; /* five dwords */
1508 unsigned int n_elem;
1509
1510 /*
1511 * Fill in command table information. First, the header,
1512 * a SATA Register - Host to Device command FIS.
1513 */
1514 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1515
1516 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1517 if (is_atapi) {
1518 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1519 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1520 }
1521
1522 n_elem = 0;
1523 if (qc->flags & ATA_QCFLAG_DMAMAP)
1524 n_elem = ahci_fill_sg(qc, cmd_tbl);
1525
1526 /*
1527 * Fill in command slot information.
1528 */
1529 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1530 if (qc->tf.flags & ATA_TFLAG_WRITE)
1531 opts |= AHCI_CMD_WRITE;
1532 if (is_atapi)
1533 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1534
1535 ahci_fill_cmd_slot(pp, qc->tag, opts);
1536 }
1537
1538 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1539 {
1540 struct ahci_host_priv *hpriv = ap->host->private_data;
1541 struct ahci_port_priv *pp = ap->private_data;
1542 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1543 struct ata_link *link = NULL;
1544 struct ata_queued_cmd *active_qc;
1545 struct ata_eh_info *active_ehi;
1546 u32 serror;
1547
1548 /* determine active link */
1549 ata_port_for_each_link(link, ap)
1550 if (ata_link_active(link))
1551 break;
1552 if (!link)
1553 link = &ap->link;
1554
1555 active_qc = ata_qc_from_tag(ap, link->active_tag);
1556 active_ehi = &link->eh_info;
1557
1558 /* record irq stat */
1559 ata_ehi_clear_desc(host_ehi);
1560 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1561
1562 /* AHCI needs SError cleared; otherwise, it might lock up */
1563 ahci_scr_read(ap, SCR_ERROR, &serror);
1564 ahci_scr_write(ap, SCR_ERROR, serror);
1565 host_ehi->serror |= serror;
1566
1567 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1568 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1569 irq_stat &= ~PORT_IRQ_IF_ERR;
1570
1571 if (irq_stat & PORT_IRQ_TF_ERR) {
1572 /* If qc is active, charge it; otherwise, the active
1573 * link. There's no active qc on NCQ errors. It will
1574 * be determined by EH by reading log page 10h.
1575 */
1576 if (active_qc)
1577 active_qc->err_mask |= AC_ERR_DEV;
1578 else
1579 active_ehi->err_mask |= AC_ERR_DEV;
1580
1581 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1582 host_ehi->serror &= ~SERR_INTERNAL;
1583 }
1584
1585 if (irq_stat & PORT_IRQ_UNK_FIS) {
1586 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1587
1588 active_ehi->err_mask |= AC_ERR_HSM;
1589 active_ehi->action |= ATA_EH_RESET;
1590 ata_ehi_push_desc(active_ehi,
1591 "unknown FIS %08x %08x %08x %08x" ,
1592 unk[0], unk[1], unk[2], unk[3]);
1593 }
1594
1595 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1596 active_ehi->err_mask |= AC_ERR_HSM;
1597 active_ehi->action |= ATA_EH_RESET;
1598 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1599 }
1600
1601 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1602 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1603 host_ehi->action |= ATA_EH_RESET;
1604 ata_ehi_push_desc(host_ehi, "host bus error");
1605 }
1606
1607 if (irq_stat & PORT_IRQ_IF_ERR) {
1608 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1609 host_ehi->action |= ATA_EH_RESET;
1610 ata_ehi_push_desc(host_ehi, "interface fatal error");
1611 }
1612
1613 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1614 ata_ehi_hotplugged(host_ehi);
1615 ata_ehi_push_desc(host_ehi, "%s",
1616 irq_stat & PORT_IRQ_CONNECT ?
1617 "connection status changed" : "PHY RDY changed");
1618 }
1619
1620 /* okay, let's hand over to EH */
1621
1622 if (irq_stat & PORT_IRQ_FREEZE)
1623 ata_port_freeze(ap);
1624 else
1625 ata_port_abort(ap);
1626 }
1627
1628 static void ahci_port_intr(struct ata_port *ap)
1629 {
1630 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1631 struct ata_eh_info *ehi = &ap->link.eh_info;
1632 struct ahci_port_priv *pp = ap->private_data;
1633 struct ahci_host_priv *hpriv = ap->host->private_data;
1634 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1635 u32 status, qc_active;
1636 int rc;
1637
1638 status = readl(port_mmio + PORT_IRQ_STAT);
1639 writel(status, port_mmio + PORT_IRQ_STAT);
1640
1641 /* ignore BAD_PMP while resetting */
1642 if (unlikely(resetting))
1643 status &= ~PORT_IRQ_BAD_PMP;
1644
1645 /* If we are getting PhyRdy, this is
1646 * just a power state change, we should
1647 * clear out this, plus the PhyRdy/Comm
1648 * Wake bits from Serror
1649 */
1650 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1651 (status & PORT_IRQ_PHYRDY)) {
1652 status &= ~PORT_IRQ_PHYRDY;
1653 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1654 }
1655
1656 if (unlikely(status & PORT_IRQ_ERROR)) {
1657 ahci_error_intr(ap, status);
1658 return;
1659 }
1660
1661 if (status & PORT_IRQ_SDB_FIS) {
1662 /* If SNotification is available, leave notification
1663 * handling to sata_async_notification(). If not,
1664 * emulate it by snooping SDB FIS RX area.
1665 *
1666 * Snooping FIS RX area is probably cheaper than
1667 * poking SNotification but some constrollers which
1668 * implement SNotification, ICH9 for example, don't
1669 * store AN SDB FIS into receive area.
1670 */
1671 if (hpriv->cap & HOST_CAP_SNTF)
1672 sata_async_notification(ap);
1673 else {
1674 /* If the 'N' bit in word 0 of the FIS is set,
1675 * we just received asynchronous notification.
1676 * Tell libata about it.
1677 */
1678 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1679 u32 f0 = le32_to_cpu(f[0]);
1680
1681 if (f0 & (1 << 15))
1682 sata_async_notification(ap);
1683 }
1684 }
1685
1686 /* pp->active_link is valid iff any command is in flight */
1687 if (ap->qc_active && pp->active_link->sactive)
1688 qc_active = readl(port_mmio + PORT_SCR_ACT);
1689 else
1690 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1691
1692 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1693
1694 /* while resetting, invalid completions are expected */
1695 if (unlikely(rc < 0 && !resetting)) {
1696 ehi->err_mask |= AC_ERR_HSM;
1697 ehi->action |= ATA_EH_RESET;
1698 ata_port_freeze(ap);
1699 }
1700 }
1701
1702 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1703 {
1704 struct ata_host *host = dev_instance;
1705 struct ahci_host_priv *hpriv;
1706 unsigned int i, handled = 0;
1707 void __iomem *mmio;
1708 u32 irq_stat, irq_ack = 0;
1709
1710 VPRINTK("ENTER\n");
1711
1712 hpriv = host->private_data;
1713 mmio = host->iomap[AHCI_PCI_BAR];
1714
1715 /* sigh. 0xffffffff is a valid return from h/w */
1716 irq_stat = readl(mmio + HOST_IRQ_STAT);
1717 irq_stat &= hpriv->port_map;
1718 if (!irq_stat)
1719 return IRQ_NONE;
1720
1721 spin_lock(&host->lock);
1722
1723 for (i = 0; i < host->n_ports; i++) {
1724 struct ata_port *ap;
1725
1726 if (!(irq_stat & (1 << i)))
1727 continue;
1728
1729 ap = host->ports[i];
1730 if (ap) {
1731 ahci_port_intr(ap);
1732 VPRINTK("port %u\n", i);
1733 } else {
1734 VPRINTK("port %u (no irq)\n", i);
1735 if (ata_ratelimit())
1736 dev_printk(KERN_WARNING, host->dev,
1737 "interrupt on disabled port %u\n", i);
1738 }
1739
1740 irq_ack |= (1 << i);
1741 }
1742
1743 if (irq_ack) {
1744 writel(irq_ack, mmio + HOST_IRQ_STAT);
1745 handled = 1;
1746 }
1747
1748 spin_unlock(&host->lock);
1749
1750 VPRINTK("EXIT\n");
1751
1752 return IRQ_RETVAL(handled);
1753 }
1754
1755 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1756 {
1757 struct ata_port *ap = qc->ap;
1758 void __iomem *port_mmio = ahci_port_base(ap);
1759 struct ahci_port_priv *pp = ap->private_data;
1760
1761 /* Keep track of the currently active link. It will be used
1762 * in completion path to determine whether NCQ phase is in
1763 * progress.
1764 */
1765 pp->active_link = qc->dev->link;
1766
1767 if (qc->tf.protocol == ATA_PROT_NCQ)
1768 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1769 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1770 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1771
1772 return 0;
1773 }
1774
1775 static void ahci_freeze(struct ata_port *ap)
1776 {
1777 void __iomem *port_mmio = ahci_port_base(ap);
1778
1779 /* turn IRQ off */
1780 writel(0, port_mmio + PORT_IRQ_MASK);
1781 }
1782
1783 static void ahci_thaw(struct ata_port *ap)
1784 {
1785 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1786 void __iomem *port_mmio = ahci_port_base(ap);
1787 u32 tmp;
1788 struct ahci_port_priv *pp = ap->private_data;
1789
1790 /* clear IRQ */
1791 tmp = readl(port_mmio + PORT_IRQ_STAT);
1792 writel(tmp, port_mmio + PORT_IRQ_STAT);
1793 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1794
1795 /* turn IRQ back on */
1796 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1797 }
1798
1799 static void ahci_error_handler(struct ata_port *ap)
1800 {
1801 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1802 /* restart engine */
1803 ahci_stop_engine(ap);
1804 ahci_start_engine(ap);
1805 }
1806
1807 sata_pmp_error_handler(ap);
1808 }
1809
1810 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1811 {
1812 struct ata_port *ap = qc->ap;
1813
1814 /* make DMA engine forget about the failed command */
1815 if (qc->flags & ATA_QCFLAG_FAILED)
1816 ahci_kick_engine(ap, 1);
1817 }
1818
1819 static void ahci_pmp_attach(struct ata_port *ap)
1820 {
1821 void __iomem *port_mmio = ahci_port_base(ap);
1822 struct ahci_port_priv *pp = ap->private_data;
1823 u32 cmd;
1824
1825 cmd = readl(port_mmio + PORT_CMD);
1826 cmd |= PORT_CMD_PMP;
1827 writel(cmd, port_mmio + PORT_CMD);
1828
1829 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1830 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1831 }
1832
1833 static void ahci_pmp_detach(struct ata_port *ap)
1834 {
1835 void __iomem *port_mmio = ahci_port_base(ap);
1836 struct ahci_port_priv *pp = ap->private_data;
1837 u32 cmd;
1838
1839 cmd = readl(port_mmio + PORT_CMD);
1840 cmd &= ~PORT_CMD_PMP;
1841 writel(cmd, port_mmio + PORT_CMD);
1842
1843 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1844 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1845 }
1846
1847 static int ahci_port_resume(struct ata_port *ap)
1848 {
1849 ahci_power_up(ap);
1850 ahci_start_port(ap);
1851
1852 if (ap->nr_pmp_links)
1853 ahci_pmp_attach(ap);
1854 else
1855 ahci_pmp_detach(ap);
1856
1857 return 0;
1858 }
1859
1860 #ifdef CONFIG_PM
1861 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1862 {
1863 const char *emsg = NULL;
1864 int rc;
1865
1866 rc = ahci_deinit_port(ap, &emsg);
1867 if (rc == 0)
1868 ahci_power_down(ap);
1869 else {
1870 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1871 ahci_start_port(ap);
1872 }
1873
1874 return rc;
1875 }
1876
1877 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1878 {
1879 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1880 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1881 u32 ctl;
1882
1883 if (mesg.event & PM_EVENT_SLEEP) {
1884 /* AHCI spec rev1.1 section 8.3.3:
1885 * Software must disable interrupts prior to requesting a
1886 * transition of the HBA to D3 state.
1887 */
1888 ctl = readl(mmio + HOST_CTL);
1889 ctl &= ~HOST_IRQ_EN;
1890 writel(ctl, mmio + HOST_CTL);
1891 readl(mmio + HOST_CTL); /* flush */
1892 }
1893
1894 return ata_pci_device_suspend(pdev, mesg);
1895 }
1896
1897 static int ahci_pci_device_resume(struct pci_dev *pdev)
1898 {
1899 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1900 int rc;
1901
1902 rc = ata_pci_device_do_resume(pdev);
1903 if (rc)
1904 return rc;
1905
1906 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1907 rc = ahci_reset_controller(host);
1908 if (rc)
1909 return rc;
1910
1911 ahci_init_controller(host);
1912 }
1913
1914 ata_host_resume(host);
1915
1916 return 0;
1917 }
1918 #endif
1919
1920 static int ahci_port_start(struct ata_port *ap)
1921 {
1922 struct device *dev = ap->host->dev;
1923 struct ahci_port_priv *pp;
1924 void *mem;
1925 dma_addr_t mem_dma;
1926
1927 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1928 if (!pp)
1929 return -ENOMEM;
1930
1931 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1932 GFP_KERNEL);
1933 if (!mem)
1934 return -ENOMEM;
1935 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1936
1937 /*
1938 * First item in chunk of DMA memory: 32-slot command table,
1939 * 32 bytes each in size
1940 */
1941 pp->cmd_slot = mem;
1942 pp->cmd_slot_dma = mem_dma;
1943
1944 mem += AHCI_CMD_SLOT_SZ;
1945 mem_dma += AHCI_CMD_SLOT_SZ;
1946
1947 /*
1948 * Second item: Received-FIS area
1949 */
1950 pp->rx_fis = mem;
1951 pp->rx_fis_dma = mem_dma;
1952
1953 mem += AHCI_RX_FIS_SZ;
1954 mem_dma += AHCI_RX_FIS_SZ;
1955
1956 /*
1957 * Third item: data area for storing a single command
1958 * and its scatter-gather table
1959 */
1960 pp->cmd_tbl = mem;
1961 pp->cmd_tbl_dma = mem_dma;
1962
1963 /*
1964 * Save off initial list of interrupts to be enabled.
1965 * This could be changed later
1966 */
1967 pp->intr_mask = DEF_PORT_IRQ;
1968
1969 ap->private_data = pp;
1970
1971 /* engage engines, captain */
1972 return ahci_port_resume(ap);
1973 }
1974
1975 static void ahci_port_stop(struct ata_port *ap)
1976 {
1977 const char *emsg = NULL;
1978 int rc;
1979
1980 /* de-initialize port */
1981 rc = ahci_deinit_port(ap, &emsg);
1982 if (rc)
1983 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1984 }
1985
1986 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1987 {
1988 int rc;
1989
1990 if (using_dac &&
1991 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1992 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1993 if (rc) {
1994 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1995 if (rc) {
1996 dev_printk(KERN_ERR, &pdev->dev,
1997 "64-bit DMA enable failed\n");
1998 return rc;
1999 }
2000 }
2001 } else {
2002 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2003 if (rc) {
2004 dev_printk(KERN_ERR, &pdev->dev,
2005 "32-bit DMA enable failed\n");
2006 return rc;
2007 }
2008 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2009 if (rc) {
2010 dev_printk(KERN_ERR, &pdev->dev,
2011 "32-bit consistent DMA enable failed\n");
2012 return rc;
2013 }
2014 }
2015 return 0;
2016 }
2017
2018 static void ahci_print_info(struct ata_host *host)
2019 {
2020 struct ahci_host_priv *hpriv = host->private_data;
2021 struct pci_dev *pdev = to_pci_dev(host->dev);
2022 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2023 u32 vers, cap, impl, speed;
2024 const char *speed_s;
2025 u16 cc;
2026 const char *scc_s;
2027
2028 vers = readl(mmio + HOST_VERSION);
2029 cap = hpriv->cap;
2030 impl = hpriv->port_map;
2031
2032 speed = (cap >> 20) & 0xf;
2033 if (speed == 1)
2034 speed_s = "1.5";
2035 else if (speed == 2)
2036 speed_s = "3";
2037 else
2038 speed_s = "?";
2039
2040 pci_read_config_word(pdev, 0x0a, &cc);
2041 if (cc == PCI_CLASS_STORAGE_IDE)
2042 scc_s = "IDE";
2043 else if (cc == PCI_CLASS_STORAGE_SATA)
2044 scc_s = "SATA";
2045 else if (cc == PCI_CLASS_STORAGE_RAID)
2046 scc_s = "RAID";
2047 else
2048 scc_s = "unknown";
2049
2050 dev_printk(KERN_INFO, &pdev->dev,
2051 "AHCI %02x%02x.%02x%02x "
2052 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2053 ,
2054
2055 (vers >> 24) & 0xff,
2056 (vers >> 16) & 0xff,
2057 (vers >> 8) & 0xff,
2058 vers & 0xff,
2059
2060 ((cap >> 8) & 0x1f) + 1,
2061 (cap & 0x1f) + 1,
2062 speed_s,
2063 impl,
2064 scc_s);
2065
2066 dev_printk(KERN_INFO, &pdev->dev,
2067 "flags: "
2068 "%s%s%s%s%s%s%s"
2069 "%s%s%s%s%s%s%s\n"
2070 ,
2071
2072 cap & (1 << 31) ? "64bit " : "",
2073 cap & (1 << 30) ? "ncq " : "",
2074 cap & (1 << 29) ? "sntf " : "",
2075 cap & (1 << 28) ? "ilck " : "",
2076 cap & (1 << 27) ? "stag " : "",
2077 cap & (1 << 26) ? "pm " : "",
2078 cap & (1 << 25) ? "led " : "",
2079
2080 cap & (1 << 24) ? "clo " : "",
2081 cap & (1 << 19) ? "nz " : "",
2082 cap & (1 << 18) ? "only " : "",
2083 cap & (1 << 17) ? "pmp " : "",
2084 cap & (1 << 15) ? "pio " : "",
2085 cap & (1 << 14) ? "slum " : "",
2086 cap & (1 << 13) ? "part " : ""
2087 );
2088 }
2089
2090 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2091 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2092 * support PMP and the 4726 either directly exports the device
2093 * attached to the first downstream port or acts as a hardware storage
2094 * controller and emulate a single ATA device (can be RAID 0/1 or some
2095 * other configuration).
2096 *
2097 * When there's no device attached to the first downstream port of the
2098 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2099 * configure the 4726. However, ATA emulation of the device is very
2100 * lame. It doesn't send signature D2H Reg FIS after the initial
2101 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2102 *
2103 * The following function works around the problem by always using
2104 * hardreset on the port and not depending on receiving signature FIS
2105 * afterward. If signature FIS isn't received soon, ATA class is
2106 * assumed without follow-up softreset.
2107 */
2108 static void ahci_p5wdh_workaround(struct ata_host *host)
2109 {
2110 static struct dmi_system_id sysids[] = {
2111 {
2112 .ident = "P5W DH Deluxe",
2113 .matches = {
2114 DMI_MATCH(DMI_SYS_VENDOR,
2115 "ASUSTEK COMPUTER INC"),
2116 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2117 },
2118 },
2119 { }
2120 };
2121 struct pci_dev *pdev = to_pci_dev(host->dev);
2122
2123 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2124 dmi_check_system(sysids)) {
2125 struct ata_port *ap = host->ports[1];
2126
2127 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2128 "Deluxe on-board SIMG4726 workaround\n");
2129
2130 ap->ops = &ahci_p5wdh_ops;
2131 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2132 }
2133 }
2134
2135 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2136 {
2137 static int printed_version;
2138 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2139 const struct ata_port_info *ppi[] = { &pi, NULL };
2140 struct device *dev = &pdev->dev;
2141 struct ahci_host_priv *hpriv;
2142 struct ata_host *host;
2143 int n_ports, i, rc;
2144
2145 VPRINTK("ENTER\n");
2146
2147 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2148
2149 if (!printed_version++)
2150 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2151
2152 /* acquire resources */
2153 rc = pcim_enable_device(pdev);
2154 if (rc)
2155 return rc;
2156
2157 /* AHCI controllers often implement SFF compatible interface.
2158 * Grab all PCI BARs just in case.
2159 */
2160 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2161 if (rc == -EBUSY)
2162 pcim_pin_device(pdev);
2163 if (rc)
2164 return rc;
2165
2166 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2167 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2168 u8 map;
2169
2170 /* ICH6s share the same PCI ID for both piix and ahci
2171 * modes. Enabling ahci mode while MAP indicates
2172 * combined mode is a bad idea. Yield to ata_piix.
2173 */
2174 pci_read_config_byte(pdev, ICH_MAP, &map);
2175 if (map & 0x3) {
2176 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2177 "combined mode, can't enable AHCI mode\n");
2178 return -ENODEV;
2179 }
2180 }
2181
2182 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2183 if (!hpriv)
2184 return -ENOMEM;
2185 hpriv->flags |= (unsigned long)pi.private_data;
2186
2187 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2188 pci_intx(pdev, 1);
2189
2190 /* save initial config */
2191 ahci_save_initial_config(pdev, hpriv);
2192
2193 /* prepare host */
2194 if (hpriv->cap & HOST_CAP_NCQ)
2195 pi.flags |= ATA_FLAG_NCQ;
2196
2197 if (hpriv->cap & HOST_CAP_PMP)
2198 pi.flags |= ATA_FLAG_PMP;
2199
2200 /* CAP.NP sometimes indicate the index of the last enabled
2201 * port, at other times, that of the last possible port, so
2202 * determining the maximum port number requires looking at
2203 * both CAP.NP and port_map.
2204 */
2205 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2206
2207 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2208 if (!host)
2209 return -ENOMEM;
2210 host->iomap = pcim_iomap_table(pdev);
2211 host->private_data = hpriv;
2212
2213 for (i = 0; i < host->n_ports; i++) {
2214 struct ata_port *ap = host->ports[i];
2215 void __iomem *port_mmio = ahci_port_base(ap);
2216
2217 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2218 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2219 0x100 + ap->port_no * 0x80, "port");
2220
2221 /* set initial link pm policy */
2222 ap->pm_policy = NOT_AVAILABLE;
2223
2224 /* standard SATA port setup */
2225 if (hpriv->port_map & (1 << i))
2226 ap->ioaddr.cmd_addr = port_mmio;
2227
2228 /* disabled/not-implemented port */
2229 else
2230 ap->ops = &ata_dummy_port_ops;
2231 }
2232
2233 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2234 ahci_p5wdh_workaround(host);
2235
2236 /* initialize adapter */
2237 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2238 if (rc)
2239 return rc;
2240
2241 rc = ahci_reset_controller(host);
2242 if (rc)
2243 return rc;
2244
2245 ahci_init_controller(host);
2246 ahci_print_info(host);
2247
2248 pci_set_master(pdev);
2249 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2250 &ahci_sht);
2251 }
2252
2253 static int __init ahci_init(void)
2254 {
2255 return pci_register_driver(&ahci_pci_driver);
2256 }
2257
2258 static void __exit ahci_exit(void)
2259 {
2260 pci_unregister_driver(&ahci_pci_driver);
2261 }
2262
2263
2264 MODULE_AUTHOR("Jeff Garzik");
2265 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2266 MODULE_LICENSE("GPL");
2267 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2268 MODULE_VERSION(DRV_VERSION);
2269
2270 module_init(ahci_init);
2271 module_exit(ahci_exit);
Ubuntu Eoan Linux kernel mirror