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ahci: work around ATI SB600 h/w quirk
[mirror_ubuntu-artful-kernel.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_enable_alpm(struct ata_port *ap,
53 enum link_pm policy);
54 static void ahci_disable_alpm(struct ata_port *ap);
55
56 enum {
57 AHCI_PCI_BAR = 5,
58 AHCI_MAX_PORTS = 32,
59 AHCI_MAX_SG = 168, /* hardware max is 64K */
60 AHCI_DMA_BOUNDARY = 0xffffffff,
61 AHCI_USE_CLUSTERING = 1,
62 AHCI_MAX_CMDS = 32,
63 AHCI_CMD_SZ = 32,
64 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
65 AHCI_RX_FIS_SZ = 256,
66 AHCI_CMD_TBL_CDB = 0x40,
67 AHCI_CMD_TBL_HDR_SZ = 0x80,
68 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
69 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
70 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
71 AHCI_RX_FIS_SZ,
72 AHCI_IRQ_ON_SG = (1 << 31),
73 AHCI_CMD_ATAPI = (1 << 5),
74 AHCI_CMD_WRITE = (1 << 6),
75 AHCI_CMD_PREFETCH = (1 << 7),
76 AHCI_CMD_RESET = (1 << 8),
77 AHCI_CMD_CLR_BUSY = (1 << 10),
78
79 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
80 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
81 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
82
83 board_ahci = 0,
84 board_ahci_vt8251 = 1,
85 board_ahci_ign_iferr = 2,
86 board_ahci_sb600 = 3,
87 board_ahci_mv = 4,
88 board_ahci_sb700 = 5,
89
90 /* global controller registers */
91 HOST_CAP = 0x00, /* host capabilities */
92 HOST_CTL = 0x04, /* global host control */
93 HOST_IRQ_STAT = 0x08, /* interrupt status */
94 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
95 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
96
97 /* HOST_CTL bits */
98 HOST_RESET = (1 << 0), /* reset controller; self-clear */
99 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
100 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
101
102 /* HOST_CAP bits */
103 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
104 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
105 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
106 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
107 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
108 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
109 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
110 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
111
112 /* registers for each SATA port */
113 PORT_LST_ADDR = 0x00, /* command list DMA addr */
114 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
115 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
116 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
117 PORT_IRQ_STAT = 0x10, /* interrupt status */
118 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
119 PORT_CMD = 0x18, /* port command */
120 PORT_TFDATA = 0x20, /* taskfile data */
121 PORT_SIG = 0x24, /* device TF signature */
122 PORT_CMD_ISSUE = 0x38, /* command issue */
123 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
124 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
125 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
126 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
127 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
128
129 /* PORT_IRQ_{STAT,MASK} bits */
130 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
131 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
132 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
133 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
134 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
135 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
136 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
137 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
138
139 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
140 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
141 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
142 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
143 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
144 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
145 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
146 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
147 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
148
149 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
150 PORT_IRQ_IF_ERR |
151 PORT_IRQ_CONNECT |
152 PORT_IRQ_PHYRDY |
153 PORT_IRQ_UNK_FIS |
154 PORT_IRQ_BAD_PMP,
155 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
156 PORT_IRQ_TF_ERR |
157 PORT_IRQ_HBUS_DATA_ERR,
158 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
159 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
160 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
161
162 /* PORT_CMD bits */
163 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
164 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
165 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
166 PORT_CMD_PMP = (1 << 17), /* PMP attached */
167 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
168 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
169 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
170 PORT_CMD_CLO = (1 << 3), /* Command list override */
171 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
172 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
173 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
174
175 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
176 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
177 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
178 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
179
180 /* hpriv->flags bits */
181 AHCI_HFLAG_NO_NCQ = (1 << 0),
182 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
183 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
184 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
185 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
186 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
187 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
188 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
189 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
190
191 /* ap->flags bits */
192
193 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
194 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
195 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
196 ATA_FLAG_IPM,
197 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
198
199 ICH_MAP = 0x90, /* ICH MAP register */
200 };
201
202 struct ahci_cmd_hdr {
203 __le32 opts;
204 __le32 status;
205 __le32 tbl_addr;
206 __le32 tbl_addr_hi;
207 __le32 reserved[4];
208 };
209
210 struct ahci_sg {
211 __le32 addr;
212 __le32 addr_hi;
213 __le32 reserved;
214 __le32 flags_size;
215 };
216
217 struct ahci_host_priv {
218 unsigned int flags; /* AHCI_HFLAG_* */
219 u32 cap; /* cap to use */
220 u32 port_map; /* port map to use */
221 u32 saved_cap; /* saved initial cap */
222 u32 saved_port_map; /* saved initial port_map */
223 };
224
225 struct ahci_port_priv {
226 struct ata_link *active_link;
227 struct ahci_cmd_hdr *cmd_slot;
228 dma_addr_t cmd_slot_dma;
229 void *cmd_tbl;
230 dma_addr_t cmd_tbl_dma;
231 void *rx_fis;
232 dma_addr_t rx_fis_dma;
233 /* for NCQ spurious interrupt analysis */
234 unsigned int ncq_saw_d2h:1;
235 unsigned int ncq_saw_dmas:1;
236 unsigned int ncq_saw_sdb:1;
237 u32 intr_mask; /* interrupts to enable */
238 };
239
240 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
241 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
242 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
243 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
244 static void ahci_irq_clear(struct ata_port *ap);
245 static int ahci_port_start(struct ata_port *ap);
246 static void ahci_port_stop(struct ata_port *ap);
247 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
248 static void ahci_qc_prep(struct ata_queued_cmd *qc);
249 static u8 ahci_check_status(struct ata_port *ap);
250 static void ahci_freeze(struct ata_port *ap);
251 static void ahci_thaw(struct ata_port *ap);
252 static void ahci_pmp_attach(struct ata_port *ap);
253 static void ahci_pmp_detach(struct ata_port *ap);
254 static void ahci_error_handler(struct ata_port *ap);
255 static void ahci_vt8251_error_handler(struct ata_port *ap);
256 static void ahci_p5wdh_error_handler(struct ata_port *ap);
257 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
258 static int ahci_port_resume(struct ata_port *ap);
259 static void ahci_dev_config(struct ata_device *dev);
260 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
261 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
262 u32 opts);
263 #ifdef CONFIG_PM
264 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
265 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
266 static int ahci_pci_device_resume(struct pci_dev *pdev);
267 #endif
268
269 static struct class_device_attribute *ahci_shost_attrs[] = {
270 &class_device_attr_link_power_management_policy,
271 NULL
272 };
273
274 static struct scsi_host_template ahci_sht = {
275 .module = THIS_MODULE,
276 .name = DRV_NAME,
277 .ioctl = ata_scsi_ioctl,
278 .queuecommand = ata_scsi_queuecmd,
279 .change_queue_depth = ata_scsi_change_queue_depth,
280 .can_queue = AHCI_MAX_CMDS - 1,
281 .this_id = ATA_SHT_THIS_ID,
282 .sg_tablesize = AHCI_MAX_SG,
283 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
284 .emulated = ATA_SHT_EMULATED,
285 .use_clustering = AHCI_USE_CLUSTERING,
286 .proc_name = DRV_NAME,
287 .dma_boundary = AHCI_DMA_BOUNDARY,
288 .slave_configure = ata_scsi_slave_config,
289 .slave_destroy = ata_scsi_slave_destroy,
290 .bios_param = ata_std_bios_param,
291 .shost_attrs = ahci_shost_attrs,
292 };
293
294 static const struct ata_port_operations ahci_ops = {
295 .check_status = ahci_check_status,
296 .check_altstatus = ahci_check_status,
297 .dev_select = ata_noop_dev_select,
298
299 .dev_config = ahci_dev_config,
300
301 .tf_read = ahci_tf_read,
302
303 .qc_defer = sata_pmp_qc_defer_cmd_switch,
304 .qc_prep = ahci_qc_prep,
305 .qc_issue = ahci_qc_issue,
306
307 .irq_clear = ahci_irq_clear,
308
309 .scr_read = ahci_scr_read,
310 .scr_write = ahci_scr_write,
311
312 .freeze = ahci_freeze,
313 .thaw = ahci_thaw,
314
315 .error_handler = ahci_error_handler,
316 .post_internal_cmd = ahci_post_internal_cmd,
317
318 .pmp_attach = ahci_pmp_attach,
319 .pmp_detach = ahci_pmp_detach,
320
321 #ifdef CONFIG_PM
322 .port_suspend = ahci_port_suspend,
323 .port_resume = ahci_port_resume,
324 #endif
325 .enable_pm = ahci_enable_alpm,
326 .disable_pm = ahci_disable_alpm,
327
328 .port_start = ahci_port_start,
329 .port_stop = ahci_port_stop,
330 };
331
332 static const struct ata_port_operations ahci_vt8251_ops = {
333 .check_status = ahci_check_status,
334 .check_altstatus = ahci_check_status,
335 .dev_select = ata_noop_dev_select,
336
337 .tf_read = ahci_tf_read,
338
339 .qc_defer = sata_pmp_qc_defer_cmd_switch,
340 .qc_prep = ahci_qc_prep,
341 .qc_issue = ahci_qc_issue,
342
343 .irq_clear = ahci_irq_clear,
344
345 .scr_read = ahci_scr_read,
346 .scr_write = ahci_scr_write,
347
348 .freeze = ahci_freeze,
349 .thaw = ahci_thaw,
350
351 .error_handler = ahci_vt8251_error_handler,
352 .post_internal_cmd = ahci_post_internal_cmd,
353
354 .pmp_attach = ahci_pmp_attach,
355 .pmp_detach = ahci_pmp_detach,
356
357 #ifdef CONFIG_PM
358 .port_suspend = ahci_port_suspend,
359 .port_resume = ahci_port_resume,
360 #endif
361
362 .port_start = ahci_port_start,
363 .port_stop = ahci_port_stop,
364 };
365
366 static const struct ata_port_operations ahci_p5wdh_ops = {
367 .check_status = ahci_check_status,
368 .check_altstatus = ahci_check_status,
369 .dev_select = ata_noop_dev_select,
370
371 .tf_read = ahci_tf_read,
372
373 .qc_defer = sata_pmp_qc_defer_cmd_switch,
374 .qc_prep = ahci_qc_prep,
375 .qc_issue = ahci_qc_issue,
376
377 .irq_clear = ahci_irq_clear,
378
379 .scr_read = ahci_scr_read,
380 .scr_write = ahci_scr_write,
381
382 .freeze = ahci_freeze,
383 .thaw = ahci_thaw,
384
385 .error_handler = ahci_p5wdh_error_handler,
386 .post_internal_cmd = ahci_post_internal_cmd,
387
388 .pmp_attach = ahci_pmp_attach,
389 .pmp_detach = ahci_pmp_detach,
390
391 #ifdef CONFIG_PM
392 .port_suspend = ahci_port_suspend,
393 .port_resume = ahci_port_resume,
394 #endif
395
396 .port_start = ahci_port_start,
397 .port_stop = ahci_port_stop,
398 };
399
400 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
401
402 static const struct ata_port_info ahci_port_info[] = {
403 /* board_ahci */
404 {
405 .flags = AHCI_FLAG_COMMON,
406 .link_flags = AHCI_LFLAG_COMMON,
407 .pio_mask = 0x1f, /* pio0-4 */
408 .udma_mask = ATA_UDMA6,
409 .port_ops = &ahci_ops,
410 },
411 /* board_ahci_vt8251 */
412 {
413 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
414 .flags = AHCI_FLAG_COMMON,
415 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
416 .pio_mask = 0x1f, /* pio0-4 */
417 .udma_mask = ATA_UDMA6,
418 .port_ops = &ahci_vt8251_ops,
419 },
420 /* board_ahci_ign_iferr */
421 {
422 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
423 .flags = AHCI_FLAG_COMMON,
424 .link_flags = AHCI_LFLAG_COMMON,
425 .pio_mask = 0x1f, /* pio0-4 */
426 .udma_mask = ATA_UDMA6,
427 .port_ops = &ahci_ops,
428 },
429 /* board_ahci_sb600 */
430 {
431 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
432 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
433 .flags = AHCI_FLAG_COMMON,
434 .link_flags = AHCI_LFLAG_COMMON,
435 .pio_mask = 0x1f, /* pio0-4 */
436 .udma_mask = ATA_UDMA6,
437 .port_ops = &ahci_ops,
438 },
439 /* board_ahci_mv */
440 {
441 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
442 AHCI_HFLAG_MV_PATA),
443 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
444 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
445 .link_flags = AHCI_LFLAG_COMMON,
446 .pio_mask = 0x1f, /* pio0-4 */
447 .udma_mask = ATA_UDMA6,
448 .port_ops = &ahci_ops,
449 },
450 /* board_ahci_sb700 */
451 {
452 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
453 AHCI_HFLAG_NO_PMP),
454 .flags = AHCI_FLAG_COMMON,
455 .link_flags = AHCI_LFLAG_COMMON,
456 .pio_mask = 0x1f, /* pio0-4 */
457 .udma_mask = ATA_UDMA6,
458 .port_ops = &ahci_ops,
459 },
460 };
461
462 static const struct pci_device_id ahci_pci_tbl[] = {
463 /* Intel */
464 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
465 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
466 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
467 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
468 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
469 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
470 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
471 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
472 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
473 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
474 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
475 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
476 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
477 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
478 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
479 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
480 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
481 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
482 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
483 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
484 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
485 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
486 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
487 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
488 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
489 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
490 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
491 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
492 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
493 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
494 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
495
496 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
497 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
498 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
499
500 /* ATI */
501 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
502 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
503 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
504 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
505 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
506 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
507 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
508
509 /* VIA */
510 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
511 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
512
513 /* NVIDIA */
514 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
516 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
517 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
518 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
519 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
520 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
521 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
522 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
526 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
530 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
531 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
532 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
533 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
534 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
543 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
544 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
545 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
554 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
555 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
556 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
557 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
558 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
562 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
566 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
567 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
568 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
569 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
570
571 /* SiS */
572 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
573 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
574 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
575
576 /* Marvell */
577 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
578
579 /* Generic, PCI class code for AHCI */
580 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
581 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
582
583 { } /* terminate list */
584 };
585
586
587 static struct pci_driver ahci_pci_driver = {
588 .name = DRV_NAME,
589 .id_table = ahci_pci_tbl,
590 .probe = ahci_init_one,
591 .remove = ata_pci_remove_one,
592 #ifdef CONFIG_PM
593 .suspend = ahci_pci_device_suspend,
594 .resume = ahci_pci_device_resume,
595 #endif
596 };
597
598
599 static inline int ahci_nr_ports(u32 cap)
600 {
601 return (cap & 0x1f) + 1;
602 }
603
604 static inline void __iomem *__ahci_port_base(struct ata_host *host,
605 unsigned int port_no)
606 {
607 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
608
609 return mmio + 0x100 + (port_no * 0x80);
610 }
611
612 static inline void __iomem *ahci_port_base(struct ata_port *ap)
613 {
614 return __ahci_port_base(ap->host, ap->port_no);
615 }
616
617 static void ahci_enable_ahci(void __iomem *mmio)
618 {
619 u32 tmp;
620
621 /* turn on AHCI_EN */
622 tmp = readl(mmio + HOST_CTL);
623 if (!(tmp & HOST_AHCI_EN)) {
624 tmp |= HOST_AHCI_EN;
625 writel(tmp, mmio + HOST_CTL);
626 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
627 WARN_ON(!(tmp & HOST_AHCI_EN));
628 }
629 }
630
631 /**
632 * ahci_save_initial_config - Save and fixup initial config values
633 * @pdev: target PCI device
634 * @hpriv: host private area to store config values
635 *
636 * Some registers containing configuration info might be setup by
637 * BIOS and might be cleared on reset. This function saves the
638 * initial values of those registers into @hpriv such that they
639 * can be restored after controller reset.
640 *
641 * If inconsistent, config values are fixed up by this function.
642 *
643 * LOCKING:
644 * None.
645 */
646 static void ahci_save_initial_config(struct pci_dev *pdev,
647 struct ahci_host_priv *hpriv)
648 {
649 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
650 u32 cap, port_map;
651 int i;
652
653 /* make sure AHCI mode is enabled before accessing CAP */
654 ahci_enable_ahci(mmio);
655
656 /* Values prefixed with saved_ are written back to host after
657 * reset. Values without are used for driver operation.
658 */
659 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
660 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
661
662 /* some chips have errata preventing 64bit use */
663 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
664 dev_printk(KERN_INFO, &pdev->dev,
665 "controller can't do 64bit DMA, forcing 32bit\n");
666 cap &= ~HOST_CAP_64;
667 }
668
669 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
670 dev_printk(KERN_INFO, &pdev->dev,
671 "controller can't do NCQ, turning off CAP_NCQ\n");
672 cap &= ~HOST_CAP_NCQ;
673 }
674
675 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
676 dev_printk(KERN_INFO, &pdev->dev,
677 "controller can't do PMP, turning off CAP_PMP\n");
678 cap &= ~HOST_CAP_PMP;
679 }
680
681 /*
682 * Temporary Marvell 6145 hack: PATA port presence
683 * is asserted through the standard AHCI port
684 * presence register, as bit 4 (counting from 0)
685 */
686 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
687 dev_printk(KERN_ERR, &pdev->dev,
688 "MV_AHCI HACK: port_map %x -> %x\n",
689 hpriv->port_map,
690 hpriv->port_map & 0xf);
691
692 port_map &= 0xf;
693 }
694
695 /* cross check port_map and cap.n_ports */
696 if (port_map) {
697 int map_ports = 0;
698
699 for (i = 0; i < AHCI_MAX_PORTS; i++)
700 if (port_map & (1 << i))
701 map_ports++;
702
703 /* If PI has more ports than n_ports, whine, clear
704 * port_map and let it be generated from n_ports.
705 */
706 if (map_ports > ahci_nr_ports(cap)) {
707 dev_printk(KERN_WARNING, &pdev->dev,
708 "implemented port map (0x%x) contains more "
709 "ports than nr_ports (%u), using nr_ports\n",
710 port_map, ahci_nr_ports(cap));
711 port_map = 0;
712 }
713 }
714
715 /* fabricate port_map from cap.nr_ports */
716 if (!port_map) {
717 port_map = (1 << ahci_nr_ports(cap)) - 1;
718 dev_printk(KERN_WARNING, &pdev->dev,
719 "forcing PORTS_IMPL to 0x%x\n", port_map);
720
721 /* write the fixed up value to the PI register */
722 hpriv->saved_port_map = port_map;
723 }
724
725 /* record values to use during operation */
726 hpriv->cap = cap;
727 hpriv->port_map = port_map;
728 }
729
730 /**
731 * ahci_restore_initial_config - Restore initial config
732 * @host: target ATA host
733 *
734 * Restore initial config stored by ahci_save_initial_config().
735 *
736 * LOCKING:
737 * None.
738 */
739 static void ahci_restore_initial_config(struct ata_host *host)
740 {
741 struct ahci_host_priv *hpriv = host->private_data;
742 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
743
744 writel(hpriv->saved_cap, mmio + HOST_CAP);
745 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
746 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
747 }
748
749 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
750 {
751 static const int offset[] = {
752 [SCR_STATUS] = PORT_SCR_STAT,
753 [SCR_CONTROL] = PORT_SCR_CTL,
754 [SCR_ERROR] = PORT_SCR_ERR,
755 [SCR_ACTIVE] = PORT_SCR_ACT,
756 [SCR_NOTIFICATION] = PORT_SCR_NTF,
757 };
758 struct ahci_host_priv *hpriv = ap->host->private_data;
759
760 if (sc_reg < ARRAY_SIZE(offset) &&
761 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
762 return offset[sc_reg];
763 return 0;
764 }
765
766 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
767 {
768 void __iomem *port_mmio = ahci_port_base(ap);
769 int offset = ahci_scr_offset(ap, sc_reg);
770
771 if (offset) {
772 *val = readl(port_mmio + offset);
773 return 0;
774 }
775 return -EINVAL;
776 }
777
778 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
779 {
780 void __iomem *port_mmio = ahci_port_base(ap);
781 int offset = ahci_scr_offset(ap, sc_reg);
782
783 if (offset) {
784 writel(val, port_mmio + offset);
785 return 0;
786 }
787 return -EINVAL;
788 }
789
790 static void ahci_start_engine(struct ata_port *ap)
791 {
792 void __iomem *port_mmio = ahci_port_base(ap);
793 u32 tmp;
794
795 /* start DMA */
796 tmp = readl(port_mmio + PORT_CMD);
797 tmp |= PORT_CMD_START;
798 writel(tmp, port_mmio + PORT_CMD);
799 readl(port_mmio + PORT_CMD); /* flush */
800 }
801
802 static int ahci_stop_engine(struct ata_port *ap)
803 {
804 void __iomem *port_mmio = ahci_port_base(ap);
805 u32 tmp;
806
807 tmp = readl(port_mmio + PORT_CMD);
808
809 /* check if the HBA is idle */
810 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
811 return 0;
812
813 /* setting HBA to idle */
814 tmp &= ~PORT_CMD_START;
815 writel(tmp, port_mmio + PORT_CMD);
816
817 /* wait for engine to stop. This could be as long as 500 msec */
818 tmp = ata_wait_register(port_mmio + PORT_CMD,
819 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
820 if (tmp & PORT_CMD_LIST_ON)
821 return -EIO;
822
823 return 0;
824 }
825
826 static void ahci_start_fis_rx(struct ata_port *ap)
827 {
828 void __iomem *port_mmio = ahci_port_base(ap);
829 struct ahci_host_priv *hpriv = ap->host->private_data;
830 struct ahci_port_priv *pp = ap->private_data;
831 u32 tmp;
832
833 /* set FIS registers */
834 if (hpriv->cap & HOST_CAP_64)
835 writel((pp->cmd_slot_dma >> 16) >> 16,
836 port_mmio + PORT_LST_ADDR_HI);
837 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
838
839 if (hpriv->cap & HOST_CAP_64)
840 writel((pp->rx_fis_dma >> 16) >> 16,
841 port_mmio + PORT_FIS_ADDR_HI);
842 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
843
844 /* enable FIS reception */
845 tmp = readl(port_mmio + PORT_CMD);
846 tmp |= PORT_CMD_FIS_RX;
847 writel(tmp, port_mmio + PORT_CMD);
848
849 /* flush */
850 readl(port_mmio + PORT_CMD);
851 }
852
853 static int ahci_stop_fis_rx(struct ata_port *ap)
854 {
855 void __iomem *port_mmio = ahci_port_base(ap);
856 u32 tmp;
857
858 /* disable FIS reception */
859 tmp = readl(port_mmio + PORT_CMD);
860 tmp &= ~PORT_CMD_FIS_RX;
861 writel(tmp, port_mmio + PORT_CMD);
862
863 /* wait for completion, spec says 500ms, give it 1000 */
864 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
865 PORT_CMD_FIS_ON, 10, 1000);
866 if (tmp & PORT_CMD_FIS_ON)
867 return -EBUSY;
868
869 return 0;
870 }
871
872 static void ahci_power_up(struct ata_port *ap)
873 {
874 struct ahci_host_priv *hpriv = ap->host->private_data;
875 void __iomem *port_mmio = ahci_port_base(ap);
876 u32 cmd;
877
878 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
879
880 /* spin up device */
881 if (hpriv->cap & HOST_CAP_SSS) {
882 cmd |= PORT_CMD_SPIN_UP;
883 writel(cmd, port_mmio + PORT_CMD);
884 }
885
886 /* wake up link */
887 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
888 }
889
890 static void ahci_disable_alpm(struct ata_port *ap)
891 {
892 struct ahci_host_priv *hpriv = ap->host->private_data;
893 void __iomem *port_mmio = ahci_port_base(ap);
894 u32 cmd;
895 struct ahci_port_priv *pp = ap->private_data;
896
897 /* IPM bits should be disabled by libata-core */
898 /* get the existing command bits */
899 cmd = readl(port_mmio + PORT_CMD);
900
901 /* disable ALPM and ASP */
902 cmd &= ~PORT_CMD_ASP;
903 cmd &= ~PORT_CMD_ALPE;
904
905 /* force the interface back to active */
906 cmd |= PORT_CMD_ICC_ACTIVE;
907
908 /* write out new cmd value */
909 writel(cmd, port_mmio + PORT_CMD);
910 cmd = readl(port_mmio + PORT_CMD);
911
912 /* wait 10ms to be sure we've come out of any low power state */
913 msleep(10);
914
915 /* clear out any PhyRdy stuff from interrupt status */
916 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
917
918 /* go ahead and clean out PhyRdy Change from Serror too */
919 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
920
921 /*
922 * Clear flag to indicate that we should ignore all PhyRdy
923 * state changes
924 */
925 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
926
927 /*
928 * Enable interrupts on Phy Ready.
929 */
930 pp->intr_mask |= PORT_IRQ_PHYRDY;
931 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
932
933 /*
934 * don't change the link pm policy - we can be called
935 * just to turn of link pm temporarily
936 */
937 }
938
939 static int ahci_enable_alpm(struct ata_port *ap,
940 enum link_pm policy)
941 {
942 struct ahci_host_priv *hpriv = ap->host->private_data;
943 void __iomem *port_mmio = ahci_port_base(ap);
944 u32 cmd;
945 struct ahci_port_priv *pp = ap->private_data;
946 u32 asp;
947
948 /* Make sure the host is capable of link power management */
949 if (!(hpriv->cap & HOST_CAP_ALPM))
950 return -EINVAL;
951
952 switch (policy) {
953 case MAX_PERFORMANCE:
954 case NOT_AVAILABLE:
955 /*
956 * if we came here with NOT_AVAILABLE,
957 * it just means this is the first time we
958 * have tried to enable - default to max performance,
959 * and let the user go to lower power modes on request.
960 */
961 ahci_disable_alpm(ap);
962 return 0;
963 case MIN_POWER:
964 /* configure HBA to enter SLUMBER */
965 asp = PORT_CMD_ASP;
966 break;
967 case MEDIUM_POWER:
968 /* configure HBA to enter PARTIAL */
969 asp = 0;
970 break;
971 default:
972 return -EINVAL;
973 }
974
975 /*
976 * Disable interrupts on Phy Ready. This keeps us from
977 * getting woken up due to spurious phy ready interrupts
978 * TBD - Hot plug should be done via polling now, is
979 * that even supported?
980 */
981 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
982 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
983
984 /*
985 * Set a flag to indicate that we should ignore all PhyRdy
986 * state changes since these can happen now whenever we
987 * change link state
988 */
989 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
990
991 /* get the existing command bits */
992 cmd = readl(port_mmio + PORT_CMD);
993
994 /*
995 * Set ASP based on Policy
996 */
997 cmd |= asp;
998
999 /*
1000 * Setting this bit will instruct the HBA to aggressively
1001 * enter a lower power link state when it's appropriate and
1002 * based on the value set above for ASP
1003 */
1004 cmd |= PORT_CMD_ALPE;
1005
1006 /* write out new cmd value */
1007 writel(cmd, port_mmio + PORT_CMD);
1008 cmd = readl(port_mmio + PORT_CMD);
1009
1010 /* IPM bits should be set by libata-core */
1011 return 0;
1012 }
1013
1014 #ifdef CONFIG_PM
1015 static void ahci_power_down(struct ata_port *ap)
1016 {
1017 struct ahci_host_priv *hpriv = ap->host->private_data;
1018 void __iomem *port_mmio = ahci_port_base(ap);
1019 u32 cmd, scontrol;
1020
1021 if (!(hpriv->cap & HOST_CAP_SSS))
1022 return;
1023
1024 /* put device into listen mode, first set PxSCTL.DET to 0 */
1025 scontrol = readl(port_mmio + PORT_SCR_CTL);
1026 scontrol &= ~0xf;
1027 writel(scontrol, port_mmio + PORT_SCR_CTL);
1028
1029 /* then set PxCMD.SUD to 0 */
1030 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1031 cmd &= ~PORT_CMD_SPIN_UP;
1032 writel(cmd, port_mmio + PORT_CMD);
1033 }
1034 #endif
1035
1036 static void ahci_start_port(struct ata_port *ap)
1037 {
1038 /* enable FIS reception */
1039 ahci_start_fis_rx(ap);
1040
1041 /* enable DMA */
1042 ahci_start_engine(ap);
1043 }
1044
1045 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1046 {
1047 int rc;
1048
1049 /* disable DMA */
1050 rc = ahci_stop_engine(ap);
1051 if (rc) {
1052 *emsg = "failed to stop engine";
1053 return rc;
1054 }
1055
1056 /* disable FIS reception */
1057 rc = ahci_stop_fis_rx(ap);
1058 if (rc) {
1059 *emsg = "failed stop FIS RX";
1060 return rc;
1061 }
1062
1063 return 0;
1064 }
1065
1066 static int ahci_reset_controller(struct ata_host *host)
1067 {
1068 struct pci_dev *pdev = to_pci_dev(host->dev);
1069 struct ahci_host_priv *hpriv = host->private_data;
1070 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1071 u32 tmp;
1072
1073 /* we must be in AHCI mode, before using anything
1074 * AHCI-specific, such as HOST_RESET.
1075 */
1076 ahci_enable_ahci(mmio);
1077
1078 /* global controller reset */
1079 tmp = readl(mmio + HOST_CTL);
1080 if ((tmp & HOST_RESET) == 0) {
1081 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1082 readl(mmio + HOST_CTL); /* flush */
1083 }
1084
1085 /* reset must complete within 1 second, or
1086 * the hardware should be considered fried.
1087 */
1088 ssleep(1);
1089
1090 tmp = readl(mmio + HOST_CTL);
1091 if (tmp & HOST_RESET) {
1092 dev_printk(KERN_ERR, host->dev,
1093 "controller reset failed (0x%x)\n", tmp);
1094 return -EIO;
1095 }
1096
1097 /* turn on AHCI mode */
1098 ahci_enable_ahci(mmio);
1099
1100 /* some registers might be cleared on reset. restore initial values */
1101 ahci_restore_initial_config(host);
1102
1103 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1104 u16 tmp16;
1105
1106 /* configure PCS */
1107 pci_read_config_word(pdev, 0x92, &tmp16);
1108 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1109 tmp16 |= hpriv->port_map;
1110 pci_write_config_word(pdev, 0x92, tmp16);
1111 }
1112 }
1113
1114 return 0;
1115 }
1116
1117 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1118 int port_no, void __iomem *mmio,
1119 void __iomem *port_mmio)
1120 {
1121 const char *emsg = NULL;
1122 int rc;
1123 u32 tmp;
1124
1125 /* make sure port is not active */
1126 rc = ahci_deinit_port(ap, &emsg);
1127 if (rc)
1128 dev_printk(KERN_WARNING, &pdev->dev,
1129 "%s (%d)\n", emsg, rc);
1130
1131 /* clear SError */
1132 tmp = readl(port_mmio + PORT_SCR_ERR);
1133 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1134 writel(tmp, port_mmio + PORT_SCR_ERR);
1135
1136 /* clear port IRQ */
1137 tmp = readl(port_mmio + PORT_IRQ_STAT);
1138 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1139 if (tmp)
1140 writel(tmp, port_mmio + PORT_IRQ_STAT);
1141
1142 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1143 }
1144
1145 static void ahci_init_controller(struct ata_host *host)
1146 {
1147 struct ahci_host_priv *hpriv = host->private_data;
1148 struct pci_dev *pdev = to_pci_dev(host->dev);
1149 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1150 int i;
1151 void __iomem *port_mmio;
1152 u32 tmp;
1153
1154 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1155 port_mmio = __ahci_port_base(host, 4);
1156
1157 writel(0, port_mmio + PORT_IRQ_MASK);
1158
1159 /* clear port IRQ */
1160 tmp = readl(port_mmio + PORT_IRQ_STAT);
1161 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1162 if (tmp)
1163 writel(tmp, port_mmio + PORT_IRQ_STAT);
1164 }
1165
1166 for (i = 0; i < host->n_ports; i++) {
1167 struct ata_port *ap = host->ports[i];
1168
1169 port_mmio = ahci_port_base(ap);
1170 if (ata_port_is_dummy(ap))
1171 continue;
1172
1173 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1174 }
1175
1176 tmp = readl(mmio + HOST_CTL);
1177 VPRINTK("HOST_CTL 0x%x\n", tmp);
1178 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1179 tmp = readl(mmio + HOST_CTL);
1180 VPRINTK("HOST_CTL 0x%x\n", tmp);
1181 }
1182
1183 static void ahci_dev_config(struct ata_device *dev)
1184 {
1185 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1186
1187 if (hpriv->flags & AHCI_HFLAG_SECT255)
1188 dev->max_sectors = 255;
1189 }
1190
1191 static unsigned int ahci_dev_classify(struct ata_port *ap)
1192 {
1193 void __iomem *port_mmio = ahci_port_base(ap);
1194 struct ata_taskfile tf;
1195 u32 tmp;
1196
1197 tmp = readl(port_mmio + PORT_SIG);
1198 tf.lbah = (tmp >> 24) & 0xff;
1199 tf.lbam = (tmp >> 16) & 0xff;
1200 tf.lbal = (tmp >> 8) & 0xff;
1201 tf.nsect = (tmp) & 0xff;
1202
1203 return ata_dev_classify(&tf);
1204 }
1205
1206 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1207 u32 opts)
1208 {
1209 dma_addr_t cmd_tbl_dma;
1210
1211 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1212
1213 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1214 pp->cmd_slot[tag].status = 0;
1215 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1216 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1217 }
1218
1219 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1220 {
1221 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1222 struct ahci_host_priv *hpriv = ap->host->private_data;
1223 u32 tmp;
1224 int busy, rc;
1225
1226 /* do we need to kick the port? */
1227 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1228 if (!busy && !force_restart)
1229 return 0;
1230
1231 /* stop engine */
1232 rc = ahci_stop_engine(ap);
1233 if (rc)
1234 goto out_restart;
1235
1236 /* need to do CLO? */
1237 if (!busy) {
1238 rc = 0;
1239 goto out_restart;
1240 }
1241
1242 if (!(hpriv->cap & HOST_CAP_CLO)) {
1243 rc = -EOPNOTSUPP;
1244 goto out_restart;
1245 }
1246
1247 /* perform CLO */
1248 tmp = readl(port_mmio + PORT_CMD);
1249 tmp |= PORT_CMD_CLO;
1250 writel(tmp, port_mmio + PORT_CMD);
1251
1252 rc = 0;
1253 tmp = ata_wait_register(port_mmio + PORT_CMD,
1254 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1255 if (tmp & PORT_CMD_CLO)
1256 rc = -EIO;
1257
1258 /* restart engine */
1259 out_restart:
1260 ahci_start_engine(ap);
1261 return rc;
1262 }
1263
1264 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1265 struct ata_taskfile *tf, int is_cmd, u16 flags,
1266 unsigned long timeout_msec)
1267 {
1268 const u32 cmd_fis_len = 5; /* five dwords */
1269 struct ahci_port_priv *pp = ap->private_data;
1270 void __iomem *port_mmio = ahci_port_base(ap);
1271 u8 *fis = pp->cmd_tbl;
1272 u32 tmp;
1273
1274 /* prep the command */
1275 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1276 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1277
1278 /* issue & wait */
1279 writel(1, port_mmio + PORT_CMD_ISSUE);
1280
1281 if (timeout_msec) {
1282 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1283 1, timeout_msec);
1284 if (tmp & 0x1) {
1285 ahci_kick_engine(ap, 1);
1286 return -EBUSY;
1287 }
1288 } else
1289 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1290
1291 return 0;
1292 }
1293
1294 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1295 int pmp, unsigned long deadline)
1296 {
1297 struct ata_port *ap = link->ap;
1298 const char *reason = NULL;
1299 unsigned long now, msecs;
1300 struct ata_taskfile tf;
1301 int rc;
1302
1303 DPRINTK("ENTER\n");
1304
1305 if (ata_link_offline(link)) {
1306 DPRINTK("PHY reports no device\n");
1307 *class = ATA_DEV_NONE;
1308 return 0;
1309 }
1310
1311 /* prepare for SRST (AHCI-1.1 10.4.1) */
1312 rc = ahci_kick_engine(ap, 1);
1313 if (rc && rc != -EOPNOTSUPP)
1314 ata_link_printk(link, KERN_WARNING,
1315 "failed to reset engine (errno=%d)\n", rc);
1316
1317 ata_tf_init(link->device, &tf);
1318
1319 /* issue the first D2H Register FIS */
1320 msecs = 0;
1321 now = jiffies;
1322 if (time_after(now, deadline))
1323 msecs = jiffies_to_msecs(deadline - now);
1324
1325 tf.ctl |= ATA_SRST;
1326 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1327 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1328 rc = -EIO;
1329 reason = "1st FIS failed";
1330 goto fail;
1331 }
1332
1333 /* spec says at least 5us, but be generous and sleep for 1ms */
1334 msleep(1);
1335
1336 /* issue the second D2H Register FIS */
1337 tf.ctl &= ~ATA_SRST;
1338 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1339
1340 /* wait a while before checking status */
1341 ata_wait_after_reset(ap, deadline);
1342
1343 rc = ata_wait_ready(ap, deadline);
1344 /* link occupied, -ENODEV too is an error */
1345 if (rc) {
1346 reason = "device not ready";
1347 goto fail;
1348 }
1349 *class = ahci_dev_classify(ap);
1350
1351 DPRINTK("EXIT, class=%u\n", *class);
1352 return 0;
1353
1354 fail:
1355 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1356 return rc;
1357 }
1358
1359 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1360 unsigned long deadline)
1361 {
1362 int pmp = 0;
1363
1364 if (link->ap->flags & ATA_FLAG_PMP)
1365 pmp = SATA_PMP_CTRL_PORT;
1366
1367 return ahci_do_softreset(link, class, pmp, deadline);
1368 }
1369
1370 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1371 unsigned long deadline)
1372 {
1373 struct ata_port *ap = link->ap;
1374 struct ahci_port_priv *pp = ap->private_data;
1375 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1376 struct ata_taskfile tf;
1377 int rc;
1378
1379 DPRINTK("ENTER\n");
1380
1381 ahci_stop_engine(ap);
1382
1383 /* clear D2H reception area to properly wait for D2H FIS */
1384 ata_tf_init(link->device, &tf);
1385 tf.command = 0x80;
1386 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1387
1388 rc = sata_std_hardreset(link, class, deadline);
1389
1390 ahci_start_engine(ap);
1391
1392 if (rc == 0 && ata_link_online(link))
1393 *class = ahci_dev_classify(ap);
1394 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1395 *class = ATA_DEV_NONE;
1396
1397 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1398 return rc;
1399 }
1400
1401 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1402 unsigned long deadline)
1403 {
1404 struct ata_port *ap = link->ap;
1405 u32 serror;
1406 int rc;
1407
1408 DPRINTK("ENTER\n");
1409
1410 ahci_stop_engine(ap);
1411
1412 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1413 deadline);
1414
1415 /* vt8251 needs SError cleared for the port to operate */
1416 ahci_scr_read(ap, SCR_ERROR, &serror);
1417 ahci_scr_write(ap, SCR_ERROR, serror);
1418
1419 ahci_start_engine(ap);
1420
1421 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1422
1423 /* vt8251 doesn't clear BSY on signature FIS reception,
1424 * request follow-up softreset.
1425 */
1426 return rc ?: -EAGAIN;
1427 }
1428
1429 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1430 unsigned long deadline)
1431 {
1432 struct ata_port *ap = link->ap;
1433 struct ahci_port_priv *pp = ap->private_data;
1434 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1435 struct ata_taskfile tf;
1436 int rc;
1437
1438 ahci_stop_engine(ap);
1439
1440 /* clear D2H reception area to properly wait for D2H FIS */
1441 ata_tf_init(link->device, &tf);
1442 tf.command = 0x80;
1443 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1444
1445 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1446 deadline);
1447
1448 ahci_start_engine(ap);
1449
1450 if (rc || ata_link_offline(link))
1451 return rc;
1452
1453 /* spec mandates ">= 2ms" before checking status */
1454 msleep(150);
1455
1456 /* The pseudo configuration device on SIMG4726 attached to
1457 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1458 * hardreset if no device is attached to the first downstream
1459 * port && the pseudo device locks up on SRST w/ PMP==0. To
1460 * work around this, wait for !BSY only briefly. If BSY isn't
1461 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1462 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1463 *
1464 * Wait for two seconds. Devices attached to downstream port
1465 * which can't process the following IDENTIFY after this will
1466 * have to be reset again. For most cases, this should
1467 * suffice while making probing snappish enough.
1468 */
1469 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1470 if (rc)
1471 ahci_kick_engine(ap, 0);
1472
1473 return 0;
1474 }
1475
1476 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1477 {
1478 struct ata_port *ap = link->ap;
1479 void __iomem *port_mmio = ahci_port_base(ap);
1480 u32 new_tmp, tmp;
1481
1482 ata_std_postreset(link, class);
1483
1484 /* Make sure port's ATAPI bit is set appropriately */
1485 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1486 if (*class == ATA_DEV_ATAPI)
1487 new_tmp |= PORT_CMD_ATAPI;
1488 else
1489 new_tmp &= ~PORT_CMD_ATAPI;
1490 if (new_tmp != tmp) {
1491 writel(new_tmp, port_mmio + PORT_CMD);
1492 readl(port_mmio + PORT_CMD); /* flush */
1493 }
1494 }
1495
1496 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1497 unsigned long deadline)
1498 {
1499 return ahci_do_softreset(link, class, link->pmp, deadline);
1500 }
1501
1502 static u8 ahci_check_status(struct ata_port *ap)
1503 {
1504 void __iomem *mmio = ap->ioaddr.cmd_addr;
1505
1506 return readl(mmio + PORT_TFDATA) & 0xFF;
1507 }
1508
1509 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1510 {
1511 struct ahci_port_priv *pp = ap->private_data;
1512 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1513
1514 ata_tf_from_fis(d2h_fis, tf);
1515 }
1516
1517 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1518 {
1519 struct scatterlist *sg;
1520 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1521 unsigned int si;
1522
1523 VPRINTK("ENTER\n");
1524
1525 /*
1526 * Next, the S/G list.
1527 */
1528 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1529 dma_addr_t addr = sg_dma_address(sg);
1530 u32 sg_len = sg_dma_len(sg);
1531
1532 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1533 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1534 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1535 }
1536
1537 return si;
1538 }
1539
1540 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1541 {
1542 struct ata_port *ap = qc->ap;
1543 struct ahci_port_priv *pp = ap->private_data;
1544 int is_atapi = ata_is_atapi(qc->tf.protocol);
1545 void *cmd_tbl;
1546 u32 opts;
1547 const u32 cmd_fis_len = 5; /* five dwords */
1548 unsigned int n_elem;
1549
1550 /*
1551 * Fill in command table information. First, the header,
1552 * a SATA Register - Host to Device command FIS.
1553 */
1554 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1555
1556 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1557 if (is_atapi) {
1558 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1559 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1560 }
1561
1562 n_elem = 0;
1563 if (qc->flags & ATA_QCFLAG_DMAMAP)
1564 n_elem = ahci_fill_sg(qc, cmd_tbl);
1565
1566 /*
1567 * Fill in command slot information.
1568 */
1569 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1570 if (qc->tf.flags & ATA_TFLAG_WRITE)
1571 opts |= AHCI_CMD_WRITE;
1572 if (is_atapi)
1573 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1574
1575 ahci_fill_cmd_slot(pp, qc->tag, opts);
1576 }
1577
1578 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1579 {
1580 struct ahci_host_priv *hpriv = ap->host->private_data;
1581 struct ahci_port_priv *pp = ap->private_data;
1582 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1583 struct ata_link *link = NULL;
1584 struct ata_queued_cmd *active_qc;
1585 struct ata_eh_info *active_ehi;
1586 u32 serror;
1587
1588 /* determine active link */
1589 ata_port_for_each_link(link, ap)
1590 if (ata_link_active(link))
1591 break;
1592 if (!link)
1593 link = &ap->link;
1594
1595 active_qc = ata_qc_from_tag(ap, link->active_tag);
1596 active_ehi = &link->eh_info;
1597
1598 /* record irq stat */
1599 ata_ehi_clear_desc(host_ehi);
1600 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1601
1602 /* AHCI needs SError cleared; otherwise, it might lock up */
1603 ahci_scr_read(ap, SCR_ERROR, &serror);
1604 ahci_scr_write(ap, SCR_ERROR, serror);
1605 host_ehi->serror |= serror;
1606
1607 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1608 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1609 irq_stat &= ~PORT_IRQ_IF_ERR;
1610
1611 if (irq_stat & PORT_IRQ_TF_ERR) {
1612 /* If qc is active, charge it; otherwise, the active
1613 * link. There's no active qc on NCQ errors. It will
1614 * be determined by EH by reading log page 10h.
1615 */
1616 if (active_qc)
1617 active_qc->err_mask |= AC_ERR_DEV;
1618 else
1619 active_ehi->err_mask |= AC_ERR_DEV;
1620
1621 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1622 host_ehi->serror &= ~SERR_INTERNAL;
1623 }
1624
1625 if (irq_stat & PORT_IRQ_UNK_FIS) {
1626 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1627
1628 active_ehi->err_mask |= AC_ERR_HSM;
1629 active_ehi->action |= ATA_EH_SOFTRESET;
1630 ata_ehi_push_desc(active_ehi,
1631 "unknown FIS %08x %08x %08x %08x" ,
1632 unk[0], unk[1], unk[2], unk[3]);
1633 }
1634
1635 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1636 active_ehi->err_mask |= AC_ERR_HSM;
1637 active_ehi->action |= ATA_EH_SOFTRESET;
1638 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1639 }
1640
1641 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1642 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1643 host_ehi->action |= ATA_EH_SOFTRESET;
1644 ata_ehi_push_desc(host_ehi, "host bus error");
1645 }
1646
1647 if (irq_stat & PORT_IRQ_IF_ERR) {
1648 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1649 host_ehi->action |= ATA_EH_SOFTRESET;
1650 ata_ehi_push_desc(host_ehi, "interface fatal error");
1651 }
1652
1653 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1654 ata_ehi_hotplugged(host_ehi);
1655 ata_ehi_push_desc(host_ehi, "%s",
1656 irq_stat & PORT_IRQ_CONNECT ?
1657 "connection status changed" : "PHY RDY changed");
1658 }
1659
1660 /* okay, let's hand over to EH */
1661
1662 if (irq_stat & PORT_IRQ_FREEZE)
1663 ata_port_freeze(ap);
1664 else
1665 ata_port_abort(ap);
1666 }
1667
1668 static void ahci_port_intr(struct ata_port *ap)
1669 {
1670 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1671 struct ata_eh_info *ehi = &ap->link.eh_info;
1672 struct ahci_port_priv *pp = ap->private_data;
1673 struct ahci_host_priv *hpriv = ap->host->private_data;
1674 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1675 u32 status, qc_active;
1676 int rc;
1677
1678 status = readl(port_mmio + PORT_IRQ_STAT);
1679 writel(status, port_mmio + PORT_IRQ_STAT);
1680
1681 /* ignore BAD_PMP while resetting */
1682 if (unlikely(resetting))
1683 status &= ~PORT_IRQ_BAD_PMP;
1684
1685 /* If we are getting PhyRdy, this is
1686 * just a power state change, we should
1687 * clear out this, plus the PhyRdy/Comm
1688 * Wake bits from Serror
1689 */
1690 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1691 (status & PORT_IRQ_PHYRDY)) {
1692 status &= ~PORT_IRQ_PHYRDY;
1693 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1694 }
1695
1696 if (unlikely(status & PORT_IRQ_ERROR)) {
1697 ahci_error_intr(ap, status);
1698 return;
1699 }
1700
1701 if (status & PORT_IRQ_SDB_FIS) {
1702 /* If SNotification is available, leave notification
1703 * handling to sata_async_notification(). If not,
1704 * emulate it by snooping SDB FIS RX area.
1705 *
1706 * Snooping FIS RX area is probably cheaper than
1707 * poking SNotification but some constrollers which
1708 * implement SNotification, ICH9 for example, don't
1709 * store AN SDB FIS into receive area.
1710 */
1711 if (hpriv->cap & HOST_CAP_SNTF)
1712 sata_async_notification(ap);
1713 else {
1714 /* If the 'N' bit in word 0 of the FIS is set,
1715 * we just received asynchronous notification.
1716 * Tell libata about it.
1717 */
1718 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1719 u32 f0 = le32_to_cpu(f[0]);
1720
1721 if (f0 & (1 << 15))
1722 sata_async_notification(ap);
1723 }
1724 }
1725
1726 /* pp->active_link is valid iff any command is in flight */
1727 if (ap->qc_active && pp->active_link->sactive)
1728 qc_active = readl(port_mmio + PORT_SCR_ACT);
1729 else
1730 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1731
1732 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1733
1734 /* while resetting, invalid completions are expected */
1735 if (unlikely(rc < 0 && !resetting)) {
1736 ehi->err_mask |= AC_ERR_HSM;
1737 ehi->action |= ATA_EH_SOFTRESET;
1738 ata_port_freeze(ap);
1739 }
1740 }
1741
1742 static void ahci_irq_clear(struct ata_port *ap)
1743 {
1744 /* TODO */
1745 }
1746
1747 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1748 {
1749 struct ata_host *host = dev_instance;
1750 struct ahci_host_priv *hpriv;
1751 unsigned int i, handled = 0;
1752 void __iomem *mmio;
1753 u32 irq_stat, irq_ack = 0;
1754
1755 VPRINTK("ENTER\n");
1756
1757 hpriv = host->private_data;
1758 mmio = host->iomap[AHCI_PCI_BAR];
1759
1760 /* sigh. 0xffffffff is a valid return from h/w */
1761 irq_stat = readl(mmio + HOST_IRQ_STAT);
1762 irq_stat &= hpriv->port_map;
1763 if (!irq_stat)
1764 return IRQ_NONE;
1765
1766 spin_lock(&host->lock);
1767
1768 for (i = 0; i < host->n_ports; i++) {
1769 struct ata_port *ap;
1770
1771 if (!(irq_stat & (1 << i)))
1772 continue;
1773
1774 ap = host->ports[i];
1775 if (ap) {
1776 ahci_port_intr(ap);
1777 VPRINTK("port %u\n", i);
1778 } else {
1779 VPRINTK("port %u (no irq)\n", i);
1780 if (ata_ratelimit())
1781 dev_printk(KERN_WARNING, host->dev,
1782 "interrupt on disabled port %u\n", i);
1783 }
1784
1785 irq_ack |= (1 << i);
1786 }
1787
1788 if (irq_ack) {
1789 writel(irq_ack, mmio + HOST_IRQ_STAT);
1790 handled = 1;
1791 }
1792
1793 spin_unlock(&host->lock);
1794
1795 VPRINTK("EXIT\n");
1796
1797 return IRQ_RETVAL(handled);
1798 }
1799
1800 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1801 {
1802 struct ata_port *ap = qc->ap;
1803 void __iomem *port_mmio = ahci_port_base(ap);
1804 struct ahci_port_priv *pp = ap->private_data;
1805
1806 /* Keep track of the currently active link. It will be used
1807 * in completion path to determine whether NCQ phase is in
1808 * progress.
1809 */
1810 pp->active_link = qc->dev->link;
1811
1812 if (qc->tf.protocol == ATA_PROT_NCQ)
1813 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1814 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1815 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1816
1817 return 0;
1818 }
1819
1820 static void ahci_freeze(struct ata_port *ap)
1821 {
1822 void __iomem *port_mmio = ahci_port_base(ap);
1823
1824 /* turn IRQ off */
1825 writel(0, port_mmio + PORT_IRQ_MASK);
1826 }
1827
1828 static void ahci_thaw(struct ata_port *ap)
1829 {
1830 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1831 void __iomem *port_mmio = ahci_port_base(ap);
1832 u32 tmp;
1833 struct ahci_port_priv *pp = ap->private_data;
1834
1835 /* clear IRQ */
1836 tmp = readl(port_mmio + PORT_IRQ_STAT);
1837 writel(tmp, port_mmio + PORT_IRQ_STAT);
1838 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1839
1840 /* turn IRQ back on */
1841 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1842 }
1843
1844 static void ahci_error_handler(struct ata_port *ap)
1845 {
1846 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1847 /* restart engine */
1848 ahci_stop_engine(ap);
1849 ahci_start_engine(ap);
1850 }
1851
1852 /* perform recovery */
1853 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1854 ahci_hardreset, ahci_postreset,
1855 sata_pmp_std_prereset, ahci_pmp_softreset,
1856 sata_pmp_std_hardreset, sata_pmp_std_postreset);
1857 }
1858
1859 static void ahci_vt8251_error_handler(struct ata_port *ap)
1860 {
1861 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1862 /* restart engine */
1863 ahci_stop_engine(ap);
1864 ahci_start_engine(ap);
1865 }
1866
1867 /* perform recovery */
1868 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1869 ahci_postreset);
1870 }
1871
1872 static void ahci_p5wdh_error_handler(struct ata_port *ap)
1873 {
1874 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1875 /* restart engine */
1876 ahci_stop_engine(ap);
1877 ahci_start_engine(ap);
1878 }
1879
1880 /* perform recovery */
1881 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1882 ahci_postreset);
1883 }
1884
1885 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1886 {
1887 struct ata_port *ap = qc->ap;
1888
1889 /* make DMA engine forget about the failed command */
1890 if (qc->flags & ATA_QCFLAG_FAILED)
1891 ahci_kick_engine(ap, 1);
1892 }
1893
1894 static void ahci_pmp_attach(struct ata_port *ap)
1895 {
1896 void __iomem *port_mmio = ahci_port_base(ap);
1897 struct ahci_port_priv *pp = ap->private_data;
1898 u32 cmd;
1899
1900 cmd = readl(port_mmio + PORT_CMD);
1901 cmd |= PORT_CMD_PMP;
1902 writel(cmd, port_mmio + PORT_CMD);
1903
1904 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1905 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1906 }
1907
1908 static void ahci_pmp_detach(struct ata_port *ap)
1909 {
1910 void __iomem *port_mmio = ahci_port_base(ap);
1911 struct ahci_port_priv *pp = ap->private_data;
1912 u32 cmd;
1913
1914 cmd = readl(port_mmio + PORT_CMD);
1915 cmd &= ~PORT_CMD_PMP;
1916 writel(cmd, port_mmio + PORT_CMD);
1917
1918 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1919 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1920 }
1921
1922 static int ahci_port_resume(struct ata_port *ap)
1923 {
1924 ahci_power_up(ap);
1925 ahci_start_port(ap);
1926
1927 if (ap->nr_pmp_links)
1928 ahci_pmp_attach(ap);
1929 else
1930 ahci_pmp_detach(ap);
1931
1932 return 0;
1933 }
1934
1935 #ifdef CONFIG_PM
1936 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1937 {
1938 const char *emsg = NULL;
1939 int rc;
1940
1941 rc = ahci_deinit_port(ap, &emsg);
1942 if (rc == 0)
1943 ahci_power_down(ap);
1944 else {
1945 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1946 ahci_start_port(ap);
1947 }
1948
1949 return rc;
1950 }
1951
1952 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1953 {
1954 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1955 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1956 u32 ctl;
1957
1958 if (mesg.event & PM_EVENT_SLEEP) {
1959 /* AHCI spec rev1.1 section 8.3.3:
1960 * Software must disable interrupts prior to requesting a
1961 * transition of the HBA to D3 state.
1962 */
1963 ctl = readl(mmio + HOST_CTL);
1964 ctl &= ~HOST_IRQ_EN;
1965 writel(ctl, mmio + HOST_CTL);
1966 readl(mmio + HOST_CTL); /* flush */
1967 }
1968
1969 return ata_pci_device_suspend(pdev, mesg);
1970 }
1971
1972 static int ahci_pci_device_resume(struct pci_dev *pdev)
1973 {
1974 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1975 int rc;
1976
1977 rc = ata_pci_device_do_resume(pdev);
1978 if (rc)
1979 return rc;
1980
1981 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1982 rc = ahci_reset_controller(host);
1983 if (rc)
1984 return rc;
1985
1986 ahci_init_controller(host);
1987 }
1988
1989 ata_host_resume(host);
1990
1991 return 0;
1992 }
1993 #endif
1994
1995 static int ahci_port_start(struct ata_port *ap)
1996 {
1997 struct device *dev = ap->host->dev;
1998 struct ahci_port_priv *pp;
1999 void *mem;
2000 dma_addr_t mem_dma;
2001
2002 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2003 if (!pp)
2004 return -ENOMEM;
2005
2006 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2007 GFP_KERNEL);
2008 if (!mem)
2009 return -ENOMEM;
2010 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2011
2012 /*
2013 * First item in chunk of DMA memory: 32-slot command table,
2014 * 32 bytes each in size
2015 */
2016 pp->cmd_slot = mem;
2017 pp->cmd_slot_dma = mem_dma;
2018
2019 mem += AHCI_CMD_SLOT_SZ;
2020 mem_dma += AHCI_CMD_SLOT_SZ;
2021
2022 /*
2023 * Second item: Received-FIS area
2024 */
2025 pp->rx_fis = mem;
2026 pp->rx_fis_dma = mem_dma;
2027
2028 mem += AHCI_RX_FIS_SZ;
2029 mem_dma += AHCI_RX_FIS_SZ;
2030
2031 /*
2032 * Third item: data area for storing a single command
2033 * and its scatter-gather table
2034 */
2035 pp->cmd_tbl = mem;
2036 pp->cmd_tbl_dma = mem_dma;
2037
2038 /*
2039 * Save off initial list of interrupts to be enabled.
2040 * This could be changed later
2041 */
2042 pp->intr_mask = DEF_PORT_IRQ;
2043
2044 ap->private_data = pp;
2045
2046 /* engage engines, captain */
2047 return ahci_port_resume(ap);
2048 }
2049
2050 static void ahci_port_stop(struct ata_port *ap)
2051 {
2052 const char *emsg = NULL;
2053 int rc;
2054
2055 /* de-initialize port */
2056 rc = ahci_deinit_port(ap, &emsg);
2057 if (rc)
2058 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2059 }
2060
2061 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2062 {
2063 int rc;
2064
2065 if (using_dac &&
2066 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2067 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2068 if (rc) {
2069 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2070 if (rc) {
2071 dev_printk(KERN_ERR, &pdev->dev,
2072 "64-bit DMA enable failed\n");
2073 return rc;
2074 }
2075 }
2076 } else {
2077 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2078 if (rc) {
2079 dev_printk(KERN_ERR, &pdev->dev,
2080 "32-bit DMA enable failed\n");
2081 return rc;
2082 }
2083 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2084 if (rc) {
2085 dev_printk(KERN_ERR, &pdev->dev,
2086 "32-bit consistent DMA enable failed\n");
2087 return rc;
2088 }
2089 }
2090 return 0;
2091 }
2092
2093 static void ahci_print_info(struct ata_host *host)
2094 {
2095 struct ahci_host_priv *hpriv = host->private_data;
2096 struct pci_dev *pdev = to_pci_dev(host->dev);
2097 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2098 u32 vers, cap, impl, speed;
2099 const char *speed_s;
2100 u16 cc;
2101 const char *scc_s;
2102
2103 vers = readl(mmio + HOST_VERSION);
2104 cap = hpriv->cap;
2105 impl = hpriv->port_map;
2106
2107 speed = (cap >> 20) & 0xf;
2108 if (speed == 1)
2109 speed_s = "1.5";
2110 else if (speed == 2)
2111 speed_s = "3";
2112 else
2113 speed_s = "?";
2114
2115 pci_read_config_word(pdev, 0x0a, &cc);
2116 if (cc == PCI_CLASS_STORAGE_IDE)
2117 scc_s = "IDE";
2118 else if (cc == PCI_CLASS_STORAGE_SATA)
2119 scc_s = "SATA";
2120 else if (cc == PCI_CLASS_STORAGE_RAID)
2121 scc_s = "RAID";
2122 else
2123 scc_s = "unknown";
2124
2125 dev_printk(KERN_INFO, &pdev->dev,
2126 "AHCI %02x%02x.%02x%02x "
2127 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2128 ,
2129
2130 (vers >> 24) & 0xff,
2131 (vers >> 16) & 0xff,
2132 (vers >> 8) & 0xff,
2133 vers & 0xff,
2134
2135 ((cap >> 8) & 0x1f) + 1,
2136 (cap & 0x1f) + 1,
2137 speed_s,
2138 impl,
2139 scc_s);
2140
2141 dev_printk(KERN_INFO, &pdev->dev,
2142 "flags: "
2143 "%s%s%s%s%s%s%s"
2144 "%s%s%s%s%s%s%s\n"
2145 ,
2146
2147 cap & (1 << 31) ? "64bit " : "",
2148 cap & (1 << 30) ? "ncq " : "",
2149 cap & (1 << 29) ? "sntf " : "",
2150 cap & (1 << 28) ? "ilck " : "",
2151 cap & (1 << 27) ? "stag " : "",
2152 cap & (1 << 26) ? "pm " : "",
2153 cap & (1 << 25) ? "led " : "",
2154
2155 cap & (1 << 24) ? "clo " : "",
2156 cap & (1 << 19) ? "nz " : "",
2157 cap & (1 << 18) ? "only " : "",
2158 cap & (1 << 17) ? "pmp " : "",
2159 cap & (1 << 15) ? "pio " : "",
2160 cap & (1 << 14) ? "slum " : "",
2161 cap & (1 << 13) ? "part " : ""
2162 );
2163 }
2164
2165 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2166 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2167 * support PMP and the 4726 either directly exports the device
2168 * attached to the first downstream port or acts as a hardware storage
2169 * controller and emulate a single ATA device (can be RAID 0/1 or some
2170 * other configuration).
2171 *
2172 * When there's no device attached to the first downstream port of the
2173 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2174 * configure the 4726. However, ATA emulation of the device is very
2175 * lame. It doesn't send signature D2H Reg FIS after the initial
2176 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2177 *
2178 * The following function works around the problem by always using
2179 * hardreset on the port and not depending on receiving signature FIS
2180 * afterward. If signature FIS isn't received soon, ATA class is
2181 * assumed without follow-up softreset.
2182 */
2183 static void ahci_p5wdh_workaround(struct ata_host *host)
2184 {
2185 static struct dmi_system_id sysids[] = {
2186 {
2187 .ident = "P5W DH Deluxe",
2188 .matches = {
2189 DMI_MATCH(DMI_SYS_VENDOR,
2190 "ASUSTEK COMPUTER INC"),
2191 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2192 },
2193 },
2194 { }
2195 };
2196 struct pci_dev *pdev = to_pci_dev(host->dev);
2197
2198 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2199 dmi_check_system(sysids)) {
2200 struct ata_port *ap = host->ports[1];
2201
2202 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2203 "Deluxe on-board SIMG4726 workaround\n");
2204
2205 ap->ops = &ahci_p5wdh_ops;
2206 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2207 }
2208 }
2209
2210 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2211 {
2212 static int printed_version;
2213 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2214 const struct ata_port_info *ppi[] = { &pi, NULL };
2215 struct device *dev = &pdev->dev;
2216 struct ahci_host_priv *hpriv;
2217 struct ata_host *host;
2218 int n_ports, i, rc;
2219
2220 VPRINTK("ENTER\n");
2221
2222 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2223
2224 if (!printed_version++)
2225 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2226
2227 /* acquire resources */
2228 rc = pcim_enable_device(pdev);
2229 if (rc)
2230 return rc;
2231
2232 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2233 if (rc == -EBUSY)
2234 pcim_pin_device(pdev);
2235 if (rc)
2236 return rc;
2237
2238 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2239 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2240 u8 map;
2241
2242 /* ICH6s share the same PCI ID for both piix and ahci
2243 * modes. Enabling ahci mode while MAP indicates
2244 * combined mode is a bad idea. Yield to ata_piix.
2245 */
2246 pci_read_config_byte(pdev, ICH_MAP, &map);
2247 if (map & 0x3) {
2248 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2249 "combined mode, can't enable AHCI mode\n");
2250 return -ENODEV;
2251 }
2252 }
2253
2254 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2255 if (!hpriv)
2256 return -ENOMEM;
2257 hpriv->flags |= (unsigned long)pi.private_data;
2258
2259 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2260 pci_intx(pdev, 1);
2261
2262 /* save initial config */
2263 ahci_save_initial_config(pdev, hpriv);
2264
2265 /* prepare host */
2266 if (hpriv->cap & HOST_CAP_NCQ)
2267 pi.flags |= ATA_FLAG_NCQ;
2268
2269 if (hpriv->cap & HOST_CAP_PMP)
2270 pi.flags |= ATA_FLAG_PMP;
2271
2272 /* CAP.NP sometimes indicate the index of the last enabled
2273 * port, at other times, that of the last possible port, so
2274 * determining the maximum port number requires looking at
2275 * both CAP.NP and port_map.
2276 */
2277 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2278
2279 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2280 if (!host)
2281 return -ENOMEM;
2282 host->iomap = pcim_iomap_table(pdev);
2283 host->private_data = hpriv;
2284
2285 for (i = 0; i < host->n_ports; i++) {
2286 struct ata_port *ap = host->ports[i];
2287 void __iomem *port_mmio = ahci_port_base(ap);
2288
2289 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2290 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2291 0x100 + ap->port_no * 0x80, "port");
2292
2293 /* set initial link pm policy */
2294 ap->pm_policy = NOT_AVAILABLE;
2295
2296 /* standard SATA port setup */
2297 if (hpriv->port_map & (1 << i))
2298 ap->ioaddr.cmd_addr = port_mmio;
2299
2300 /* disabled/not-implemented port */
2301 else
2302 ap->ops = &ata_dummy_port_ops;
2303 }
2304
2305 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2306 ahci_p5wdh_workaround(host);
2307
2308 /* initialize adapter */
2309 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2310 if (rc)
2311 return rc;
2312
2313 rc = ahci_reset_controller(host);
2314 if (rc)
2315 return rc;
2316
2317 ahci_init_controller(host);
2318 ahci_print_info(host);
2319
2320 pci_set_master(pdev);
2321 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2322 &ahci_sht);
2323 }
2324
2325 static int __init ahci_init(void)
2326 {
2327 return pci_register_driver(&ahci_pci_driver);
2328 }
2329
2330 static void __exit ahci_exit(void)
2331 {
2332 pci_unregister_driver(&ahci_pci_driver);
2333 }
2334
2335
2336 MODULE_AUTHOR("Jeff Garzik");
2337 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2338 MODULE_LICENSE("GPL");
2339 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2340 MODULE_VERSION(DRV_VERSION);
2341
2342 module_init(ahci_init);
2343 module_exit(ahci_exit);
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