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ahci: Add Marvell 88se91a2 device id
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_CAVIUM = 0,
57 AHCI_PCI_BAR_ENMOTUS = 2,
58 AHCI_PCI_BAR_STANDARD = 5,
59 };
60
61 enum board_ids {
62 /* board IDs by feature in alphabetical order */
63 board_ahci,
64 board_ahci_ign_iferr,
65 board_ahci_nomsi,
66 board_ahci_noncq,
67 board_ahci_nosntf,
68 board_ahci_yes_fbs,
69
70 /* board IDs for specific chipsets in alphabetical order */
71 board_ahci_avn,
72 board_ahci_mcp65,
73 board_ahci_mcp77,
74 board_ahci_mcp89,
75 board_ahci_mv,
76 board_ahci_sb600,
77 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_vt8251,
79
80 /* aliases */
81 board_ahci_mcp_linux = board_ahci_mcp65,
82 board_ahci_mcp67 = board_ahci_mcp65,
83 board_ahci_mcp73 = board_ahci_mcp65,
84 board_ahci_mcp79 = board_ahci_mcp77,
85 };
86
87 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93 static bool is_mcp89_apple(struct pci_dev *pdev);
94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
96 #ifdef CONFIG_PM
97 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
98 static int ahci_pci_device_resume(struct pci_dev *pdev);
99 #endif
100
101 static struct scsi_host_template ahci_sht = {
102 AHCI_SHT("ahci"),
103 };
104
105 static struct ata_port_operations ahci_vt8251_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_vt8251_hardreset,
108 };
109
110 static struct ata_port_operations ahci_p5wdh_ops = {
111 .inherits = &ahci_ops,
112 .hardreset = ahci_p5wdh_hardreset,
113 };
114
115 static struct ata_port_operations ahci_avn_ops = {
116 .inherits = &ahci_ops,
117 .hardreset = ahci_avn_hardreset,
118 };
119
120 static const struct ata_port_info ahci_port_info[] = {
121 /* by features */
122 [board_ahci] = {
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
127 },
128 [board_ahci_ign_iferr] = {
129 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
134 },
135 [board_ahci_nomsi] = {
136 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
141 },
142 [board_ahci_noncq] = {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_nosntf] = {
150 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
151 .flags = AHCI_FLAG_COMMON,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
155 },
156 [board_ahci_yes_fbs] = {
157 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
158 .flags = AHCI_FLAG_COMMON,
159 .pio_mask = ATA_PIO4,
160 .udma_mask = ATA_UDMA6,
161 .port_ops = &ahci_ops,
162 },
163 /* by chipsets */
164 [board_ahci_avn] = {
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_avn_ops,
169 },
170 [board_ahci_mcp65] = {
171 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
172 AHCI_HFLAG_YES_NCQ),
173 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_ops,
177 },
178 [board_ahci_mcp77] = {
179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
184 },
185 [board_ahci_mcp89] = {
186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
191 },
192 [board_ahci_mv] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
194 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
195 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
199 },
200 [board_ahci_sb600] = {
201 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
202 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
203 AHCI_HFLAG_32BIT_ONLY),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_pmp_retry_srst_ops,
208 },
209 [board_ahci_sb700] = { /* for SB700 and SB800 */
210 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_pmp_retry_srst_ops,
215 },
216 [board_ahci_vt8251] = {
217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
218 .flags = AHCI_FLAG_COMMON,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_vt8251_ops,
222 },
223 };
224
225 static const struct pci_device_id ahci_pci_tbl[] = {
226 /* Intel */
227 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
228 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
229 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
230 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
231 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
232 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
233 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
234 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
235 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
236 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
237 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
238 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
239 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
240 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
241 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
242 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
243 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
244 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
245 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
246 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
247 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
248 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
249 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
250 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
251 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
252 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
254 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
255 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
256 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
257 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
258 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
259 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
260 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
261 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
262 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
263 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
264 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
265 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
266 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
268 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
269 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
270 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
271 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
272 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
273 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
274 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
275 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
276 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
277 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
278 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
279 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
280 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
281 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
282 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
283 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
284 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
285 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
286 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
287 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
288 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
289 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
290 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
291 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
292 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
293 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
294 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
295 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
296 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
297 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
298 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
299 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
300 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
301 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
302 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
303 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
304 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
305 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
306 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
307 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
308 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
309 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
310 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
311 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
312 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
313 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
314 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
315 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
316 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
317 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
318 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
319 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
320 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
321 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
322 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
323 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
324 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
325 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
326 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
327 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
328 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
329 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
330 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
331 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
332 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
333 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
334 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
335 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
336 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
337 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
338 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
339 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
340 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
341 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
343 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
344 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
345 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
346 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
347
348 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
349 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
350 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
351 /* JMicron 362B and 362C have an AHCI function with IDE class code */
352 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
353 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
354 /* May need to update quirk_jmicron_async_suspend() for additions */
355
356 /* ATI */
357 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
358 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
359 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
360 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
361 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
362 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
363 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
364
365 /* AMD */
366 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
367 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
368 /* AMD is using RAID class only for ahci controllers */
369 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
370 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
371
372 /* VIA */
373 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
374 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
375
376 /* NVIDIA */
377 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
378 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
379 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
380 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
381 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
382 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
383 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
384 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
385 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
386 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
387 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
388 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
389 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
390 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
391 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
392 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
393 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
394 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
395 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
396 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
397 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
398 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
399 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
400 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
401 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
402 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
403 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
404 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
405 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
406 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
407 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
408 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
409 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
410 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
411 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
412 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
413 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
414 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
415 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
416 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
417 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
418 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
419 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
420 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
421 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
422 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
423 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
424 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
425 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
426 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
427 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
428 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
429 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
430 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
431 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
432 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
433 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
434 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
435 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
436 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
437 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
438 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
439 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
440 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
441 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
442 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
443 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
444 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
445 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
446 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
447 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
448 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
449 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
450 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
451 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
452 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
453 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
454 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
455 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
456 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
457 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
458 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
459 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
460 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
461
462 /* SiS */
463 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
464 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
465 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
466
467 /* ST Microelectronics */
468 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
469
470 /* Marvell */
471 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
472 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
473 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
474 .class = PCI_CLASS_STORAGE_SATA_AHCI,
475 .class_mask = 0xffffff,
476 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
477 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
478 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
479 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
480 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
481 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
482 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
483 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
484 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
485 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
486 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
487 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
488 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
489 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
490 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
491 .driver_data = board_ahci_yes_fbs },
492 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
493 .driver_data = board_ahci_yes_fbs },
494 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
495 .driver_data = board_ahci_yes_fbs },
496 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
497 .driver_data = board_ahci_yes_fbs },
498 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
499 .driver_data = board_ahci_yes_fbs },
500
501 /* Promise */
502 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
503 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
504
505 /* Asmedia */
506 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
507 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
508 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
509 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
510
511 /*
512 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
513 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
514 */
515 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
516 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
517
518 /* Enmotus */
519 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
520
521 /* Generic, PCI class code for AHCI */
522 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
523 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
524
525 { } /* terminate list */
526 };
527
528
529 static struct pci_driver ahci_pci_driver = {
530 .name = DRV_NAME,
531 .id_table = ahci_pci_tbl,
532 .probe = ahci_init_one,
533 .remove = ata_pci_remove_one,
534 #ifdef CONFIG_PM
535 .suspend = ahci_pci_device_suspend,
536 .resume = ahci_pci_device_resume,
537 #endif
538 };
539
540 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
541 static int marvell_enable;
542 #else
543 static int marvell_enable = 1;
544 #endif
545 module_param(marvell_enable, int, 0644);
546 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
547
548
549 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
550 struct ahci_host_priv *hpriv)
551 {
552 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
553 dev_info(&pdev->dev, "JMB361 has only one port\n");
554 hpriv->force_port_map = 1;
555 }
556
557 /*
558 * Temporary Marvell 6145 hack: PATA port presence
559 * is asserted through the standard AHCI port
560 * presence register, as bit 4 (counting from 0)
561 */
562 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
563 if (pdev->device == 0x6121)
564 hpriv->mask_port_map = 0x3;
565 else
566 hpriv->mask_port_map = 0xf;
567 dev_info(&pdev->dev,
568 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
569 }
570
571 ahci_save_initial_config(&pdev->dev, hpriv);
572 }
573
574 static int ahci_pci_reset_controller(struct ata_host *host)
575 {
576 struct pci_dev *pdev = to_pci_dev(host->dev);
577
578 ahci_reset_controller(host);
579
580 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
581 struct ahci_host_priv *hpriv = host->private_data;
582 u16 tmp16;
583
584 /* configure PCS */
585 pci_read_config_word(pdev, 0x92, &tmp16);
586 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
587 tmp16 |= hpriv->port_map;
588 pci_write_config_word(pdev, 0x92, tmp16);
589 }
590 }
591
592 return 0;
593 }
594
595 static void ahci_pci_init_controller(struct ata_host *host)
596 {
597 struct ahci_host_priv *hpriv = host->private_data;
598 struct pci_dev *pdev = to_pci_dev(host->dev);
599 void __iomem *port_mmio;
600 u32 tmp;
601 int mv;
602
603 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
604 if (pdev->device == 0x6121)
605 mv = 2;
606 else
607 mv = 4;
608 port_mmio = __ahci_port_base(host, mv);
609
610 writel(0, port_mmio + PORT_IRQ_MASK);
611
612 /* clear port IRQ */
613 tmp = readl(port_mmio + PORT_IRQ_STAT);
614 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
615 if (tmp)
616 writel(tmp, port_mmio + PORT_IRQ_STAT);
617 }
618
619 ahci_init_controller(host);
620 }
621
622 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
623 unsigned long deadline)
624 {
625 struct ata_port *ap = link->ap;
626 struct ahci_host_priv *hpriv = ap->host->private_data;
627 bool online;
628 int rc;
629
630 DPRINTK("ENTER\n");
631
632 ahci_stop_engine(ap);
633
634 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
635 deadline, &online, NULL);
636
637 hpriv->start_engine(ap);
638
639 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
640
641 /* vt8251 doesn't clear BSY on signature FIS reception,
642 * request follow-up softreset.
643 */
644 return online ? -EAGAIN : rc;
645 }
646
647 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
648 unsigned long deadline)
649 {
650 struct ata_port *ap = link->ap;
651 struct ahci_port_priv *pp = ap->private_data;
652 struct ahci_host_priv *hpriv = ap->host->private_data;
653 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
654 struct ata_taskfile tf;
655 bool online;
656 int rc;
657
658 ahci_stop_engine(ap);
659
660 /* clear D2H reception area to properly wait for D2H FIS */
661 ata_tf_init(link->device, &tf);
662 tf.command = ATA_BUSY;
663 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
664
665 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
666 deadline, &online, NULL);
667
668 hpriv->start_engine(ap);
669
670 /* The pseudo configuration device on SIMG4726 attached to
671 * ASUS P5W-DH Deluxe doesn't send signature FIS after
672 * hardreset if no device is attached to the first downstream
673 * port && the pseudo device locks up on SRST w/ PMP==0. To
674 * work around this, wait for !BSY only briefly. If BSY isn't
675 * cleared, perform CLO and proceed to IDENTIFY (achieved by
676 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
677 *
678 * Wait for two seconds. Devices attached to downstream port
679 * which can't process the following IDENTIFY after this will
680 * have to be reset again. For most cases, this should
681 * suffice while making probing snappish enough.
682 */
683 if (online) {
684 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
685 ahci_check_ready);
686 if (rc)
687 ahci_kick_engine(ap);
688 }
689 return rc;
690 }
691
692 /*
693 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
694 *
695 * It has been observed with some SSDs that the timing of events in the
696 * link synchronization phase can leave the port in a state that can not
697 * be recovered by a SATA-hard-reset alone. The failing signature is
698 * SStatus.DET stuck at 1 ("Device presence detected but Phy
699 * communication not established"). It was found that unloading and
700 * reloading the driver when this problem occurs allows the drive
701 * connection to be recovered (DET advanced to 0x3). The critical
702 * component of reloading the driver is that the port state machines are
703 * reset by bouncing "port enable" in the AHCI PCS configuration
704 * register. So, reproduce that effect by bouncing a port whenever we
705 * see DET==1 after a reset.
706 */
707 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
708 unsigned long deadline)
709 {
710 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
711 struct ata_port *ap = link->ap;
712 struct ahci_port_priv *pp = ap->private_data;
713 struct ahci_host_priv *hpriv = ap->host->private_data;
714 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
715 unsigned long tmo = deadline - jiffies;
716 struct ata_taskfile tf;
717 bool online;
718 int rc, i;
719
720 DPRINTK("ENTER\n");
721
722 ahci_stop_engine(ap);
723
724 for (i = 0; i < 2; i++) {
725 u16 val;
726 u32 sstatus;
727 int port = ap->port_no;
728 struct ata_host *host = ap->host;
729 struct pci_dev *pdev = to_pci_dev(host->dev);
730
731 /* clear D2H reception area to properly wait for D2H FIS */
732 ata_tf_init(link->device, &tf);
733 tf.command = ATA_BUSY;
734 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
735
736 rc = sata_link_hardreset(link, timing, deadline, &online,
737 ahci_check_ready);
738
739 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
740 (sstatus & 0xf) != 1)
741 break;
742
743 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
744 port);
745
746 pci_read_config_word(pdev, 0x92, &val);
747 val &= ~(1 << port);
748 pci_write_config_word(pdev, 0x92, val);
749 ata_msleep(ap, 1000);
750 val |= 1 << port;
751 pci_write_config_word(pdev, 0x92, val);
752 deadline += tmo;
753 }
754
755 hpriv->start_engine(ap);
756
757 if (online)
758 *class = ahci_dev_classify(ap);
759
760 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
761 return rc;
762 }
763
764
765 #ifdef CONFIG_PM
766 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
767 {
768 struct ata_host *host = pci_get_drvdata(pdev);
769 struct ahci_host_priv *hpriv = host->private_data;
770 void __iomem *mmio = hpriv->mmio;
771 u32 ctl;
772
773 if (mesg.event & PM_EVENT_SUSPEND &&
774 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
775 dev_err(&pdev->dev,
776 "BIOS update required for suspend/resume\n");
777 return -EIO;
778 }
779
780 if (mesg.event & PM_EVENT_SLEEP) {
781 /* AHCI spec rev1.1 section 8.3.3:
782 * Software must disable interrupts prior to requesting a
783 * transition of the HBA to D3 state.
784 */
785 ctl = readl(mmio + HOST_CTL);
786 ctl &= ~HOST_IRQ_EN;
787 writel(ctl, mmio + HOST_CTL);
788 readl(mmio + HOST_CTL); /* flush */
789 }
790
791 return ata_pci_device_suspend(pdev, mesg);
792 }
793
794 static int ahci_pci_device_resume(struct pci_dev *pdev)
795 {
796 struct ata_host *host = pci_get_drvdata(pdev);
797 int rc;
798
799 rc = ata_pci_device_do_resume(pdev);
800 if (rc)
801 return rc;
802
803 /* Apple BIOS helpfully mangles the registers on resume */
804 if (is_mcp89_apple(pdev))
805 ahci_mcp89_apple_enable(pdev);
806
807 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
808 rc = ahci_pci_reset_controller(host);
809 if (rc)
810 return rc;
811
812 ahci_pci_init_controller(host);
813 }
814
815 ata_host_resume(host);
816
817 return 0;
818 }
819 #endif
820
821 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
822 {
823 int rc;
824
825 /*
826 * If the device fixup already set the dma_mask to some non-standard
827 * value, don't extend it here. This happens on STA2X11, for example.
828 */
829 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
830 return 0;
831
832 if (using_dac &&
833 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
834 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
835 if (rc) {
836 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
837 if (rc) {
838 dev_err(&pdev->dev,
839 "64-bit DMA enable failed\n");
840 return rc;
841 }
842 }
843 } else {
844 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
845 if (rc) {
846 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
847 return rc;
848 }
849 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
850 if (rc) {
851 dev_err(&pdev->dev,
852 "32-bit consistent DMA enable failed\n");
853 return rc;
854 }
855 }
856 return 0;
857 }
858
859 static void ahci_pci_print_info(struct ata_host *host)
860 {
861 struct pci_dev *pdev = to_pci_dev(host->dev);
862 u16 cc;
863 const char *scc_s;
864
865 pci_read_config_word(pdev, 0x0a, &cc);
866 if (cc == PCI_CLASS_STORAGE_IDE)
867 scc_s = "IDE";
868 else if (cc == PCI_CLASS_STORAGE_SATA)
869 scc_s = "SATA";
870 else if (cc == PCI_CLASS_STORAGE_RAID)
871 scc_s = "RAID";
872 else
873 scc_s = "unknown";
874
875 ahci_print_info(host, scc_s);
876 }
877
878 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
879 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
880 * support PMP and the 4726 either directly exports the device
881 * attached to the first downstream port or acts as a hardware storage
882 * controller and emulate a single ATA device (can be RAID 0/1 or some
883 * other configuration).
884 *
885 * When there's no device attached to the first downstream port of the
886 * 4726, "Config Disk" appears, which is a pseudo ATA device to
887 * configure the 4726. However, ATA emulation of the device is very
888 * lame. It doesn't send signature D2H Reg FIS after the initial
889 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
890 *
891 * The following function works around the problem by always using
892 * hardreset on the port and not depending on receiving signature FIS
893 * afterward. If signature FIS isn't received soon, ATA class is
894 * assumed without follow-up softreset.
895 */
896 static void ahci_p5wdh_workaround(struct ata_host *host)
897 {
898 static const struct dmi_system_id sysids[] = {
899 {
900 .ident = "P5W DH Deluxe",
901 .matches = {
902 DMI_MATCH(DMI_SYS_VENDOR,
903 "ASUSTEK COMPUTER INC"),
904 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
905 },
906 },
907 { }
908 };
909 struct pci_dev *pdev = to_pci_dev(host->dev);
910
911 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
912 dmi_check_system(sysids)) {
913 struct ata_port *ap = host->ports[1];
914
915 dev_info(&pdev->dev,
916 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
917
918 ap->ops = &ahci_p5wdh_ops;
919 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
920 }
921 }
922
923 /*
924 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
925 * booting in BIOS compatibility mode. We restore the registers but not ID.
926 */
927 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
928 {
929 u32 val;
930
931 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
932
933 pci_read_config_dword(pdev, 0xf8, &val);
934 val |= 1 << 0x1b;
935 /* the following changes the device ID, but appears not to affect function */
936 /* val = (val & ~0xf0000000) | 0x80000000; */
937 pci_write_config_dword(pdev, 0xf8, val);
938
939 pci_read_config_dword(pdev, 0x54c, &val);
940 val |= 1 << 0xc;
941 pci_write_config_dword(pdev, 0x54c, val);
942
943 pci_read_config_dword(pdev, 0x4a4, &val);
944 val &= 0xff;
945 val |= 0x01060100;
946 pci_write_config_dword(pdev, 0x4a4, val);
947
948 pci_read_config_dword(pdev, 0x54c, &val);
949 val &= ~(1 << 0xc);
950 pci_write_config_dword(pdev, 0x54c, val);
951
952 pci_read_config_dword(pdev, 0xf8, &val);
953 val &= ~(1 << 0x1b);
954 pci_write_config_dword(pdev, 0xf8, val);
955 }
956
957 static bool is_mcp89_apple(struct pci_dev *pdev)
958 {
959 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
960 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
961 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
962 pdev->subsystem_device == 0xcb89;
963 }
964
965 /* only some SB600 ahci controllers can do 64bit DMA */
966 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
967 {
968 static const struct dmi_system_id sysids[] = {
969 /*
970 * The oldest version known to be broken is 0901 and
971 * working is 1501 which was released on 2007-10-26.
972 * Enable 64bit DMA on 1501 and anything newer.
973 *
974 * Please read bko#9412 for more info.
975 */
976 {
977 .ident = "ASUS M2A-VM",
978 .matches = {
979 DMI_MATCH(DMI_BOARD_VENDOR,
980 "ASUSTeK Computer INC."),
981 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
982 },
983 .driver_data = "20071026", /* yyyymmdd */
984 },
985 /*
986 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
987 * support 64bit DMA.
988 *
989 * BIOS versions earlier than 1.5 had the Manufacturer DMI
990 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
991 * This spelling mistake was fixed in BIOS version 1.5, so
992 * 1.5 and later have the Manufacturer as
993 * "MICRO-STAR INTERNATIONAL CO.,LTD".
994 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
995 *
996 * BIOS versions earlier than 1.9 had a Board Product Name
997 * DMI field of "MS-7376". This was changed to be
998 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
999 * match on DMI_BOARD_NAME of "MS-7376".
1000 */
1001 {
1002 .ident = "MSI K9A2 Platinum",
1003 .matches = {
1004 DMI_MATCH(DMI_BOARD_VENDOR,
1005 "MICRO-STAR INTER"),
1006 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1007 },
1008 },
1009 /*
1010 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1011 * 64bit DMA.
1012 *
1013 * This board also had the typo mentioned above in the
1014 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1015 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1016 */
1017 {
1018 .ident = "MSI K9AGM2",
1019 .matches = {
1020 DMI_MATCH(DMI_BOARD_VENDOR,
1021 "MICRO-STAR INTER"),
1022 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1023 },
1024 },
1025 /*
1026 * All BIOS versions for the Asus M3A support 64bit DMA.
1027 * (all release versions from 0301 to 1206 were tested)
1028 */
1029 {
1030 .ident = "ASUS M3A",
1031 .matches = {
1032 DMI_MATCH(DMI_BOARD_VENDOR,
1033 "ASUSTeK Computer INC."),
1034 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1035 },
1036 },
1037 { }
1038 };
1039 const struct dmi_system_id *match;
1040 int year, month, date;
1041 char buf[9];
1042
1043 match = dmi_first_match(sysids);
1044 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1045 !match)
1046 return false;
1047
1048 if (!match->driver_data)
1049 goto enable_64bit;
1050
1051 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1052 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1053
1054 if (strcmp(buf, match->driver_data) >= 0)
1055 goto enable_64bit;
1056 else {
1057 dev_warn(&pdev->dev,
1058 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1059 match->ident);
1060 return false;
1061 }
1062
1063 enable_64bit:
1064 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1065 return true;
1066 }
1067
1068 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1069 {
1070 static const struct dmi_system_id broken_systems[] = {
1071 {
1072 .ident = "HP Compaq nx6310",
1073 .matches = {
1074 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1075 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1076 },
1077 /* PCI slot number of the controller */
1078 .driver_data = (void *)0x1FUL,
1079 },
1080 {
1081 .ident = "HP Compaq 6720s",
1082 .matches = {
1083 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1084 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1085 },
1086 /* PCI slot number of the controller */
1087 .driver_data = (void *)0x1FUL,
1088 },
1089
1090 { } /* terminate list */
1091 };
1092 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1093
1094 if (dmi) {
1095 unsigned long slot = (unsigned long)dmi->driver_data;
1096 /* apply the quirk only to on-board controllers */
1097 return slot == PCI_SLOT(pdev->devfn);
1098 }
1099
1100 return false;
1101 }
1102
1103 static bool ahci_broken_suspend(struct pci_dev *pdev)
1104 {
1105 static const struct dmi_system_id sysids[] = {
1106 /*
1107 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1108 * to the harddisk doesn't become online after
1109 * resuming from STR. Warn and fail suspend.
1110 *
1111 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1112 *
1113 * Use dates instead of versions to match as HP is
1114 * apparently recycling both product and version
1115 * strings.
1116 *
1117 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1118 */
1119 {
1120 .ident = "dv4",
1121 .matches = {
1122 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1123 DMI_MATCH(DMI_PRODUCT_NAME,
1124 "HP Pavilion dv4 Notebook PC"),
1125 },
1126 .driver_data = "20090105", /* F.30 */
1127 },
1128 {
1129 .ident = "dv5",
1130 .matches = {
1131 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1132 DMI_MATCH(DMI_PRODUCT_NAME,
1133 "HP Pavilion dv5 Notebook PC"),
1134 },
1135 .driver_data = "20090506", /* F.16 */
1136 },
1137 {
1138 .ident = "dv6",
1139 .matches = {
1140 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1141 DMI_MATCH(DMI_PRODUCT_NAME,
1142 "HP Pavilion dv6 Notebook PC"),
1143 },
1144 .driver_data = "20090423", /* F.21 */
1145 },
1146 {
1147 .ident = "HDX18",
1148 .matches = {
1149 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1150 DMI_MATCH(DMI_PRODUCT_NAME,
1151 "HP HDX18 Notebook PC"),
1152 },
1153 .driver_data = "20090430", /* F.23 */
1154 },
1155 /*
1156 * Acer eMachines G725 has the same problem. BIOS
1157 * V1.03 is known to be broken. V3.04 is known to
1158 * work. Between, there are V1.06, V2.06 and V3.03
1159 * that we don't have much idea about. For now,
1160 * blacklist anything older than V3.04.
1161 *
1162 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1163 */
1164 {
1165 .ident = "G725",
1166 .matches = {
1167 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1168 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1169 },
1170 .driver_data = "20091216", /* V3.04 */
1171 },
1172 { } /* terminate list */
1173 };
1174 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1175 int year, month, date;
1176 char buf[9];
1177
1178 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1179 return false;
1180
1181 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1182 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1183
1184 return strcmp(buf, dmi->driver_data) < 0;
1185 }
1186
1187 static bool ahci_broken_online(struct pci_dev *pdev)
1188 {
1189 #define ENCODE_BUSDEVFN(bus, slot, func) \
1190 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1191 static const struct dmi_system_id sysids[] = {
1192 /*
1193 * There are several gigabyte boards which use
1194 * SIMG5723s configured as hardware RAID. Certain
1195 * 5723 firmware revisions shipped there keep the link
1196 * online but fail to answer properly to SRST or
1197 * IDENTIFY when no device is attached downstream
1198 * causing libata to retry quite a few times leading
1199 * to excessive detection delay.
1200 *
1201 * As these firmwares respond to the second reset try
1202 * with invalid device signature, considering unknown
1203 * sig as offline works around the problem acceptably.
1204 */
1205 {
1206 .ident = "EP45-DQ6",
1207 .matches = {
1208 DMI_MATCH(DMI_BOARD_VENDOR,
1209 "Gigabyte Technology Co., Ltd."),
1210 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1211 },
1212 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1213 },
1214 {
1215 .ident = "EP45-DS5",
1216 .matches = {
1217 DMI_MATCH(DMI_BOARD_VENDOR,
1218 "Gigabyte Technology Co., Ltd."),
1219 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1220 },
1221 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1222 },
1223 { } /* terminate list */
1224 };
1225 #undef ENCODE_BUSDEVFN
1226 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1227 unsigned int val;
1228
1229 if (!dmi)
1230 return false;
1231
1232 val = (unsigned long)dmi->driver_data;
1233
1234 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1235 }
1236
1237 static bool ahci_broken_devslp(struct pci_dev *pdev)
1238 {
1239 /* device with broken DEVSLP but still showing SDS capability */
1240 static const struct pci_device_id ids[] = {
1241 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1242 {}
1243 };
1244
1245 return pci_match_id(ids, pdev);
1246 }
1247
1248 #ifdef CONFIG_ATA_ACPI
1249 static void ahci_gtf_filter_workaround(struct ata_host *host)
1250 {
1251 static const struct dmi_system_id sysids[] = {
1252 /*
1253 * Aspire 3810T issues a bunch of SATA enable commands
1254 * via _GTF including an invalid one and one which is
1255 * rejected by the device. Among the successful ones
1256 * is FPDMA non-zero offset enable which when enabled
1257 * only on the drive side leads to NCQ command
1258 * failures. Filter it out.
1259 */
1260 {
1261 .ident = "Aspire 3810T",
1262 .matches = {
1263 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1264 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1265 },
1266 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1267 },
1268 { }
1269 };
1270 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1271 unsigned int filter;
1272 int i;
1273
1274 if (!dmi)
1275 return;
1276
1277 filter = (unsigned long)dmi->driver_data;
1278 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1279 filter, dmi->ident);
1280
1281 for (i = 0; i < host->n_ports; i++) {
1282 struct ata_port *ap = host->ports[i];
1283 struct ata_link *link;
1284 struct ata_device *dev;
1285
1286 ata_for_each_link(link, ap, EDGE)
1287 ata_for_each_dev(dev, link, ALL)
1288 dev->gtf_filter |= filter;
1289 }
1290 }
1291 #else
1292 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1293 {}
1294 #endif
1295
1296 /*
1297 * ahci_init_msix() only implements single MSI-X support, not multiple
1298 * MSI-X per-port interrupts. This is needed for host controllers that only
1299 * have MSI-X support implemented, but no MSI or intx.
1300 */
1301 static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports,
1302 struct ahci_host_priv *hpriv)
1303 {
1304 int rc, nvec;
1305 struct msix_entry entry = {};
1306
1307 /* Do not init MSI-X if MSI is disabled for the device */
1308 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1309 return -ENODEV;
1310
1311 nvec = pci_msix_vec_count(pdev);
1312 if (nvec < 0)
1313 return nvec;
1314
1315 if (!nvec) {
1316 rc = -ENODEV;
1317 goto fail;
1318 }
1319
1320 /*
1321 * There can be more than one vector (e.g. for error detection or
1322 * hdd hotplug). Only the first vector (entry.entry = 0) is used.
1323 */
1324 rc = pci_enable_msix_exact(pdev, &entry, 1);
1325 if (rc < 0)
1326 goto fail;
1327
1328 hpriv->irq = entry.vector;
1329
1330 return 1;
1331 fail:
1332 dev_err(&pdev->dev,
1333 "failed to enable MSI-X with error %d, # of vectors: %d\n",
1334 rc, nvec);
1335
1336 return rc;
1337 }
1338
1339 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1340 struct ahci_host_priv *hpriv)
1341 {
1342 int rc, nvec;
1343
1344 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1345 return -ENODEV;
1346
1347 nvec = pci_msi_vec_count(pdev);
1348 if (nvec < 0)
1349 return nvec;
1350
1351 /*
1352 * If number of MSIs is less than number of ports then Sharing Last
1353 * Message mode could be enforced. In this case assume that advantage
1354 * of multipe MSIs is negated and use single MSI mode instead.
1355 */
1356 if (nvec < n_ports)
1357 goto single_msi;
1358
1359 rc = pci_enable_msi_exact(pdev, nvec);
1360 if (rc == -ENOSPC)
1361 goto single_msi;
1362 if (rc < 0)
1363 return rc;
1364
1365 /* fallback to single MSI mode if the controller enforced MRSM mode */
1366 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1367 pci_disable_msi(pdev);
1368 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1369 goto single_msi;
1370 }
1371
1372 if (nvec > 1)
1373 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1374
1375 goto out;
1376
1377 single_msi:
1378 nvec = 1;
1379
1380 rc = pci_enable_msi(pdev);
1381 if (rc < 0)
1382 return rc;
1383 out:
1384 hpriv->irq = pdev->irq;
1385
1386 return nvec;
1387 }
1388
1389 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1390 struct ahci_host_priv *hpriv)
1391 {
1392 int nvec;
1393
1394 nvec = ahci_init_msi(pdev, n_ports, hpriv);
1395 if (nvec >= 0)
1396 return nvec;
1397
1398 /*
1399 * Currently, MSI-X support only implements single IRQ mode and
1400 * exists for controllers which can't do other types of IRQ. Only
1401 * set it up if MSI fails.
1402 */
1403 nvec = ahci_init_msix(pdev, n_ports, hpriv);
1404 if (nvec >= 0)
1405 return nvec;
1406
1407 /* lagacy intx interrupts */
1408 pci_intx(pdev, 1);
1409 hpriv->irq = pdev->irq;
1410
1411 return 0;
1412 }
1413
1414 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1415 {
1416 unsigned int board_id = ent->driver_data;
1417 struct ata_port_info pi = ahci_port_info[board_id];
1418 const struct ata_port_info *ppi[] = { &pi, NULL };
1419 struct device *dev = &pdev->dev;
1420 struct ahci_host_priv *hpriv;
1421 struct ata_host *host;
1422 int n_ports, i, rc;
1423 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1424
1425 VPRINTK("ENTER\n");
1426
1427 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1428
1429 ata_print_version_once(&pdev->dev, DRV_VERSION);
1430
1431 /* The AHCI driver can only drive the SATA ports, the PATA driver
1432 can drive them all so if both drivers are selected make sure
1433 AHCI stays out of the way */
1434 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1435 return -ENODEV;
1436
1437 /* Apple BIOS on MCP89 prevents us using AHCI */
1438 if (is_mcp89_apple(pdev))
1439 ahci_mcp89_apple_enable(pdev);
1440
1441 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1442 * At the moment, we can only use the AHCI mode. Let the users know
1443 * that for SAS drives they're out of luck.
1444 */
1445 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1446 dev_info(&pdev->dev,
1447 "PDC42819 can only drive SATA devices with this driver\n");
1448
1449 /* Some devices use non-standard BARs */
1450 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1451 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1452 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1453 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1454 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1455 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1456
1457 /* acquire resources */
1458 rc = pcim_enable_device(pdev);
1459 if (rc)
1460 return rc;
1461
1462 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1463 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1464 u8 map;
1465
1466 /* ICH6s share the same PCI ID for both piix and ahci
1467 * modes. Enabling ahci mode while MAP indicates
1468 * combined mode is a bad idea. Yield to ata_piix.
1469 */
1470 pci_read_config_byte(pdev, ICH_MAP, &map);
1471 if (map & 0x3) {
1472 dev_info(&pdev->dev,
1473 "controller is in combined mode, can't enable AHCI mode\n");
1474 return -ENODEV;
1475 }
1476 }
1477
1478 /* AHCI controllers often implement SFF compatible interface.
1479 * Grab all PCI BARs just in case.
1480 */
1481 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1482 if (rc == -EBUSY)
1483 pcim_pin_device(pdev);
1484 if (rc)
1485 return rc;
1486
1487 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1488 if (!hpriv)
1489 return -ENOMEM;
1490 hpriv->flags |= (unsigned long)pi.private_data;
1491
1492 /* MCP65 revision A1 and A2 can't do MSI */
1493 if (board_id == board_ahci_mcp65 &&
1494 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1495 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1496
1497 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1498 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1499 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1500
1501 /* only some SB600s can do 64bit DMA */
1502 if (ahci_sb600_enable_64bit(pdev))
1503 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1504
1505 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1506
1507 /* must set flag prior to save config in order to take effect */
1508 if (ahci_broken_devslp(pdev))
1509 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1510
1511 /* save initial config */
1512 ahci_pci_save_initial_config(pdev, hpriv);
1513
1514 /* prepare host */
1515 if (hpriv->cap & HOST_CAP_NCQ) {
1516 pi.flags |= ATA_FLAG_NCQ;
1517 /*
1518 * Auto-activate optimization is supposed to be
1519 * supported on all AHCI controllers indicating NCQ
1520 * capability, but it seems to be broken on some
1521 * chipsets including NVIDIAs.
1522 */
1523 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1524 pi.flags |= ATA_FLAG_FPDMA_AA;
1525
1526 /*
1527 * All AHCI controllers should be forward-compatible
1528 * with the new auxiliary field. This code should be
1529 * conditionalized if any buggy AHCI controllers are
1530 * encountered.
1531 */
1532 pi.flags |= ATA_FLAG_FPDMA_AUX;
1533 }
1534
1535 if (hpriv->cap & HOST_CAP_PMP)
1536 pi.flags |= ATA_FLAG_PMP;
1537
1538 ahci_set_em_messages(hpriv, &pi);
1539
1540 if (ahci_broken_system_poweroff(pdev)) {
1541 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1542 dev_info(&pdev->dev,
1543 "quirky BIOS, skipping spindown on poweroff\n");
1544 }
1545
1546 if (ahci_broken_suspend(pdev)) {
1547 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1548 dev_warn(&pdev->dev,
1549 "BIOS update required for suspend/resume\n");
1550 }
1551
1552 if (ahci_broken_online(pdev)) {
1553 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1554 dev_info(&pdev->dev,
1555 "online status unreliable, applying workaround\n");
1556 }
1557
1558 /* CAP.NP sometimes indicate the index of the last enabled
1559 * port, at other times, that of the last possible port, so
1560 * determining the maximum port number requires looking at
1561 * both CAP.NP and port_map.
1562 */
1563 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1564
1565 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1566 if (!host)
1567 return -ENOMEM;
1568 host->private_data = hpriv;
1569
1570 ahci_init_interrupts(pdev, n_ports, hpriv);
1571
1572 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1573 host->flags |= ATA_HOST_PARALLEL_SCAN;
1574 else
1575 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1576
1577 if (pi.flags & ATA_FLAG_EM)
1578 ahci_reset_em(host);
1579
1580 for (i = 0; i < host->n_ports; i++) {
1581 struct ata_port *ap = host->ports[i];
1582
1583 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1584 ata_port_pbar_desc(ap, ahci_pci_bar,
1585 0x100 + ap->port_no * 0x80, "port");
1586
1587 /* set enclosure management message type */
1588 if (ap->flags & ATA_FLAG_EM)
1589 ap->em_message_type = hpriv->em_msg_type;
1590
1591
1592 /* disabled/not-implemented port */
1593 if (!(hpriv->port_map & (1 << i)))
1594 ap->ops = &ata_dummy_port_ops;
1595 }
1596
1597 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1598 ahci_p5wdh_workaround(host);
1599
1600 /* apply gtf filter quirk */
1601 ahci_gtf_filter_workaround(host);
1602
1603 /* initialize adapter */
1604 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1605 if (rc)
1606 return rc;
1607
1608 rc = ahci_pci_reset_controller(host);
1609 if (rc)
1610 return rc;
1611
1612 ahci_pci_init_controller(host);
1613 ahci_pci_print_info(host);
1614
1615 pci_set_master(pdev);
1616
1617 return ahci_host_activate(host, &ahci_sht);
1618 }
1619
1620 module_pci_driver(ahci_pci_driver);
1621
1622 MODULE_AUTHOR("Jeff Garzik");
1623 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1624 MODULE_LICENSE("GPL");
1625 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1626 MODULE_VERSION(DRV_VERSION);
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