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libata: remove ATA_FLAG_LPM
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 };
57
58 enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
63 board_ahci_yes_fbs,
64
65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
67 board_ahci_mcp77,
68 board_ahci_mcp89,
69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
79 };
80
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 #ifdef CONFIG_PM
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
91 #endif
92
93 static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95 };
96
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
100 };
101
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
105 };
106
107 static struct ata_port_operations ahci_sb600_ops = {
108 .inherits = &ahci_ops,
109 .softreset = ahci_sb600_softreset,
110 .pmp_softreset = ahci_sb600_softreset,
111 };
112
113 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114
115 static const struct ata_port_info ahci_port_info[] = {
116 /* by features */
117 [board_ahci] =
118 {
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
123 },
124 [board_ahci_ign_iferr] =
125 {
126 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_nosntf] =
133 {
134 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
140 [board_ahci_yes_fbs] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
147 },
148 /* by chipsets */
149 [board_ahci_mcp65] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
152 AHCI_HFLAG_YES_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp77] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_mcp89] =
167 {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_mv] =
175 {
176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
178 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
182 },
183 [board_ahci_sb600] =
184 {
185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_sb600_ops,
192 },
193 [board_ahci_sb700] = /* for SB700 and SB800 */
194 {
195 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_sb600_ops,
200 },
201 [board_ahci_vt8251] =
202 {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_vt8251_ops,
208 },
209 };
210
211 static const struct pci_device_id ahci_pci_tbl[] = {
212 /* Intel */
213 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
214 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
215 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
216 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
217 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
218 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
219 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
221 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
223 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
224 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
225 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
227 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
228 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
239 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
240 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
241 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
242 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
243 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
244 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
245 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
246 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
248 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
250 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
251 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
252 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
253 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
254 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
259 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
260 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
261 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
262 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
263
264 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
265 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
266 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
267
268 /* ATI */
269 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
270 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
271 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
276
277 /* AMD */
278 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
279 /* AMD is using RAID class only for ahci controllers */
280 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
281 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
282
283 /* VIA */
284 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
285 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
286
287 /* NVIDIA */
288 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
372
373 /* SiS */
374 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
375 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
376 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
377
378 /* Marvell */
379 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
380 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
381 { PCI_DEVICE(0x1b4b, 0x9123),
382 .class = PCI_CLASS_STORAGE_SATA_AHCI,
383 .class_mask = 0xffffff,
384 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
385
386 /* Promise */
387 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
388
389 /* Generic, PCI class code for AHCI */
390 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
391 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
392
393 { } /* terminate list */
394 };
395
396
397 static struct pci_driver ahci_pci_driver = {
398 .name = DRV_NAME,
399 .id_table = ahci_pci_tbl,
400 .probe = ahci_init_one,
401 .remove = ata_pci_remove_one,
402 #ifdef CONFIG_PM
403 .suspend = ahci_pci_device_suspend,
404 .resume = ahci_pci_device_resume,
405 #endif
406 };
407
408 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
409 static int marvell_enable;
410 #else
411 static int marvell_enable = 1;
412 #endif
413 module_param(marvell_enable, int, 0644);
414 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
415
416
417 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
418 struct ahci_host_priv *hpriv)
419 {
420 unsigned int force_port_map = 0;
421 unsigned int mask_port_map = 0;
422
423 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
424 dev_info(&pdev->dev, "JMB361 has only one port\n");
425 force_port_map = 1;
426 }
427
428 /*
429 * Temporary Marvell 6145 hack: PATA port presence
430 * is asserted through the standard AHCI port
431 * presence register, as bit 4 (counting from 0)
432 */
433 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
434 if (pdev->device == 0x6121)
435 mask_port_map = 0x3;
436 else
437 mask_port_map = 0xf;
438 dev_info(&pdev->dev,
439 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
440 }
441
442 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
443 mask_port_map);
444 }
445
446 static int ahci_pci_reset_controller(struct ata_host *host)
447 {
448 struct pci_dev *pdev = to_pci_dev(host->dev);
449
450 ahci_reset_controller(host);
451
452 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
453 struct ahci_host_priv *hpriv = host->private_data;
454 u16 tmp16;
455
456 /* configure PCS */
457 pci_read_config_word(pdev, 0x92, &tmp16);
458 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
459 tmp16 |= hpriv->port_map;
460 pci_write_config_word(pdev, 0x92, tmp16);
461 }
462 }
463
464 return 0;
465 }
466
467 static void ahci_pci_init_controller(struct ata_host *host)
468 {
469 struct ahci_host_priv *hpriv = host->private_data;
470 struct pci_dev *pdev = to_pci_dev(host->dev);
471 void __iomem *port_mmio;
472 u32 tmp;
473 int mv;
474
475 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
476 if (pdev->device == 0x6121)
477 mv = 2;
478 else
479 mv = 4;
480 port_mmio = __ahci_port_base(host, mv);
481
482 writel(0, port_mmio + PORT_IRQ_MASK);
483
484 /* clear port IRQ */
485 tmp = readl(port_mmio + PORT_IRQ_STAT);
486 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
487 if (tmp)
488 writel(tmp, port_mmio + PORT_IRQ_STAT);
489 }
490
491 ahci_init_controller(host);
492 }
493
494 static int ahci_sb600_check_ready(struct ata_link *link)
495 {
496 void __iomem *port_mmio = ahci_port_base(link->ap);
497 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
498 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
499
500 /*
501 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
502 * which can save timeout delay.
503 */
504 if (irq_status & PORT_IRQ_BAD_PMP)
505 return -EIO;
506
507 return ata_check_ready(status);
508 }
509
510 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
511 unsigned long deadline)
512 {
513 struct ata_port *ap = link->ap;
514 void __iomem *port_mmio = ahci_port_base(ap);
515 int pmp = sata_srst_pmp(link);
516 int rc;
517 u32 irq_sts;
518
519 DPRINTK("ENTER\n");
520
521 rc = ahci_do_softreset(link, class, pmp, deadline,
522 ahci_sb600_check_ready);
523
524 /*
525 * Soft reset fails on some ATI chips with IPMS set when PMP
526 * is enabled but SATA HDD/ODD is connected to SATA port,
527 * do soft reset again to port 0.
528 */
529 if (rc == -EIO) {
530 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
531 if (irq_sts & PORT_IRQ_BAD_PMP) {
532 ata_link_printk(link, KERN_WARNING,
533 "applying SB600 PMP SRST workaround "
534 "and retrying\n");
535 rc = ahci_do_softreset(link, class, 0, deadline,
536 ahci_check_ready);
537 }
538 }
539
540 return rc;
541 }
542
543 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
544 unsigned long deadline)
545 {
546 struct ata_port *ap = link->ap;
547 bool online;
548 int rc;
549
550 DPRINTK("ENTER\n");
551
552 ahci_stop_engine(ap);
553
554 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
555 deadline, &online, NULL);
556
557 ahci_start_engine(ap);
558
559 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
560
561 /* vt8251 doesn't clear BSY on signature FIS reception,
562 * request follow-up softreset.
563 */
564 return online ? -EAGAIN : rc;
565 }
566
567 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
568 unsigned long deadline)
569 {
570 struct ata_port *ap = link->ap;
571 struct ahci_port_priv *pp = ap->private_data;
572 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
573 struct ata_taskfile tf;
574 bool online;
575 int rc;
576
577 ahci_stop_engine(ap);
578
579 /* clear D2H reception area to properly wait for D2H FIS */
580 ata_tf_init(link->device, &tf);
581 tf.command = 0x80;
582 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
583
584 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
585 deadline, &online, NULL);
586
587 ahci_start_engine(ap);
588
589 /* The pseudo configuration device on SIMG4726 attached to
590 * ASUS P5W-DH Deluxe doesn't send signature FIS after
591 * hardreset if no device is attached to the first downstream
592 * port && the pseudo device locks up on SRST w/ PMP==0. To
593 * work around this, wait for !BSY only briefly. If BSY isn't
594 * cleared, perform CLO and proceed to IDENTIFY (achieved by
595 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
596 *
597 * Wait for two seconds. Devices attached to downstream port
598 * which can't process the following IDENTIFY after this will
599 * have to be reset again. For most cases, this should
600 * suffice while making probing snappish enough.
601 */
602 if (online) {
603 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
604 ahci_check_ready);
605 if (rc)
606 ahci_kick_engine(ap);
607 }
608 return rc;
609 }
610
611 #ifdef CONFIG_PM
612 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
613 {
614 struct ata_host *host = dev_get_drvdata(&pdev->dev);
615 struct ahci_host_priv *hpriv = host->private_data;
616 void __iomem *mmio = hpriv->mmio;
617 u32 ctl;
618
619 if (mesg.event & PM_EVENT_SUSPEND &&
620 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
621 dev_printk(KERN_ERR, &pdev->dev,
622 "BIOS update required for suspend/resume\n");
623 return -EIO;
624 }
625
626 if (mesg.event & PM_EVENT_SLEEP) {
627 /* AHCI spec rev1.1 section 8.3.3:
628 * Software must disable interrupts prior to requesting a
629 * transition of the HBA to D3 state.
630 */
631 ctl = readl(mmio + HOST_CTL);
632 ctl &= ~HOST_IRQ_EN;
633 writel(ctl, mmio + HOST_CTL);
634 readl(mmio + HOST_CTL); /* flush */
635 }
636
637 return ata_pci_device_suspend(pdev, mesg);
638 }
639
640 static int ahci_pci_device_resume(struct pci_dev *pdev)
641 {
642 struct ata_host *host = dev_get_drvdata(&pdev->dev);
643 int rc;
644
645 rc = ata_pci_device_do_resume(pdev);
646 if (rc)
647 return rc;
648
649 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
650 rc = ahci_pci_reset_controller(host);
651 if (rc)
652 return rc;
653
654 ahci_pci_init_controller(host);
655 }
656
657 ata_host_resume(host);
658
659 return 0;
660 }
661 #endif
662
663 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
664 {
665 int rc;
666
667 if (using_dac &&
668 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
669 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
670 if (rc) {
671 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
672 if (rc) {
673 dev_printk(KERN_ERR, &pdev->dev,
674 "64-bit DMA enable failed\n");
675 return rc;
676 }
677 }
678 } else {
679 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
680 if (rc) {
681 dev_printk(KERN_ERR, &pdev->dev,
682 "32-bit DMA enable failed\n");
683 return rc;
684 }
685 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
686 if (rc) {
687 dev_printk(KERN_ERR, &pdev->dev,
688 "32-bit consistent DMA enable failed\n");
689 return rc;
690 }
691 }
692 return 0;
693 }
694
695 static void ahci_pci_print_info(struct ata_host *host)
696 {
697 struct pci_dev *pdev = to_pci_dev(host->dev);
698 u16 cc;
699 const char *scc_s;
700
701 pci_read_config_word(pdev, 0x0a, &cc);
702 if (cc == PCI_CLASS_STORAGE_IDE)
703 scc_s = "IDE";
704 else if (cc == PCI_CLASS_STORAGE_SATA)
705 scc_s = "SATA";
706 else if (cc == PCI_CLASS_STORAGE_RAID)
707 scc_s = "RAID";
708 else
709 scc_s = "unknown";
710
711 ahci_print_info(host, scc_s);
712 }
713
714 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
715 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
716 * support PMP and the 4726 either directly exports the device
717 * attached to the first downstream port or acts as a hardware storage
718 * controller and emulate a single ATA device (can be RAID 0/1 or some
719 * other configuration).
720 *
721 * When there's no device attached to the first downstream port of the
722 * 4726, "Config Disk" appears, which is a pseudo ATA device to
723 * configure the 4726. However, ATA emulation of the device is very
724 * lame. It doesn't send signature D2H Reg FIS after the initial
725 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
726 *
727 * The following function works around the problem by always using
728 * hardreset on the port and not depending on receiving signature FIS
729 * afterward. If signature FIS isn't received soon, ATA class is
730 * assumed without follow-up softreset.
731 */
732 static void ahci_p5wdh_workaround(struct ata_host *host)
733 {
734 static struct dmi_system_id sysids[] = {
735 {
736 .ident = "P5W DH Deluxe",
737 .matches = {
738 DMI_MATCH(DMI_SYS_VENDOR,
739 "ASUSTEK COMPUTER INC"),
740 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
741 },
742 },
743 { }
744 };
745 struct pci_dev *pdev = to_pci_dev(host->dev);
746
747 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
748 dmi_check_system(sysids)) {
749 struct ata_port *ap = host->ports[1];
750
751 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
752 "Deluxe on-board SIMG4726 workaround\n");
753
754 ap->ops = &ahci_p5wdh_ops;
755 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
756 }
757 }
758
759 /* only some SB600 ahci controllers can do 64bit DMA */
760 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
761 {
762 static const struct dmi_system_id sysids[] = {
763 /*
764 * The oldest version known to be broken is 0901 and
765 * working is 1501 which was released on 2007-10-26.
766 * Enable 64bit DMA on 1501 and anything newer.
767 *
768 * Please read bko#9412 for more info.
769 */
770 {
771 .ident = "ASUS M2A-VM",
772 .matches = {
773 DMI_MATCH(DMI_BOARD_VENDOR,
774 "ASUSTeK Computer INC."),
775 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
776 },
777 .driver_data = "20071026", /* yyyymmdd */
778 },
779 /*
780 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
781 * support 64bit DMA.
782 *
783 * BIOS versions earlier than 1.5 had the Manufacturer DMI
784 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
785 * This spelling mistake was fixed in BIOS version 1.5, so
786 * 1.5 and later have the Manufacturer as
787 * "MICRO-STAR INTERNATIONAL CO.,LTD".
788 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
789 *
790 * BIOS versions earlier than 1.9 had a Board Product Name
791 * DMI field of "MS-7376". This was changed to be
792 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
793 * match on DMI_BOARD_NAME of "MS-7376".
794 */
795 {
796 .ident = "MSI K9A2 Platinum",
797 .matches = {
798 DMI_MATCH(DMI_BOARD_VENDOR,
799 "MICRO-STAR INTER"),
800 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
801 },
802 },
803 { }
804 };
805 const struct dmi_system_id *match;
806 int year, month, date;
807 char buf[9];
808
809 match = dmi_first_match(sysids);
810 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
811 !match)
812 return false;
813
814 if (!match->driver_data)
815 goto enable_64bit;
816
817 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
818 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
819
820 if (strcmp(buf, match->driver_data) >= 0)
821 goto enable_64bit;
822 else {
823 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
824 "forcing 32bit DMA, update BIOS\n", match->ident);
825 return false;
826 }
827
828 enable_64bit:
829 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
830 match->ident);
831 return true;
832 }
833
834 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
835 {
836 static const struct dmi_system_id broken_systems[] = {
837 {
838 .ident = "HP Compaq nx6310",
839 .matches = {
840 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
841 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
842 },
843 /* PCI slot number of the controller */
844 .driver_data = (void *)0x1FUL,
845 },
846 {
847 .ident = "HP Compaq 6720s",
848 .matches = {
849 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
850 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
851 },
852 /* PCI slot number of the controller */
853 .driver_data = (void *)0x1FUL,
854 },
855
856 { } /* terminate list */
857 };
858 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
859
860 if (dmi) {
861 unsigned long slot = (unsigned long)dmi->driver_data;
862 /* apply the quirk only to on-board controllers */
863 return slot == PCI_SLOT(pdev->devfn);
864 }
865
866 return false;
867 }
868
869 static bool ahci_broken_suspend(struct pci_dev *pdev)
870 {
871 static const struct dmi_system_id sysids[] = {
872 /*
873 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
874 * to the harddisk doesn't become online after
875 * resuming from STR. Warn and fail suspend.
876 *
877 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
878 *
879 * Use dates instead of versions to match as HP is
880 * apparently recycling both product and version
881 * strings.
882 *
883 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
884 */
885 {
886 .ident = "dv4",
887 .matches = {
888 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
889 DMI_MATCH(DMI_PRODUCT_NAME,
890 "HP Pavilion dv4 Notebook PC"),
891 },
892 .driver_data = "20090105", /* F.30 */
893 },
894 {
895 .ident = "dv5",
896 .matches = {
897 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
898 DMI_MATCH(DMI_PRODUCT_NAME,
899 "HP Pavilion dv5 Notebook PC"),
900 },
901 .driver_data = "20090506", /* F.16 */
902 },
903 {
904 .ident = "dv6",
905 .matches = {
906 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
907 DMI_MATCH(DMI_PRODUCT_NAME,
908 "HP Pavilion dv6 Notebook PC"),
909 },
910 .driver_data = "20090423", /* F.21 */
911 },
912 {
913 .ident = "HDX18",
914 .matches = {
915 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
916 DMI_MATCH(DMI_PRODUCT_NAME,
917 "HP HDX18 Notebook PC"),
918 },
919 .driver_data = "20090430", /* F.23 */
920 },
921 /*
922 * Acer eMachines G725 has the same problem. BIOS
923 * V1.03 is known to be broken. V3.04 is known to
924 * work. Inbetween, there are V1.06, V2.06 and V3.03
925 * that we don't have much idea about. For now,
926 * blacklist anything older than V3.04.
927 *
928 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
929 */
930 {
931 .ident = "G725",
932 .matches = {
933 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
934 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
935 },
936 .driver_data = "20091216", /* V3.04 */
937 },
938 { } /* terminate list */
939 };
940 const struct dmi_system_id *dmi = dmi_first_match(sysids);
941 int year, month, date;
942 char buf[9];
943
944 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
945 return false;
946
947 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
948 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
949
950 return strcmp(buf, dmi->driver_data) < 0;
951 }
952
953 static bool ahci_broken_online(struct pci_dev *pdev)
954 {
955 #define ENCODE_BUSDEVFN(bus, slot, func) \
956 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
957 static const struct dmi_system_id sysids[] = {
958 /*
959 * There are several gigabyte boards which use
960 * SIMG5723s configured as hardware RAID. Certain
961 * 5723 firmware revisions shipped there keep the link
962 * online but fail to answer properly to SRST or
963 * IDENTIFY when no device is attached downstream
964 * causing libata to retry quite a few times leading
965 * to excessive detection delay.
966 *
967 * As these firmwares respond to the second reset try
968 * with invalid device signature, considering unknown
969 * sig as offline works around the problem acceptably.
970 */
971 {
972 .ident = "EP45-DQ6",
973 .matches = {
974 DMI_MATCH(DMI_BOARD_VENDOR,
975 "Gigabyte Technology Co., Ltd."),
976 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
977 },
978 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
979 },
980 {
981 .ident = "EP45-DS5",
982 .matches = {
983 DMI_MATCH(DMI_BOARD_VENDOR,
984 "Gigabyte Technology Co., Ltd."),
985 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
986 },
987 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
988 },
989 { } /* terminate list */
990 };
991 #undef ENCODE_BUSDEVFN
992 const struct dmi_system_id *dmi = dmi_first_match(sysids);
993 unsigned int val;
994
995 if (!dmi)
996 return false;
997
998 val = (unsigned long)dmi->driver_data;
999
1000 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1001 }
1002
1003 #ifdef CONFIG_ATA_ACPI
1004 static void ahci_gtf_filter_workaround(struct ata_host *host)
1005 {
1006 static const struct dmi_system_id sysids[] = {
1007 /*
1008 * Aspire 3810T issues a bunch of SATA enable commands
1009 * via _GTF including an invalid one and one which is
1010 * rejected by the device. Among the successful ones
1011 * is FPDMA non-zero offset enable which when enabled
1012 * only on the drive side leads to NCQ command
1013 * failures. Filter it out.
1014 */
1015 {
1016 .ident = "Aspire 3810T",
1017 .matches = {
1018 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1019 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1020 },
1021 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1022 },
1023 { }
1024 };
1025 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1026 unsigned int filter;
1027 int i;
1028
1029 if (!dmi)
1030 return;
1031
1032 filter = (unsigned long)dmi->driver_data;
1033 dev_printk(KERN_INFO, host->dev,
1034 "applying extra ACPI _GTF filter 0x%x for %s\n",
1035 filter, dmi->ident);
1036
1037 for (i = 0; i < host->n_ports; i++) {
1038 struct ata_port *ap = host->ports[i];
1039 struct ata_link *link;
1040 struct ata_device *dev;
1041
1042 ata_for_each_link(link, ap, EDGE)
1043 ata_for_each_dev(dev, link, ALL)
1044 dev->gtf_filter |= filter;
1045 }
1046 }
1047 #else
1048 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1049 {}
1050 #endif
1051
1052 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1053 {
1054 static int printed_version;
1055 unsigned int board_id = ent->driver_data;
1056 struct ata_port_info pi = ahci_port_info[board_id];
1057 const struct ata_port_info *ppi[] = { &pi, NULL };
1058 struct device *dev = &pdev->dev;
1059 struct ahci_host_priv *hpriv;
1060 struct ata_host *host;
1061 int n_ports, i, rc;
1062
1063 VPRINTK("ENTER\n");
1064
1065 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1066
1067 if (!printed_version++)
1068 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1069
1070 /* The AHCI driver can only drive the SATA ports, the PATA driver
1071 can drive them all so if both drivers are selected make sure
1072 AHCI stays out of the way */
1073 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1074 return -ENODEV;
1075
1076 /*
1077 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1078 * ahci, use ata_generic instead.
1079 */
1080 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1081 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1082 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1083 pdev->subsystem_device == 0xcb89)
1084 return -ENODEV;
1085
1086 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1087 * At the moment, we can only use the AHCI mode. Let the users know
1088 * that for SAS drives they're out of luck.
1089 */
1090 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1091 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1092 "can only drive SATA devices with this driver\n");
1093
1094 /* acquire resources */
1095 rc = pcim_enable_device(pdev);
1096 if (rc)
1097 return rc;
1098
1099 /* AHCI controllers often implement SFF compatible interface.
1100 * Grab all PCI BARs just in case.
1101 */
1102 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1103 if (rc == -EBUSY)
1104 pcim_pin_device(pdev);
1105 if (rc)
1106 return rc;
1107
1108 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1109 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1110 u8 map;
1111
1112 /* ICH6s share the same PCI ID for both piix and ahci
1113 * modes. Enabling ahci mode while MAP indicates
1114 * combined mode is a bad idea. Yield to ata_piix.
1115 */
1116 pci_read_config_byte(pdev, ICH_MAP, &map);
1117 if (map & 0x3) {
1118 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1119 "combined mode, can't enable AHCI mode\n");
1120 return -ENODEV;
1121 }
1122 }
1123
1124 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1125 if (!hpriv)
1126 return -ENOMEM;
1127 hpriv->flags |= (unsigned long)pi.private_data;
1128
1129 /* MCP65 revision A1 and A2 can't do MSI */
1130 if (board_id == board_ahci_mcp65 &&
1131 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1132 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1133
1134 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1135 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1136 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1137
1138 /* only some SB600s can do 64bit DMA */
1139 if (ahci_sb600_enable_64bit(pdev))
1140 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1141
1142 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1143 pci_intx(pdev, 1);
1144
1145 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1146
1147 /* save initial config */
1148 ahci_pci_save_initial_config(pdev, hpriv);
1149
1150 /* prepare host */
1151 if (hpriv->cap & HOST_CAP_NCQ) {
1152 pi.flags |= ATA_FLAG_NCQ;
1153 /*
1154 * Auto-activate optimization is supposed to be
1155 * supported on all AHCI controllers indicating NCQ
1156 * capability, but it seems to be broken on some
1157 * chipsets including NVIDIAs.
1158 */
1159 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1160 pi.flags |= ATA_FLAG_FPDMA_AA;
1161 }
1162
1163 if (hpriv->cap & HOST_CAP_PMP)
1164 pi.flags |= ATA_FLAG_PMP;
1165
1166 ahci_set_em_messages(hpriv, &pi);
1167
1168 if (ahci_broken_system_poweroff(pdev)) {
1169 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1170 dev_info(&pdev->dev,
1171 "quirky BIOS, skipping spindown on poweroff\n");
1172 }
1173
1174 if (ahci_broken_suspend(pdev)) {
1175 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1176 dev_printk(KERN_WARNING, &pdev->dev,
1177 "BIOS update required for suspend/resume\n");
1178 }
1179
1180 if (ahci_broken_online(pdev)) {
1181 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1182 dev_info(&pdev->dev,
1183 "online status unreliable, applying workaround\n");
1184 }
1185
1186 /* CAP.NP sometimes indicate the index of the last enabled
1187 * port, at other times, that of the last possible port, so
1188 * determining the maximum port number requires looking at
1189 * both CAP.NP and port_map.
1190 */
1191 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1192
1193 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1194 if (!host)
1195 return -ENOMEM;
1196 host->private_data = hpriv;
1197
1198 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1199 host->flags |= ATA_HOST_PARALLEL_SCAN;
1200 else
1201 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1202
1203 if (pi.flags & ATA_FLAG_EM)
1204 ahci_reset_em(host);
1205
1206 for (i = 0; i < host->n_ports; i++) {
1207 struct ata_port *ap = host->ports[i];
1208
1209 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1210 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1211 0x100 + ap->port_no * 0x80, "port");
1212
1213 /* set enclosure management message type */
1214 if (ap->flags & ATA_FLAG_EM)
1215 ap->em_message_type = hpriv->em_msg_type;
1216
1217
1218 /* disabled/not-implemented port */
1219 if (!(hpriv->port_map & (1 << i)))
1220 ap->ops = &ata_dummy_port_ops;
1221 }
1222
1223 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1224 ahci_p5wdh_workaround(host);
1225
1226 /* apply gtf filter quirk */
1227 ahci_gtf_filter_workaround(host);
1228
1229 /* initialize adapter */
1230 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1231 if (rc)
1232 return rc;
1233
1234 rc = ahci_pci_reset_controller(host);
1235 if (rc)
1236 return rc;
1237
1238 ahci_pci_init_controller(host);
1239 ahci_pci_print_info(host);
1240
1241 pci_set_master(pdev);
1242 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1243 &ahci_sht);
1244 }
1245
1246 static int __init ahci_init(void)
1247 {
1248 return pci_register_driver(&ahci_pci_driver);
1249 }
1250
1251 static void __exit ahci_exit(void)
1252 {
1253 pci_unregister_driver(&ahci_pci_driver);
1254 }
1255
1256
1257 MODULE_AUTHOR("Jeff Garzik");
1258 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1259 MODULE_LICENSE("GPL");
1260 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1261 MODULE_VERSION(DRV_VERSION);
1262
1263 module_init(ahci_init);
1264 module_exit(ahci_exit);
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