2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.3"
55 AHCI_MAX_SG
= 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY
= 0xffffffff,
57 AHCI_USE_CLUSTERING
= 1,
60 AHCI_CMD_SLOT_SZ
= AHCI_MAX_CMDS
* AHCI_CMD_SZ
,
62 AHCI_CMD_TBL_CDB
= 0x40,
63 AHCI_CMD_TBL_HDR_SZ
= 0x80,
64 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR_SZ
+ (AHCI_MAX_SG
* 16),
65 AHCI_CMD_TBL_AR_SZ
= AHCI_CMD_TBL_SZ
* AHCI_MAX_CMDS
,
66 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_AR_SZ
+
68 AHCI_IRQ_ON_SG
= (1 << 31),
69 AHCI_CMD_ATAPI
= (1 << 5),
70 AHCI_CMD_WRITE
= (1 << 6),
71 AHCI_CMD_PREFETCH
= (1 << 7),
72 AHCI_CMD_RESET
= (1 << 8),
73 AHCI_CMD_CLR_BUSY
= (1 << 10),
75 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB
= 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK
= 0x60, /* offset of Unknown FIS data */
81 board_ahci_vt8251
= 2,
82 board_ahci_ign_iferr
= 3,
86 /* global controller registers */
87 HOST_CAP
= 0x00, /* host capabilities */
88 HOST_CTL
= 0x04, /* global host control */
89 HOST_IRQ_STAT
= 0x08, /* interrupt status */
90 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
91 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
94 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
95 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
96 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
99 HOST_CAP_SSC
= (1 << 14), /* Slumber capable */
100 HOST_CAP_CLO
= (1 << 24), /* Command List Override support */
101 HOST_CAP_SSS
= (1 << 27), /* Staggered Spin-up */
102 HOST_CAP_NCQ
= (1 << 30), /* Native Command Queueing */
103 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
105 /* registers for each SATA port */
106 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
107 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
108 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
109 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
110 PORT_IRQ_STAT
= 0x10, /* interrupt status */
111 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
112 PORT_CMD
= 0x18, /* port command */
113 PORT_TFDATA
= 0x20, /* taskfile data */
114 PORT_SIG
= 0x24, /* device TF signature */
115 PORT_CMD_ISSUE
= 0x38, /* command issue */
116 PORT_SCR
= 0x28, /* SATA phy register block */
117 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
122 /* PORT_IRQ_{STAT,MASK} bits */
123 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
124 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
125 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
126 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
127 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
128 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
129 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
130 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
132 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
133 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
134 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
135 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
136 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
137 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
138 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
139 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
140 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
142 PORT_IRQ_FREEZE
= PORT_IRQ_HBUS_ERR
|
147 PORT_IRQ_ERROR
= PORT_IRQ_FREEZE
|
149 PORT_IRQ_HBUS_DATA_ERR
,
150 DEF_PORT_IRQ
= PORT_IRQ_ERROR
| PORT_IRQ_SG_DONE
|
151 PORT_IRQ_SDB_FIS
| PORT_IRQ_DMAS_FIS
|
152 PORT_IRQ_PIOS_FIS
| PORT_IRQ_D2H_REG_FIS
,
155 PORT_CMD_ATAPI
= (1 << 24), /* Device is ATAPI */
156 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
157 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
158 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
159 PORT_CMD_CLO
= (1 << 3), /* Command list override */
160 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
161 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
162 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
164 PORT_CMD_ICC_MASK
= (0xf << 28), /* i/f ICC state mask */
165 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
166 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
167 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
170 AHCI_FLAG_NO_NCQ
= (1 << 24),
171 AHCI_FLAG_IGN_IRQ_IF_ERR
= (1 << 25), /* ignore IRQ_IF_ERR */
172 AHCI_FLAG_HONOR_PI
= (1 << 26), /* honor PORTS_IMPL */
173 AHCI_FLAG_IGN_SERR_INTERNAL
= (1 << 27), /* ignore SERR_INTERNAL */
174 AHCI_FLAG_32BIT_ONLY
= (1 << 28), /* force 32bit */
175 AHCI_FLAG_MV_PATA
= (1 << 29), /* PATA port */
176 AHCI_FLAG_NO_MSI
= (1 << 30), /* no PCI MSI */
178 AHCI_FLAG_COMMON
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
179 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
180 ATA_FLAG_SKIP_D2H_BSY
|
184 struct ahci_cmd_hdr
{
199 struct ahci_host_priv
{
200 u32 cap
; /* cap to use */
201 u32 port_map
; /* port map to use */
202 u32 saved_cap
; /* saved initial cap */
203 u32 saved_port_map
; /* saved initial port_map */
206 struct ahci_port_priv
{
207 struct ahci_cmd_hdr
*cmd_slot
;
208 dma_addr_t cmd_slot_dma
;
210 dma_addr_t cmd_tbl_dma
;
212 dma_addr_t rx_fis_dma
;
213 /* for NCQ spurious interrupt analysis */
214 unsigned int ncq_saw_d2h
:1;
215 unsigned int ncq_saw_dmas
:1;
216 unsigned int ncq_saw_sdb
:1;
219 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
220 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
221 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
222 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
);
223 static void ahci_irq_clear(struct ata_port
*ap
);
224 static int ahci_port_start(struct ata_port
*ap
);
225 static void ahci_port_stop(struct ata_port
*ap
);
226 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
227 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
228 static u8
ahci_check_status(struct ata_port
*ap
);
229 static void ahci_freeze(struct ata_port
*ap
);
230 static void ahci_thaw(struct ata_port
*ap
);
231 static void ahci_error_handler(struct ata_port
*ap
);
232 static void ahci_vt8251_error_handler(struct ata_port
*ap
);
233 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
);
234 static int ahci_port_resume(struct ata_port
*ap
);
235 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_tbl
);
236 static void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, unsigned int tag
,
239 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
);
240 static int ahci_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
);
241 static int ahci_pci_device_resume(struct pci_dev
*pdev
);
244 static struct scsi_host_template ahci_sht
= {
245 .module
= THIS_MODULE
,
247 .ioctl
= ata_scsi_ioctl
,
248 .queuecommand
= ata_scsi_queuecmd
,
249 .change_queue_depth
= ata_scsi_change_queue_depth
,
250 .can_queue
= AHCI_MAX_CMDS
- 1,
251 .this_id
= ATA_SHT_THIS_ID
,
252 .sg_tablesize
= AHCI_MAX_SG
,
253 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
254 .emulated
= ATA_SHT_EMULATED
,
255 .use_clustering
= AHCI_USE_CLUSTERING
,
256 .proc_name
= DRV_NAME
,
257 .dma_boundary
= AHCI_DMA_BOUNDARY
,
258 .slave_configure
= ata_scsi_slave_config
,
259 .slave_destroy
= ata_scsi_slave_destroy
,
260 .bios_param
= ata_std_bios_param
,
263 static const struct ata_port_operations ahci_ops
= {
264 .port_disable
= ata_port_disable
,
266 .check_status
= ahci_check_status
,
267 .check_altstatus
= ahci_check_status
,
268 .dev_select
= ata_noop_dev_select
,
270 .tf_read
= ahci_tf_read
,
272 .qc_prep
= ahci_qc_prep
,
273 .qc_issue
= ahci_qc_issue
,
275 .irq_clear
= ahci_irq_clear
,
276 .irq_on
= ata_dummy_irq_on
,
277 .irq_ack
= ata_dummy_irq_ack
,
279 .scr_read
= ahci_scr_read
,
280 .scr_write
= ahci_scr_write
,
282 .freeze
= ahci_freeze
,
285 .error_handler
= ahci_error_handler
,
286 .post_internal_cmd
= ahci_post_internal_cmd
,
289 .port_suspend
= ahci_port_suspend
,
290 .port_resume
= ahci_port_resume
,
293 .port_start
= ahci_port_start
,
294 .port_stop
= ahci_port_stop
,
297 static const struct ata_port_operations ahci_vt8251_ops
= {
298 .port_disable
= ata_port_disable
,
300 .check_status
= ahci_check_status
,
301 .check_altstatus
= ahci_check_status
,
302 .dev_select
= ata_noop_dev_select
,
304 .tf_read
= ahci_tf_read
,
306 .qc_prep
= ahci_qc_prep
,
307 .qc_issue
= ahci_qc_issue
,
309 .irq_clear
= ahci_irq_clear
,
310 .irq_on
= ata_dummy_irq_on
,
311 .irq_ack
= ata_dummy_irq_ack
,
313 .scr_read
= ahci_scr_read
,
314 .scr_write
= ahci_scr_write
,
316 .freeze
= ahci_freeze
,
319 .error_handler
= ahci_vt8251_error_handler
,
320 .post_internal_cmd
= ahci_post_internal_cmd
,
323 .port_suspend
= ahci_port_suspend
,
324 .port_resume
= ahci_port_resume
,
327 .port_start
= ahci_port_start
,
328 .port_stop
= ahci_port_stop
,
331 static const struct ata_port_info ahci_port_info
[] = {
334 .flags
= AHCI_FLAG_COMMON
,
335 .pio_mask
= 0x1f, /* pio0-4 */
336 .udma_mask
= ATA_UDMA6
,
337 .port_ops
= &ahci_ops
,
341 .flags
= AHCI_FLAG_COMMON
| AHCI_FLAG_HONOR_PI
,
342 .pio_mask
= 0x1f, /* pio0-4 */
343 .udma_mask
= ATA_UDMA6
,
344 .port_ops
= &ahci_ops
,
346 /* board_ahci_vt8251 */
348 .flags
= AHCI_FLAG_COMMON
| ATA_FLAG_HRST_TO_RESUME
|
350 .pio_mask
= 0x1f, /* pio0-4 */
351 .udma_mask
= ATA_UDMA6
,
352 .port_ops
= &ahci_vt8251_ops
,
354 /* board_ahci_ign_iferr */
356 .flags
= AHCI_FLAG_COMMON
| AHCI_FLAG_IGN_IRQ_IF_ERR
,
357 .pio_mask
= 0x1f, /* pio0-4 */
358 .udma_mask
= ATA_UDMA6
,
359 .port_ops
= &ahci_ops
,
361 /* board_ahci_sb600 */
363 .flags
= AHCI_FLAG_COMMON
|
364 AHCI_FLAG_IGN_SERR_INTERNAL
|
365 AHCI_FLAG_32BIT_ONLY
,
366 .pio_mask
= 0x1f, /* pio0-4 */
367 .udma_mask
= ATA_UDMA6
,
368 .port_ops
= &ahci_ops
,
373 .flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
374 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
375 ATA_FLAG_SKIP_D2H_BSY
| AHCI_FLAG_HONOR_PI
|
376 AHCI_FLAG_NO_NCQ
| AHCI_FLAG_NO_MSI
|
378 .pio_mask
= 0x1f, /* pio0-4 */
379 .udma_mask
= ATA_UDMA6
,
380 .port_ops
= &ahci_ops
,
384 static const struct pci_device_id ahci_pci_tbl
[] = {
386 { PCI_VDEVICE(INTEL
, 0x2652), board_ahci
}, /* ICH6 */
387 { PCI_VDEVICE(INTEL
, 0x2653), board_ahci
}, /* ICH6M */
388 { PCI_VDEVICE(INTEL
, 0x27c1), board_ahci
}, /* ICH7 */
389 { PCI_VDEVICE(INTEL
, 0x27c5), board_ahci
}, /* ICH7M */
390 { PCI_VDEVICE(INTEL
, 0x27c3), board_ahci
}, /* ICH7R */
391 { PCI_VDEVICE(AL
, 0x5288), board_ahci_ign_iferr
}, /* ULi M5288 */
392 { PCI_VDEVICE(INTEL
, 0x2681), board_ahci
}, /* ESB2 */
393 { PCI_VDEVICE(INTEL
, 0x2682), board_ahci
}, /* ESB2 */
394 { PCI_VDEVICE(INTEL
, 0x2683), board_ahci
}, /* ESB2 */
395 { PCI_VDEVICE(INTEL
, 0x27c6), board_ahci
}, /* ICH7-M DH */
396 { PCI_VDEVICE(INTEL
, 0x2821), board_ahci_pi
}, /* ICH8 */
397 { PCI_VDEVICE(INTEL
, 0x2822), board_ahci_pi
}, /* ICH8 */
398 { PCI_VDEVICE(INTEL
, 0x2824), board_ahci_pi
}, /* ICH8 */
399 { PCI_VDEVICE(INTEL
, 0x2829), board_ahci_pi
}, /* ICH8M */
400 { PCI_VDEVICE(INTEL
, 0x282a), board_ahci_pi
}, /* ICH8M */
401 { PCI_VDEVICE(INTEL
, 0x2922), board_ahci_pi
}, /* ICH9 */
402 { PCI_VDEVICE(INTEL
, 0x2923), board_ahci_pi
}, /* ICH9 */
403 { PCI_VDEVICE(INTEL
, 0x2924), board_ahci_pi
}, /* ICH9 */
404 { PCI_VDEVICE(INTEL
, 0x2925), board_ahci_pi
}, /* ICH9 */
405 { PCI_VDEVICE(INTEL
, 0x2927), board_ahci_pi
}, /* ICH9 */
406 { PCI_VDEVICE(INTEL
, 0x2929), board_ahci_pi
}, /* ICH9M */
407 { PCI_VDEVICE(INTEL
, 0x292a), board_ahci_pi
}, /* ICH9M */
408 { PCI_VDEVICE(INTEL
, 0x292b), board_ahci_pi
}, /* ICH9M */
409 { PCI_VDEVICE(INTEL
, 0x292c), board_ahci_pi
}, /* ICH9M */
410 { PCI_VDEVICE(INTEL
, 0x292f), board_ahci_pi
}, /* ICH9M */
411 { PCI_VDEVICE(INTEL
, 0x294d), board_ahci_pi
}, /* ICH9 */
412 { PCI_VDEVICE(INTEL
, 0x294e), board_ahci_pi
}, /* ICH9M */
414 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
415 { PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
,
416 PCI_CLASS_STORAGE_SATA_AHCI
, 0xffffff, board_ahci_ign_iferr
},
419 { PCI_VDEVICE(ATI
, 0x4380), board_ahci_sb600
}, /* ATI SB600 */
420 { PCI_VDEVICE(ATI
, 0x4390), board_ahci_sb600
}, /* ATI SB700 */
423 { PCI_VDEVICE(VIA
, 0x3349), board_ahci_vt8251
}, /* VIA VT8251 */
424 { PCI_VDEVICE(VIA
, 0x6287), board_ahci_vt8251
}, /* VIA VT8251 */
427 { PCI_VDEVICE(NVIDIA
, 0x044c), board_ahci
}, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA
, 0x044d), board_ahci
}, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA
, 0x044e), board_ahci
}, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA
, 0x044f), board_ahci
}, /* MCP65 */
431 { PCI_VDEVICE(NVIDIA
, 0x045c), board_ahci
}, /* MCP65 */
432 { PCI_VDEVICE(NVIDIA
, 0x045d), board_ahci
}, /* MCP65 */
433 { PCI_VDEVICE(NVIDIA
, 0x045e), board_ahci
}, /* MCP65 */
434 { PCI_VDEVICE(NVIDIA
, 0x045f), board_ahci
}, /* MCP65 */
435 { PCI_VDEVICE(NVIDIA
, 0x0550), board_ahci
}, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA
, 0x0551), board_ahci
}, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA
, 0x0552), board_ahci
}, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA
, 0x0553), board_ahci
}, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA
, 0x0554), board_ahci
}, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA
, 0x0555), board_ahci
}, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA
, 0x0556), board_ahci
}, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA
, 0x0557), board_ahci
}, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA
, 0x0558), board_ahci
}, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA
, 0x0559), board_ahci
}, /* MCP67 */
445 { PCI_VDEVICE(NVIDIA
, 0x055a), board_ahci
}, /* MCP67 */
446 { PCI_VDEVICE(NVIDIA
, 0x055b), board_ahci
}, /* MCP67 */
447 { PCI_VDEVICE(NVIDIA
, 0x07f0), board_ahci
}, /* MCP73 */
448 { PCI_VDEVICE(NVIDIA
, 0x07f1), board_ahci
}, /* MCP73 */
449 { PCI_VDEVICE(NVIDIA
, 0x07f2), board_ahci
}, /* MCP73 */
450 { PCI_VDEVICE(NVIDIA
, 0x07f3), board_ahci
}, /* MCP73 */
451 { PCI_VDEVICE(NVIDIA
, 0x07f4), board_ahci
}, /* MCP73 */
452 { PCI_VDEVICE(NVIDIA
, 0x07f5), board_ahci
}, /* MCP73 */
453 { PCI_VDEVICE(NVIDIA
, 0x07f6), board_ahci
}, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA
, 0x07f7), board_ahci
}, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA
, 0x07f8), board_ahci
}, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA
, 0x07f9), board_ahci
}, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA
, 0x07fa), board_ahci
}, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA
, 0x07fb), board_ahci
}, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA
, 0x0ad0), board_ahci
}, /* MCP77 */
460 { PCI_VDEVICE(NVIDIA
, 0x0ad1), board_ahci
}, /* MCP77 */
461 { PCI_VDEVICE(NVIDIA
, 0x0ad2), board_ahci
}, /* MCP77 */
462 { PCI_VDEVICE(NVIDIA
, 0x0ad3), board_ahci
}, /* MCP77 */
463 { PCI_VDEVICE(NVIDIA
, 0x0ad4), board_ahci
}, /* MCP77 */
464 { PCI_VDEVICE(NVIDIA
, 0x0ad5), board_ahci
}, /* MCP77 */
465 { PCI_VDEVICE(NVIDIA
, 0x0ad6), board_ahci
}, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA
, 0x0ad7), board_ahci
}, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA
, 0x0ad8), board_ahci
}, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA
, 0x0ad9), board_ahci
}, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA
, 0x0ada), board_ahci
}, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA
, 0x0adb), board_ahci
}, /* MCP77 */
473 { PCI_VDEVICE(SI
, 0x1184), board_ahci
}, /* SiS 966 */
474 { PCI_VDEVICE(SI
, 0x1185), board_ahci
}, /* SiS 966 */
475 { PCI_VDEVICE(SI
, 0x0186), board_ahci
}, /* SiS 968 */
478 { PCI_VDEVICE(MARVELL
, 0x6145), board_ahci_mv
}, /* 6145 */
480 /* Generic, PCI class code for AHCI */
481 { PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
,
482 PCI_CLASS_STORAGE_SATA_AHCI
, 0xffffff, board_ahci
},
484 { } /* terminate list */
488 static struct pci_driver ahci_pci_driver
= {
490 .id_table
= ahci_pci_tbl
,
491 .probe
= ahci_init_one
,
492 .remove
= ata_pci_remove_one
,
494 .suspend
= ahci_pci_device_suspend
,
495 .resume
= ahci_pci_device_resume
,
500 static inline int ahci_nr_ports(u32 cap
)
502 return (cap
& 0x1f) + 1;
505 static inline void __iomem
*__ahci_port_base(struct ata_host
*host
,
506 unsigned int port_no
)
508 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
510 return mmio
+ 0x100 + (port_no
* 0x80);
513 static inline void __iomem
*ahci_port_base(struct ata_port
*ap
)
515 return __ahci_port_base(ap
->host
, ap
->port_no
);
519 * ahci_save_initial_config - Save and fixup initial config values
520 * @pdev: target PCI device
521 * @pi: associated ATA port info
522 * @hpriv: host private area to store config values
524 * Some registers containing configuration info might be setup by
525 * BIOS and might be cleared on reset. This function saves the
526 * initial values of those registers into @hpriv such that they
527 * can be restored after controller reset.
529 * If inconsistent, config values are fixed up by this function.
534 static void ahci_save_initial_config(struct pci_dev
*pdev
,
535 const struct ata_port_info
*pi
,
536 struct ahci_host_priv
*hpriv
)
538 void __iomem
*mmio
= pcim_iomap_table(pdev
)[AHCI_PCI_BAR
];
542 /* Values prefixed with saved_ are written back to host after
543 * reset. Values without are used for driver operation.
545 hpriv
->saved_cap
= cap
= readl(mmio
+ HOST_CAP
);
546 hpriv
->saved_port_map
= port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
548 /* some chips lie about 64bit support */
549 if ((cap
& HOST_CAP_64
) && (pi
->flags
& AHCI_FLAG_32BIT_ONLY
)) {
550 dev_printk(KERN_INFO
, &pdev
->dev
,
551 "controller can't do 64bit DMA, forcing 32bit\n");
555 /* fixup zero port_map */
557 port_map
= (1 << ahci_nr_ports(cap
)) - 1;
558 dev_printk(KERN_WARNING
, &pdev
->dev
,
559 "PORTS_IMPL is zero, forcing 0x%x\n", port_map
);
561 /* write the fixed up value to the PI register */
562 hpriv
->saved_port_map
= port_map
;
566 * Temporary Marvell 6145 hack: PATA port presence
567 * is asserted through the standard AHCI port
568 * presence register, as bit 4 (counting from 0)
570 if (pi
->flags
& AHCI_FLAG_MV_PATA
) {
571 dev_printk(KERN_ERR
, &pdev
->dev
,
572 "MV_AHCI HACK: port_map %x -> %x\n",
574 hpriv
->port_map
& 0xf);
579 /* cross check port_map and cap.n_ports */
580 if (pi
->flags
& AHCI_FLAG_HONOR_PI
) {
581 u32 tmp_port_map
= port_map
;
582 int n_ports
= ahci_nr_ports(cap
);
584 for (i
= 0; i
< AHCI_MAX_PORTS
&& n_ports
; i
++) {
585 if (tmp_port_map
& (1 << i
)) {
587 tmp_port_map
&= ~(1 << i
);
591 /* Whine if inconsistent. No need to update cap.
592 * port_map is used to determine number of ports.
594 if (n_ports
|| tmp_port_map
)
595 dev_printk(KERN_WARNING
, &pdev
->dev
,
596 "nr_ports (%u) and implemented port map "
597 "(0x%x) don't match\n",
598 ahci_nr_ports(cap
), port_map
);
600 /* fabricate port_map from cap.nr_ports */
601 port_map
= (1 << ahci_nr_ports(cap
)) - 1;
604 /* record values to use during operation */
606 hpriv
->port_map
= port_map
;
610 * ahci_restore_initial_config - Restore initial config
611 * @host: target ATA host
613 * Restore initial config stored by ahci_save_initial_config().
618 static void ahci_restore_initial_config(struct ata_host
*host
)
620 struct ahci_host_priv
*hpriv
= host
->private_data
;
621 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
623 writel(hpriv
->saved_cap
, mmio
+ HOST_CAP
);
624 writel(hpriv
->saved_port_map
, mmio
+ HOST_PORTS_IMPL
);
625 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
628 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg_in
)
633 case SCR_STATUS
: sc_reg
= 0; break;
634 case SCR_CONTROL
: sc_reg
= 1; break;
635 case SCR_ERROR
: sc_reg
= 2; break;
636 case SCR_ACTIVE
: sc_reg
= 3; break;
641 return readl(ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
645 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg_in
,
651 case SCR_STATUS
: sc_reg
= 0; break;
652 case SCR_CONTROL
: sc_reg
= 1; break;
653 case SCR_ERROR
: sc_reg
= 2; break;
654 case SCR_ACTIVE
: sc_reg
= 3; break;
659 writel(val
, ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
662 static void ahci_start_engine(struct ata_port
*ap
)
664 void __iomem
*port_mmio
= ahci_port_base(ap
);
668 tmp
= readl(port_mmio
+ PORT_CMD
);
669 tmp
|= PORT_CMD_START
;
670 writel(tmp
, port_mmio
+ PORT_CMD
);
671 readl(port_mmio
+ PORT_CMD
); /* flush */
674 static int ahci_stop_engine(struct ata_port
*ap
)
676 void __iomem
*port_mmio
= ahci_port_base(ap
);
679 tmp
= readl(port_mmio
+ PORT_CMD
);
681 /* check if the HBA is idle */
682 if ((tmp
& (PORT_CMD_START
| PORT_CMD_LIST_ON
)) == 0)
685 /* setting HBA to idle */
686 tmp
&= ~PORT_CMD_START
;
687 writel(tmp
, port_mmio
+ PORT_CMD
);
689 /* wait for engine to stop. This could be as long as 500 msec */
690 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
691 PORT_CMD_LIST_ON
, PORT_CMD_LIST_ON
, 1, 500);
692 if (tmp
& PORT_CMD_LIST_ON
)
698 static void ahci_start_fis_rx(struct ata_port
*ap
)
700 void __iomem
*port_mmio
= ahci_port_base(ap
);
701 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
702 struct ahci_port_priv
*pp
= ap
->private_data
;
705 /* set FIS registers */
706 if (hpriv
->cap
& HOST_CAP_64
)
707 writel((pp
->cmd_slot_dma
>> 16) >> 16,
708 port_mmio
+ PORT_LST_ADDR_HI
);
709 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
711 if (hpriv
->cap
& HOST_CAP_64
)
712 writel((pp
->rx_fis_dma
>> 16) >> 16,
713 port_mmio
+ PORT_FIS_ADDR_HI
);
714 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
716 /* enable FIS reception */
717 tmp
= readl(port_mmio
+ PORT_CMD
);
718 tmp
|= PORT_CMD_FIS_RX
;
719 writel(tmp
, port_mmio
+ PORT_CMD
);
722 readl(port_mmio
+ PORT_CMD
);
725 static int ahci_stop_fis_rx(struct ata_port
*ap
)
727 void __iomem
*port_mmio
= ahci_port_base(ap
);
730 /* disable FIS reception */
731 tmp
= readl(port_mmio
+ PORT_CMD
);
732 tmp
&= ~PORT_CMD_FIS_RX
;
733 writel(tmp
, port_mmio
+ PORT_CMD
);
735 /* wait for completion, spec says 500ms, give it 1000 */
736 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
, PORT_CMD_FIS_ON
,
737 PORT_CMD_FIS_ON
, 10, 1000);
738 if (tmp
& PORT_CMD_FIS_ON
)
744 static void ahci_power_up(struct ata_port
*ap
)
746 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
747 void __iomem
*port_mmio
= ahci_port_base(ap
);
750 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
753 if (hpriv
->cap
& HOST_CAP_SSS
) {
754 cmd
|= PORT_CMD_SPIN_UP
;
755 writel(cmd
, port_mmio
+ PORT_CMD
);
759 writel(cmd
| PORT_CMD_ICC_ACTIVE
, port_mmio
+ PORT_CMD
);
763 static void ahci_power_down(struct ata_port
*ap
)
765 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
766 void __iomem
*port_mmio
= ahci_port_base(ap
);
769 if (!(hpriv
->cap
& HOST_CAP_SSS
))
772 /* put device into listen mode, first set PxSCTL.DET to 0 */
773 scontrol
= readl(port_mmio
+ PORT_SCR_CTL
);
775 writel(scontrol
, port_mmio
+ PORT_SCR_CTL
);
777 /* then set PxCMD.SUD to 0 */
778 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
779 cmd
&= ~PORT_CMD_SPIN_UP
;
780 writel(cmd
, port_mmio
+ PORT_CMD
);
784 static void ahci_start_port(struct ata_port
*ap
)
786 /* enable FIS reception */
787 ahci_start_fis_rx(ap
);
790 ahci_start_engine(ap
);
793 static int ahci_deinit_port(struct ata_port
*ap
, const char **emsg
)
798 rc
= ahci_stop_engine(ap
);
800 *emsg
= "failed to stop engine";
804 /* disable FIS reception */
805 rc
= ahci_stop_fis_rx(ap
);
807 *emsg
= "failed stop FIS RX";
814 static int ahci_reset_controller(struct ata_host
*host
)
816 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
817 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
820 /* global controller reset */
821 tmp
= readl(mmio
+ HOST_CTL
);
822 if ((tmp
& HOST_RESET
) == 0) {
823 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
824 readl(mmio
+ HOST_CTL
); /* flush */
827 /* reset must complete within 1 second, or
828 * the hardware should be considered fried.
832 tmp
= readl(mmio
+ HOST_CTL
);
833 if (tmp
& HOST_RESET
) {
834 dev_printk(KERN_ERR
, host
->dev
,
835 "controller reset failed (0x%x)\n", tmp
);
839 /* turn on AHCI mode */
840 writel(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
841 (void) readl(mmio
+ HOST_CTL
); /* flush */
843 /* some registers might be cleared on reset. restore initial values */
844 ahci_restore_initial_config(host
);
846 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
) {
850 pci_read_config_word(pdev
, 0x92, &tmp16
);
852 pci_write_config_word(pdev
, 0x92, tmp16
);
858 static void ahci_port_init(struct pci_dev
*pdev
, struct ata_port
*ap
,
859 int port_no
, void __iomem
*mmio
,
860 void __iomem
*port_mmio
)
862 const char *emsg
= NULL
;
866 /* make sure port is not active */
867 rc
= ahci_deinit_port(ap
, &emsg
);
869 dev_printk(KERN_WARNING
, &pdev
->dev
,
870 "%s (%d)\n", emsg
, rc
);
873 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
874 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
875 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
878 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
879 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
881 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
883 writel(1 << port_no
, mmio
+ HOST_IRQ_STAT
);
886 static void ahci_init_controller(struct ata_host
*host
)
888 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
889 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
891 void __iomem
*port_mmio
;
894 if (host
->ports
[0]->flags
& AHCI_FLAG_MV_PATA
) {
895 port_mmio
= __ahci_port_base(host
, 4);
897 writel(0, port_mmio
+ PORT_IRQ_MASK
);
900 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
901 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
903 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
906 for (i
= 0; i
< host
->n_ports
; i
++) {
907 struct ata_port
*ap
= host
->ports
[i
];
909 port_mmio
= ahci_port_base(ap
);
910 if (ata_port_is_dummy(ap
))
913 ahci_port_init(pdev
, ap
, i
, mmio
, port_mmio
);
916 tmp
= readl(mmio
+ HOST_CTL
);
917 VPRINTK("HOST_CTL 0x%x\n", tmp
);
918 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
919 tmp
= readl(mmio
+ HOST_CTL
);
920 VPRINTK("HOST_CTL 0x%x\n", tmp
);
923 static unsigned int ahci_dev_classify(struct ata_port
*ap
)
925 void __iomem
*port_mmio
= ahci_port_base(ap
);
926 struct ata_taskfile tf
;
929 tmp
= readl(port_mmio
+ PORT_SIG
);
930 tf
.lbah
= (tmp
>> 24) & 0xff;
931 tf
.lbam
= (tmp
>> 16) & 0xff;
932 tf
.lbal
= (tmp
>> 8) & 0xff;
933 tf
.nsect
= (tmp
) & 0xff;
935 return ata_dev_classify(&tf
);
938 static void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, unsigned int tag
,
941 dma_addr_t cmd_tbl_dma
;
943 cmd_tbl_dma
= pp
->cmd_tbl_dma
+ tag
* AHCI_CMD_TBL_SZ
;
945 pp
->cmd_slot
[tag
].opts
= cpu_to_le32(opts
);
946 pp
->cmd_slot
[tag
].status
= 0;
947 pp
->cmd_slot
[tag
].tbl_addr
= cpu_to_le32(cmd_tbl_dma
& 0xffffffff);
948 pp
->cmd_slot
[tag
].tbl_addr_hi
= cpu_to_le32((cmd_tbl_dma
>> 16) >> 16);
951 static int ahci_clo(struct ata_port
*ap
)
953 void __iomem
*port_mmio
= ap
->ioaddr
.cmd_addr
;
954 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
957 if (!(hpriv
->cap
& HOST_CAP_CLO
))
960 tmp
= readl(port_mmio
+ PORT_CMD
);
962 writel(tmp
, port_mmio
+ PORT_CMD
);
964 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
965 PORT_CMD_CLO
, PORT_CMD_CLO
, 1, 500);
966 if (tmp
& PORT_CMD_CLO
)
972 static int ahci_softreset(struct ata_port
*ap
, unsigned int *class,
973 unsigned long deadline
)
975 struct ahci_port_priv
*pp
= ap
->private_data
;
976 void __iomem
*port_mmio
= ahci_port_base(ap
);
977 const u32 cmd_fis_len
= 5; /* five dwords */
978 const char *reason
= NULL
;
979 struct ata_taskfile tf
;
986 if (ata_port_offline(ap
)) {
987 DPRINTK("PHY reports no device\n");
988 *class = ATA_DEV_NONE
;
992 /* prepare for SRST (AHCI-1.1 10.4.1) */
993 rc
= ahci_stop_engine(ap
);
995 reason
= "failed to stop engine";
999 /* check BUSY/DRQ, perform Command List Override if necessary */
1000 if (ahci_check_status(ap
) & (ATA_BUSY
| ATA_DRQ
)) {
1003 if (rc
== -EOPNOTSUPP
) {
1004 reason
= "port busy but CLO unavailable";
1007 reason
= "port busy but CLO failed";
1012 /* restart engine */
1013 ahci_start_engine(ap
);
1015 ata_tf_init(ap
->device
, &tf
);
1018 /* issue the first D2H Register FIS */
1019 ahci_fill_cmd_slot(pp
, 0,
1020 cmd_fis_len
| AHCI_CMD_RESET
| AHCI_CMD_CLR_BUSY
);
1023 ata_tf_to_fis(&tf
, fis
, 0);
1024 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
1026 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
1028 tmp
= ata_wait_register(port_mmio
+ PORT_CMD_ISSUE
, 0x1, 0x1, 1, 500);
1031 reason
= "1st FIS failed";
1035 /* spec says at least 5us, but be generous and sleep for 1ms */
1038 /* issue the second D2H Register FIS */
1039 ahci_fill_cmd_slot(pp
, 0, cmd_fis_len
);
1041 tf
.ctl
&= ~ATA_SRST
;
1042 ata_tf_to_fis(&tf
, fis
, 0);
1043 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
1045 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
1046 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
1048 /* spec mandates ">= 2ms" before checking status.
1049 * We wait 150ms, because that was the magic delay used for
1050 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1051 * between when the ATA command register is written, and then
1052 * status is checked. Because waiting for "a while" before
1053 * checking status is fine, post SRST, we perform this magic
1054 * delay here as well.
1058 rc
= ata_wait_ready(ap
, deadline
);
1059 /* link occupied, -ENODEV too is an error */
1061 reason
= "device not ready";
1064 *class = ahci_dev_classify(ap
);
1066 DPRINTK("EXIT, class=%u\n", *class);
1070 ahci_start_engine(ap
);
1072 ata_port_printk(ap
, KERN_ERR
, "softreset failed (%s)\n", reason
);
1076 static int ahci_hardreset(struct ata_port
*ap
, unsigned int *class,
1077 unsigned long deadline
)
1079 struct ahci_port_priv
*pp
= ap
->private_data
;
1080 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
1081 struct ata_taskfile tf
;
1086 ahci_stop_engine(ap
);
1088 /* clear D2H reception area to properly wait for D2H FIS */
1089 ata_tf_init(ap
->device
, &tf
);
1091 ata_tf_to_fis(&tf
, d2h_fis
, 0);
1093 rc
= sata_std_hardreset(ap
, class, deadline
);
1095 ahci_start_engine(ap
);
1097 if (rc
== 0 && ata_port_online(ap
))
1098 *class = ahci_dev_classify(ap
);
1099 if (*class == ATA_DEV_UNKNOWN
)
1100 *class = ATA_DEV_NONE
;
1102 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
1106 static int ahci_vt8251_hardreset(struct ata_port
*ap
, unsigned int *class,
1107 unsigned long deadline
)
1113 ahci_stop_engine(ap
);
1115 rc
= sata_port_hardreset(ap
, sata_ehc_deb_timing(&ap
->eh_context
),
1118 /* vt8251 needs SError cleared for the port to operate */
1119 ahci_scr_write(ap
, SCR_ERROR
, ahci_scr_read(ap
, SCR_ERROR
));
1121 ahci_start_engine(ap
);
1123 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
1125 /* vt8251 doesn't clear BSY on signature FIS reception,
1126 * request follow-up softreset.
1128 return rc
?: -EAGAIN
;
1131 static void ahci_postreset(struct ata_port
*ap
, unsigned int *class)
1133 void __iomem
*port_mmio
= ahci_port_base(ap
);
1136 ata_std_postreset(ap
, class);
1138 /* Make sure port's ATAPI bit is set appropriately */
1139 new_tmp
= tmp
= readl(port_mmio
+ PORT_CMD
);
1140 if (*class == ATA_DEV_ATAPI
)
1141 new_tmp
|= PORT_CMD_ATAPI
;
1143 new_tmp
&= ~PORT_CMD_ATAPI
;
1144 if (new_tmp
!= tmp
) {
1145 writel(new_tmp
, port_mmio
+ PORT_CMD
);
1146 readl(port_mmio
+ PORT_CMD
); /* flush */
1150 static u8
ahci_check_status(struct ata_port
*ap
)
1152 void __iomem
*mmio
= ap
->ioaddr
.cmd_addr
;
1154 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
1157 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
1159 struct ahci_port_priv
*pp
= ap
->private_data
;
1160 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
1162 ata_tf_from_fis(d2h_fis
, tf
);
1165 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_tbl
)
1167 struct scatterlist
*sg
;
1168 struct ahci_sg
*ahci_sg
;
1169 unsigned int n_sg
= 0;
1174 * Next, the S/G list.
1176 ahci_sg
= cmd_tbl
+ AHCI_CMD_TBL_HDR_SZ
;
1177 ata_for_each_sg(sg
, qc
) {
1178 dma_addr_t addr
= sg_dma_address(sg
);
1179 u32 sg_len
= sg_dma_len(sg
);
1181 ahci_sg
->addr
= cpu_to_le32(addr
& 0xffffffff);
1182 ahci_sg
->addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
1183 ahci_sg
->flags_size
= cpu_to_le32(sg_len
- 1);
1192 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
1194 struct ata_port
*ap
= qc
->ap
;
1195 struct ahci_port_priv
*pp
= ap
->private_data
;
1196 int is_atapi
= is_atapi_taskfile(&qc
->tf
);
1199 const u32 cmd_fis_len
= 5; /* five dwords */
1200 unsigned int n_elem
;
1203 * Fill in command table information. First, the header,
1204 * a SATA Register - Host to Device command FIS.
1206 cmd_tbl
= pp
->cmd_tbl
+ qc
->tag
* AHCI_CMD_TBL_SZ
;
1208 ata_tf_to_fis(&qc
->tf
, cmd_tbl
, 0);
1210 memset(cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
1211 memcpy(cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, qc
->dev
->cdb_len
);
1215 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
1216 n_elem
= ahci_fill_sg(qc
, cmd_tbl
);
1219 * Fill in command slot information.
1221 opts
= cmd_fis_len
| n_elem
<< 16;
1222 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
1223 opts
|= AHCI_CMD_WRITE
;
1225 opts
|= AHCI_CMD_ATAPI
| AHCI_CMD_PREFETCH
;
1227 ahci_fill_cmd_slot(pp
, qc
->tag
, opts
);
1230 static void ahci_error_intr(struct ata_port
*ap
, u32 irq_stat
)
1232 struct ahci_port_priv
*pp
= ap
->private_data
;
1233 struct ata_eh_info
*ehi
= &ap
->eh_info
;
1234 unsigned int err_mask
= 0, action
= 0;
1235 struct ata_queued_cmd
*qc
;
1238 ata_ehi_clear_desc(ehi
);
1240 /* AHCI needs SError cleared; otherwise, it might lock up */
1241 serror
= ahci_scr_read(ap
, SCR_ERROR
);
1242 ahci_scr_write(ap
, SCR_ERROR
, serror
);
1244 /* analyze @irq_stat */
1245 ata_ehi_push_desc(ehi
, "irq_stat 0x%08x", irq_stat
);
1247 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1248 if (ap
->flags
& AHCI_FLAG_IGN_IRQ_IF_ERR
)
1249 irq_stat
&= ~PORT_IRQ_IF_ERR
;
1251 if (irq_stat
& PORT_IRQ_TF_ERR
) {
1252 err_mask
|= AC_ERR_DEV
;
1253 if (ap
->flags
& AHCI_FLAG_IGN_SERR_INTERNAL
)
1254 serror
&= ~SERR_INTERNAL
;
1257 if (irq_stat
& (PORT_IRQ_HBUS_ERR
| PORT_IRQ_HBUS_DATA_ERR
)) {
1258 err_mask
|= AC_ERR_HOST_BUS
;
1259 action
|= ATA_EH_SOFTRESET
;
1262 if (irq_stat
& PORT_IRQ_IF_ERR
) {
1263 err_mask
|= AC_ERR_ATA_BUS
;
1264 action
|= ATA_EH_SOFTRESET
;
1265 ata_ehi_push_desc(ehi
, ", interface fatal error");
1268 if (irq_stat
& (PORT_IRQ_CONNECT
| PORT_IRQ_PHYRDY
)) {
1269 ata_ehi_hotplugged(ehi
);
1270 ata_ehi_push_desc(ehi
, ", %s", irq_stat
& PORT_IRQ_CONNECT
?
1271 "connection status changed" : "PHY RDY changed");
1274 if (irq_stat
& PORT_IRQ_UNK_FIS
) {
1275 u32
*unk
= (u32
*)(pp
->rx_fis
+ RX_FIS_UNK
);
1277 err_mask
|= AC_ERR_HSM
;
1278 action
|= ATA_EH_SOFTRESET
;
1279 ata_ehi_push_desc(ehi
, ", unknown FIS %08x %08x %08x %08x",
1280 unk
[0], unk
[1], unk
[2], unk
[3]);
1283 /* okay, let's hand over to EH */
1284 ehi
->serror
|= serror
;
1285 ehi
->action
|= action
;
1287 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
1289 qc
->err_mask
|= err_mask
;
1291 ehi
->err_mask
|= err_mask
;
1293 if (irq_stat
& PORT_IRQ_FREEZE
)
1294 ata_port_freeze(ap
);
1299 static void ahci_port_intr(struct ata_port
*ap
)
1301 void __iomem
*port_mmio
= ap
->ioaddr
.cmd_addr
;
1302 struct ata_eh_info
*ehi
= &ap
->eh_info
;
1303 struct ahci_port_priv
*pp
= ap
->private_data
;
1304 u32 status
, qc_active
;
1305 int rc
, known_irq
= 0;
1307 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
1308 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
1310 if (unlikely(status
& PORT_IRQ_ERROR
)) {
1311 ahci_error_intr(ap
, status
);
1316 qc_active
= readl(port_mmio
+ PORT_SCR_ACT
);
1318 qc_active
= readl(port_mmio
+ PORT_CMD_ISSUE
);
1320 rc
= ata_qc_complete_multiple(ap
, qc_active
, NULL
);
1324 ehi
->err_mask
|= AC_ERR_HSM
;
1325 ehi
->action
|= ATA_EH_SOFTRESET
;
1326 ata_port_freeze(ap
);
1330 /* hmmm... a spurious interupt */
1332 /* if !NCQ, ignore. No modern ATA device has broken HSM
1333 * implementation for non-NCQ commands.
1338 if (status
& PORT_IRQ_D2H_REG_FIS
) {
1339 if (!pp
->ncq_saw_d2h
)
1340 ata_port_printk(ap
, KERN_INFO
,
1341 "D2H reg with I during NCQ, "
1342 "this message won't be printed again\n");
1343 pp
->ncq_saw_d2h
= 1;
1347 if (status
& PORT_IRQ_DMAS_FIS
) {
1348 if (!pp
->ncq_saw_dmas
)
1349 ata_port_printk(ap
, KERN_INFO
,
1350 "DMAS FIS during NCQ, "
1351 "this message won't be printed again\n");
1352 pp
->ncq_saw_dmas
= 1;
1356 if (status
& PORT_IRQ_SDB_FIS
) {
1357 const __le32
*f
= pp
->rx_fis
+ RX_FIS_SDB
;
1359 if (le32_to_cpu(f
[1])) {
1360 /* SDB FIS containing spurious completions
1361 * might be dangerous, whine and fail commands
1362 * with HSM violation. EH will turn off NCQ
1363 * after several such failures.
1365 ata_ehi_push_desc(ehi
,
1366 "spurious completions during NCQ "
1367 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1368 readl(port_mmio
+ PORT_CMD_ISSUE
),
1369 readl(port_mmio
+ PORT_SCR_ACT
),
1370 le32_to_cpu(f
[0]), le32_to_cpu(f
[1]));
1371 ehi
->err_mask
|= AC_ERR_HSM
;
1372 ehi
->action
|= ATA_EH_SOFTRESET
;
1373 ata_port_freeze(ap
);
1375 if (!pp
->ncq_saw_sdb
)
1376 ata_port_printk(ap
, KERN_INFO
,
1377 "spurious SDB FIS %08x:%08x during NCQ, "
1378 "this message won't be printed again\n",
1379 le32_to_cpu(f
[0]), le32_to_cpu(f
[1]));
1380 pp
->ncq_saw_sdb
= 1;
1386 ata_port_printk(ap
, KERN_INFO
, "spurious interrupt "
1387 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1388 status
, ap
->active_tag
, ap
->sactive
);
1391 static void ahci_irq_clear(struct ata_port
*ap
)
1396 static irqreturn_t
ahci_interrupt(int irq
, void *dev_instance
)
1398 struct ata_host
*host
= dev_instance
;
1399 struct ahci_host_priv
*hpriv
;
1400 unsigned int i
, handled
= 0;
1402 u32 irq_stat
, irq_ack
= 0;
1406 hpriv
= host
->private_data
;
1407 mmio
= host
->iomap
[AHCI_PCI_BAR
];
1409 /* sigh. 0xffffffff is a valid return from h/w */
1410 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
1411 irq_stat
&= hpriv
->port_map
;
1415 spin_lock(&host
->lock
);
1417 for (i
= 0; i
< host
->n_ports
; i
++) {
1418 struct ata_port
*ap
;
1420 if (!(irq_stat
& (1 << i
)))
1423 ap
= host
->ports
[i
];
1426 VPRINTK("port %u\n", i
);
1428 VPRINTK("port %u (no irq)\n", i
);
1429 if (ata_ratelimit())
1430 dev_printk(KERN_WARNING
, host
->dev
,
1431 "interrupt on disabled port %u\n", i
);
1434 irq_ack
|= (1 << i
);
1438 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
1442 spin_unlock(&host
->lock
);
1446 return IRQ_RETVAL(handled
);
1449 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
)
1451 struct ata_port
*ap
= qc
->ap
;
1452 void __iomem
*port_mmio
= ahci_port_base(ap
);
1454 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
1455 writel(1 << qc
->tag
, port_mmio
+ PORT_SCR_ACT
);
1456 writel(1 << qc
->tag
, port_mmio
+ PORT_CMD_ISSUE
);
1457 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
1462 static void ahci_freeze(struct ata_port
*ap
)
1464 void __iomem
*port_mmio
= ahci_port_base(ap
);
1467 writel(0, port_mmio
+ PORT_IRQ_MASK
);
1470 static void ahci_thaw(struct ata_port
*ap
)
1472 void __iomem
*mmio
= ap
->host
->iomap
[AHCI_PCI_BAR
];
1473 void __iomem
*port_mmio
= ahci_port_base(ap
);
1477 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1478 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1479 writel(1 << ap
->port_no
, mmio
+ HOST_IRQ_STAT
);
1481 /* turn IRQ back on */
1482 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
1485 static void ahci_error_handler(struct ata_port
*ap
)
1487 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
1488 /* restart engine */
1489 ahci_stop_engine(ap
);
1490 ahci_start_engine(ap
);
1493 /* perform recovery */
1494 ata_do_eh(ap
, ata_std_prereset
, ahci_softreset
, ahci_hardreset
,
1498 static void ahci_vt8251_error_handler(struct ata_port
*ap
)
1500 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
1501 /* restart engine */
1502 ahci_stop_engine(ap
);
1503 ahci_start_engine(ap
);
1506 /* perform recovery */
1507 ata_do_eh(ap
, ata_std_prereset
, ahci_softreset
, ahci_vt8251_hardreset
,
1511 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
)
1513 struct ata_port
*ap
= qc
->ap
;
1515 if (qc
->flags
& ATA_QCFLAG_FAILED
) {
1516 /* make DMA engine forget about the failed command */
1517 ahci_stop_engine(ap
);
1518 ahci_start_engine(ap
);
1523 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
)
1525 const char *emsg
= NULL
;
1528 rc
= ahci_deinit_port(ap
, &emsg
);
1530 ahci_power_down(ap
);
1532 ata_port_printk(ap
, KERN_ERR
, "%s (%d)\n", emsg
, rc
);
1533 ahci_start_port(ap
);
1539 static int ahci_port_resume(struct ata_port
*ap
)
1542 ahci_start_port(ap
);
1547 static int ahci_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1549 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1550 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
1553 if (mesg
.event
== PM_EVENT_SUSPEND
) {
1554 /* AHCI spec rev1.1 section 8.3.3:
1555 * Software must disable interrupts prior to requesting a
1556 * transition of the HBA to D3 state.
1558 ctl
= readl(mmio
+ HOST_CTL
);
1559 ctl
&= ~HOST_IRQ_EN
;
1560 writel(ctl
, mmio
+ HOST_CTL
);
1561 readl(mmio
+ HOST_CTL
); /* flush */
1564 return ata_pci_device_suspend(pdev
, mesg
);
1567 static int ahci_pci_device_resume(struct pci_dev
*pdev
)
1569 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1572 rc
= ata_pci_device_do_resume(pdev
);
1576 if (pdev
->dev
.power
.power_state
.event
== PM_EVENT_SUSPEND
) {
1577 rc
= ahci_reset_controller(host
);
1581 ahci_init_controller(host
);
1584 ata_host_resume(host
);
1590 static int ahci_port_start(struct ata_port
*ap
)
1592 struct device
*dev
= ap
->host
->dev
;
1593 struct ahci_port_priv
*pp
;
1598 pp
= devm_kzalloc(dev
, sizeof(*pp
), GFP_KERNEL
);
1602 rc
= ata_pad_alloc(ap
, dev
);
1606 mem
= dmam_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
,
1610 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
1613 * First item in chunk of DMA memory: 32-slot command table,
1614 * 32 bytes each in size
1617 pp
->cmd_slot_dma
= mem_dma
;
1619 mem
+= AHCI_CMD_SLOT_SZ
;
1620 mem_dma
+= AHCI_CMD_SLOT_SZ
;
1623 * Second item: Received-FIS area
1626 pp
->rx_fis_dma
= mem_dma
;
1628 mem
+= AHCI_RX_FIS_SZ
;
1629 mem_dma
+= AHCI_RX_FIS_SZ
;
1632 * Third item: data area for storing a single command
1633 * and its scatter-gather table
1636 pp
->cmd_tbl_dma
= mem_dma
;
1638 ap
->private_data
= pp
;
1640 /* engage engines, captain */
1641 return ahci_port_resume(ap
);
1644 static void ahci_port_stop(struct ata_port
*ap
)
1646 const char *emsg
= NULL
;
1649 /* de-initialize port */
1650 rc
= ahci_deinit_port(ap
, &emsg
);
1652 ata_port_printk(ap
, KERN_WARNING
, "%s (%d)\n", emsg
, rc
);
1655 static int ahci_configure_dma_masks(struct pci_dev
*pdev
, int using_dac
)
1660 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
1661 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
1663 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1665 dev_printk(KERN_ERR
, &pdev
->dev
,
1666 "64-bit DMA enable failed\n");
1671 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1673 dev_printk(KERN_ERR
, &pdev
->dev
,
1674 "32-bit DMA enable failed\n");
1677 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1679 dev_printk(KERN_ERR
, &pdev
->dev
,
1680 "32-bit consistent DMA enable failed\n");
1687 static void ahci_print_info(struct ata_host
*host
)
1689 struct ahci_host_priv
*hpriv
= host
->private_data
;
1690 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1691 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
1692 u32 vers
, cap
, impl
, speed
;
1693 const char *speed_s
;
1697 vers
= readl(mmio
+ HOST_VERSION
);
1699 impl
= hpriv
->port_map
;
1701 speed
= (cap
>> 20) & 0xf;
1704 else if (speed
== 2)
1709 pci_read_config_word(pdev
, 0x0a, &cc
);
1710 if (cc
== PCI_CLASS_STORAGE_IDE
)
1712 else if (cc
== PCI_CLASS_STORAGE_SATA
)
1714 else if (cc
== PCI_CLASS_STORAGE_RAID
)
1719 dev_printk(KERN_INFO
, &pdev
->dev
,
1720 "AHCI %02x%02x.%02x%02x "
1721 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1724 (vers
>> 24) & 0xff,
1725 (vers
>> 16) & 0xff,
1729 ((cap
>> 8) & 0x1f) + 1,
1735 dev_printk(KERN_INFO
, &pdev
->dev
,
1741 cap
& (1 << 31) ? "64bit " : "",
1742 cap
& (1 << 30) ? "ncq " : "",
1743 cap
& (1 << 28) ? "ilck " : "",
1744 cap
& (1 << 27) ? "stag " : "",
1745 cap
& (1 << 26) ? "pm " : "",
1746 cap
& (1 << 25) ? "led " : "",
1748 cap
& (1 << 24) ? "clo " : "",
1749 cap
& (1 << 19) ? "nz " : "",
1750 cap
& (1 << 18) ? "only " : "",
1751 cap
& (1 << 17) ? "pmp " : "",
1752 cap
& (1 << 15) ? "pio " : "",
1753 cap
& (1 << 14) ? "slum " : "",
1754 cap
& (1 << 13) ? "part " : ""
1758 static int ahci_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1760 static int printed_version
;
1761 struct ata_port_info pi
= ahci_port_info
[ent
->driver_data
];
1762 const struct ata_port_info
*ppi
[] = { &pi
, NULL
};
1763 struct device
*dev
= &pdev
->dev
;
1764 struct ahci_host_priv
*hpriv
;
1765 struct ata_host
*host
;
1770 WARN_ON(ATA_MAX_QUEUE
> AHCI_MAX_CMDS
);
1772 if (!printed_version
++)
1773 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
1775 /* acquire resources */
1776 rc
= pcim_enable_device(pdev
);
1780 rc
= pcim_iomap_regions(pdev
, 1 << AHCI_PCI_BAR
, DRV_NAME
);
1782 pcim_pin_device(pdev
);
1786 if ((pi
.flags
& AHCI_FLAG_NO_MSI
) || pci_enable_msi(pdev
))
1789 hpriv
= devm_kzalloc(dev
, sizeof(*hpriv
), GFP_KERNEL
);
1793 /* save initial config */
1794 ahci_save_initial_config(pdev
, &pi
, hpriv
);
1797 if (!(pi
.flags
& AHCI_FLAG_NO_NCQ
) && (hpriv
->cap
& HOST_CAP_NCQ
))
1798 pi
.flags
|= ATA_FLAG_NCQ
;
1800 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, fls(hpriv
->port_map
));
1803 host
->iomap
= pcim_iomap_table(pdev
);
1804 host
->private_data
= hpriv
;
1806 for (i
= 0; i
< host
->n_ports
; i
++) {
1807 struct ata_port
*ap
= host
->ports
[i
];
1808 void __iomem
*port_mmio
= ahci_port_base(ap
);
1810 /* standard SATA port setup */
1811 if (hpriv
->port_map
& (1 << i
)) {
1812 ap
->ioaddr
.cmd_addr
= port_mmio
;
1813 ap
->ioaddr
.scr_addr
= port_mmio
+ PORT_SCR
;
1816 /* disabled/not-implemented port */
1818 ap
->ops
= &ata_dummy_port_ops
;
1821 /* initialize adapter */
1822 rc
= ahci_configure_dma_masks(pdev
, hpriv
->cap
& HOST_CAP_64
);
1826 rc
= ahci_reset_controller(host
);
1830 ahci_init_controller(host
);
1831 ahci_print_info(host
);
1833 pci_set_master(pdev
);
1834 return ata_host_activate(host
, pdev
->irq
, ahci_interrupt
, IRQF_SHARED
,
1838 static int __init
ahci_init(void)
1840 return pci_register_driver(&ahci_pci_driver
);
1843 static void __exit
ahci_exit(void)
1845 pci_unregister_driver(&ahci_pci_driver
);
1849 MODULE_AUTHOR("Jeff Garzik");
1850 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1851 MODULE_LICENSE("GPL");
1852 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
1853 MODULE_VERSION(DRV_VERSION
);
1855 module_init(ahci_init
);
1856 module_exit(ahci_exit
);