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UBUNTU: Ubuntu-5.15.0-39.42
[mirror_ubuntu-jammy-kernel.git] / drivers / ata / ahci.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <linux/msi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <linux/libata.h>
33 #include <linux/ahci-remap.h>
34 #include <linux/io-64-nonatomic-lo-hi.h>
35 #include "ahci.h"
36
37 #define DRV_NAME "ahci"
38 #define DRV_VERSION "3.0"
39
40 enum {
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_LOONGSON = 0,
44 AHCI_PCI_BAR_ENMOTUS = 2,
45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
46 AHCI_PCI_BAR_STANDARD = 5,
47 };
48
49 enum board_ids {
50 /* board IDs by feature in alphabetical order */
51 board_ahci,
52 board_ahci_ign_iferr,
53 board_ahci_mobile,
54 board_ahci_nomsi,
55 board_ahci_noncq,
56 board_ahci_nosntf,
57 board_ahci_yes_fbs,
58
59 /* board IDs for specific chipsets in alphabetical order */
60 board_ahci_al,
61 board_ahci_avn,
62 board_ahci_mcp65,
63 board_ahci_mcp77,
64 board_ahci_mcp89,
65 board_ahci_mv,
66 board_ahci_sb600,
67 board_ahci_sb700, /* for SB700 and SB800 */
68 board_ahci_vt8251,
69
70 /*
71 * board IDs for Intel chipsets that support more than 6 ports
72 * *and* end up needing the PCS quirk.
73 */
74 board_ahci_pcs7,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
81 };
82
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static void ahci_remove_one(struct pci_dev *dev);
85 static void ahci_shutdown_one(struct pci_dev *dev);
86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
91 static bool is_mcp89_apple(struct pci_dev *pdev);
92 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94 #ifdef CONFIG_PM
95 static int ahci_pci_device_runtime_suspend(struct device *dev);
96 static int ahci_pci_device_runtime_resume(struct device *dev);
97 #ifdef CONFIG_PM_SLEEP
98 static int ahci_pci_device_suspend(struct device *dev);
99 static int ahci_pci_device_resume(struct device *dev);
100 #endif
101 #endif /* CONFIG_PM */
102
103 static struct scsi_host_template ahci_sht = {
104 AHCI_SHT("ahci"),
105 };
106
107 static struct ata_port_operations ahci_vt8251_ops = {
108 .inherits = &ahci_ops,
109 .hardreset = ahci_vt8251_hardreset,
110 };
111
112 static struct ata_port_operations ahci_p5wdh_ops = {
113 .inherits = &ahci_ops,
114 .hardreset = ahci_p5wdh_hardreset,
115 };
116
117 static struct ata_port_operations ahci_avn_ops = {
118 .inherits = &ahci_ops,
119 .hardreset = ahci_avn_hardreset,
120 };
121
122 static const struct ata_port_info ahci_port_info[] = {
123 /* by features */
124 [board_ahci] = {
125 .flags = AHCI_FLAG_COMMON,
126 .pio_mask = ATA_PIO4,
127 .udma_mask = ATA_UDMA6,
128 .port_ops = &ahci_ops,
129 },
130 [board_ahci_ign_iferr] = {
131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
136 },
137 [board_ahci_mobile] = {
138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
144 [board_ahci_nomsi] = {
145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
151 [board_ahci_noncq] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_nosntf] = {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_yes_fbs] = {
166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
172 /* by chipsets */
173 [board_ahci_al] = {
174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
180 [board_ahci_avn] = {
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_avn_ops,
185 },
186 [board_ahci_mcp65] = {
187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 AHCI_HFLAG_YES_NCQ),
189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_ops,
193 },
194 [board_ahci_mcp77] = {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
201 [board_ahci_mcp89] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
208 [board_ahci_mv] = {
209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
216 [board_ahci_sb600] = {
217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
219 AHCI_HFLAG_32BIT_ONLY),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
224 },
225 [board_ahci_sb700] = { /* for SB700 and SB800 */
226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_pmp_retry_srst_ops,
231 },
232 [board_ahci_vt8251] = {
233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
237 .port_ops = &ahci_vt8251_ops,
238 },
239 [board_ahci_pcs7] = {
240 .flags = AHCI_FLAG_COMMON,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_ops,
244 },
245 };
246
247 static const struct pci_device_id ahci_pci_tbl[] = {
248 /* Intel */
249 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
250 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
251 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
252 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
253 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
254 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
255 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
256 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
257 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
258 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
259 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
260 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
261 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
262 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
263 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
264 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
265 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
266 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
267 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
268 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
269 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
270 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
271 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
272 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
273 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
274 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
275 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
276 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
277 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
278 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
279 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
280 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
281 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
282 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
283 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
284 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
285 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
286 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
287 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
288 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
289 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
290 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
311 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
312 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
313 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
314 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
315 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
316 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
317 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
318 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
319 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
320 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
321 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
322 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
323 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
324 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
325 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
326 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
327 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
328 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
329 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
330 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
331 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
332 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
333 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
334 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
335 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
336 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
337 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
338 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
339 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
343 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
344 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
345 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
347 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
352 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
353 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
354 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
355 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
361 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
362 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
363 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
364 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
365 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
366 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
367 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
368 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
369 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
370 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
371 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
372 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
373 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
374 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
375 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
376 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
377 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
378 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
379 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
380 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
381 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
382 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
383 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
384 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
385 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
386 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
387 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
388 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
389 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
390 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
391 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
392 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
393 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
394 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
395 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
396 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
397 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
398 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
399 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
400 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
401 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
402 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
403 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
404 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
405 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
406 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
407 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
408 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
409 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
410 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
411 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
412 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
413 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
414 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
415 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
416 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
417 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
418 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
419
420 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
421 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
422 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
423 /* JMicron 362B and 362C have an AHCI function with IDE class code */
424 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
425 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
426 /* May need to update quirk_jmicron_async_suspend() for additions */
427
428 /* ATI */
429 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
430 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
431 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
436
437 /* Amazon's Annapurna Labs support */
438 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
439 .class = PCI_CLASS_STORAGE_SATA_AHCI,
440 .class_mask = 0xffffff,
441 board_ahci_al },
442 /* AMD */
443 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
444 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
445 { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
446 /* AMD is using RAID class only for ahci controllers */
447 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
448 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
449
450 /* Dell S140/S150 */
451 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
452 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
453
454 /* VIA */
455 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
456 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
457
458 /* NVIDIA */
459 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
460 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
461 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
462 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
463 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
464 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
465 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
466 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
467 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
471 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
472 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
473 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
474 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
475 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
476 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
477 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
478 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
479 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
483 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
484 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
485 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
486 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
487 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
488 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
489 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
490 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
491 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
492 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
493 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
494 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
495 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
496 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
497 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
498 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
499 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
500 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
501 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
502 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
503 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
504 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
505 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
506 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
507 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
508 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
509 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
510 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
511 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
512 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
513 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
514 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
515 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
516 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
517 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
518 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
519 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
520 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
521 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
522 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
523 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
524 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
525 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
526 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
527 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
528 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
529 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
530 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
531 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
532 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
533 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
534 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
535 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
536 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
537 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
538 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
539 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
540 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
541 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
542 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
543
544 /* SiS */
545 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
546 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
547 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
548
549 /* ST Microelectronics */
550 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
551
552 /* Marvell */
553 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
554 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
555 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
556 .class = PCI_CLASS_STORAGE_SATA_AHCI,
557 .class_mask = 0xffffff,
558 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
559 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
560 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
561 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
562 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
563 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
564 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
565 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
566 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
567 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
568 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
569 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
570 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
571 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
572 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
573 .driver_data = board_ahci_yes_fbs },
574 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
575 .driver_data = board_ahci_yes_fbs },
576 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
577 .driver_data = board_ahci_yes_fbs },
578 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
579 .driver_data = board_ahci_yes_fbs },
580 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
581 .driver_data = board_ahci_yes_fbs },
582 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
583 .driver_data = board_ahci_yes_fbs },
584
585 /* Promise */
586 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
587 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
588
589 /* Asmedia */
590 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
591 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
592 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
593 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
594 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
595 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
596
597 /*
598 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
599 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
600 */
601 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
602 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
603
604 /* Enmotus */
605 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
606
607 /* Loongson */
608 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
609
610 /* Generic, PCI class code for AHCI */
611 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
612 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
613
614 { } /* terminate list */
615 };
616
617 static const struct dev_pm_ops ahci_pci_pm_ops = {
618 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
619 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
620 ahci_pci_device_runtime_resume, NULL)
621 };
622
623 static struct pci_driver ahci_pci_driver = {
624 .name = DRV_NAME,
625 .id_table = ahci_pci_tbl,
626 .probe = ahci_init_one,
627 .remove = ahci_remove_one,
628 .shutdown = ahci_shutdown_one,
629 .driver = {
630 .pm = &ahci_pci_pm_ops,
631 },
632 };
633
634 #if IS_ENABLED(CONFIG_PATA_MARVELL)
635 static int marvell_enable;
636 #else
637 static int marvell_enable = 1;
638 #endif
639 module_param(marvell_enable, int, 0644);
640 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
641
642 static int mobile_lpm_policy = -1;
643 module_param(mobile_lpm_policy, int, 0644);
644 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
645
646 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
647 struct ahci_host_priv *hpriv)
648 {
649 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
650 dev_info(&pdev->dev, "JMB361 has only one port\n");
651 hpriv->force_port_map = 1;
652 }
653
654 /*
655 * Temporary Marvell 6145 hack: PATA port presence
656 * is asserted through the standard AHCI port
657 * presence register, as bit 4 (counting from 0)
658 */
659 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
660 if (pdev->device == 0x6121)
661 hpriv->mask_port_map = 0x3;
662 else
663 hpriv->mask_port_map = 0xf;
664 dev_info(&pdev->dev,
665 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
666 }
667
668 ahci_save_initial_config(&pdev->dev, hpriv);
669 }
670
671 static void ahci_pci_init_controller(struct ata_host *host)
672 {
673 struct ahci_host_priv *hpriv = host->private_data;
674 struct pci_dev *pdev = to_pci_dev(host->dev);
675 void __iomem *port_mmio;
676 u32 tmp;
677 int mv;
678
679 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
680 if (pdev->device == 0x6121)
681 mv = 2;
682 else
683 mv = 4;
684 port_mmio = __ahci_port_base(host, mv);
685
686 writel(0, port_mmio + PORT_IRQ_MASK);
687
688 /* clear port IRQ */
689 tmp = readl(port_mmio + PORT_IRQ_STAT);
690 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
691 if (tmp)
692 writel(tmp, port_mmio + PORT_IRQ_STAT);
693 }
694
695 ahci_init_controller(host);
696 }
697
698 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
699 unsigned long deadline)
700 {
701 struct ata_port *ap = link->ap;
702 struct ahci_host_priv *hpriv = ap->host->private_data;
703 bool online;
704 int rc;
705
706 DPRINTK("ENTER\n");
707
708 hpriv->stop_engine(ap);
709
710 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
711 deadline, &online, NULL);
712
713 hpriv->start_engine(ap);
714
715 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
716
717 /* vt8251 doesn't clear BSY on signature FIS reception,
718 * request follow-up softreset.
719 */
720 return online ? -EAGAIN : rc;
721 }
722
723 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
724 unsigned long deadline)
725 {
726 struct ata_port *ap = link->ap;
727 struct ahci_port_priv *pp = ap->private_data;
728 struct ahci_host_priv *hpriv = ap->host->private_data;
729 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
730 struct ata_taskfile tf;
731 bool online;
732 int rc;
733
734 hpriv->stop_engine(ap);
735
736 /* clear D2H reception area to properly wait for D2H FIS */
737 ata_tf_init(link->device, &tf);
738 tf.command = ATA_BUSY;
739 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
740
741 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
742 deadline, &online, NULL);
743
744 hpriv->start_engine(ap);
745
746 /* The pseudo configuration device on SIMG4726 attached to
747 * ASUS P5W-DH Deluxe doesn't send signature FIS after
748 * hardreset if no device is attached to the first downstream
749 * port && the pseudo device locks up on SRST w/ PMP==0. To
750 * work around this, wait for !BSY only briefly. If BSY isn't
751 * cleared, perform CLO and proceed to IDENTIFY (achieved by
752 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
753 *
754 * Wait for two seconds. Devices attached to downstream port
755 * which can't process the following IDENTIFY after this will
756 * have to be reset again. For most cases, this should
757 * suffice while making probing snappish enough.
758 */
759 if (online) {
760 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
761 ahci_check_ready);
762 if (rc)
763 ahci_kick_engine(ap);
764 }
765 return rc;
766 }
767
768 /*
769 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
770 *
771 * It has been observed with some SSDs that the timing of events in the
772 * link synchronization phase can leave the port in a state that can not
773 * be recovered by a SATA-hard-reset alone. The failing signature is
774 * SStatus.DET stuck at 1 ("Device presence detected but Phy
775 * communication not established"). It was found that unloading and
776 * reloading the driver when this problem occurs allows the drive
777 * connection to be recovered (DET advanced to 0x3). The critical
778 * component of reloading the driver is that the port state machines are
779 * reset by bouncing "port enable" in the AHCI PCS configuration
780 * register. So, reproduce that effect by bouncing a port whenever we
781 * see DET==1 after a reset.
782 */
783 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
784 unsigned long deadline)
785 {
786 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
787 struct ata_port *ap = link->ap;
788 struct ahci_port_priv *pp = ap->private_data;
789 struct ahci_host_priv *hpriv = ap->host->private_data;
790 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
791 unsigned long tmo = deadline - jiffies;
792 struct ata_taskfile tf;
793 bool online;
794 int rc, i;
795
796 DPRINTK("ENTER\n");
797
798 hpriv->stop_engine(ap);
799
800 for (i = 0; i < 2; i++) {
801 u16 val;
802 u32 sstatus;
803 int port = ap->port_no;
804 struct ata_host *host = ap->host;
805 struct pci_dev *pdev = to_pci_dev(host->dev);
806
807 /* clear D2H reception area to properly wait for D2H FIS */
808 ata_tf_init(link->device, &tf);
809 tf.command = ATA_BUSY;
810 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
811
812 rc = sata_link_hardreset(link, timing, deadline, &online,
813 ahci_check_ready);
814
815 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
816 (sstatus & 0xf) != 1)
817 break;
818
819 ata_link_info(link, "avn bounce port%d\n", port);
820
821 pci_read_config_word(pdev, 0x92, &val);
822 val &= ~(1 << port);
823 pci_write_config_word(pdev, 0x92, val);
824 ata_msleep(ap, 1000);
825 val |= 1 << port;
826 pci_write_config_word(pdev, 0x92, val);
827 deadline += tmo;
828 }
829
830 hpriv->start_engine(ap);
831
832 if (online)
833 *class = ahci_dev_classify(ap);
834
835 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
836 return rc;
837 }
838
839
840 #ifdef CONFIG_PM
841 static void ahci_pci_disable_interrupts(struct ata_host *host)
842 {
843 struct ahci_host_priv *hpriv = host->private_data;
844 void __iomem *mmio = hpriv->mmio;
845 u32 ctl;
846
847 /* AHCI spec rev1.1 section 8.3.3:
848 * Software must disable interrupts prior to requesting a
849 * transition of the HBA to D3 state.
850 */
851 ctl = readl(mmio + HOST_CTL);
852 ctl &= ~HOST_IRQ_EN;
853 writel(ctl, mmio + HOST_CTL);
854 readl(mmio + HOST_CTL); /* flush */
855 }
856
857 static int ahci_pci_device_runtime_suspend(struct device *dev)
858 {
859 struct pci_dev *pdev = to_pci_dev(dev);
860 struct ata_host *host = pci_get_drvdata(pdev);
861
862 ahci_pci_disable_interrupts(host);
863 return 0;
864 }
865
866 static int ahci_pci_device_runtime_resume(struct device *dev)
867 {
868 struct pci_dev *pdev = to_pci_dev(dev);
869 struct ata_host *host = pci_get_drvdata(pdev);
870 int rc;
871
872 rc = ahci_reset_controller(host);
873 if (rc)
874 return rc;
875 ahci_pci_init_controller(host);
876 return 0;
877 }
878
879 #ifdef CONFIG_PM_SLEEP
880 static int ahci_pci_device_suspend(struct device *dev)
881 {
882 struct pci_dev *pdev = to_pci_dev(dev);
883 struct ata_host *host = pci_get_drvdata(pdev);
884 struct ahci_host_priv *hpriv = host->private_data;
885
886 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
887 dev_err(&pdev->dev,
888 "BIOS update required for suspend/resume\n");
889 return -EIO;
890 }
891
892 ahci_pci_disable_interrupts(host);
893 return ata_host_suspend(host, PMSG_SUSPEND);
894 }
895
896 static int ahci_pci_device_resume(struct device *dev)
897 {
898 struct pci_dev *pdev = to_pci_dev(dev);
899 struct ata_host *host = pci_get_drvdata(pdev);
900 int rc;
901
902 /* Apple BIOS helpfully mangles the registers on resume */
903 if (is_mcp89_apple(pdev))
904 ahci_mcp89_apple_enable(pdev);
905
906 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
907 rc = ahci_reset_controller(host);
908 if (rc)
909 return rc;
910
911 ahci_pci_init_controller(host);
912 }
913
914 ata_host_resume(host);
915
916 return 0;
917 }
918 #endif
919
920 #endif /* CONFIG_PM */
921
922 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
923 {
924 const int dma_bits = using_dac ? 64 : 32;
925 int rc;
926
927 /*
928 * If the device fixup already set the dma_mask to some non-standard
929 * value, don't extend it here. This happens on STA2X11, for example.
930 *
931 * XXX: manipulating the DMA mask from platform code is completely
932 * bogus, platform code should use dev->bus_dma_limit instead..
933 */
934 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
935 return 0;
936
937 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
938 if (rc)
939 dev_err(&pdev->dev, "DMA enable failed\n");
940 return rc;
941 }
942
943 static void ahci_pci_print_info(struct ata_host *host)
944 {
945 struct pci_dev *pdev = to_pci_dev(host->dev);
946 u16 cc;
947 const char *scc_s;
948
949 pci_read_config_word(pdev, 0x0a, &cc);
950 if (cc == PCI_CLASS_STORAGE_IDE)
951 scc_s = "IDE";
952 else if (cc == PCI_CLASS_STORAGE_SATA)
953 scc_s = "SATA";
954 else if (cc == PCI_CLASS_STORAGE_RAID)
955 scc_s = "RAID";
956 else
957 scc_s = "unknown";
958
959 ahci_print_info(host, scc_s);
960 }
961
962 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
963 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
964 * support PMP and the 4726 either directly exports the device
965 * attached to the first downstream port or acts as a hardware storage
966 * controller and emulate a single ATA device (can be RAID 0/1 or some
967 * other configuration).
968 *
969 * When there's no device attached to the first downstream port of the
970 * 4726, "Config Disk" appears, which is a pseudo ATA device to
971 * configure the 4726. However, ATA emulation of the device is very
972 * lame. It doesn't send signature D2H Reg FIS after the initial
973 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
974 *
975 * The following function works around the problem by always using
976 * hardreset on the port and not depending on receiving signature FIS
977 * afterward. If signature FIS isn't received soon, ATA class is
978 * assumed without follow-up softreset.
979 */
980 static void ahci_p5wdh_workaround(struct ata_host *host)
981 {
982 static const struct dmi_system_id sysids[] = {
983 {
984 .ident = "P5W DH Deluxe",
985 .matches = {
986 DMI_MATCH(DMI_SYS_VENDOR,
987 "ASUSTEK COMPUTER INC"),
988 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
989 },
990 },
991 { }
992 };
993 struct pci_dev *pdev = to_pci_dev(host->dev);
994
995 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
996 dmi_check_system(sysids)) {
997 struct ata_port *ap = host->ports[1];
998
999 dev_info(&pdev->dev,
1000 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1001
1002 ap->ops = &ahci_p5wdh_ops;
1003 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1004 }
1005 }
1006
1007 /*
1008 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1009 * booting in BIOS compatibility mode. We restore the registers but not ID.
1010 */
1011 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1012 {
1013 u32 val;
1014
1015 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1016
1017 pci_read_config_dword(pdev, 0xf8, &val);
1018 val |= 1 << 0x1b;
1019 /* the following changes the device ID, but appears not to affect function */
1020 /* val = (val & ~0xf0000000) | 0x80000000; */
1021 pci_write_config_dword(pdev, 0xf8, val);
1022
1023 pci_read_config_dword(pdev, 0x54c, &val);
1024 val |= 1 << 0xc;
1025 pci_write_config_dword(pdev, 0x54c, val);
1026
1027 pci_read_config_dword(pdev, 0x4a4, &val);
1028 val &= 0xff;
1029 val |= 0x01060100;
1030 pci_write_config_dword(pdev, 0x4a4, val);
1031
1032 pci_read_config_dword(pdev, 0x54c, &val);
1033 val &= ~(1 << 0xc);
1034 pci_write_config_dword(pdev, 0x54c, val);
1035
1036 pci_read_config_dword(pdev, 0xf8, &val);
1037 val &= ~(1 << 0x1b);
1038 pci_write_config_dword(pdev, 0xf8, val);
1039 }
1040
1041 static bool is_mcp89_apple(struct pci_dev *pdev)
1042 {
1043 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1044 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1045 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1046 pdev->subsystem_device == 0xcb89;
1047 }
1048
1049 /* only some SB600 ahci controllers can do 64bit DMA */
1050 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1051 {
1052 static const struct dmi_system_id sysids[] = {
1053 /*
1054 * The oldest version known to be broken is 0901 and
1055 * working is 1501 which was released on 2007-10-26.
1056 * Enable 64bit DMA on 1501 and anything newer.
1057 *
1058 * Please read bko#9412 for more info.
1059 */
1060 {
1061 .ident = "ASUS M2A-VM",
1062 .matches = {
1063 DMI_MATCH(DMI_BOARD_VENDOR,
1064 "ASUSTeK Computer INC."),
1065 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1066 },
1067 .driver_data = "20071026", /* yyyymmdd */
1068 },
1069 /*
1070 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1071 * support 64bit DMA.
1072 *
1073 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1074 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1075 * This spelling mistake was fixed in BIOS version 1.5, so
1076 * 1.5 and later have the Manufacturer as
1077 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1078 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1079 *
1080 * BIOS versions earlier than 1.9 had a Board Product Name
1081 * DMI field of "MS-7376". This was changed to be
1082 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1083 * match on DMI_BOARD_NAME of "MS-7376".
1084 */
1085 {
1086 .ident = "MSI K9A2 Platinum",
1087 .matches = {
1088 DMI_MATCH(DMI_BOARD_VENDOR,
1089 "MICRO-STAR INTER"),
1090 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1091 },
1092 },
1093 /*
1094 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1095 * 64bit DMA.
1096 *
1097 * This board also had the typo mentioned above in the
1098 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1099 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1100 */
1101 {
1102 .ident = "MSI K9AGM2",
1103 .matches = {
1104 DMI_MATCH(DMI_BOARD_VENDOR,
1105 "MICRO-STAR INTER"),
1106 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1107 },
1108 },
1109 /*
1110 * All BIOS versions for the Asus M3A support 64bit DMA.
1111 * (all release versions from 0301 to 1206 were tested)
1112 */
1113 {
1114 .ident = "ASUS M3A",
1115 .matches = {
1116 DMI_MATCH(DMI_BOARD_VENDOR,
1117 "ASUSTeK Computer INC."),
1118 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1119 },
1120 },
1121 { }
1122 };
1123 const struct dmi_system_id *match;
1124 int year, month, date;
1125 char buf[9];
1126
1127 match = dmi_first_match(sysids);
1128 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1129 !match)
1130 return false;
1131
1132 if (!match->driver_data)
1133 goto enable_64bit;
1134
1135 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1136 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1137
1138 if (strcmp(buf, match->driver_data) >= 0)
1139 goto enable_64bit;
1140 else {
1141 dev_warn(&pdev->dev,
1142 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1143 match->ident);
1144 return false;
1145 }
1146
1147 enable_64bit:
1148 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1149 return true;
1150 }
1151
1152 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1153 {
1154 static const struct dmi_system_id broken_systems[] = {
1155 {
1156 .ident = "HP Compaq nx6310",
1157 .matches = {
1158 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1159 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1160 },
1161 /* PCI slot number of the controller */
1162 .driver_data = (void *)0x1FUL,
1163 },
1164 {
1165 .ident = "HP Compaq 6720s",
1166 .matches = {
1167 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1168 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1169 },
1170 /* PCI slot number of the controller */
1171 .driver_data = (void *)0x1FUL,
1172 },
1173
1174 { } /* terminate list */
1175 };
1176 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1177
1178 if (dmi) {
1179 unsigned long slot = (unsigned long)dmi->driver_data;
1180 /* apply the quirk only to on-board controllers */
1181 return slot == PCI_SLOT(pdev->devfn);
1182 }
1183
1184 return false;
1185 }
1186
1187 static bool ahci_broken_suspend(struct pci_dev *pdev)
1188 {
1189 static const struct dmi_system_id sysids[] = {
1190 /*
1191 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1192 * to the harddisk doesn't become online after
1193 * resuming from STR. Warn and fail suspend.
1194 *
1195 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1196 *
1197 * Use dates instead of versions to match as HP is
1198 * apparently recycling both product and version
1199 * strings.
1200 *
1201 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1202 */
1203 {
1204 .ident = "dv4",
1205 .matches = {
1206 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1207 DMI_MATCH(DMI_PRODUCT_NAME,
1208 "HP Pavilion dv4 Notebook PC"),
1209 },
1210 .driver_data = "20090105", /* F.30 */
1211 },
1212 {
1213 .ident = "dv5",
1214 .matches = {
1215 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1216 DMI_MATCH(DMI_PRODUCT_NAME,
1217 "HP Pavilion dv5 Notebook PC"),
1218 },
1219 .driver_data = "20090506", /* F.16 */
1220 },
1221 {
1222 .ident = "dv6",
1223 .matches = {
1224 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1225 DMI_MATCH(DMI_PRODUCT_NAME,
1226 "HP Pavilion dv6 Notebook PC"),
1227 },
1228 .driver_data = "20090423", /* F.21 */
1229 },
1230 {
1231 .ident = "HDX18",
1232 .matches = {
1233 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1234 DMI_MATCH(DMI_PRODUCT_NAME,
1235 "HP HDX18 Notebook PC"),
1236 },
1237 .driver_data = "20090430", /* F.23 */
1238 },
1239 /*
1240 * Acer eMachines G725 has the same problem. BIOS
1241 * V1.03 is known to be broken. V3.04 is known to
1242 * work. Between, there are V1.06, V2.06 and V3.03
1243 * that we don't have much idea about. For now,
1244 * blacklist anything older than V3.04.
1245 *
1246 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1247 */
1248 {
1249 .ident = "G725",
1250 .matches = {
1251 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1252 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1253 },
1254 .driver_data = "20091216", /* V3.04 */
1255 },
1256 { } /* terminate list */
1257 };
1258 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1259 int year, month, date;
1260 char buf[9];
1261
1262 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1263 return false;
1264
1265 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1266 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1267
1268 return strcmp(buf, dmi->driver_data) < 0;
1269 }
1270
1271 static bool ahci_broken_lpm(struct pci_dev *pdev)
1272 {
1273 static const struct dmi_system_id sysids[] = {
1274 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1275 {
1276 .matches = {
1277 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1278 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1279 },
1280 .driver_data = "20180406", /* 1.31 */
1281 },
1282 {
1283 .matches = {
1284 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1285 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1286 },
1287 .driver_data = "20180420", /* 1.28 */
1288 },
1289 {
1290 .matches = {
1291 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1292 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1293 },
1294 .driver_data = "20180315", /* 1.33 */
1295 },
1296 {
1297 .matches = {
1298 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1299 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1300 },
1301 /*
1302 * Note date based on release notes, 2.35 has been
1303 * reported to be good, but I've been unable to get
1304 * a hold of the reporter to get the DMI BIOS date.
1305 * TODO: fix this.
1306 */
1307 .driver_data = "20180310", /* 2.35 */
1308 },
1309 { } /* terminate list */
1310 };
1311 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1312 int year, month, date;
1313 char buf[9];
1314
1315 if (!dmi)
1316 return false;
1317
1318 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1319 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1320
1321 return strcmp(buf, dmi->driver_data) < 0;
1322 }
1323
1324 static bool ahci_broken_online(struct pci_dev *pdev)
1325 {
1326 #define ENCODE_BUSDEVFN(bus, slot, func) \
1327 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1328 static const struct dmi_system_id sysids[] = {
1329 /*
1330 * There are several gigabyte boards which use
1331 * SIMG5723s configured as hardware RAID. Certain
1332 * 5723 firmware revisions shipped there keep the link
1333 * online but fail to answer properly to SRST or
1334 * IDENTIFY when no device is attached downstream
1335 * causing libata to retry quite a few times leading
1336 * to excessive detection delay.
1337 *
1338 * As these firmwares respond to the second reset try
1339 * with invalid device signature, considering unknown
1340 * sig as offline works around the problem acceptably.
1341 */
1342 {
1343 .ident = "EP45-DQ6",
1344 .matches = {
1345 DMI_MATCH(DMI_BOARD_VENDOR,
1346 "Gigabyte Technology Co., Ltd."),
1347 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1348 },
1349 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1350 },
1351 {
1352 .ident = "EP45-DS5",
1353 .matches = {
1354 DMI_MATCH(DMI_BOARD_VENDOR,
1355 "Gigabyte Technology Co., Ltd."),
1356 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1357 },
1358 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1359 },
1360 { } /* terminate list */
1361 };
1362 #undef ENCODE_BUSDEVFN
1363 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1364 unsigned int val;
1365
1366 if (!dmi)
1367 return false;
1368
1369 val = (unsigned long)dmi->driver_data;
1370
1371 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1372 }
1373
1374 static bool ahci_broken_devslp(struct pci_dev *pdev)
1375 {
1376 /* device with broken DEVSLP but still showing SDS capability */
1377 static const struct pci_device_id ids[] = {
1378 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1379 {}
1380 };
1381
1382 return pci_match_id(ids, pdev);
1383 }
1384
1385 #ifdef CONFIG_ATA_ACPI
1386 static void ahci_gtf_filter_workaround(struct ata_host *host)
1387 {
1388 static const struct dmi_system_id sysids[] = {
1389 /*
1390 * Aspire 3810T issues a bunch of SATA enable commands
1391 * via _GTF including an invalid one and one which is
1392 * rejected by the device. Among the successful ones
1393 * is FPDMA non-zero offset enable which when enabled
1394 * only on the drive side leads to NCQ command
1395 * failures. Filter it out.
1396 */
1397 {
1398 .ident = "Aspire 3810T",
1399 .matches = {
1400 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1401 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1402 },
1403 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1404 },
1405 { }
1406 };
1407 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1408 unsigned int filter;
1409 int i;
1410
1411 if (!dmi)
1412 return;
1413
1414 filter = (unsigned long)dmi->driver_data;
1415 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1416 filter, dmi->ident);
1417
1418 for (i = 0; i < host->n_ports; i++) {
1419 struct ata_port *ap = host->ports[i];
1420 struct ata_link *link;
1421 struct ata_device *dev;
1422
1423 ata_for_each_link(link, ap, EDGE)
1424 ata_for_each_dev(dev, link, ALL)
1425 dev->gtf_filter |= filter;
1426 }
1427 }
1428 #else
1429 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1430 {}
1431 #endif
1432
1433 /*
1434 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1435 * as DUMMY, or detected but eventually get a "link down" and never get up
1436 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1437 * port_map may hold a value of 0x00.
1438 *
1439 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1440 * and can significantly reduce the occurrence of the problem.
1441 *
1442 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1443 */
1444 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1445 struct pci_dev *pdev)
1446 {
1447 static const struct dmi_system_id sysids[] = {
1448 {
1449 .ident = "Acer Switch Alpha 12",
1450 .matches = {
1451 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1452 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1453 },
1454 },
1455 { }
1456 };
1457
1458 if (dmi_check_system(sysids)) {
1459 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1460 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1461 hpriv->port_map = 0x7;
1462 hpriv->cap = 0xC734FF02;
1463 }
1464 }
1465 }
1466
1467 #ifdef CONFIG_ARM64
1468 /*
1469 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1470 * Workaround is to make sure all pending IRQs are served before leaving
1471 * handler.
1472 */
1473 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1474 {
1475 struct ata_host *host = dev_instance;
1476 struct ahci_host_priv *hpriv;
1477 unsigned int rc = 0;
1478 void __iomem *mmio;
1479 u32 irq_stat, irq_masked;
1480 unsigned int handled = 1;
1481
1482 VPRINTK("ENTER\n");
1483 hpriv = host->private_data;
1484 mmio = hpriv->mmio;
1485 irq_stat = readl(mmio + HOST_IRQ_STAT);
1486 if (!irq_stat)
1487 return IRQ_NONE;
1488
1489 do {
1490 irq_masked = irq_stat & hpriv->port_map;
1491 spin_lock(&host->lock);
1492 rc = ahci_handle_port_intr(host, irq_masked);
1493 if (!rc)
1494 handled = 0;
1495 writel(irq_stat, mmio + HOST_IRQ_STAT);
1496 irq_stat = readl(mmio + HOST_IRQ_STAT);
1497 spin_unlock(&host->lock);
1498 } while (irq_stat);
1499 VPRINTK("EXIT\n");
1500
1501 return IRQ_RETVAL(handled);
1502 }
1503 #endif
1504
1505 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1506 struct ahci_host_priv *hpriv)
1507 {
1508 int i;
1509 u32 cap;
1510
1511 /*
1512 * Check if this device might have remapped nvme devices.
1513 */
1514 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1515 pci_resource_len(pdev, bar) < SZ_512K ||
1516 bar != AHCI_PCI_BAR_STANDARD ||
1517 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1518 return;
1519
1520 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1521 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1522 if ((cap & (1 << i)) == 0)
1523 continue;
1524 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1525 != PCI_CLASS_STORAGE_EXPRESS)
1526 continue;
1527
1528 /* We've found a remapped device */
1529 hpriv->remapped_nvme++;
1530 }
1531
1532 if (!hpriv->remapped_nvme)
1533 return;
1534
1535 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1536 hpriv->remapped_nvme);
1537 dev_warn(&pdev->dev,
1538 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1539
1540 /*
1541 * Don't rely on the msi-x capability in the remap case,
1542 * share the legacy interrupt across ahci and remapped devices.
1543 */
1544 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1545 }
1546
1547 static int ahci_get_irq_vector(struct ata_host *host, int port)
1548 {
1549 return pci_irq_vector(to_pci_dev(host->dev), port);
1550 }
1551
1552 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1553 struct ahci_host_priv *hpriv)
1554 {
1555 int nvec;
1556
1557 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1558 return -ENODEV;
1559
1560 /*
1561 * If number of MSIs is less than number of ports then Sharing Last
1562 * Message mode could be enforced. In this case assume that advantage
1563 * of multipe MSIs is negated and use single MSI mode instead.
1564 */
1565 if (n_ports > 1) {
1566 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1567 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1568 if (nvec > 0) {
1569 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1570 hpriv->get_irq_vector = ahci_get_irq_vector;
1571 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1572 return nvec;
1573 }
1574
1575 /*
1576 * Fallback to single MSI mode if the controller
1577 * enforced MRSM mode.
1578 */
1579 printk(KERN_INFO
1580 "ahci: MRSM is on, fallback to single MSI\n");
1581 pci_free_irq_vectors(pdev);
1582 }
1583 }
1584
1585 /*
1586 * If the host is not capable of supporting per-port vectors, fall
1587 * back to single MSI before finally attempting single MSI-X.
1588 */
1589 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1590 if (nvec == 1)
1591 return nvec;
1592 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1593 }
1594
1595 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1596 struct ahci_host_priv *hpriv)
1597 {
1598 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1599
1600
1601 /* Ignore processing for non mobile platforms */
1602 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1603 return;
1604
1605 /* user modified policy via module param */
1606 if (mobile_lpm_policy != -1) {
1607 policy = mobile_lpm_policy;
1608 goto update_policy;
1609 }
1610
1611 #ifdef CONFIG_ACPI
1612 if (policy > ATA_LPM_MED_POWER &&
1613 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1614 if (hpriv->cap & HOST_CAP_PART)
1615 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1616 else if (hpriv->cap & HOST_CAP_SSC)
1617 policy = ATA_LPM_MIN_POWER;
1618 }
1619 #endif
1620
1621 update_policy:
1622 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1623 ap->target_lpm_policy = policy;
1624 }
1625
1626 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1627 {
1628 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1629 u16 tmp16;
1630
1631 /*
1632 * Only apply the 6-port PCS quirk for known legacy platforms.
1633 */
1634 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1635 return;
1636
1637 /* Skip applying the quirk on Denverton and beyond */
1638 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1639 return;
1640
1641 /*
1642 * port_map is determined from PORTS_IMPL PCI register which is
1643 * implemented as write or write-once register. If the register
1644 * isn't programmed, ahci automatically generates it from number
1645 * of ports, which is good enough for PCS programming. It is
1646 * otherwise expected that platform firmware enables the ports
1647 * before the OS boots.
1648 */
1649 pci_read_config_word(pdev, PCS_6, &tmp16);
1650 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1651 tmp16 |= hpriv->port_map;
1652 pci_write_config_word(pdev, PCS_6, tmp16);
1653 }
1654 }
1655
1656 static ssize_t remapped_nvme_show(struct device *dev,
1657 struct device_attribute *attr,
1658 char *buf)
1659 {
1660 struct ata_host *host = dev_get_drvdata(dev);
1661 struct ahci_host_priv *hpriv = host->private_data;
1662
1663 return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1664 }
1665
1666 static DEVICE_ATTR_RO(remapped_nvme);
1667
1668 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1669 {
1670 unsigned int board_id = ent->driver_data;
1671 struct ata_port_info pi = ahci_port_info[board_id];
1672 const struct ata_port_info *ppi[] = { &pi, NULL };
1673 struct device *dev = &pdev->dev;
1674 struct ahci_host_priv *hpriv;
1675 struct ata_host *host;
1676 int n_ports, i, rc;
1677 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1678
1679 VPRINTK("ENTER\n");
1680
1681 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1682
1683 ata_print_version_once(&pdev->dev, DRV_VERSION);
1684
1685 /* The AHCI driver can only drive the SATA ports, the PATA driver
1686 can drive them all so if both drivers are selected make sure
1687 AHCI stays out of the way */
1688 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1689 return -ENODEV;
1690
1691 /* Apple BIOS on MCP89 prevents us using AHCI */
1692 if (is_mcp89_apple(pdev))
1693 ahci_mcp89_apple_enable(pdev);
1694
1695 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1696 * At the moment, we can only use the AHCI mode. Let the users know
1697 * that for SAS drives they're out of luck.
1698 */
1699 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1700 dev_info(&pdev->dev,
1701 "PDC42819 can only drive SATA devices with this driver\n");
1702
1703 /* Some devices use non-standard BARs */
1704 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1705 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1706 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1707 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1708 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1709 if (pdev->device == 0xa01c)
1710 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1711 if (pdev->device == 0xa084)
1712 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1713 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1714 if (pdev->device == 0x7a08)
1715 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1716 }
1717
1718 /* acquire resources */
1719 rc = pcim_enable_device(pdev);
1720 if (rc)
1721 return rc;
1722
1723 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1724 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1725 u8 map;
1726
1727 /* ICH6s share the same PCI ID for both piix and ahci
1728 * modes. Enabling ahci mode while MAP indicates
1729 * combined mode is a bad idea. Yield to ata_piix.
1730 */
1731 pci_read_config_byte(pdev, ICH_MAP, &map);
1732 if (map & 0x3) {
1733 dev_info(&pdev->dev,
1734 "controller is in combined mode, can't enable AHCI mode\n");
1735 return -ENODEV;
1736 }
1737 }
1738
1739 /* AHCI controllers often implement SFF compatible interface.
1740 * Grab all PCI BARs just in case.
1741 */
1742 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1743 if (rc == -EBUSY)
1744 pcim_pin_device(pdev);
1745 if (rc)
1746 return rc;
1747
1748 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1749 if (!hpriv)
1750 return -ENOMEM;
1751 hpriv->flags |= (unsigned long)pi.private_data;
1752
1753 /* MCP65 revision A1 and A2 can't do MSI */
1754 if (board_id == board_ahci_mcp65 &&
1755 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1756 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1757
1758 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1759 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1760 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1761
1762 /* only some SB600s can do 64bit DMA */
1763 if (ahci_sb600_enable_64bit(pdev))
1764 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1765
1766 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1767
1768 /* detect remapped nvme devices */
1769 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1770
1771 sysfs_add_file_to_group(&pdev->dev.kobj,
1772 &dev_attr_remapped_nvme.attr,
1773 NULL);
1774
1775 /* must set flag prior to save config in order to take effect */
1776 if (ahci_broken_devslp(pdev))
1777 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1778
1779 #ifdef CONFIG_ARM64
1780 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1781 pdev->device == 0xa235 &&
1782 pdev->revision < 0x30)
1783 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1784
1785 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1786 hpriv->irq_handler = ahci_thunderx_irq_handler;
1787 #endif
1788
1789 /* save initial config */
1790 ahci_pci_save_initial_config(pdev, hpriv);
1791
1792 /*
1793 * If platform firmware failed to enable ports, try to enable
1794 * them here.
1795 */
1796 ahci_intel_pcs_quirk(pdev, hpriv);
1797
1798 /* prepare host */
1799 if (hpriv->cap & HOST_CAP_NCQ) {
1800 pi.flags |= ATA_FLAG_NCQ;
1801 /*
1802 * Auto-activate optimization is supposed to be
1803 * supported on all AHCI controllers indicating NCQ
1804 * capability, but it seems to be broken on some
1805 * chipsets including NVIDIAs.
1806 */
1807 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1808 pi.flags |= ATA_FLAG_FPDMA_AA;
1809
1810 /*
1811 * All AHCI controllers should be forward-compatible
1812 * with the new auxiliary field. This code should be
1813 * conditionalized if any buggy AHCI controllers are
1814 * encountered.
1815 */
1816 pi.flags |= ATA_FLAG_FPDMA_AUX;
1817 }
1818
1819 if (hpriv->cap & HOST_CAP_PMP)
1820 pi.flags |= ATA_FLAG_PMP;
1821
1822 ahci_set_em_messages(hpriv, &pi);
1823
1824 if (ahci_broken_system_poweroff(pdev)) {
1825 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1826 dev_info(&pdev->dev,
1827 "quirky BIOS, skipping spindown on poweroff\n");
1828 }
1829
1830 if (ahci_broken_lpm(pdev)) {
1831 pi.flags |= ATA_FLAG_NO_LPM;
1832 dev_warn(&pdev->dev,
1833 "BIOS update required for Link Power Management support\n");
1834 }
1835
1836 if (ahci_broken_suspend(pdev)) {
1837 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1838 dev_warn(&pdev->dev,
1839 "BIOS update required for suspend/resume\n");
1840 }
1841
1842 if (ahci_broken_online(pdev)) {
1843 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1844 dev_info(&pdev->dev,
1845 "online status unreliable, applying workaround\n");
1846 }
1847
1848
1849 /* Acer SA5-271 workaround modifies private_data */
1850 acer_sa5_271_workaround(hpriv, pdev);
1851
1852 /* CAP.NP sometimes indicate the index of the last enabled
1853 * port, at other times, that of the last possible port, so
1854 * determining the maximum port number requires looking at
1855 * both CAP.NP and port_map.
1856 */
1857 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1858
1859 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1860 if (!host)
1861 return -ENOMEM;
1862 host->private_data = hpriv;
1863
1864 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1865 /* legacy intx interrupts */
1866 pci_intx(pdev, 1);
1867 }
1868 hpriv->irq = pci_irq_vector(pdev, 0);
1869
1870 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1871 host->flags |= ATA_HOST_PARALLEL_SCAN;
1872 else
1873 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1874
1875 if (pi.flags & ATA_FLAG_EM)
1876 ahci_reset_em(host);
1877
1878 for (i = 0; i < host->n_ports; i++) {
1879 struct ata_port *ap = host->ports[i];
1880
1881 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1882 ata_port_pbar_desc(ap, ahci_pci_bar,
1883 0x100 + ap->port_no * 0x80, "port");
1884
1885 /* set enclosure management message type */
1886 if (ap->flags & ATA_FLAG_EM)
1887 ap->em_message_type = hpriv->em_msg_type;
1888
1889 ahci_update_initial_lpm_policy(ap, hpriv);
1890
1891 /* disabled/not-implemented port */
1892 if (!(hpriv->port_map & (1 << i)))
1893 ap->ops = &ata_dummy_port_ops;
1894 }
1895
1896 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1897 ahci_p5wdh_workaround(host);
1898
1899 /* apply gtf filter quirk */
1900 ahci_gtf_filter_workaround(host);
1901
1902 /* initialize adapter */
1903 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1904 if (rc)
1905 return rc;
1906
1907 rc = ahci_reset_controller(host);
1908 if (rc)
1909 return rc;
1910
1911 ahci_pci_init_controller(host);
1912 ahci_pci_print_info(host);
1913
1914 pci_set_master(pdev);
1915
1916 rc = ahci_host_activate(host, &ahci_sht);
1917 if (rc)
1918 return rc;
1919
1920 pm_runtime_put_noidle(&pdev->dev);
1921 return 0;
1922 }
1923
1924 static void ahci_shutdown_one(struct pci_dev *pdev)
1925 {
1926 ata_pci_shutdown_one(pdev);
1927 }
1928
1929 static void ahci_remove_one(struct pci_dev *pdev)
1930 {
1931 sysfs_remove_file_from_group(&pdev->dev.kobj,
1932 &dev_attr_remapped_nvme.attr,
1933 NULL);
1934 pm_runtime_get_noresume(&pdev->dev);
1935 ata_pci_remove_one(pdev);
1936 }
1937
1938 module_pci_driver(ahci_pci_driver);
1939
1940 MODULE_AUTHOR("Jeff Garzik");
1941 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1942 MODULE_LICENSE("GPL");
1943 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1944 MODULE_VERSION(DRV_VERSION);
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