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[libata] ahci: minor internal cleanups
[mirror_ubuntu-artful-kernel.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.2"
50
51
52 enum {
53 AHCI_PCI_BAR = 5,
54 AHCI_MAX_PORTS = 32,
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 1,
58 AHCI_MAX_CMDS = 32,
59 AHCI_CMD_SZ = 32,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
61 AHCI_RX_FIS_SZ = 256,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
67 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_pi = 1,
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
83 board_ahci_sb600 = 4,
84
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
101 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
102 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
103
104 /* registers for each SATA port */
105 PORT_LST_ADDR = 0x00, /* command list DMA addr */
106 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
107 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
108 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
109 PORT_IRQ_STAT = 0x10, /* interrupt status */
110 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
111 PORT_CMD = 0x18, /* port command */
112 PORT_TFDATA = 0x20, /* taskfile data */
113 PORT_SIG = 0x24, /* device TF signature */
114 PORT_CMD_ISSUE = 0x38, /* command issue */
115 PORT_SCR = 0x28, /* SATA phy register block */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
120
121 /* PORT_IRQ_{STAT,MASK} bits */
122 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
123 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
124 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
125 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
126 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
127 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
128 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
129 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
130
131 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
132 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
133 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
134 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
135 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
136 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
137 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
138 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
139 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
140
141 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
142 PORT_IRQ_IF_ERR |
143 PORT_IRQ_CONNECT |
144 PORT_IRQ_PHYRDY |
145 PORT_IRQ_UNK_FIS,
146 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
147 PORT_IRQ_TF_ERR |
148 PORT_IRQ_HBUS_DATA_ERR,
149 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
150 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
151 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
152
153 /* PORT_CMD bits */
154 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
155 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
156 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
157 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
158 PORT_CMD_CLO = (1 << 3), /* Command list override */
159 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
160 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
161 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
162
163 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
164 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
165 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
166 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
167
168 /* ap->flags bits */
169 AHCI_FLAG_NO_NCQ = (1 << 24),
170 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
171 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
172 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
173 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
174
175 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
176 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
177 ATA_FLAG_SKIP_D2H_BSY |
178 ATA_FLAG_ACPI_SATA,
179 };
180
181 struct ahci_cmd_hdr {
182 u32 opts;
183 u32 status;
184 u32 tbl_addr;
185 u32 tbl_addr_hi;
186 u32 reserved[4];
187 };
188
189 struct ahci_sg {
190 u32 addr;
191 u32 addr_hi;
192 u32 reserved;
193 u32 flags_size;
194 };
195
196 struct ahci_host_priv {
197 u32 cap; /* cap to use */
198 u32 port_map; /* port map to use */
199 u32 saved_cap; /* saved initial cap */
200 u32 saved_port_map; /* saved initial port_map */
201 };
202
203 struct ahci_port_priv {
204 struct ahci_cmd_hdr *cmd_slot;
205 dma_addr_t cmd_slot_dma;
206 void *cmd_tbl;
207 dma_addr_t cmd_tbl_dma;
208 void *rx_fis;
209 dma_addr_t rx_fis_dma;
210 /* for NCQ spurious interrupt analysis */
211 unsigned int ncq_saw_d2h:1;
212 unsigned int ncq_saw_dmas:1;
213 unsigned int ncq_saw_sdb:1;
214 };
215
216 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
217 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
218 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
219 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
220 static void ahci_irq_clear(struct ata_port *ap);
221 static int ahci_port_start(struct ata_port *ap);
222 static void ahci_port_stop(struct ata_port *ap);
223 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
224 static void ahci_qc_prep(struct ata_queued_cmd *qc);
225 static u8 ahci_check_status(struct ata_port *ap);
226 static void ahci_freeze(struct ata_port *ap);
227 static void ahci_thaw(struct ata_port *ap);
228 static void ahci_error_handler(struct ata_port *ap);
229 static void ahci_vt8251_error_handler(struct ata_port *ap);
230 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
231 static int ahci_port_resume(struct ata_port *ap);
232 #ifdef CONFIG_PM
233 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
234 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
235 static int ahci_pci_device_resume(struct pci_dev *pdev);
236 #endif
237
238 static struct scsi_host_template ahci_sht = {
239 .module = THIS_MODULE,
240 .name = DRV_NAME,
241 .ioctl = ata_scsi_ioctl,
242 .queuecommand = ata_scsi_queuecmd,
243 .change_queue_depth = ata_scsi_change_queue_depth,
244 .can_queue = AHCI_MAX_CMDS - 1,
245 .this_id = ATA_SHT_THIS_ID,
246 .sg_tablesize = AHCI_MAX_SG,
247 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
248 .emulated = ATA_SHT_EMULATED,
249 .use_clustering = AHCI_USE_CLUSTERING,
250 .proc_name = DRV_NAME,
251 .dma_boundary = AHCI_DMA_BOUNDARY,
252 .slave_configure = ata_scsi_slave_config,
253 .slave_destroy = ata_scsi_slave_destroy,
254 .bios_param = ata_std_bios_param,
255 };
256
257 static const struct ata_port_operations ahci_ops = {
258 .port_disable = ata_port_disable,
259
260 .check_status = ahci_check_status,
261 .check_altstatus = ahci_check_status,
262 .dev_select = ata_noop_dev_select,
263
264 .tf_read = ahci_tf_read,
265
266 .qc_prep = ahci_qc_prep,
267 .qc_issue = ahci_qc_issue,
268
269 .irq_clear = ahci_irq_clear,
270 .irq_on = ata_dummy_irq_on,
271 .irq_ack = ata_dummy_irq_ack,
272
273 .scr_read = ahci_scr_read,
274 .scr_write = ahci_scr_write,
275
276 .freeze = ahci_freeze,
277 .thaw = ahci_thaw,
278
279 .error_handler = ahci_error_handler,
280 .post_internal_cmd = ahci_post_internal_cmd,
281
282 #ifdef CONFIG_PM
283 .port_suspend = ahci_port_suspend,
284 .port_resume = ahci_port_resume,
285 #endif
286
287 .port_start = ahci_port_start,
288 .port_stop = ahci_port_stop,
289 };
290
291 static const struct ata_port_operations ahci_vt8251_ops = {
292 .port_disable = ata_port_disable,
293
294 .check_status = ahci_check_status,
295 .check_altstatus = ahci_check_status,
296 .dev_select = ata_noop_dev_select,
297
298 .tf_read = ahci_tf_read,
299
300 .qc_prep = ahci_qc_prep,
301 .qc_issue = ahci_qc_issue,
302
303 .irq_clear = ahci_irq_clear,
304 .irq_on = ata_dummy_irq_on,
305 .irq_ack = ata_dummy_irq_ack,
306
307 .scr_read = ahci_scr_read,
308 .scr_write = ahci_scr_write,
309
310 .freeze = ahci_freeze,
311 .thaw = ahci_thaw,
312
313 .error_handler = ahci_vt8251_error_handler,
314 .post_internal_cmd = ahci_post_internal_cmd,
315
316 #ifdef CONFIG_PM
317 .port_suspend = ahci_port_suspend,
318 .port_resume = ahci_port_resume,
319 #endif
320
321 .port_start = ahci_port_start,
322 .port_stop = ahci_port_stop,
323 };
324
325 static const struct ata_port_info ahci_port_info[] = {
326 /* board_ahci */
327 {
328 .flags = AHCI_FLAG_COMMON,
329 .pio_mask = 0x1f, /* pio0-4 */
330 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
331 .port_ops = &ahci_ops,
332 },
333 /* board_ahci_pi */
334 {
335 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI,
336 .pio_mask = 0x1f, /* pio0-4 */
337 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
338 .port_ops = &ahci_ops,
339 },
340 /* board_ahci_vt8251 */
341 {
342 .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME |
343 AHCI_FLAG_NO_NCQ,
344 .pio_mask = 0x1f, /* pio0-4 */
345 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
346 .port_ops = &ahci_vt8251_ops,
347 },
348 /* board_ahci_ign_iferr */
349 {
350 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
351 .pio_mask = 0x1f, /* pio0-4 */
352 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
353 .port_ops = &ahci_ops,
354 },
355 /* board_ahci_sb600 */
356 {
357 .flags = AHCI_FLAG_COMMON |
358 AHCI_FLAG_IGN_SERR_INTERNAL |
359 AHCI_FLAG_32BIT_ONLY,
360 .pio_mask = 0x1f, /* pio0-4 */
361 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
362 .port_ops = &ahci_ops,
363 },
364 };
365
366 static const struct pci_device_id ahci_pci_tbl[] = {
367 /* Intel */
368 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
369 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
370 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
371 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
372 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
373 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
374 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
375 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
376 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
377 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
378 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
379 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
380 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
381 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
382 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
383 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
384 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
385 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
386 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
387 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
388 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
389 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
390 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
391 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */
392 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
393 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
394 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
395
396 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
397 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
398 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
399
400 /* ATI */
401 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
402 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700 */
403
404 /* VIA */
405 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
406 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
407
408 /* NVIDIA */
409 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
410 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
411 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
412 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
413 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
414 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
415 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
416 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
417 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
419 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
420 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
421 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
422 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
423 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
424 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
426 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
430 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
431 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
432 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
433 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
434 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
435 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
436 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
437 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
438 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
439 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
440 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
441 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
442 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
443 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
444 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
445 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
446 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
447 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
448 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
449 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
450 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
451 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
452 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
453
454 /* SiS */
455 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
456 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
457 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
458
459 /* Generic, PCI class code for AHCI */
460 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
461 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
462
463 { } /* terminate list */
464 };
465
466
467 static struct pci_driver ahci_pci_driver = {
468 .name = DRV_NAME,
469 .id_table = ahci_pci_tbl,
470 .probe = ahci_init_one,
471 .remove = ata_pci_remove_one,
472 #ifdef CONFIG_PM
473 .suspend = ahci_pci_device_suspend,
474 .resume = ahci_pci_device_resume,
475 #endif
476 };
477
478
479 static inline int ahci_nr_ports(u32 cap)
480 {
481 return (cap & 0x1f) + 1;
482 }
483
484 static inline void __iomem *ahci_port_base(struct ata_port *ap)
485 {
486 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
487
488 return mmio + 0x100 + (ap->port_no * 0x80);
489 }
490
491 /**
492 * ahci_save_initial_config - Save and fixup initial config values
493 * @pdev: target PCI device
494 * @pi: associated ATA port info
495 * @hpriv: host private area to store config values
496 *
497 * Some registers containing configuration info might be setup by
498 * BIOS and might be cleared on reset. This function saves the
499 * initial values of those registers into @hpriv such that they
500 * can be restored after controller reset.
501 *
502 * If inconsistent, config values are fixed up by this function.
503 *
504 * LOCKING:
505 * None.
506 */
507 static void ahci_save_initial_config(struct pci_dev *pdev,
508 const struct ata_port_info *pi,
509 struct ahci_host_priv *hpriv)
510 {
511 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
512 u32 cap, port_map;
513 int i;
514
515 /* Values prefixed with saved_ are written back to host after
516 * reset. Values without are used for driver operation.
517 */
518 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
519 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
520
521 /* some chips lie about 64bit support */
522 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
523 dev_printk(KERN_INFO, &pdev->dev,
524 "controller can't do 64bit DMA, forcing 32bit\n");
525 cap &= ~HOST_CAP_64;
526 }
527
528 /* fixup zero port_map */
529 if (!port_map) {
530 port_map = (1 << ahci_nr_ports(cap)) - 1;
531 dev_printk(KERN_WARNING, &pdev->dev,
532 "PORTS_IMPL is zero, forcing 0x%x\n", port_map);
533
534 /* write the fixed up value to the PI register */
535 hpriv->saved_port_map = port_map;
536 }
537
538 /* cross check port_map and cap.n_ports */
539 if (pi->flags & AHCI_FLAG_HONOR_PI) {
540 u32 tmp_port_map = port_map;
541 int n_ports = ahci_nr_ports(cap);
542
543 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
544 if (tmp_port_map & (1 << i)) {
545 n_ports--;
546 tmp_port_map &= ~(1 << i);
547 }
548 }
549
550 /* Whine if inconsistent. No need to update cap.
551 * port_map is used to determine number of ports.
552 */
553 if (n_ports || tmp_port_map)
554 dev_printk(KERN_WARNING, &pdev->dev,
555 "nr_ports (%u) and implemented port map "
556 "(0x%x) don't match\n",
557 ahci_nr_ports(cap), port_map);
558 } else {
559 /* fabricate port_map from cap.nr_ports */
560 port_map = (1 << ahci_nr_ports(cap)) - 1;
561 }
562
563 /* record values to use during operation */
564 hpriv->cap = cap;
565 hpriv->port_map = port_map;
566 }
567
568 /**
569 * ahci_restore_initial_config - Restore initial config
570 * @host: target ATA host
571 *
572 * Restore initial config stored by ahci_save_initial_config().
573 *
574 * LOCKING:
575 * None.
576 */
577 static void ahci_restore_initial_config(struct ata_host *host)
578 {
579 struct ahci_host_priv *hpriv = host->private_data;
580 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
581
582 writel(hpriv->saved_cap, mmio + HOST_CAP);
583 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
584 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
585 }
586
587 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
588 {
589 unsigned int sc_reg;
590
591 switch (sc_reg_in) {
592 case SCR_STATUS: sc_reg = 0; break;
593 case SCR_CONTROL: sc_reg = 1; break;
594 case SCR_ERROR: sc_reg = 2; break;
595 case SCR_ACTIVE: sc_reg = 3; break;
596 default:
597 return 0xffffffffU;
598 }
599
600 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
601 }
602
603
604 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
605 u32 val)
606 {
607 unsigned int sc_reg;
608
609 switch (sc_reg_in) {
610 case SCR_STATUS: sc_reg = 0; break;
611 case SCR_CONTROL: sc_reg = 1; break;
612 case SCR_ERROR: sc_reg = 2; break;
613 case SCR_ACTIVE: sc_reg = 3; break;
614 default:
615 return;
616 }
617
618 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
619 }
620
621 static void ahci_start_engine(struct ata_port *ap)
622 {
623 void __iomem *port_mmio = ahci_port_base(ap);
624 u32 tmp;
625
626 /* start DMA */
627 tmp = readl(port_mmio + PORT_CMD);
628 tmp |= PORT_CMD_START;
629 writel(tmp, port_mmio + PORT_CMD);
630 readl(port_mmio + PORT_CMD); /* flush */
631 }
632
633 static int ahci_stop_engine(struct ata_port *ap)
634 {
635 void __iomem *port_mmio = ahci_port_base(ap);
636 u32 tmp;
637
638 tmp = readl(port_mmio + PORT_CMD);
639
640 /* check if the HBA is idle */
641 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
642 return 0;
643
644 /* setting HBA to idle */
645 tmp &= ~PORT_CMD_START;
646 writel(tmp, port_mmio + PORT_CMD);
647
648 /* wait for engine to stop. This could be as long as 500 msec */
649 tmp = ata_wait_register(port_mmio + PORT_CMD,
650 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
651 if (tmp & PORT_CMD_LIST_ON)
652 return -EIO;
653
654 return 0;
655 }
656
657 static void ahci_start_fis_rx(struct ata_port *ap)
658 {
659 void __iomem *port_mmio = ahci_port_base(ap);
660 struct ahci_host_priv *hpriv = ap->host->private_data;
661 struct ahci_port_priv *pp = ap->private_data;
662 u32 tmp;
663
664 /* set FIS registers */
665 if (hpriv->cap & HOST_CAP_64)
666 writel((pp->cmd_slot_dma >> 16) >> 16,
667 port_mmio + PORT_LST_ADDR_HI);
668 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
669
670 if (hpriv->cap & HOST_CAP_64)
671 writel((pp->rx_fis_dma >> 16) >> 16,
672 port_mmio + PORT_FIS_ADDR_HI);
673 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
674
675 /* enable FIS reception */
676 tmp = readl(port_mmio + PORT_CMD);
677 tmp |= PORT_CMD_FIS_RX;
678 writel(tmp, port_mmio + PORT_CMD);
679
680 /* flush */
681 readl(port_mmio + PORT_CMD);
682 }
683
684 static int ahci_stop_fis_rx(struct ata_port *ap)
685 {
686 void __iomem *port_mmio = ahci_port_base(ap);
687 u32 tmp;
688
689 /* disable FIS reception */
690 tmp = readl(port_mmio + PORT_CMD);
691 tmp &= ~PORT_CMD_FIS_RX;
692 writel(tmp, port_mmio + PORT_CMD);
693
694 /* wait for completion, spec says 500ms, give it 1000 */
695 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
696 PORT_CMD_FIS_ON, 10, 1000);
697 if (tmp & PORT_CMD_FIS_ON)
698 return -EBUSY;
699
700 return 0;
701 }
702
703 static void ahci_power_up(struct ata_port *ap)
704 {
705 struct ahci_host_priv *hpriv = ap->host->private_data;
706 void __iomem *port_mmio = ahci_port_base(ap);
707 u32 cmd;
708
709 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
710
711 /* spin up device */
712 if (hpriv->cap & HOST_CAP_SSS) {
713 cmd |= PORT_CMD_SPIN_UP;
714 writel(cmd, port_mmio + PORT_CMD);
715 }
716
717 /* wake up link */
718 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
719 }
720
721 #ifdef CONFIG_PM
722 static void ahci_power_down(struct ata_port *ap)
723 {
724 struct ahci_host_priv *hpriv = ap->host->private_data;
725 void __iomem *port_mmio = ahci_port_base(ap);
726 u32 cmd, scontrol;
727
728 if (!(hpriv->cap & HOST_CAP_SSS))
729 return;
730
731 /* put device into listen mode, first set PxSCTL.DET to 0 */
732 scontrol = readl(port_mmio + PORT_SCR_CTL);
733 scontrol &= ~0xf;
734 writel(scontrol, port_mmio + PORT_SCR_CTL);
735
736 /* then set PxCMD.SUD to 0 */
737 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
738 cmd &= ~PORT_CMD_SPIN_UP;
739 writel(cmd, port_mmio + PORT_CMD);
740 }
741 #endif
742
743 static void ahci_start_port(struct ata_port *ap)
744 {
745 /* enable FIS reception */
746 ahci_start_fis_rx(ap);
747
748 /* enable DMA */
749 ahci_start_engine(ap);
750 }
751
752 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
753 {
754 int rc;
755
756 /* disable DMA */
757 rc = ahci_stop_engine(ap);
758 if (rc) {
759 *emsg = "failed to stop engine";
760 return rc;
761 }
762
763 /* disable FIS reception */
764 rc = ahci_stop_fis_rx(ap);
765 if (rc) {
766 *emsg = "failed stop FIS RX";
767 return rc;
768 }
769
770 return 0;
771 }
772
773 static int ahci_reset_controller(struct ata_host *host)
774 {
775 struct pci_dev *pdev = to_pci_dev(host->dev);
776 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
777 u32 tmp;
778
779 /* global controller reset */
780 tmp = readl(mmio + HOST_CTL);
781 if ((tmp & HOST_RESET) == 0) {
782 writel(tmp | HOST_RESET, mmio + HOST_CTL);
783 readl(mmio + HOST_CTL); /* flush */
784 }
785
786 /* reset must complete within 1 second, or
787 * the hardware should be considered fried.
788 */
789 ssleep(1);
790
791 tmp = readl(mmio + HOST_CTL);
792 if (tmp & HOST_RESET) {
793 dev_printk(KERN_ERR, host->dev,
794 "controller reset failed (0x%x)\n", tmp);
795 return -EIO;
796 }
797
798 /* turn on AHCI mode */
799 writel(HOST_AHCI_EN, mmio + HOST_CTL);
800 (void) readl(mmio + HOST_CTL); /* flush */
801
802 /* some registers might be cleared on reset. restore initial values */
803 ahci_restore_initial_config(host);
804
805 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
806 u16 tmp16;
807
808 /* configure PCS */
809 pci_read_config_word(pdev, 0x92, &tmp16);
810 tmp16 |= 0xf;
811 pci_write_config_word(pdev, 0x92, tmp16);
812 }
813
814 return 0;
815 }
816
817 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
818 int port_no, void __iomem *mmio,
819 void __iomem *port_mmio)
820 {
821 const char *emsg = NULL;
822 int rc;
823 u32 tmp;
824
825 /* make sure port is not active */
826 rc = ahci_deinit_port(ap, &emsg);
827 if (rc)
828 dev_printk(KERN_WARNING, &pdev->dev,
829 "%s (%d)\n", emsg, rc);
830
831 /* clear SError */
832 tmp = readl(port_mmio + PORT_SCR_ERR);
833 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
834 writel(tmp, port_mmio + PORT_SCR_ERR);
835
836 /* clear port IRQ */
837 tmp = readl(port_mmio + PORT_IRQ_STAT);
838 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
839 if (tmp)
840 writel(tmp, port_mmio + PORT_IRQ_STAT);
841
842 writel(1 << port_no, mmio + HOST_IRQ_STAT);
843 }
844
845 static void ahci_init_controller(struct ata_host *host)
846 {
847 struct pci_dev *pdev = to_pci_dev(host->dev);
848 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
849 int i;
850 u32 tmp;
851
852 for (i = 0; i < host->n_ports; i++) {
853 struct ata_port *ap = host->ports[i];
854 void __iomem *port_mmio = ahci_port_base(ap);
855
856 if (ata_port_is_dummy(ap))
857 continue;
858
859 ahci_port_init(pdev, ap, i, mmio, port_mmio);
860 }
861
862 tmp = readl(mmio + HOST_CTL);
863 VPRINTK("HOST_CTL 0x%x\n", tmp);
864 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
865 tmp = readl(mmio + HOST_CTL);
866 VPRINTK("HOST_CTL 0x%x\n", tmp);
867 }
868
869 static unsigned int ahci_dev_classify(struct ata_port *ap)
870 {
871 void __iomem *port_mmio = ahci_port_base(ap);
872 struct ata_taskfile tf;
873 u32 tmp;
874
875 tmp = readl(port_mmio + PORT_SIG);
876 tf.lbah = (tmp >> 24) & 0xff;
877 tf.lbam = (tmp >> 16) & 0xff;
878 tf.lbal = (tmp >> 8) & 0xff;
879 tf.nsect = (tmp) & 0xff;
880
881 return ata_dev_classify(&tf);
882 }
883
884 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
885 u32 opts)
886 {
887 dma_addr_t cmd_tbl_dma;
888
889 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
890
891 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
892 pp->cmd_slot[tag].status = 0;
893 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
894 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
895 }
896
897 static int ahci_clo(struct ata_port *ap)
898 {
899 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
900 struct ahci_host_priv *hpriv = ap->host->private_data;
901 u32 tmp;
902
903 if (!(hpriv->cap & HOST_CAP_CLO))
904 return -EOPNOTSUPP;
905
906 tmp = readl(port_mmio + PORT_CMD);
907 tmp |= PORT_CMD_CLO;
908 writel(tmp, port_mmio + PORT_CMD);
909
910 tmp = ata_wait_register(port_mmio + PORT_CMD,
911 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
912 if (tmp & PORT_CMD_CLO)
913 return -EIO;
914
915 return 0;
916 }
917
918 static int ahci_softreset(struct ata_port *ap, unsigned int *class,
919 unsigned long deadline)
920 {
921 struct ahci_port_priv *pp = ap->private_data;
922 void __iomem *port_mmio = ahci_port_base(ap);
923 const u32 cmd_fis_len = 5; /* five dwords */
924 const char *reason = NULL;
925 struct ata_taskfile tf;
926 u32 tmp;
927 u8 *fis;
928 int rc;
929
930 DPRINTK("ENTER\n");
931
932 if (ata_port_offline(ap)) {
933 DPRINTK("PHY reports no device\n");
934 *class = ATA_DEV_NONE;
935 return 0;
936 }
937
938 /* prepare for SRST (AHCI-1.1 10.4.1) */
939 rc = ahci_stop_engine(ap);
940 if (rc) {
941 reason = "failed to stop engine";
942 goto fail_restart;
943 }
944
945 /* check BUSY/DRQ, perform Command List Override if necessary */
946 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
947 rc = ahci_clo(ap);
948
949 if (rc == -EOPNOTSUPP) {
950 reason = "port busy but CLO unavailable";
951 goto fail_restart;
952 } else if (rc) {
953 reason = "port busy but CLO failed";
954 goto fail_restart;
955 }
956 }
957
958 /* restart engine */
959 ahci_start_engine(ap);
960
961 ata_tf_init(ap->device, &tf);
962 fis = pp->cmd_tbl;
963
964 /* issue the first D2H Register FIS */
965 ahci_fill_cmd_slot(pp, 0,
966 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
967
968 tf.ctl |= ATA_SRST;
969 ata_tf_to_fis(&tf, fis, 0);
970 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
971
972 writel(1, port_mmio + PORT_CMD_ISSUE);
973
974 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
975 if (tmp & 0x1) {
976 rc = -EIO;
977 reason = "1st FIS failed";
978 goto fail;
979 }
980
981 /* spec says at least 5us, but be generous and sleep for 1ms */
982 msleep(1);
983
984 /* issue the second D2H Register FIS */
985 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
986
987 tf.ctl &= ~ATA_SRST;
988 ata_tf_to_fis(&tf, fis, 0);
989 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
990
991 writel(1, port_mmio + PORT_CMD_ISSUE);
992 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
993
994 /* spec mandates ">= 2ms" before checking status.
995 * We wait 150ms, because that was the magic delay used for
996 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
997 * between when the ATA command register is written, and then
998 * status is checked. Because waiting for "a while" before
999 * checking status is fine, post SRST, we perform this magic
1000 * delay here as well.
1001 */
1002 msleep(150);
1003
1004 rc = ata_wait_ready(ap, deadline);
1005 /* link occupied, -ENODEV too is an error */
1006 if (rc) {
1007 reason = "device not ready";
1008 goto fail;
1009 }
1010 *class = ahci_dev_classify(ap);
1011
1012 DPRINTK("EXIT, class=%u\n", *class);
1013 return 0;
1014
1015 fail_restart:
1016 ahci_start_engine(ap);
1017 fail:
1018 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
1019 return rc;
1020 }
1021
1022 static int ahci_hardreset(struct ata_port *ap, unsigned int *class,
1023 unsigned long deadline)
1024 {
1025 struct ahci_port_priv *pp = ap->private_data;
1026 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1027 struct ata_taskfile tf;
1028 int rc;
1029
1030 DPRINTK("ENTER\n");
1031
1032 ahci_stop_engine(ap);
1033
1034 /* clear D2H reception area to properly wait for D2H FIS */
1035 ata_tf_init(ap->device, &tf);
1036 tf.command = 0x80;
1037 ata_tf_to_fis(&tf, d2h_fis, 0);
1038
1039 rc = sata_std_hardreset(ap, class, deadline);
1040
1041 ahci_start_engine(ap);
1042
1043 if (rc == 0 && ata_port_online(ap))
1044 *class = ahci_dev_classify(ap);
1045 if (*class == ATA_DEV_UNKNOWN)
1046 *class = ATA_DEV_NONE;
1047
1048 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1049 return rc;
1050 }
1051
1052 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class,
1053 unsigned long deadline)
1054 {
1055 int rc;
1056
1057 DPRINTK("ENTER\n");
1058
1059 ahci_stop_engine(ap);
1060
1061 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context),
1062 deadline);
1063
1064 /* vt8251 needs SError cleared for the port to operate */
1065 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
1066
1067 ahci_start_engine(ap);
1068
1069 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1070
1071 /* vt8251 doesn't clear BSY on signature FIS reception,
1072 * request follow-up softreset.
1073 */
1074 return rc ?: -EAGAIN;
1075 }
1076
1077 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
1078 {
1079 void __iomem *port_mmio = ahci_port_base(ap);
1080 u32 new_tmp, tmp;
1081
1082 ata_std_postreset(ap, class);
1083
1084 /* Make sure port's ATAPI bit is set appropriately */
1085 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1086 if (*class == ATA_DEV_ATAPI)
1087 new_tmp |= PORT_CMD_ATAPI;
1088 else
1089 new_tmp &= ~PORT_CMD_ATAPI;
1090 if (new_tmp != tmp) {
1091 writel(new_tmp, port_mmio + PORT_CMD);
1092 readl(port_mmio + PORT_CMD); /* flush */
1093 }
1094 }
1095
1096 static u8 ahci_check_status(struct ata_port *ap)
1097 {
1098 void __iomem *mmio = ap->ioaddr.cmd_addr;
1099
1100 return readl(mmio + PORT_TFDATA) & 0xFF;
1101 }
1102
1103 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1104 {
1105 struct ahci_port_priv *pp = ap->private_data;
1106 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1107
1108 ata_tf_from_fis(d2h_fis, tf);
1109 }
1110
1111 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1112 {
1113 struct scatterlist *sg;
1114 struct ahci_sg *ahci_sg;
1115 unsigned int n_sg = 0;
1116
1117 VPRINTK("ENTER\n");
1118
1119 /*
1120 * Next, the S/G list.
1121 */
1122 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1123 ata_for_each_sg(sg, qc) {
1124 dma_addr_t addr = sg_dma_address(sg);
1125 u32 sg_len = sg_dma_len(sg);
1126
1127 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1128 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1129 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1130
1131 ahci_sg++;
1132 n_sg++;
1133 }
1134
1135 return n_sg;
1136 }
1137
1138 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1139 {
1140 struct ata_port *ap = qc->ap;
1141 struct ahci_port_priv *pp = ap->private_data;
1142 int is_atapi = is_atapi_taskfile(&qc->tf);
1143 void *cmd_tbl;
1144 u32 opts;
1145 const u32 cmd_fis_len = 5; /* five dwords */
1146 unsigned int n_elem;
1147
1148 /*
1149 * Fill in command table information. First, the header,
1150 * a SATA Register - Host to Device command FIS.
1151 */
1152 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1153
1154 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
1155 if (is_atapi) {
1156 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1157 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1158 }
1159
1160 n_elem = 0;
1161 if (qc->flags & ATA_QCFLAG_DMAMAP)
1162 n_elem = ahci_fill_sg(qc, cmd_tbl);
1163
1164 /*
1165 * Fill in command slot information.
1166 */
1167 opts = cmd_fis_len | n_elem << 16;
1168 if (qc->tf.flags & ATA_TFLAG_WRITE)
1169 opts |= AHCI_CMD_WRITE;
1170 if (is_atapi)
1171 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1172
1173 ahci_fill_cmd_slot(pp, qc->tag, opts);
1174 }
1175
1176 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1177 {
1178 struct ahci_port_priv *pp = ap->private_data;
1179 struct ata_eh_info *ehi = &ap->eh_info;
1180 unsigned int err_mask = 0, action = 0;
1181 struct ata_queued_cmd *qc;
1182 u32 serror;
1183
1184 ata_ehi_clear_desc(ehi);
1185
1186 /* AHCI needs SError cleared; otherwise, it might lock up */
1187 serror = ahci_scr_read(ap, SCR_ERROR);
1188 ahci_scr_write(ap, SCR_ERROR, serror);
1189
1190 /* analyze @irq_stat */
1191 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1192
1193 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1194 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1195 irq_stat &= ~PORT_IRQ_IF_ERR;
1196
1197 if (irq_stat & PORT_IRQ_TF_ERR) {
1198 err_mask |= AC_ERR_DEV;
1199 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1200 serror &= ~SERR_INTERNAL;
1201 }
1202
1203 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1204 err_mask |= AC_ERR_HOST_BUS;
1205 action |= ATA_EH_SOFTRESET;
1206 }
1207
1208 if (irq_stat & PORT_IRQ_IF_ERR) {
1209 err_mask |= AC_ERR_ATA_BUS;
1210 action |= ATA_EH_SOFTRESET;
1211 ata_ehi_push_desc(ehi, ", interface fatal error");
1212 }
1213
1214 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1215 ata_ehi_hotplugged(ehi);
1216 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1217 "connection status changed" : "PHY RDY changed");
1218 }
1219
1220 if (irq_stat & PORT_IRQ_UNK_FIS) {
1221 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1222
1223 err_mask |= AC_ERR_HSM;
1224 action |= ATA_EH_SOFTRESET;
1225 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1226 unk[0], unk[1], unk[2], unk[3]);
1227 }
1228
1229 /* okay, let's hand over to EH */
1230 ehi->serror |= serror;
1231 ehi->action |= action;
1232
1233 qc = ata_qc_from_tag(ap, ap->active_tag);
1234 if (qc)
1235 qc->err_mask |= err_mask;
1236 else
1237 ehi->err_mask |= err_mask;
1238
1239 if (irq_stat & PORT_IRQ_FREEZE)
1240 ata_port_freeze(ap);
1241 else
1242 ata_port_abort(ap);
1243 }
1244
1245 static void ahci_port_intr(struct ata_port *ap)
1246 {
1247 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1248 struct ata_eh_info *ehi = &ap->eh_info;
1249 struct ahci_port_priv *pp = ap->private_data;
1250 u32 status, qc_active;
1251 int rc, known_irq = 0;
1252
1253 status = readl(port_mmio + PORT_IRQ_STAT);
1254 writel(status, port_mmio + PORT_IRQ_STAT);
1255
1256 if (unlikely(status & PORT_IRQ_ERROR)) {
1257 ahci_error_intr(ap, status);
1258 return;
1259 }
1260
1261 if (ap->sactive)
1262 qc_active = readl(port_mmio + PORT_SCR_ACT);
1263 else
1264 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1265
1266 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1267 if (rc > 0)
1268 return;
1269 if (rc < 0) {
1270 ehi->err_mask |= AC_ERR_HSM;
1271 ehi->action |= ATA_EH_SOFTRESET;
1272 ata_port_freeze(ap);
1273 return;
1274 }
1275
1276 /* hmmm... a spurious interupt */
1277
1278 /* if !NCQ, ignore. No modern ATA device has broken HSM
1279 * implementation for non-NCQ commands.
1280 */
1281 if (!ap->sactive)
1282 return;
1283
1284 if (status & PORT_IRQ_D2H_REG_FIS) {
1285 if (!pp->ncq_saw_d2h)
1286 ata_port_printk(ap, KERN_INFO,
1287 "D2H reg with I during NCQ, "
1288 "this message won't be printed again\n");
1289 pp->ncq_saw_d2h = 1;
1290 known_irq = 1;
1291 }
1292
1293 if (status & PORT_IRQ_DMAS_FIS) {
1294 if (!pp->ncq_saw_dmas)
1295 ata_port_printk(ap, KERN_INFO,
1296 "DMAS FIS during NCQ, "
1297 "this message won't be printed again\n");
1298 pp->ncq_saw_dmas = 1;
1299 known_irq = 1;
1300 }
1301
1302 if (status & PORT_IRQ_SDB_FIS) {
1303 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1304
1305 if (le32_to_cpu(f[1])) {
1306 /* SDB FIS containing spurious completions
1307 * might be dangerous, whine and fail commands
1308 * with HSM violation. EH will turn off NCQ
1309 * after several such failures.
1310 */
1311 ata_ehi_push_desc(ehi,
1312 "spurious completions during NCQ "
1313 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1314 readl(port_mmio + PORT_CMD_ISSUE),
1315 readl(port_mmio + PORT_SCR_ACT),
1316 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1317 ehi->err_mask |= AC_ERR_HSM;
1318 ehi->action |= ATA_EH_SOFTRESET;
1319 ata_port_freeze(ap);
1320 } else {
1321 if (!pp->ncq_saw_sdb)
1322 ata_port_printk(ap, KERN_INFO,
1323 "spurious SDB FIS %08x:%08x during NCQ, "
1324 "this message won't be printed again\n",
1325 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1326 pp->ncq_saw_sdb = 1;
1327 }
1328 known_irq = 1;
1329 }
1330
1331 if (!known_irq)
1332 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1333 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1334 status, ap->active_tag, ap->sactive);
1335 }
1336
1337 static void ahci_irq_clear(struct ata_port *ap)
1338 {
1339 /* TODO */
1340 }
1341
1342 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1343 {
1344 struct ata_host *host = dev_instance;
1345 struct ahci_host_priv *hpriv;
1346 unsigned int i, handled = 0;
1347 void __iomem *mmio;
1348 u32 irq_stat, irq_ack = 0;
1349
1350 VPRINTK("ENTER\n");
1351
1352 hpriv = host->private_data;
1353 mmio = host->iomap[AHCI_PCI_BAR];
1354
1355 /* sigh. 0xffffffff is a valid return from h/w */
1356 irq_stat = readl(mmio + HOST_IRQ_STAT);
1357 irq_stat &= hpriv->port_map;
1358 if (!irq_stat)
1359 return IRQ_NONE;
1360
1361 spin_lock(&host->lock);
1362
1363 for (i = 0; i < host->n_ports; i++) {
1364 struct ata_port *ap;
1365
1366 if (!(irq_stat & (1 << i)))
1367 continue;
1368
1369 ap = host->ports[i];
1370 if (ap) {
1371 ahci_port_intr(ap);
1372 VPRINTK("port %u\n", i);
1373 } else {
1374 VPRINTK("port %u (no irq)\n", i);
1375 if (ata_ratelimit())
1376 dev_printk(KERN_WARNING, host->dev,
1377 "interrupt on disabled port %u\n", i);
1378 }
1379
1380 irq_ack |= (1 << i);
1381 }
1382
1383 if (irq_ack) {
1384 writel(irq_ack, mmio + HOST_IRQ_STAT);
1385 handled = 1;
1386 }
1387
1388 spin_unlock(&host->lock);
1389
1390 VPRINTK("EXIT\n");
1391
1392 return IRQ_RETVAL(handled);
1393 }
1394
1395 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1396 {
1397 struct ata_port *ap = qc->ap;
1398 void __iomem *port_mmio = ahci_port_base(ap);
1399
1400 if (qc->tf.protocol == ATA_PROT_NCQ)
1401 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1402 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1403 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1404
1405 return 0;
1406 }
1407
1408 static void ahci_freeze(struct ata_port *ap)
1409 {
1410 void __iomem *port_mmio = ahci_port_base(ap);
1411
1412 /* turn IRQ off */
1413 writel(0, port_mmio + PORT_IRQ_MASK);
1414 }
1415
1416 static void ahci_thaw(struct ata_port *ap)
1417 {
1418 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1419 void __iomem *port_mmio = ahci_port_base(ap);
1420 u32 tmp;
1421
1422 /* clear IRQ */
1423 tmp = readl(port_mmio + PORT_IRQ_STAT);
1424 writel(tmp, port_mmio + PORT_IRQ_STAT);
1425 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1426
1427 /* turn IRQ back on */
1428 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1429 }
1430
1431 static void ahci_error_handler(struct ata_port *ap)
1432 {
1433 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1434 /* restart engine */
1435 ahci_stop_engine(ap);
1436 ahci_start_engine(ap);
1437 }
1438
1439 /* perform recovery */
1440 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1441 ahci_postreset);
1442 }
1443
1444 static void ahci_vt8251_error_handler(struct ata_port *ap)
1445 {
1446 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1447 /* restart engine */
1448 ahci_stop_engine(ap);
1449 ahci_start_engine(ap);
1450 }
1451
1452 /* perform recovery */
1453 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1454 ahci_postreset);
1455 }
1456
1457 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1458 {
1459 struct ata_port *ap = qc->ap;
1460
1461 if (qc->flags & ATA_QCFLAG_FAILED) {
1462 /* make DMA engine forget about the failed command */
1463 ahci_stop_engine(ap);
1464 ahci_start_engine(ap);
1465 }
1466 }
1467
1468 #ifdef CONFIG_PM
1469 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1470 {
1471 const char *emsg = NULL;
1472 int rc;
1473
1474 rc = ahci_deinit_port(ap, &emsg);
1475 if (rc == 0)
1476 ahci_power_down(ap);
1477 else {
1478 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1479 ahci_start_port(ap);
1480 }
1481
1482 return rc;
1483 }
1484
1485 static int ahci_port_resume(struct ata_port *ap)
1486 {
1487 ahci_power_up(ap);
1488 ahci_start_port(ap);
1489
1490 return 0;
1491 }
1492
1493 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1494 {
1495 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1496 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1497 u32 ctl;
1498
1499 if (mesg.event == PM_EVENT_SUSPEND) {
1500 /* AHCI spec rev1.1 section 8.3.3:
1501 * Software must disable interrupts prior to requesting a
1502 * transition of the HBA to D3 state.
1503 */
1504 ctl = readl(mmio + HOST_CTL);
1505 ctl &= ~HOST_IRQ_EN;
1506 writel(ctl, mmio + HOST_CTL);
1507 readl(mmio + HOST_CTL); /* flush */
1508 }
1509
1510 return ata_pci_device_suspend(pdev, mesg);
1511 }
1512
1513 static int ahci_pci_device_resume(struct pci_dev *pdev)
1514 {
1515 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1516 int rc;
1517
1518 rc = ata_pci_device_do_resume(pdev);
1519 if (rc)
1520 return rc;
1521
1522 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1523 rc = ahci_reset_controller(host);
1524 if (rc)
1525 return rc;
1526
1527 ahci_init_controller(host);
1528 }
1529
1530 ata_host_resume(host);
1531
1532 return 0;
1533 }
1534 #endif
1535
1536 static int ahci_port_start(struct ata_port *ap)
1537 {
1538 struct device *dev = ap->host->dev;
1539 struct ahci_port_priv *pp;
1540 void *mem;
1541 dma_addr_t mem_dma;
1542 int rc;
1543
1544 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1545 if (!pp)
1546 return -ENOMEM;
1547
1548 rc = ata_pad_alloc(ap, dev);
1549 if (rc)
1550 return rc;
1551
1552 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1553 GFP_KERNEL);
1554 if (!mem)
1555 return -ENOMEM;
1556 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1557
1558 /*
1559 * First item in chunk of DMA memory: 32-slot command table,
1560 * 32 bytes each in size
1561 */
1562 pp->cmd_slot = mem;
1563 pp->cmd_slot_dma = mem_dma;
1564
1565 mem += AHCI_CMD_SLOT_SZ;
1566 mem_dma += AHCI_CMD_SLOT_SZ;
1567
1568 /*
1569 * Second item: Received-FIS area
1570 */
1571 pp->rx_fis = mem;
1572 pp->rx_fis_dma = mem_dma;
1573
1574 mem += AHCI_RX_FIS_SZ;
1575 mem_dma += AHCI_RX_FIS_SZ;
1576
1577 /*
1578 * Third item: data area for storing a single command
1579 * and its scatter-gather table
1580 */
1581 pp->cmd_tbl = mem;
1582 pp->cmd_tbl_dma = mem_dma;
1583
1584 ap->private_data = pp;
1585
1586 /* engage engines, captain */
1587 return ahci_port_resume(ap);
1588 }
1589
1590 static void ahci_port_stop(struct ata_port *ap)
1591 {
1592 const char *emsg = NULL;
1593 int rc;
1594
1595 /* de-initialize port */
1596 rc = ahci_deinit_port(ap, &emsg);
1597 if (rc)
1598 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1599 }
1600
1601 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1602 {
1603 int rc;
1604
1605 if (using_dac &&
1606 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1607 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1608 if (rc) {
1609 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1610 if (rc) {
1611 dev_printk(KERN_ERR, &pdev->dev,
1612 "64-bit DMA enable failed\n");
1613 return rc;
1614 }
1615 }
1616 } else {
1617 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1618 if (rc) {
1619 dev_printk(KERN_ERR, &pdev->dev,
1620 "32-bit DMA enable failed\n");
1621 return rc;
1622 }
1623 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1624 if (rc) {
1625 dev_printk(KERN_ERR, &pdev->dev,
1626 "32-bit consistent DMA enable failed\n");
1627 return rc;
1628 }
1629 }
1630 return 0;
1631 }
1632
1633 static void ahci_print_info(struct ata_host *host)
1634 {
1635 struct ahci_host_priv *hpriv = host->private_data;
1636 struct pci_dev *pdev = to_pci_dev(host->dev);
1637 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1638 u32 vers, cap, impl, speed;
1639 const char *speed_s;
1640 u16 cc;
1641 const char *scc_s;
1642
1643 vers = readl(mmio + HOST_VERSION);
1644 cap = hpriv->cap;
1645 impl = hpriv->port_map;
1646
1647 speed = (cap >> 20) & 0xf;
1648 if (speed == 1)
1649 speed_s = "1.5";
1650 else if (speed == 2)
1651 speed_s = "3";
1652 else
1653 speed_s = "?";
1654
1655 pci_read_config_word(pdev, 0x0a, &cc);
1656 if (cc == PCI_CLASS_STORAGE_IDE)
1657 scc_s = "IDE";
1658 else if (cc == PCI_CLASS_STORAGE_SATA)
1659 scc_s = "SATA";
1660 else if (cc == PCI_CLASS_STORAGE_RAID)
1661 scc_s = "RAID";
1662 else
1663 scc_s = "unknown";
1664
1665 dev_printk(KERN_INFO, &pdev->dev,
1666 "AHCI %02x%02x.%02x%02x "
1667 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1668 ,
1669
1670 (vers >> 24) & 0xff,
1671 (vers >> 16) & 0xff,
1672 (vers >> 8) & 0xff,
1673 vers & 0xff,
1674
1675 ((cap >> 8) & 0x1f) + 1,
1676 (cap & 0x1f) + 1,
1677 speed_s,
1678 impl,
1679 scc_s);
1680
1681 dev_printk(KERN_INFO, &pdev->dev,
1682 "flags: "
1683 "%s%s%s%s%s%s"
1684 "%s%s%s%s%s%s%s\n"
1685 ,
1686
1687 cap & (1 << 31) ? "64bit " : "",
1688 cap & (1 << 30) ? "ncq " : "",
1689 cap & (1 << 28) ? "ilck " : "",
1690 cap & (1 << 27) ? "stag " : "",
1691 cap & (1 << 26) ? "pm " : "",
1692 cap & (1 << 25) ? "led " : "",
1693
1694 cap & (1 << 24) ? "clo " : "",
1695 cap & (1 << 19) ? "nz " : "",
1696 cap & (1 << 18) ? "only " : "",
1697 cap & (1 << 17) ? "pmp " : "",
1698 cap & (1 << 15) ? "pio " : "",
1699 cap & (1 << 14) ? "slum " : "",
1700 cap & (1 << 13) ? "part " : ""
1701 );
1702 }
1703
1704 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1705 {
1706 static int printed_version;
1707 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1708 const struct ata_port_info *ppi[] = { &pi, NULL };
1709 struct device *dev = &pdev->dev;
1710 struct ahci_host_priv *hpriv;
1711 struct ata_host *host;
1712 int i, rc;
1713
1714 VPRINTK("ENTER\n");
1715
1716 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1717
1718 if (!printed_version++)
1719 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1720
1721 /* acquire resources */
1722 rc = pcim_enable_device(pdev);
1723 if (rc)
1724 return rc;
1725
1726 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1727 if (rc == -EBUSY)
1728 pcim_pin_device(pdev);
1729 if (rc)
1730 return rc;
1731
1732 if (pci_enable_msi(pdev))
1733 pci_intx(pdev, 1);
1734
1735 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1736 if (!hpriv)
1737 return -ENOMEM;
1738
1739 /* save initial config */
1740 ahci_save_initial_config(pdev, &pi, hpriv);
1741
1742 /* prepare host */
1743 if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ))
1744 pi.flags |= ATA_FLAG_NCQ;
1745
1746 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1747 if (!host)
1748 return -ENOMEM;
1749 host->iomap = pcim_iomap_table(pdev);
1750 host->private_data = hpriv;
1751
1752 for (i = 0; i < host->n_ports; i++) {
1753 if (hpriv->port_map & (1 << i)) {
1754 struct ata_port *ap = host->ports[i];
1755 void __iomem *port_mmio = ahci_port_base(ap);
1756
1757 ap->ioaddr.cmd_addr = port_mmio;
1758 ap->ioaddr.scr_addr = port_mmio + PORT_SCR;
1759 } else
1760 host->ports[i]->ops = &ata_dummy_port_ops;
1761 }
1762
1763 /* initialize adapter */
1764 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1765 if (rc)
1766 return rc;
1767
1768 rc = ahci_reset_controller(host);
1769 if (rc)
1770 return rc;
1771
1772 ahci_init_controller(host);
1773 ahci_print_info(host);
1774
1775 pci_set_master(pdev);
1776 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1777 &ahci_sht);
1778 }
1779
1780 static int __init ahci_init(void)
1781 {
1782 return pci_register_driver(&ahci_pci_driver);
1783 }
1784
1785 static void __exit ahci_exit(void)
1786 {
1787 pci_unregister_driver(&ahci_pci_driver);
1788 }
1789
1790
1791 MODULE_AUTHOR("Jeff Garzik");
1792 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1793 MODULE_LICENSE("GPL");
1794 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1795 MODULE_VERSION(DRV_VERSION);
1796
1797 module_init(ahci_init);
1798 module_exit(ahci_exit);
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