2 * AppliedMicro X-Gene SoC SATA Host Controller Driver
4 * Copyright (c) 2014, Applied Micro Circuits Corporation
5 * Author: Loc Ho <lho@apm.com>
6 * Tuan Phan <tphan@apm.com>
7 * Suman Tripathi <stripathi@apm.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 * NOTE: PM support is not currently available.
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/ahci_platform.h>
28 #include <linux/of_address.h>
29 #include <linux/of_irq.h>
30 #include <linux/phy/phy.h>
33 /* Max # of disk per a controller */
34 #define MAX_AHCI_CHN_PERCTR 2
37 #define SATA_ENET_CONFIG_REG 0x00000000
38 #define CFG_SATA_ENET_SELECT_MASK 0x00000001
40 /* SATA core host controller CSR */
41 #define SLVRDERRATTRIBUTES 0x00000000
42 #define SLVWRERRATTRIBUTES 0x00000004
43 #define MSTRDERRATTRIBUTES 0x00000008
44 #define MSTWRERRATTRIBUTES 0x0000000c
45 #define BUSCTLREG 0x00000014
46 #define IOFMSTRWAUX 0x00000018
47 #define INTSTATUSMASK 0x0000002c
48 #define ERRINTSTATUS 0x00000030
49 #define ERRINTSTATUSMASK 0x00000034
51 /* SATA host AHCI CSR */
52 #define PORTCFG 0x000000a4
53 #define PORTADDR_SET(dst, src) \
54 (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
55 #define PORTPHY1CFG 0x000000a8
56 #define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
57 (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
58 #define PORTPHY2CFG 0x000000ac
59 #define PORTPHY3CFG 0x000000b0
60 #define PORTPHY4CFG 0x000000b4
61 #define PORTPHY5CFG 0x000000b8
62 #define SCTL0 0x0000012C
63 #define PORTPHY5CFG_RTCHG_SET(dst, src) \
64 (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
65 #define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
66 (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
67 #define PORTAXICFG 0x000000bc
68 #define PORTAXICFG_OUTTRANS_SET(dst, src) \
69 (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
70 #define PORTRANSCFG 0x000000c8
71 #define PORTRANSCFG_RXWM_SET(dst, src) \
72 (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))
74 /* SATA host controller AXI CSR */
75 #define INT_SLV_TMOMASK 0x00000010
77 /* SATA diagnostic CSR */
78 #define CFG_MEM_RAM_SHUTDOWN 0x00000070
79 #define BLOCK_MEM_RDY 0x00000074
81 /* Max retry for link down */
82 #define MAX_LINK_DOWN_RETRY 3
84 struct xgene_ahci_context
{
85 struct ahci_host_priv
*hpriv
;
87 u8 last_cmd
[MAX_AHCI_CHN_PERCTR
]; /* tracking the last command issued*/
88 void __iomem
*csr_core
; /* Core CSR address of IP */
89 void __iomem
*csr_diag
; /* Diag CSR address of IP */
90 void __iomem
*csr_axi
; /* AXI CSR address of IP */
91 void __iomem
*csr_mux
; /* MUX CSR address of IP */
94 static int xgene_ahci_init_memram(struct xgene_ahci_context
*ctx
)
96 dev_dbg(ctx
->dev
, "Release memory from shutdown\n");
97 writel(0x0, ctx
->csr_diag
+ CFG_MEM_RAM_SHUTDOWN
);
98 readl(ctx
->csr_diag
+ CFG_MEM_RAM_SHUTDOWN
); /* Force a barrier */
99 msleep(1); /* reset may take up to 1ms */
100 if (readl(ctx
->csr_diag
+ BLOCK_MEM_RDY
) != 0xFFFFFFFF) {
101 dev_err(ctx
->dev
, "failed to release memory from shutdown\n");
108 * xgene_ahci_poll_reg_val- Poll a register on a specific value.
109 * @ap : ATA port of interest.
110 * @reg : Register of interest.
111 * @val : Value to be attained.
112 * @interval : waiting interval for polling.
113 * @timeout : timeout for achieving the value.
115 static int xgene_ahci_poll_reg_val(struct ata_port
*ap
,
116 void __iomem
*reg
, unsigned
117 int val
, unsigned long interval
,
118 unsigned long timeout
)
120 unsigned long deadline
;
124 deadline
= ata_deadline(jiffies
, timeout
);
126 while (tmp
!= val
&& time_before(jiffies
, deadline
)) {
127 ata_msleep(ap
, interval
);
135 * xgene_ahci_restart_engine - Restart the dma engine.
136 * @ap : ATA port of interest
138 * Waits for completion of multiple commands and restarts
139 * the DMA engine inside the controller.
141 static int xgene_ahci_restart_engine(struct ata_port
*ap
)
143 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
144 struct ahci_port_priv
*pp
= ap
->private_data
;
145 void __iomem
*port_mmio
= ahci_port_base(ap
);
149 * In case of PMP multiple IDENTIFY DEVICE commands can be
150 * issued inside PxCI. So need to poll PxCI for the
151 * completion of outstanding IDENTIFY DEVICE commands before
152 * we restart the DMA engine.
154 if (xgene_ahci_poll_reg_val(ap
, port_mmio
+
155 PORT_CMD_ISSUE
, 0x0, 1, 100))
158 ahci_stop_engine(ap
);
159 ahci_start_fis_rx(ap
);
162 * Enable the PxFBS.FBS_EN bit as it
163 * gets cleared due to stopping the engine.
165 if (pp
->fbs_supported
) {
166 fbs
= readl(port_mmio
+ PORT_FBS
);
167 writel(fbs
| PORT_FBS_EN
, port_mmio
+ PORT_FBS
);
168 fbs
= readl(port_mmio
+ PORT_FBS
);
171 hpriv
->start_engine(ap
);
177 * xgene_ahci_qc_issue - Issue commands to the device
178 * @qc: Command to issue
180 * Due to Hardware errata for IDENTIFY DEVICE command and PACKET
181 * command of ATAPI protocol set, the controller cannot clear the BSY bit
182 * after receiving the PIO setup FIS. This results in the DMA state machine
183 * going into the CMFatalErrorUpdate state and locks up. By restarting the
184 * DMA engine, it removes the controller out of lock up state.
186 static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd
*qc
)
188 struct ata_port
*ap
= qc
->ap
;
189 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
190 struct xgene_ahci_context
*ctx
= hpriv
->plat_data
;
193 if (unlikely((ctx
->last_cmd
[ap
->port_no
] == ATA_CMD_ID_ATA
) ||
194 (ctx
->last_cmd
[ap
->port_no
] == ATA_CMD_PACKET
)))
195 xgene_ahci_restart_engine(ap
);
197 rc
= ahci_qc_issue(qc
);
199 /* Save the last command issued */
200 ctx
->last_cmd
[ap
->port_no
] = qc
->tf
.command
;
205 static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context
*ctx
)
207 void __iomem
*diagcsr
= ctx
->csr_diag
;
209 return (readl(diagcsr
+ CFG_MEM_RAM_SHUTDOWN
) == 0 &&
210 readl(diagcsr
+ BLOCK_MEM_RDY
) == 0xFFFFFFFF);
214 * xgene_ahci_read_id - Read ID data from the specified device
216 * @tf: proposed taskfile
219 * This custom read ID function is required due to the fact that the HW
220 * does not support DEVSLP.
222 static unsigned int xgene_ahci_read_id(struct ata_device
*dev
,
223 struct ata_taskfile
*tf
, u16
*id
)
227 err_mask
= ata_do_dev_read_id(dev
, tf
, id
);
232 * Mask reserved area. Word78 spec of Link Power Management
234 * bit7: NCQ autosence
235 * bit6: Software settings preservation supported
237 * bit4: In-order sata delivery supported
238 * bit3: DIPM requests supported
239 * bit2: DMA Setup FIS Auto-Activate optimization supported
240 * bit1: DMA Setup FIX non-Zero buffer offsets supported
243 * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP
245 id
[ATA_ID_FEATURE_SUPP
] &= cpu_to_le16(~(1 << 8));
250 static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context
*ctx
, int channel
)
252 void __iomem
*mmio
= ctx
->hpriv
->mmio
;
255 dev_dbg(ctx
->dev
, "port configure mmio 0x%p channel %d\n",
257 val
= readl(mmio
+ PORTCFG
);
258 val
= PORTADDR_SET(val
, channel
== 0 ? 2 : 3);
259 writel(val
, mmio
+ PORTCFG
);
260 readl(mmio
+ PORTCFG
); /* Force a barrier */
261 /* Disable fix rate */
262 writel(0x0001fffe, mmio
+ PORTPHY1CFG
);
263 readl(mmio
+ PORTPHY1CFG
); /* Force a barrier */
264 writel(0x28183219, mmio
+ PORTPHY2CFG
);
265 readl(mmio
+ PORTPHY2CFG
); /* Force a barrier */
266 writel(0x13081008, mmio
+ PORTPHY3CFG
);
267 readl(mmio
+ PORTPHY3CFG
); /* Force a barrier */
268 writel(0x00480815, mmio
+ PORTPHY4CFG
);
269 readl(mmio
+ PORTPHY4CFG
); /* Force a barrier */
270 /* Set window negotiation */
271 val
= readl(mmio
+ PORTPHY5CFG
);
272 val
= PORTPHY5CFG_RTCHG_SET(val
, 0x300);
273 writel(val
, mmio
+ PORTPHY5CFG
);
274 readl(mmio
+ PORTPHY5CFG
); /* Force a barrier */
275 val
= readl(mmio
+ PORTAXICFG
);
276 val
= PORTAXICFG_EN_CONTEXT_SET(val
, 0x1); /* Enable context mgmt */
277 val
= PORTAXICFG_OUTTRANS_SET(val
, 0xe); /* Set outstanding */
278 writel(val
, mmio
+ PORTAXICFG
);
279 readl(mmio
+ PORTAXICFG
); /* Force a barrier */
280 /* Set the watermark threshold of the receive FIFO */
281 val
= readl(mmio
+ PORTRANSCFG
);
282 val
= PORTRANSCFG_RXWM_SET(val
, 0x30);
283 writel(val
, mmio
+ PORTRANSCFG
);
287 * xgene_ahci_do_hardreset - Issue the actual COMRESET
288 * @link: link to reset
289 * @deadline: deadline jiffies for the operation
290 * @online: Return value to indicate if device online
292 * Due to the limitation of the hardware PHY, a difference set of setting is
293 * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
294 * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
295 * report disparity error and etc. In addition, during COMRESET, there can
296 * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and
297 * SERR_10B_8B_ERR, the PHY receiver line must be reseted. Also during long
298 * reboot cycle regression, sometimes the PHY reports link down even if the
299 * device is present because of speed negotiation failure. so need to retry
300 * the COMRESET to get the link up. The following algorithm is followed to
301 * proper configure the hardware PHY during COMRESET:
304 * 1. Start the PHY at Gen3 speed (default setting)
305 * 2. Issue the COMRESET
306 * 3. If no link, go to Alg Part 3
307 * 4. If link up, determine if the negotiated speed matches the PHY
309 * 5. If they matched, go to Alg Part 2
310 * 6. If they do not matched and first time, configure the PHY for the linked
311 * up disk speed and repeat step 2
312 * 7. Go to Alg Part 2
315 * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error
316 * reported in the register PORT_SCR_ERR, then reset the PHY receiver line
317 * 2. Go to Alg Part 4
320 * 1. Check the PORT_SCR_STAT to see whether device presence detected but PHY
321 * communication establishment failed and maximum link down attempts are
322 * less than Max attempts 3 then goto Alg Part 1.
323 * 2. Go to Alg Part 4.
326 * 1. Clear any pending from register PORT_SCR_ERR.
328 * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition
329 * and until the underlying PHY supports an method to reset the receiver
330 * line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors,
331 * an warning message will be printed.
333 static int xgene_ahci_do_hardreset(struct ata_link
*link
,
334 unsigned long deadline
, bool *online
)
336 const unsigned long *timing
= sata_ehc_deb_timing(&link
->eh_context
);
337 struct ata_port
*ap
= link
->ap
;
338 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
339 struct xgene_ahci_context
*ctx
= hpriv
->plat_data
;
340 struct ahci_port_priv
*pp
= ap
->private_data
;
341 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
342 void __iomem
*port_mmio
= ahci_port_base(ap
);
343 struct ata_taskfile tf
;
344 int link_down_retry
= 0;
349 /* clear D2H reception area to properly wait for D2H FIS */
350 ata_tf_init(link
->device
, &tf
);
351 tf
.command
= ATA_BUSY
;
352 ata_tf_to_fis(&tf
, 0, 0, d2h_fis
);
353 rc
= sata_link_hardreset(link
, timing
, deadline
, online
,
356 val
= readl(port_mmio
+ PORT_SCR_ERR
);
357 if (val
& (SERR_DISPARITY
| SERR_10B_8B_ERR
))
358 dev_warn(ctx
->dev
, "link has error\n");
362 sata_scr_read(link
, SCR_STATUS
, &sstatus
);
363 } while (link_down_retry
++ < MAX_LINK_DOWN_RETRY
&&
364 (sstatus
& 0xff) == 0x1);
366 /* clear all errors if any pending */
367 val
= readl(port_mmio
+ PORT_SCR_ERR
);
368 writel(val
, port_mmio
+ PORT_SCR_ERR
);
373 static int xgene_ahci_hardreset(struct ata_link
*link
, unsigned int *class,
374 unsigned long deadline
)
376 struct ata_port
*ap
= link
->ap
;
377 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
378 void __iomem
*port_mmio
= ahci_port_base(ap
);
385 u32 portrxfishi_saved
;
387 /* As hardreset resets these CSR, save it to restore later */
388 portcmd_saved
= readl(port_mmio
+ PORT_CMD
);
389 portclb_saved
= readl(port_mmio
+ PORT_LST_ADDR
);
390 portclbhi_saved
= readl(port_mmio
+ PORT_LST_ADDR_HI
);
391 portrxfis_saved
= readl(port_mmio
+ PORT_FIS_ADDR
);
392 portrxfishi_saved
= readl(port_mmio
+ PORT_FIS_ADDR_HI
);
394 ahci_stop_engine(ap
);
396 rc
= xgene_ahci_do_hardreset(link
, deadline
, &online
);
398 /* As controller hardreset clears them, restore them */
399 writel(portcmd_saved
, port_mmio
+ PORT_CMD
);
400 writel(portclb_saved
, port_mmio
+ PORT_LST_ADDR
);
401 writel(portclbhi_saved
, port_mmio
+ PORT_LST_ADDR_HI
);
402 writel(portrxfis_saved
, port_mmio
+ PORT_FIS_ADDR
);
403 writel(portrxfishi_saved
, port_mmio
+ PORT_FIS_ADDR_HI
);
405 hpriv
->start_engine(ap
);
408 *class = ahci_dev_classify(ap
);
413 static void xgene_ahci_host_stop(struct ata_host
*host
)
415 struct ahci_host_priv
*hpriv
= host
->private_data
;
417 ahci_platform_disable_resources(hpriv
);
420 static struct ata_port_operations xgene_ahci_ops
= {
421 .inherits
= &ahci_ops
,
422 .host_stop
= xgene_ahci_host_stop
,
423 .hardreset
= xgene_ahci_hardreset
,
424 .read_id
= xgene_ahci_read_id
,
425 .qc_issue
= xgene_ahci_qc_issue
,
428 static const struct ata_port_info xgene_ahci_port_info
= {
429 .flags
= AHCI_FLAG_COMMON
| ATA_FLAG_PMP
,
430 .pio_mask
= ATA_PIO4
,
431 .udma_mask
= ATA_UDMA6
,
432 .port_ops
= &xgene_ahci_ops
,
435 static int xgene_ahci_hw_init(struct ahci_host_priv
*hpriv
)
437 struct xgene_ahci_context
*ctx
= hpriv
->plat_data
;
442 /* Remove IP RAM out of shutdown */
443 rc
= xgene_ahci_init_memram(ctx
);
447 for (i
= 0; i
< MAX_AHCI_CHN_PERCTR
; i
++)
448 xgene_ahci_set_phy_cfg(ctx
, i
);
450 /* AXI disable Mask */
451 writel(0xffffffff, hpriv
->mmio
+ HOST_IRQ_STAT
);
452 readl(hpriv
->mmio
+ HOST_IRQ_STAT
); /* Force a barrier */
453 writel(0, ctx
->csr_core
+ INTSTATUSMASK
);
454 val
= readl(ctx
->csr_core
+ INTSTATUSMASK
); /* Force a barrier */
455 dev_dbg(ctx
->dev
, "top level interrupt mask 0x%X value 0x%08X\n",
458 writel(0x0, ctx
->csr_core
+ ERRINTSTATUSMASK
);
459 readl(ctx
->csr_core
+ ERRINTSTATUSMASK
); /* Force a barrier */
460 writel(0x0, ctx
->csr_axi
+ INT_SLV_TMOMASK
);
461 readl(ctx
->csr_axi
+ INT_SLV_TMOMASK
);
463 /* Enable AXI Interrupt */
464 writel(0xffffffff, ctx
->csr_core
+ SLVRDERRATTRIBUTES
);
465 writel(0xffffffff, ctx
->csr_core
+ SLVWRERRATTRIBUTES
);
466 writel(0xffffffff, ctx
->csr_core
+ MSTRDERRATTRIBUTES
);
467 writel(0xffffffff, ctx
->csr_core
+ MSTWRERRATTRIBUTES
);
469 /* Enable coherency */
470 val
= readl(ctx
->csr_core
+ BUSCTLREG
);
471 val
&= ~0x00000002; /* Enable write coherency */
472 val
&= ~0x00000001; /* Enable read coherency */
473 writel(val
, ctx
->csr_core
+ BUSCTLREG
);
475 val
= readl(ctx
->csr_core
+ IOFMSTRWAUX
);
476 val
|= (1 << 3); /* Enable read coherency */
477 val
|= (1 << 9); /* Enable write coherency */
478 writel(val
, ctx
->csr_core
+ IOFMSTRWAUX
);
479 val
= readl(ctx
->csr_core
+ IOFMSTRWAUX
);
480 dev_dbg(ctx
->dev
, "coherency 0x%X value 0x%08X\n",
486 static int xgene_ahci_mux_select(struct xgene_ahci_context
*ctx
)
490 /* Check for optional MUX resource */
494 val
= readl(ctx
->csr_mux
+ SATA_ENET_CONFIG_REG
);
495 val
&= ~CFG_SATA_ENET_SELECT_MASK
;
496 writel(val
, ctx
->csr_mux
+ SATA_ENET_CONFIG_REG
);
497 val
= readl(ctx
->csr_mux
+ SATA_ENET_CONFIG_REG
);
498 return val
& CFG_SATA_ENET_SELECT_MASK
? -1 : 0;
501 static int xgene_ahci_probe(struct platform_device
*pdev
)
503 struct device
*dev
= &pdev
->dev
;
504 struct ahci_host_priv
*hpriv
;
505 struct xgene_ahci_context
*ctx
;
506 struct resource
*res
;
509 hpriv
= ahci_platform_get_resources(pdev
);
511 return PTR_ERR(hpriv
);
513 ctx
= devm_kzalloc(dev
, sizeof(*ctx
), GFP_KERNEL
);
517 hpriv
->plat_data
= ctx
;
521 /* Retrieve the IP core resource */
522 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
523 ctx
->csr_core
= devm_ioremap_resource(dev
, res
);
524 if (IS_ERR(ctx
->csr_core
))
525 return PTR_ERR(ctx
->csr_core
);
527 /* Retrieve the IP diagnostic resource */
528 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
529 ctx
->csr_diag
= devm_ioremap_resource(dev
, res
);
530 if (IS_ERR(ctx
->csr_diag
))
531 return PTR_ERR(ctx
->csr_diag
);
533 /* Retrieve the IP AXI resource */
534 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 3);
535 ctx
->csr_axi
= devm_ioremap_resource(dev
, res
);
536 if (IS_ERR(ctx
->csr_axi
))
537 return PTR_ERR(ctx
->csr_axi
);
539 /* Retrieve the optional IP mux resource */
540 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 4);
542 void __iomem
*csr
= devm_ioremap_resource(dev
, res
);
549 dev_dbg(dev
, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx
->csr_core
,
553 if ((rc
= xgene_ahci_mux_select(ctx
))) {
554 dev_err(dev
, "SATA mux selection failed error %d\n", rc
);
558 if (xgene_ahci_is_memram_inited(ctx
)) {
559 dev_info(dev
, "skip clock and PHY initialization\n");
563 /* Due to errata, HW requires full toggle transition */
564 rc
= ahci_platform_enable_clks(hpriv
);
566 goto disable_resources
;
567 ahci_platform_disable_clks(hpriv
);
569 rc
= ahci_platform_enable_resources(hpriv
);
571 goto disable_resources
;
573 /* Configure the host controller */
574 xgene_ahci_hw_init(hpriv
);
576 hpriv
->flags
= AHCI_HFLAG_NO_PMP
| AHCI_HFLAG_NO_NCQ
;
578 rc
= ahci_platform_init_host(pdev
, hpriv
, &xgene_ahci_port_info
);
580 goto disable_resources
;
582 dev_dbg(dev
, "X-Gene SATA host controller initialized\n");
586 ahci_platform_disable_resources(hpriv
);
590 static const struct of_device_id xgene_ahci_of_match
[] = {
591 {.compatible
= "apm,xgene-ahci"},
594 MODULE_DEVICE_TABLE(of
, xgene_ahci_of_match
);
596 static struct platform_driver xgene_ahci_driver
= {
597 .probe
= xgene_ahci_probe
,
598 .remove
= ata_platform_remove_one
,
600 .name
= "xgene-ahci",
601 .of_match_table
= xgene_ahci_of_match
,
605 module_platform_driver(xgene_ahci_driver
);
607 MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
608 MODULE_AUTHOR("Loc Ho <lho@apm.com>");
609 MODULE_LICENSE("GPL");
610 MODULE_VERSION("0.4");