2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
100 PIIX_IOCFG
= 0x54, /* IDE I/O configuration register */
101 ICH5_PMR
= 0x90, /* port mapping register */
102 ICH5_PCS
= 0x92, /* port control and status */
103 PIIX_SCC
= 0x0A, /* sub-class code register */
105 PIIX_FLAG_SCR
= (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI
= (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR
= (1 << 28), /* make sure PCI INTx enabled */
109 PIIX_PATA_FLAGS
= ATA_FLAG_SLAVE_POSS
,
110 PIIX_SATA_FLAGS
= ATA_FLAG_SATA
| PIIX_FLAG_CHECKINTR
,
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
115 PIIX_PORT_ENABLED
= (1 << 0),
116 PIIX_PORT_PRESENT
= (1 << 4),
118 PIIX_80C_PRI
= (1 << 5) | (1 << 4),
119 PIIX_80C_SEC
= (1 << 7) | (1 << 6),
122 piix_pata_33
= 0, /* PIIX4 at 33Mhz */
123 ich_pata_33
= 1, /* ICH up to UDMA 33 only */
124 ich_pata_66
= 2, /* ICH up to 66 Mhz */
125 ich_pata_100
= 3, /* ICH up to UDMA 100 */
131 piix_pata_mwdma
= 10, /* PIIX3 MWDMA only */
132 tolapai_sata_ahci
= 11,
133 ich9_2port_sata
= 12,
135 /* constants for mapping table */
141 NA
= -2, /* not avaliable */
142 RV
= -3, /* reserved */
144 PIIX_AHCI_DEVICE
= 6,
146 /* host->flags bits */
147 PIIX_HOST_BROKEN_SUSPEND
= (1 << 24),
152 const u16 port_enable
;
156 struct piix_host_priv
{
160 static int piix_init_one(struct pci_dev
*pdev
,
161 const struct pci_device_id
*ent
);
162 static void piix_pata_error_handler(struct ata_port
*ap
);
163 static void piix_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
);
164 static void piix_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
);
165 static void ich_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
);
166 static int ich_pata_cable_detect(struct ata_port
*ap
);
168 static int piix_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
);
169 static int piix_pci_device_resume(struct pci_dev
*pdev
);
172 static unsigned int in_module_init
= 1;
174 static const struct pci_device_id piix_pci_tbl
[] = {
175 /* Intel PIIX3 for the 430HX etc */
176 { 0x8086, 0x7010, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_mwdma
},
177 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
178 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
179 { 0x8086, 0x7111, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
181 { 0x8086, 0x7199, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
183 { 0x8086, 0x7601, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
185 { 0x8086, 0x84CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
186 /* Intel ICH (i810, i815, i840) UDMA 66*/
187 { 0x8086, 0x2411, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_66
},
188 /* Intel ICH0 : UDMA 33*/
189 { 0x8086, 0x2421, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_33
},
191 { 0x8086, 0x244A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
192 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
193 { 0x8086, 0x244B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
195 { 0x8086, 0x248A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
196 /* Intel ICH3 (E7500/1) UDMA 100 */
197 { 0x8086, 0x248B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
198 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
199 { 0x8086, 0x24CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
200 { 0x8086, 0x24CB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
202 { 0x8086, 0x24DB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
204 { 0x8086, 0x245B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
205 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
206 { 0x8086, 0x25A2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
207 /* ICH6 (and 6) (i915) UDMA 100 */
208 { 0x8086, 0x266F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
209 /* ICH7/7-R (i945, i975) UDMA 100*/
210 { 0x8086, 0x27DF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
211 { 0x8086, 0x269E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
212 /* ICH8 Mobile PATA Controller */
213 { 0x8086, 0x2850, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
215 /* NOTE: The following PCI ids must be kept in sync with the
216 * list in drivers/pci/quirks.c.
220 { 0x8086, 0x24d1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
222 { 0x8086, 0x24df, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
223 /* 6300ESB (ICH5 variant with broken PCS present bits) */
224 { 0x8086, 0x25a3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
225 /* 6300ESB pretending RAID */
226 { 0x8086, 0x25b0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
227 /* 82801FB/FW (ICH6/ICH6W) */
228 { 0x8086, 0x2651, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
229 /* 82801FR/FRW (ICH6R/ICH6RW) */
230 { 0x8086, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
231 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
232 { 0x8086, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6m_sata_ahci
},
233 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
234 { 0x8086, 0x27c0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
235 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
236 { 0x8086, 0x27c4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6m_sata_ahci
},
237 /* Enterprise Southbridge 2 (631xESB/632xESB) */
238 { 0x8086, 0x2680, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
239 /* SATA Controller 1 IDE (ICH8) */
240 { 0x8086, 0x2820, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
241 /* SATA Controller 2 IDE (ICH8) */
242 { 0x8086, 0x2825, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich9_2port_sata
},
243 /* Mobile SATA Controller IDE (ICH8M) */
244 { 0x8086, 0x2828, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
245 /* SATA Controller IDE (ICH9) */
246 { 0x8086, 0x2920, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
247 /* SATA Controller IDE (ICH9) */
248 { 0x8086, 0x2921, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich9_2port_sata
},
249 /* SATA Controller IDE (ICH9) */
250 { 0x8086, 0x2926, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich9_2port_sata
},
251 /* SATA Controller IDE (ICH9M) */
252 { 0x8086, 0x2928, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich9_2port_sata
},
253 /* SATA Controller IDE (ICH9M) */
254 { 0x8086, 0x292d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich9_2port_sata
},
255 /* SATA Controller IDE (ICH9M) */
256 { 0x8086, 0x292e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
257 /* SATA Controller IDE (Tolapai) */
258 { 0x8086, 0x5028, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, tolapai_sata_ahci
},
260 { } /* terminate list */
263 static struct pci_driver piix_pci_driver
= {
265 .id_table
= piix_pci_tbl
,
266 .probe
= piix_init_one
,
267 .remove
= ata_pci_remove_one
,
269 .suspend
= piix_pci_device_suspend
,
270 .resume
= piix_pci_device_resume
,
274 static struct scsi_host_template piix_sht
= {
275 .module
= THIS_MODULE
,
277 .ioctl
= ata_scsi_ioctl
,
278 .queuecommand
= ata_scsi_queuecmd
,
279 .can_queue
= ATA_DEF_QUEUE
,
280 .this_id
= ATA_SHT_THIS_ID
,
281 .sg_tablesize
= LIBATA_MAX_PRD
,
282 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
283 .emulated
= ATA_SHT_EMULATED
,
284 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
285 .proc_name
= DRV_NAME
,
286 .dma_boundary
= ATA_DMA_BOUNDARY
,
287 .slave_configure
= ata_scsi_slave_config
,
288 .slave_destroy
= ata_scsi_slave_destroy
,
289 .bios_param
= ata_std_bios_param
,
292 static const struct ata_port_operations piix_pata_ops
= {
293 .set_piomode
= piix_set_piomode
,
294 .set_dmamode
= piix_set_dmamode
,
295 .mode_filter
= ata_pci_default_filter
,
297 .tf_load
= ata_tf_load
,
298 .tf_read
= ata_tf_read
,
299 .check_status
= ata_check_status
,
300 .exec_command
= ata_exec_command
,
301 .dev_select
= ata_std_dev_select
,
303 .bmdma_setup
= ata_bmdma_setup
,
304 .bmdma_start
= ata_bmdma_start
,
305 .bmdma_stop
= ata_bmdma_stop
,
306 .bmdma_status
= ata_bmdma_status
,
307 .qc_prep
= ata_qc_prep
,
308 .qc_issue
= ata_qc_issue_prot
,
309 .data_xfer
= ata_data_xfer
,
311 .freeze
= ata_bmdma_freeze
,
312 .thaw
= ata_bmdma_thaw
,
313 .error_handler
= piix_pata_error_handler
,
314 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
315 .cable_detect
= ata_cable_40wire
,
317 .irq_handler
= ata_interrupt
,
318 .irq_clear
= ata_bmdma_irq_clear
,
319 .irq_on
= ata_irq_on
,
321 .port_start
= ata_port_start
,
324 static const struct ata_port_operations ich_pata_ops
= {
325 .set_piomode
= piix_set_piomode
,
326 .set_dmamode
= ich_set_dmamode
,
327 .mode_filter
= ata_pci_default_filter
,
329 .tf_load
= ata_tf_load
,
330 .tf_read
= ata_tf_read
,
331 .check_status
= ata_check_status
,
332 .exec_command
= ata_exec_command
,
333 .dev_select
= ata_std_dev_select
,
335 .bmdma_setup
= ata_bmdma_setup
,
336 .bmdma_start
= ata_bmdma_start
,
337 .bmdma_stop
= ata_bmdma_stop
,
338 .bmdma_status
= ata_bmdma_status
,
339 .qc_prep
= ata_qc_prep
,
340 .qc_issue
= ata_qc_issue_prot
,
341 .data_xfer
= ata_data_xfer
,
343 .freeze
= ata_bmdma_freeze
,
344 .thaw
= ata_bmdma_thaw
,
345 .error_handler
= piix_pata_error_handler
,
346 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
347 .cable_detect
= ich_pata_cable_detect
,
349 .irq_handler
= ata_interrupt
,
350 .irq_clear
= ata_bmdma_irq_clear
,
351 .irq_on
= ata_irq_on
,
353 .port_start
= ata_port_start
,
356 static const struct ata_port_operations piix_sata_ops
= {
357 .tf_load
= ata_tf_load
,
358 .tf_read
= ata_tf_read
,
359 .check_status
= ata_check_status
,
360 .exec_command
= ata_exec_command
,
361 .dev_select
= ata_std_dev_select
,
363 .bmdma_setup
= ata_bmdma_setup
,
364 .bmdma_start
= ata_bmdma_start
,
365 .bmdma_stop
= ata_bmdma_stop
,
366 .bmdma_status
= ata_bmdma_status
,
367 .qc_prep
= ata_qc_prep
,
368 .qc_issue
= ata_qc_issue_prot
,
369 .data_xfer
= ata_data_xfer
,
371 .freeze
= ata_bmdma_freeze
,
372 .thaw
= ata_bmdma_thaw
,
373 .error_handler
= ata_bmdma_error_handler
,
374 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
376 .irq_handler
= ata_interrupt
,
377 .irq_clear
= ata_bmdma_irq_clear
,
378 .irq_on
= ata_irq_on
,
380 .port_start
= ata_port_start
,
383 static const struct piix_map_db ich5_map_db
= {
387 /* PM PS SM SS MAP */
388 { P0
, NA
, P1
, NA
}, /* 000b */
389 { P1
, NA
, P0
, NA
}, /* 001b */
392 { P0
, P1
, IDE
, IDE
}, /* 100b */
393 { P1
, P0
, IDE
, IDE
}, /* 101b */
394 { IDE
, IDE
, P0
, P1
}, /* 110b */
395 { IDE
, IDE
, P1
, P0
}, /* 111b */
399 static const struct piix_map_db ich6_map_db
= {
403 /* PM PS SM SS MAP */
404 { P0
, P2
, P1
, P3
}, /* 00b */
405 { IDE
, IDE
, P1
, P3
}, /* 01b */
406 { P0
, P2
, IDE
, IDE
}, /* 10b */
411 static const struct piix_map_db ich6m_map_db
= {
415 /* Map 01b isn't specified in the doc but some notebooks use
416 * it anyway. MAP 01b have been spotted on both ICH6M and
420 /* PM PS SM SS MAP */
421 { P0
, P2
, NA
, NA
}, /* 00b */
422 { IDE
, IDE
, P1
, P3
}, /* 01b */
423 { P0
, P2
, IDE
, IDE
}, /* 10b */
428 static const struct piix_map_db ich8_map_db
= {
432 /* PM PS SM SS MAP */
433 { P0
, P2
, P1
, P3
}, /* 00b (hardwired when in AHCI) */
435 { P0
, P2
, IDE
, IDE
}, /* 10b (IDE mode) */
440 static const struct piix_map_db tolapai_map_db
= {
444 /* PM PS SM SS MAP */
445 { P0
, NA
, P1
, NA
}, /* 00b */
446 { RV
, RV
, RV
, RV
}, /* 01b */
447 { RV
, RV
, RV
, RV
}, /* 10b */
452 static const struct piix_map_db ich9_2port_map_db
= {
456 /* PM PS SM SS MAP */
457 { P0
, NA
, P1
, NA
}, /* 00b */
458 { RV
, RV
, RV
, RV
}, /* 01b */
459 { RV
, RV
, RV
, RV
}, /* 10b */
464 static const struct piix_map_db
*piix_map_db_table
[] = {
465 [ich5_sata
] = &ich5_map_db
,
466 [ich6_sata
] = &ich6_map_db
,
467 [ich6_sata_ahci
] = &ich6_map_db
,
468 [ich6m_sata_ahci
] = &ich6m_map_db
,
469 [ich8_sata_ahci
] = &ich8_map_db
,
470 [tolapai_sata_ahci
] = &tolapai_map_db
,
471 [ich9_2port_sata
] = &ich9_2port_map_db
,
474 static struct ata_port_info piix_port_info
[] = {
475 [piix_pata_33
] = /* PIIX4 at 33MHz */
478 .flags
= PIIX_PATA_FLAGS
,
479 .pio_mask
= 0x1f, /* pio0-4 */
480 .mwdma_mask
= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
481 .udma_mask
= ATA_UDMA_MASK_40C
,
482 .port_ops
= &piix_pata_ops
,
485 [ich_pata_33
] = /* ICH0 - ICH at 33Mhz*/
488 .flags
= PIIX_PATA_FLAGS
,
489 .pio_mask
= 0x1f, /* pio 0-4 */
490 .mwdma_mask
= 0x06, /* Check: maybe 0x07 */
491 .udma_mask
= ATA_UDMA2
, /* UDMA33 */
492 .port_ops
= &ich_pata_ops
,
495 [ich_pata_66
] = /* ICH controllers up to 66MHz */
498 .flags
= PIIX_PATA_FLAGS
,
499 .pio_mask
= 0x1f, /* pio 0-4 */
500 .mwdma_mask
= 0x06, /* MWDMA0 is broken on chip */
501 .udma_mask
= ATA_UDMA4
,
502 .port_ops
= &ich_pata_ops
,
508 .flags
= PIIX_PATA_FLAGS
| PIIX_FLAG_CHECKINTR
,
509 .pio_mask
= 0x1f, /* pio0-4 */
510 .mwdma_mask
= 0x06, /* mwdma1-2 */
511 .udma_mask
= ATA_UDMA5
, /* udma0-5 */
512 .port_ops
= &ich_pata_ops
,
518 .flags
= PIIX_SATA_FLAGS
,
519 .pio_mask
= 0x1f, /* pio0-4 */
520 .mwdma_mask
= 0x07, /* mwdma0-2 */
521 .udma_mask
= ATA_UDMA6
,
522 .port_ops
= &piix_sata_ops
,
528 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
,
529 .pio_mask
= 0x1f, /* pio0-4 */
530 .mwdma_mask
= 0x07, /* mwdma0-2 */
531 .udma_mask
= ATA_UDMA6
,
532 .port_ops
= &piix_sata_ops
,
538 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
540 .pio_mask
= 0x1f, /* pio0-4 */
541 .mwdma_mask
= 0x07, /* mwdma0-2 */
542 .udma_mask
= ATA_UDMA6
,
543 .port_ops
= &piix_sata_ops
,
549 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
551 .pio_mask
= 0x1f, /* pio0-4 */
552 .mwdma_mask
= 0x07, /* mwdma0-2 */
553 .udma_mask
= ATA_UDMA6
,
554 .port_ops
= &piix_sata_ops
,
560 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
562 .pio_mask
= 0x1f, /* pio0-4 */
563 .mwdma_mask
= 0x07, /* mwdma0-2 */
564 .udma_mask
= ATA_UDMA6
,
565 .port_ops
= &piix_sata_ops
,
568 [piix_pata_mwdma
] = /* PIIX3 MWDMA only */
571 .flags
= PIIX_PATA_FLAGS
,
572 .pio_mask
= 0x1f, /* pio0-4 */
573 .mwdma_mask
= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
574 .port_ops
= &piix_pata_ops
,
577 [tolapai_sata_ahci
] =
580 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
582 .pio_mask
= 0x1f, /* pio0-4 */
583 .mwdma_mask
= 0x07, /* mwdma0-2 */
584 .udma_mask
= ATA_UDMA6
,
585 .port_ops
= &piix_sata_ops
,
591 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
593 .pio_mask
= 0x1f, /* pio0-4 */
594 .mwdma_mask
= 0x07, /* mwdma0-2 */
595 .udma_mask
= ATA_UDMA6
,
596 .port_ops
= &piix_sata_ops
,
600 static struct pci_bits piix_enable_bits
[] = {
601 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port 0 */
602 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port 1 */
605 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
606 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
607 MODULE_LICENSE("GPL");
608 MODULE_DEVICE_TABLE(pci
, piix_pci_tbl
);
609 MODULE_VERSION(DRV_VERSION
);
618 * List of laptops that use short cables rather than 80 wire
621 static const struct ich_laptop ich_laptop
[] = {
622 /* devid, subvendor, subdev */
623 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
624 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
625 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
626 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
627 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
633 * ich_pata_cable_detect - Probe host controller cable detect info
634 * @ap: Port for which cable detect info is desired
636 * Read 80c cable indicator from ATA PCI device's PCI config
637 * register. This register is normally set by firmware (BIOS).
640 * None (inherited from caller).
643 static int ich_pata_cable_detect(struct ata_port
*ap
)
645 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
646 const struct ich_laptop
*lap
= &ich_laptop
[0];
649 /* Check for specials - Acer Aspire 5602WLMi */
650 while (lap
->device
) {
651 if (lap
->device
== pdev
->device
&&
652 lap
->subvendor
== pdev
->subsystem_vendor
&&
653 lap
->subdevice
== pdev
->subsystem_device
)
654 return ATA_CBL_PATA40_SHORT
;
659 /* check BIOS cable detect results */
660 mask
= ap
->port_no
== 0 ? PIIX_80C_PRI
: PIIX_80C_SEC
;
661 pci_read_config_byte(pdev
, PIIX_IOCFG
, &tmp
);
662 if ((tmp
& mask
) == 0)
663 return ATA_CBL_PATA40
;
664 return ATA_CBL_PATA80
;
668 * piix_pata_prereset - prereset for PATA host controller
670 * @deadline: deadline jiffies for the operation
673 * None (inherited from caller).
675 static int piix_pata_prereset(struct ata_link
*link
, unsigned long deadline
)
677 struct ata_port
*ap
= link
->ap
;
678 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
680 if (!pci_test_config_bits(pdev
, &piix_enable_bits
[ap
->port_no
]))
682 return ata_std_prereset(link
, deadline
);
685 static void piix_pata_error_handler(struct ata_port
*ap
)
687 ata_bmdma_drive_eh(ap
, piix_pata_prereset
, ata_std_softreset
, NULL
,
692 * piix_set_piomode - Initialize host controller PATA PIO timings
693 * @ap: Port whose timings we are configuring
696 * Set PIO mode for device, in host controller PCI config space.
699 * None (inherited from caller).
702 static void piix_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
704 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
705 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
706 unsigned int is_slave
= (adev
->devno
!= 0);
707 unsigned int master_port
= ap
->port_no
? 0x42 : 0x40;
708 unsigned int slave_port
= 0x44;
715 * See Intel Document 298600-004 for the timing programing rules
716 * for ICH controllers.
719 static const /* ISP RTC */
720 u8 timings
[][2] = { { 0, 0 },
727 control
|= 1; /* TIME1 enable */
728 if (ata_pio_need_iordy(adev
))
729 control
|= 2; /* IE enable */
731 /* Intel specifies that the PPE functionality is for disk only */
732 if (adev
->class == ATA_DEV_ATA
)
733 control
|= 4; /* PPE enable */
735 /* PIO configuration clears DTE unconditionally. It will be
736 * programmed in set_dmamode which is guaranteed to be called
737 * after set_piomode if any DMA mode is available.
739 pci_read_config_word(dev
, master_port
, &master_data
);
741 /* clear TIME1|IE1|PPE1|DTE1 */
742 master_data
&= 0xff0f;
743 /* Enable SITRE (seperate slave timing register) */
744 master_data
|= 0x4000;
745 /* enable PPE1, IE1 and TIME1 as needed */
746 master_data
|= (control
<< 4);
747 pci_read_config_byte(dev
, slave_port
, &slave_data
);
748 slave_data
&= (ap
->port_no
? 0x0f : 0xf0);
749 /* Load the timing nibble for this slave */
750 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1])
751 << (ap
->port_no
? 4 : 0);
753 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
754 master_data
&= 0xccf0;
755 /* Enable PPE, IE and TIME as appropriate */
756 master_data
|= control
;
757 /* load ISP and RCT */
759 (timings
[pio
][0] << 12) |
760 (timings
[pio
][1] << 8);
762 pci_write_config_word(dev
, master_port
, master_data
);
764 pci_write_config_byte(dev
, slave_port
, slave_data
);
766 /* Ensure the UDMA bit is off - it will be turned back on if
770 pci_read_config_byte(dev
, 0x48, &udma_enable
);
771 udma_enable
&= ~(1 << (2 * ap
->port_no
+ adev
->devno
));
772 pci_write_config_byte(dev
, 0x48, udma_enable
);
777 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
778 * @ap: Port whose timings we are configuring
779 * @adev: Drive in question
780 * @udma: udma mode, 0 - 6
781 * @isich: set if the chip is an ICH device
783 * Set UDMA mode for device, in host controller PCI config space.
786 * None (inherited from caller).
789 static void do_pata_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
, int isich
)
791 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
792 u8 master_port
= ap
->port_no
? 0x42 : 0x40;
794 u8 speed
= adev
->dma_mode
;
795 int devid
= adev
->devno
+ 2 * ap
->port_no
;
798 static const /* ISP RTC */
799 u8 timings
[][2] = { { 0, 0 },
805 pci_read_config_word(dev
, master_port
, &master_data
);
807 pci_read_config_byte(dev
, 0x48, &udma_enable
);
809 if (speed
>= XFER_UDMA_0
) {
810 unsigned int udma
= adev
->dma_mode
- XFER_UDMA_0
;
813 int u_clock
, u_speed
;
816 * UDMA is handled by a combination of clock switching and
817 * selection of dividers
819 * Handy rule: Odd modes are UDMATIMx 01, even are 02
820 * except UDMA0 which is 00
822 u_speed
= min(2 - (udma
& 1), udma
);
824 u_clock
= 0x1000; /* 100Mhz */
826 u_clock
= 1; /* 66Mhz */
828 u_clock
= 0; /* 33Mhz */
830 udma_enable
|= (1 << devid
);
832 /* Load the CT/RP selection */
833 pci_read_config_word(dev
, 0x4A, &udma_timing
);
834 udma_timing
&= ~(3 << (4 * devid
));
835 udma_timing
|= u_speed
<< (4 * devid
);
836 pci_write_config_word(dev
, 0x4A, udma_timing
);
839 /* Select a 33/66/100Mhz clock */
840 pci_read_config_word(dev
, 0x54, &ideconf
);
841 ideconf
&= ~(0x1001 << devid
);
842 ideconf
|= u_clock
<< devid
;
843 /* For ICH or later we should set bit 10 for better
844 performance (WR_PingPong_En) */
845 pci_write_config_word(dev
, 0x54, ideconf
);
849 * MWDMA is driven by the PIO timings. We must also enable
850 * IORDY unconditionally along with TIME1. PPE has already
851 * been set when the PIO timing was set.
853 unsigned int mwdma
= adev
->dma_mode
- XFER_MW_DMA_0
;
854 unsigned int control
;
856 const unsigned int needed_pio
[3] = {
857 XFER_PIO_0
, XFER_PIO_3
, XFER_PIO_4
859 int pio
= needed_pio
[mwdma
] - XFER_PIO_0
;
861 control
= 3; /* IORDY|TIME1 */
863 /* If the drive MWDMA is faster than it can do PIO then
864 we must force PIO into PIO0 */
866 if (adev
->pio_mode
< needed_pio
[mwdma
])
867 /* Enable DMA timing only */
868 control
|= 8; /* PIO cycles in PIO0 */
870 if (adev
->devno
) { /* Slave */
871 master_data
&= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
872 master_data
|= control
<< 4;
873 pci_read_config_byte(dev
, 0x44, &slave_data
);
874 slave_data
&= (ap
->port_no
? 0x0f : 0xf0);
875 /* Load the matching timing */
876 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << (ap
->port_no
? 4 : 0);
877 pci_write_config_byte(dev
, 0x44, slave_data
);
878 } else { /* Master */
879 master_data
&= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
880 and master timing bits */
881 master_data
|= control
;
883 (timings
[pio
][0] << 12) |
884 (timings
[pio
][1] << 8);
888 udma_enable
&= ~(1 << devid
);
889 pci_write_config_word(dev
, master_port
, master_data
);
892 /* Don't scribble on 0x48 if the controller does not support UDMA */
894 pci_write_config_byte(dev
, 0x48, udma_enable
);
898 * piix_set_dmamode - Initialize host controller PATA DMA timings
899 * @ap: Port whose timings we are configuring
902 * Set MW/UDMA mode for device, in host controller PCI config space.
905 * None (inherited from caller).
908 static void piix_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
910 do_pata_set_dmamode(ap
, adev
, 0);
914 * ich_set_dmamode - Initialize host controller PATA DMA timings
915 * @ap: Port whose timings we are configuring
918 * Set MW/UDMA mode for device, in host controller PCI config space.
921 * None (inherited from caller).
924 static void ich_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
926 do_pata_set_dmamode(ap
, adev
, 1);
930 static int piix_broken_suspend(void)
932 static const struct dmi_system_id sysids
[] = {
936 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
937 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M3"),
943 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
944 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M5"),
950 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
951 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M7"),
955 .ident
= "Satellite U200",
957 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
958 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite U200"),
962 .ident
= "Satellite U205",
964 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
965 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite U205"),
969 .ident
= "Portege M500",
971 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
972 DMI_MATCH(DMI_PRODUCT_NAME
, "PORTEGE M500"),
976 { } /* terminate list */
978 static const char *oemstrs
[] = {
983 if (dmi_check_system(sysids
))
986 for (i
= 0; i
< ARRAY_SIZE(oemstrs
); i
++)
987 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING
, oemstrs
[i
], NULL
))
993 static int piix_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
995 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
999 rc
= ata_host_suspend(host
, mesg
);
1003 /* Some braindamaged ACPI suspend implementations expect the
1004 * controller to be awake on entry; otherwise, it burns cpu
1005 * cycles and power trying to do something to the sleeping
1008 if (piix_broken_suspend() && mesg
.event
== PM_EVENT_SUSPEND
) {
1009 pci_save_state(pdev
);
1011 /* mark its power state as "unknown", since we don't
1012 * know if e.g. the BIOS will change its device state
1015 if (pdev
->current_state
== PCI_D0
)
1016 pdev
->current_state
= PCI_UNKNOWN
;
1018 /* tell resume that it's waking up from broken suspend */
1019 spin_lock_irqsave(&host
->lock
, flags
);
1020 host
->flags
|= PIIX_HOST_BROKEN_SUSPEND
;
1021 spin_unlock_irqrestore(&host
->lock
, flags
);
1023 ata_pci_device_do_suspend(pdev
, mesg
);
1028 static int piix_pci_device_resume(struct pci_dev
*pdev
)
1030 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1031 unsigned long flags
;
1034 if (host
->flags
& PIIX_HOST_BROKEN_SUSPEND
) {
1035 spin_lock_irqsave(&host
->lock
, flags
);
1036 host
->flags
&= ~PIIX_HOST_BROKEN_SUSPEND
;
1037 spin_unlock_irqrestore(&host
->lock
, flags
);
1039 pci_set_power_state(pdev
, PCI_D0
);
1040 pci_restore_state(pdev
);
1042 /* PCI device wasn't disabled during suspend. Use
1043 * pci_reenable_device() to avoid affecting the enable
1046 rc
= pci_reenable_device(pdev
);
1048 dev_printk(KERN_ERR
, &pdev
->dev
, "failed to enable "
1049 "device after resume (%d)\n", rc
);
1051 rc
= ata_pci_device_do_resume(pdev
);
1054 ata_host_resume(host
);
1060 #define AHCI_PCI_BAR 5
1061 #define AHCI_GLOBAL_CTL 0x04
1062 #define AHCI_ENABLE (1 << 31)
1063 static int piix_disable_ahci(struct pci_dev
*pdev
)
1069 /* BUG: pci_enable_device has not yet been called. This
1070 * works because this device is usually set up by BIOS.
1073 if (!pci_resource_start(pdev
, AHCI_PCI_BAR
) ||
1074 !pci_resource_len(pdev
, AHCI_PCI_BAR
))
1077 mmio
= pci_iomap(pdev
, AHCI_PCI_BAR
, 64);
1081 tmp
= readl(mmio
+ AHCI_GLOBAL_CTL
);
1082 if (tmp
& AHCI_ENABLE
) {
1083 tmp
&= ~AHCI_ENABLE
;
1084 writel(tmp
, mmio
+ AHCI_GLOBAL_CTL
);
1086 tmp
= readl(mmio
+ AHCI_GLOBAL_CTL
);
1087 if (tmp
& AHCI_ENABLE
)
1091 pci_iounmap(pdev
, mmio
);
1096 * piix_check_450nx_errata - Check for problem 450NX setup
1097 * @ata_dev: the PCI device to check
1099 * Check for the present of 450NX errata #19 and errata #25. If
1100 * they are found return an error code so we can turn off DMA
1103 static int __devinit
piix_check_450nx_errata(struct pci_dev
*ata_dev
)
1105 struct pci_dev
*pdev
= NULL
;
1107 int no_piix_dma
= 0;
1109 while ((pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, pdev
)) != NULL
) {
1110 /* Look for 450NX PXB. Check for problem configurations
1111 A PCI quirk checks bit 6 already */
1112 pci_read_config_word(pdev
, 0x41, &cfg
);
1113 /* Only on the original revision: IDE DMA can hang */
1114 if (pdev
->revision
== 0x00)
1116 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1117 else if (cfg
& (1<<14) && pdev
->revision
< 5)
1121 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "450NX errata present, disabling IDE DMA.\n");
1122 if (no_piix_dma
== 2)
1123 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "A BIOS update may resolve this.\n");
1127 static void __devinit
piix_init_pcs(struct pci_dev
*pdev
,
1128 struct ata_port_info
*pinfo
,
1129 const struct piix_map_db
*map_db
)
1133 pci_read_config_word(pdev
, ICH5_PCS
, &pcs
);
1135 new_pcs
= pcs
| map_db
->port_enable
;
1137 if (new_pcs
!= pcs
) {
1138 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs
, new_pcs
);
1139 pci_write_config_word(pdev
, ICH5_PCS
, new_pcs
);
1144 static void __devinit
piix_init_sata_map(struct pci_dev
*pdev
,
1145 struct ata_port_info
*pinfo
,
1146 const struct piix_map_db
*map_db
)
1148 struct piix_host_priv
*hpriv
= pinfo
[0].private_data
;
1150 int i
, invalid_map
= 0;
1153 pci_read_config_byte(pdev
, ICH5_PMR
, &map_value
);
1155 map
= map_db
->map
[map_value
& map_db
->mask
];
1157 dev_printk(KERN_INFO
, &pdev
->dev
, "MAP [");
1158 for (i
= 0; i
< 4; i
++) {
1170 WARN_ON((i
& 1) || map
[i
+ 1] != IDE
);
1171 pinfo
[i
/ 2] = piix_port_info
[ich_pata_100
];
1172 pinfo
[i
/ 2].private_data
= hpriv
;
1178 printk(" P%d", map
[i
]);
1180 pinfo
[i
/ 2].flags
|= ATA_FLAG_SLAVE_POSS
;
1187 dev_printk(KERN_ERR
, &pdev
->dev
,
1188 "invalid MAP value %u\n", map_value
);
1193 static void piix_iocfg_bit18_quirk(struct pci_dev
*pdev
)
1195 static const struct dmi_system_id sysids
[] = {
1197 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1198 * isn't used to boot the system which
1199 * disables the channel.
1203 DMI_MATCH(DMI_SYS_VENDOR
, "Clevo Co."),
1204 DMI_MATCH(DMI_PRODUCT_NAME
, "M570U"),
1208 { } /* terminate list */
1212 if (!dmi_check_system(sysids
))
1215 /* The datasheet says that bit 18 is NOOP but certain systems
1216 * seem to use it to disable a channel. Clear the bit on the
1219 pci_read_config_dword(pdev
, PIIX_IOCFG
, &iocfg
);
1220 if (iocfg
& (1 << 18)) {
1221 dev_printk(KERN_INFO
, &pdev
->dev
,
1222 "applying IOCFG bit18 quirk\n");
1223 iocfg
&= ~(1 << 18);
1224 pci_write_config_dword(pdev
, PIIX_IOCFG
, iocfg
);
1229 * piix_init_one - Register PIIX ATA PCI device with kernel services
1230 * @pdev: PCI device to register
1231 * @ent: Entry in piix_pci_tbl matching with @pdev
1233 * Called from kernel PCI layer. We probe for combined mode (sigh),
1234 * and then hand over control to libata, for it to do the rest.
1237 * Inherited from PCI layer (may sleep).
1240 * Zero on success, or -ERRNO value.
1243 static int piix_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1245 static int printed_version
;
1246 struct device
*dev
= &pdev
->dev
;
1247 struct ata_port_info port_info
[2];
1248 const struct ata_port_info
*ppi
[] = { &port_info
[0], &port_info
[1] };
1249 struct piix_host_priv
*hpriv
;
1250 unsigned long port_flags
;
1252 if (!printed_version
++)
1253 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1254 "version " DRV_VERSION
"\n");
1256 /* no hotplugging support (FIXME) */
1257 if (!in_module_init
)
1260 hpriv
= devm_kzalloc(dev
, sizeof(*hpriv
), GFP_KERNEL
);
1264 port_info
[0] = piix_port_info
[ent
->driver_data
];
1265 port_info
[1] = piix_port_info
[ent
->driver_data
];
1266 port_info
[0].private_data
= hpriv
;
1267 port_info
[1].private_data
= hpriv
;
1269 port_flags
= port_info
[0].flags
;
1271 if (port_flags
& PIIX_FLAG_AHCI
) {
1273 pci_read_config_byte(pdev
, PIIX_SCC
, &tmp
);
1274 if (tmp
== PIIX_AHCI_DEVICE
) {
1275 int rc
= piix_disable_ahci(pdev
);
1281 /* Initialize SATA map */
1282 if (port_flags
& ATA_FLAG_SATA
) {
1283 piix_init_sata_map(pdev
, port_info
,
1284 piix_map_db_table
[ent
->driver_data
]);
1285 piix_init_pcs(pdev
, port_info
,
1286 piix_map_db_table
[ent
->driver_data
]);
1289 /* apply IOCFG bit18 quirk */
1290 piix_iocfg_bit18_quirk(pdev
);
1292 /* On ICH5, some BIOSen disable the interrupt using the
1293 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1294 * On ICH6, this bit has the same effect, but only when
1295 * MSI is disabled (and it is disabled, as we don't use
1296 * message-signalled interrupts currently).
1298 if (port_flags
& PIIX_FLAG_CHECKINTR
)
1301 if (piix_check_450nx_errata(pdev
)) {
1302 /* This writes into the master table but it does not
1303 really matter for this errata as we will apply it to
1304 all the PIIX devices on the board */
1305 port_info
[0].mwdma_mask
= 0;
1306 port_info
[0].udma_mask
= 0;
1307 port_info
[1].mwdma_mask
= 0;
1308 port_info
[1].udma_mask
= 0;
1310 return ata_pci_init_one(pdev
, ppi
);
1313 static int __init
piix_init(void)
1317 DPRINTK("pci_register_driver\n");
1318 rc
= pci_register_driver(&piix_pci_driver
);
1328 static void __exit
piix_exit(void)
1330 pci_unregister_driver(&piix_pci_driver
);
1333 module_init(piix_init
);
1334 module_exit(piix_exit
);