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[mirror_ubuntu-artful-kernel.git] / drivers / ata / libahci.c
1 /*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "ahci.h"
47 #include "libata.h"
48
49 static int ahci_skip_host_reset;
50 int ahci_ignore_sss;
51 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
59 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
60 unsigned hints);
61 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
63 size_t size);
64 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
65 ssize_t size);
66
67
68
69 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73 static int ahci_port_start(struct ata_port *ap);
74 static void ahci_port_stop(struct ata_port *ap);
75 static void ahci_qc_prep(struct ata_queued_cmd *qc);
76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77 static void ahci_freeze(struct ata_port *ap);
78 static void ahci_thaw(struct ata_port *ap);
79 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
80 static void ahci_enable_fbs(struct ata_port *ap);
81 static void ahci_disable_fbs(struct ata_port *ap);
82 static void ahci_pmp_attach(struct ata_port *ap);
83 static void ahci_pmp_detach(struct ata_port *ap);
84 static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static void ahci_postreset(struct ata_link *link, unsigned int *class);
91 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
92 static void ahci_dev_config(struct ata_device *dev);
93 #ifdef CONFIG_PM
94 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
95 #endif
96 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
97 static ssize_t ahci_activity_store(struct ata_device *dev,
98 enum sw_activity val);
99 static void ahci_init_sw_activity(struct ata_link *link);
100
101 static ssize_t ahci_show_host_caps(struct device *dev,
102 struct device_attribute *attr, char *buf);
103 static ssize_t ahci_show_host_cap2(struct device *dev,
104 struct device_attribute *attr, char *buf);
105 static ssize_t ahci_show_host_version(struct device *dev,
106 struct device_attribute *attr, char *buf);
107 static ssize_t ahci_show_port_cmd(struct device *dev,
108 struct device_attribute *attr, char *buf);
109 static ssize_t ahci_read_em_buffer(struct device *dev,
110 struct device_attribute *attr, char *buf);
111 static ssize_t ahci_store_em_buffer(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t size);
114 static ssize_t ahci_show_em_supported(struct device *dev,
115 struct device_attribute *attr, char *buf);
116
117 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
118 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
119 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
120 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
121 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
122 ahci_read_em_buffer, ahci_store_em_buffer);
123 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
124
125 struct device_attribute *ahci_shost_attrs[] = {
126 &dev_attr_link_power_management_policy,
127 &dev_attr_em_message_type,
128 &dev_attr_em_message,
129 &dev_attr_ahci_host_caps,
130 &dev_attr_ahci_host_cap2,
131 &dev_attr_ahci_host_version,
132 &dev_attr_ahci_port_cmd,
133 &dev_attr_em_buffer,
134 &dev_attr_em_message_supported,
135 NULL
136 };
137 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
138
139 struct device_attribute *ahci_sdev_attrs[] = {
140 &dev_attr_sw_activity,
141 &dev_attr_unload_heads,
142 NULL
143 };
144 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
145
146 struct ata_port_operations ahci_ops = {
147 .inherits = &sata_pmp_port_ops,
148
149 .qc_defer = ahci_pmp_qc_defer,
150 .qc_prep = ahci_qc_prep,
151 .qc_issue = ahci_qc_issue,
152 .qc_fill_rtf = ahci_qc_fill_rtf,
153
154 .freeze = ahci_freeze,
155 .thaw = ahci_thaw,
156 .softreset = ahci_softreset,
157 .hardreset = ahci_hardreset,
158 .postreset = ahci_postreset,
159 .pmp_softreset = ahci_softreset,
160 .error_handler = ahci_error_handler,
161 .post_internal_cmd = ahci_post_internal_cmd,
162 .dev_config = ahci_dev_config,
163
164 .scr_read = ahci_scr_read,
165 .scr_write = ahci_scr_write,
166 .pmp_attach = ahci_pmp_attach,
167 .pmp_detach = ahci_pmp_detach,
168
169 .set_lpm = ahci_set_lpm,
170 .em_show = ahci_led_show,
171 .em_store = ahci_led_store,
172 .sw_activity_show = ahci_activity_show,
173 .sw_activity_store = ahci_activity_store,
174 .transmit_led_message = ahci_transmit_led_message,
175 #ifdef CONFIG_PM
176 .port_suspend = ahci_port_suspend,
177 .port_resume = ahci_port_resume,
178 #endif
179 .port_start = ahci_port_start,
180 .port_stop = ahci_port_stop,
181 };
182 EXPORT_SYMBOL_GPL(ahci_ops);
183
184 struct ata_port_operations ahci_pmp_retry_srst_ops = {
185 .inherits = &ahci_ops,
186 .softreset = ahci_pmp_retry_softreset,
187 };
188 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
189
190 static bool ahci_em_messages __read_mostly = true;
191 EXPORT_SYMBOL_GPL(ahci_em_messages);
192 module_param(ahci_em_messages, bool, 0444);
193 /* add other LED protocol types when they become supported */
194 MODULE_PARM_DESC(ahci_em_messages,
195 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
196
197 /* device sleep idle timeout in ms */
198 static int devslp_idle_timeout __read_mostly = 1000;
199 module_param(devslp_idle_timeout, int, 0644);
200 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
201
202 static void ahci_enable_ahci(void __iomem *mmio)
203 {
204 int i;
205 u32 tmp;
206
207 /* turn on AHCI_EN */
208 tmp = readl(mmio + HOST_CTL);
209 if (tmp & HOST_AHCI_EN)
210 return;
211
212 /* Some controllers need AHCI_EN to be written multiple times.
213 * Try a few times before giving up.
214 */
215 for (i = 0; i < 5; i++) {
216 tmp |= HOST_AHCI_EN;
217 writel(tmp, mmio + HOST_CTL);
218 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
219 if (tmp & HOST_AHCI_EN)
220 return;
221 msleep(10);
222 }
223
224 WARN_ON(1);
225 }
226
227 static ssize_t ahci_show_host_caps(struct device *dev,
228 struct device_attribute *attr, char *buf)
229 {
230 struct Scsi_Host *shost = class_to_shost(dev);
231 struct ata_port *ap = ata_shost_to_port(shost);
232 struct ahci_host_priv *hpriv = ap->host->private_data;
233
234 return sprintf(buf, "%x\n", hpriv->cap);
235 }
236
237 static ssize_t ahci_show_host_cap2(struct device *dev,
238 struct device_attribute *attr, char *buf)
239 {
240 struct Scsi_Host *shost = class_to_shost(dev);
241 struct ata_port *ap = ata_shost_to_port(shost);
242 struct ahci_host_priv *hpriv = ap->host->private_data;
243
244 return sprintf(buf, "%x\n", hpriv->cap2);
245 }
246
247 static ssize_t ahci_show_host_version(struct device *dev,
248 struct device_attribute *attr, char *buf)
249 {
250 struct Scsi_Host *shost = class_to_shost(dev);
251 struct ata_port *ap = ata_shost_to_port(shost);
252 struct ahci_host_priv *hpriv = ap->host->private_data;
253 void __iomem *mmio = hpriv->mmio;
254
255 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
256 }
257
258 static ssize_t ahci_show_port_cmd(struct device *dev,
259 struct device_attribute *attr, char *buf)
260 {
261 struct Scsi_Host *shost = class_to_shost(dev);
262 struct ata_port *ap = ata_shost_to_port(shost);
263 void __iomem *port_mmio = ahci_port_base(ap);
264
265 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
266 }
267
268 static ssize_t ahci_read_em_buffer(struct device *dev,
269 struct device_attribute *attr, char *buf)
270 {
271 struct Scsi_Host *shost = class_to_shost(dev);
272 struct ata_port *ap = ata_shost_to_port(shost);
273 struct ahci_host_priv *hpriv = ap->host->private_data;
274 void __iomem *mmio = hpriv->mmio;
275 void __iomem *em_mmio = mmio + hpriv->em_loc;
276 u32 em_ctl, msg;
277 unsigned long flags;
278 size_t count;
279 int i;
280
281 spin_lock_irqsave(ap->lock, flags);
282
283 em_ctl = readl(mmio + HOST_EM_CTL);
284 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
285 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
286 spin_unlock_irqrestore(ap->lock, flags);
287 return -EINVAL;
288 }
289
290 if (!(em_ctl & EM_CTL_MR)) {
291 spin_unlock_irqrestore(ap->lock, flags);
292 return -EAGAIN;
293 }
294
295 if (!(em_ctl & EM_CTL_SMB))
296 em_mmio += hpriv->em_buf_sz;
297
298 count = hpriv->em_buf_sz;
299
300 /* the count should not be larger than PAGE_SIZE */
301 if (count > PAGE_SIZE) {
302 if (printk_ratelimit())
303 ata_port_warn(ap,
304 "EM read buffer size too large: "
305 "buffer size %u, page size %lu\n",
306 hpriv->em_buf_sz, PAGE_SIZE);
307 count = PAGE_SIZE;
308 }
309
310 for (i = 0; i < count; i += 4) {
311 msg = readl(em_mmio + i);
312 buf[i] = msg & 0xff;
313 buf[i + 1] = (msg >> 8) & 0xff;
314 buf[i + 2] = (msg >> 16) & 0xff;
315 buf[i + 3] = (msg >> 24) & 0xff;
316 }
317
318 spin_unlock_irqrestore(ap->lock, flags);
319
320 return i;
321 }
322
323 static ssize_t ahci_store_em_buffer(struct device *dev,
324 struct device_attribute *attr,
325 const char *buf, size_t size)
326 {
327 struct Scsi_Host *shost = class_to_shost(dev);
328 struct ata_port *ap = ata_shost_to_port(shost);
329 struct ahci_host_priv *hpriv = ap->host->private_data;
330 void __iomem *mmio = hpriv->mmio;
331 void __iomem *em_mmio = mmio + hpriv->em_loc;
332 const unsigned char *msg_buf = buf;
333 u32 em_ctl, msg;
334 unsigned long flags;
335 int i;
336
337 /* check size validity */
338 if (!(ap->flags & ATA_FLAG_EM) ||
339 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
340 size % 4 || size > hpriv->em_buf_sz)
341 return -EINVAL;
342
343 spin_lock_irqsave(ap->lock, flags);
344
345 em_ctl = readl(mmio + HOST_EM_CTL);
346 if (em_ctl & EM_CTL_TM) {
347 spin_unlock_irqrestore(ap->lock, flags);
348 return -EBUSY;
349 }
350
351 for (i = 0; i < size; i += 4) {
352 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
353 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
354 writel(msg, em_mmio + i);
355 }
356
357 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
358
359 spin_unlock_irqrestore(ap->lock, flags);
360
361 return size;
362 }
363
364 static ssize_t ahci_show_em_supported(struct device *dev,
365 struct device_attribute *attr, char *buf)
366 {
367 struct Scsi_Host *shost = class_to_shost(dev);
368 struct ata_port *ap = ata_shost_to_port(shost);
369 struct ahci_host_priv *hpriv = ap->host->private_data;
370 void __iomem *mmio = hpriv->mmio;
371 u32 em_ctl;
372
373 em_ctl = readl(mmio + HOST_EM_CTL);
374
375 return sprintf(buf, "%s%s%s%s\n",
376 em_ctl & EM_CTL_LED ? "led " : "",
377 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
378 em_ctl & EM_CTL_SES ? "ses-2 " : "",
379 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
380 }
381
382 /**
383 * ahci_save_initial_config - Save and fixup initial config values
384 * @dev: target AHCI device
385 * @hpriv: host private area to store config values
386 * @force_port_map: force port map to a specified value
387 * @mask_port_map: mask out particular bits from port map
388 *
389 * Some registers containing configuration info might be setup by
390 * BIOS and might be cleared on reset. This function saves the
391 * initial values of those registers into @hpriv such that they
392 * can be restored after controller reset.
393 *
394 * If inconsistent, config values are fixed up by this function.
395 *
396 * If it is not set already this function sets hpriv->start_engine to
397 * ahci_start_engine.
398 *
399 * LOCKING:
400 * None.
401 */
402 void ahci_save_initial_config(struct device *dev,
403 struct ahci_host_priv *hpriv,
404 unsigned int force_port_map,
405 unsigned int mask_port_map)
406 {
407 void __iomem *mmio = hpriv->mmio;
408 u32 cap, cap2, vers, port_map;
409 int i;
410
411 /* make sure AHCI mode is enabled before accessing CAP */
412 ahci_enable_ahci(mmio);
413
414 /* Values prefixed with saved_ are written back to host after
415 * reset. Values without are used for driver operation.
416 */
417 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
418 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
419
420 /* CAP2 register is only defined for AHCI 1.2 and later */
421 vers = readl(mmio + HOST_VERSION);
422 if ((vers >> 16) > 1 ||
423 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
424 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
425 else
426 hpriv->saved_cap2 = cap2 = 0;
427
428 /* some chips have errata preventing 64bit use */
429 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
430 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
431 cap &= ~HOST_CAP_64;
432 }
433
434 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
435 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
436 cap &= ~HOST_CAP_NCQ;
437 }
438
439 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
440 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
441 cap |= HOST_CAP_NCQ;
442 }
443
444 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
445 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
446 cap &= ~HOST_CAP_PMP;
447 }
448
449 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
450 dev_info(dev,
451 "controller can't do SNTF, turning off CAP_SNTF\n");
452 cap &= ~HOST_CAP_SNTF;
453 }
454
455 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
456 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
457 cap |= HOST_CAP_FBS;
458 }
459
460 if (force_port_map && port_map != force_port_map) {
461 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
462 port_map, force_port_map);
463 port_map = force_port_map;
464 }
465
466 if (mask_port_map) {
467 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
468 port_map,
469 port_map & mask_port_map);
470 port_map &= mask_port_map;
471 }
472
473 /* cross check port_map and cap.n_ports */
474 if (port_map) {
475 int map_ports = 0;
476
477 for (i = 0; i < AHCI_MAX_PORTS; i++)
478 if (port_map & (1 << i))
479 map_ports++;
480
481 /* If PI has more ports than n_ports, whine, clear
482 * port_map and let it be generated from n_ports.
483 */
484 if (map_ports > ahci_nr_ports(cap)) {
485 dev_warn(dev,
486 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
487 port_map, ahci_nr_ports(cap));
488 port_map = 0;
489 }
490 }
491
492 /* fabricate port_map from cap.nr_ports */
493 if (!port_map) {
494 port_map = (1 << ahci_nr_ports(cap)) - 1;
495 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
496
497 /* write the fixed up value to the PI register */
498 hpriv->saved_port_map = port_map;
499 }
500
501 /* record values to use during operation */
502 hpriv->cap = cap;
503 hpriv->cap2 = cap2;
504 hpriv->port_map = port_map;
505
506 if (!hpriv->start_engine)
507 hpriv->start_engine = ahci_start_engine;
508 }
509 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
510
511 /**
512 * ahci_restore_initial_config - Restore initial config
513 * @host: target ATA host
514 *
515 * Restore initial config stored by ahci_save_initial_config().
516 *
517 * LOCKING:
518 * None.
519 */
520 static void ahci_restore_initial_config(struct ata_host *host)
521 {
522 struct ahci_host_priv *hpriv = host->private_data;
523 void __iomem *mmio = hpriv->mmio;
524
525 writel(hpriv->saved_cap, mmio + HOST_CAP);
526 if (hpriv->saved_cap2)
527 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
528 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
529 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
530 }
531
532 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
533 {
534 static const int offset[] = {
535 [SCR_STATUS] = PORT_SCR_STAT,
536 [SCR_CONTROL] = PORT_SCR_CTL,
537 [SCR_ERROR] = PORT_SCR_ERR,
538 [SCR_ACTIVE] = PORT_SCR_ACT,
539 [SCR_NOTIFICATION] = PORT_SCR_NTF,
540 };
541 struct ahci_host_priv *hpriv = ap->host->private_data;
542
543 if (sc_reg < ARRAY_SIZE(offset) &&
544 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
545 return offset[sc_reg];
546 return 0;
547 }
548
549 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
550 {
551 void __iomem *port_mmio = ahci_port_base(link->ap);
552 int offset = ahci_scr_offset(link->ap, sc_reg);
553
554 if (offset) {
555 *val = readl(port_mmio + offset);
556 return 0;
557 }
558 return -EINVAL;
559 }
560
561 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
562 {
563 void __iomem *port_mmio = ahci_port_base(link->ap);
564 int offset = ahci_scr_offset(link->ap, sc_reg);
565
566 if (offset) {
567 writel(val, port_mmio + offset);
568 return 0;
569 }
570 return -EINVAL;
571 }
572
573 void ahci_start_engine(struct ata_port *ap)
574 {
575 void __iomem *port_mmio = ahci_port_base(ap);
576 u32 tmp;
577
578 /* start DMA */
579 tmp = readl(port_mmio + PORT_CMD);
580 tmp |= PORT_CMD_START;
581 writel(tmp, port_mmio + PORT_CMD);
582 readl(port_mmio + PORT_CMD); /* flush */
583 }
584 EXPORT_SYMBOL_GPL(ahci_start_engine);
585
586 int ahci_stop_engine(struct ata_port *ap)
587 {
588 void __iomem *port_mmio = ahci_port_base(ap);
589 u32 tmp;
590
591 tmp = readl(port_mmio + PORT_CMD);
592
593 /* check if the HBA is idle */
594 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
595 return 0;
596
597 /* setting HBA to idle */
598 tmp &= ~PORT_CMD_START;
599 writel(tmp, port_mmio + PORT_CMD);
600
601 /* wait for engine to stop. This could be as long as 500 msec */
602 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
603 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
604 if (tmp & PORT_CMD_LIST_ON)
605 return -EIO;
606
607 return 0;
608 }
609 EXPORT_SYMBOL_GPL(ahci_stop_engine);
610
611 static void ahci_start_fis_rx(struct ata_port *ap)
612 {
613 void __iomem *port_mmio = ahci_port_base(ap);
614 struct ahci_host_priv *hpriv = ap->host->private_data;
615 struct ahci_port_priv *pp = ap->private_data;
616 u32 tmp;
617
618 /* set FIS registers */
619 if (hpriv->cap & HOST_CAP_64)
620 writel((pp->cmd_slot_dma >> 16) >> 16,
621 port_mmio + PORT_LST_ADDR_HI);
622 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
623
624 if (hpriv->cap & HOST_CAP_64)
625 writel((pp->rx_fis_dma >> 16) >> 16,
626 port_mmio + PORT_FIS_ADDR_HI);
627 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
628
629 /* enable FIS reception */
630 tmp = readl(port_mmio + PORT_CMD);
631 tmp |= PORT_CMD_FIS_RX;
632 writel(tmp, port_mmio + PORT_CMD);
633
634 /* flush */
635 readl(port_mmio + PORT_CMD);
636 }
637
638 static int ahci_stop_fis_rx(struct ata_port *ap)
639 {
640 void __iomem *port_mmio = ahci_port_base(ap);
641 u32 tmp;
642
643 /* disable FIS reception */
644 tmp = readl(port_mmio + PORT_CMD);
645 tmp &= ~PORT_CMD_FIS_RX;
646 writel(tmp, port_mmio + PORT_CMD);
647
648 /* wait for completion, spec says 500ms, give it 1000 */
649 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
650 PORT_CMD_FIS_ON, 10, 1000);
651 if (tmp & PORT_CMD_FIS_ON)
652 return -EBUSY;
653
654 return 0;
655 }
656
657 static void ahci_power_up(struct ata_port *ap)
658 {
659 struct ahci_host_priv *hpriv = ap->host->private_data;
660 void __iomem *port_mmio = ahci_port_base(ap);
661 u32 cmd;
662
663 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
664
665 /* spin up device */
666 if (hpriv->cap & HOST_CAP_SSS) {
667 cmd |= PORT_CMD_SPIN_UP;
668 writel(cmd, port_mmio + PORT_CMD);
669 }
670
671 /* wake up link */
672 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
673 }
674
675 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
676 unsigned int hints)
677 {
678 struct ata_port *ap = link->ap;
679 struct ahci_host_priv *hpriv = ap->host->private_data;
680 struct ahci_port_priv *pp = ap->private_data;
681 void __iomem *port_mmio = ahci_port_base(ap);
682
683 if (policy != ATA_LPM_MAX_POWER) {
684 /*
685 * Disable interrupts on Phy Ready. This keeps us from
686 * getting woken up due to spurious phy ready
687 * interrupts.
688 */
689 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
690 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
691
692 sata_link_scr_lpm(link, policy, false);
693 }
694
695 if (hpriv->cap & HOST_CAP_ALPM) {
696 u32 cmd = readl(port_mmio + PORT_CMD);
697
698 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
699 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
700 cmd |= PORT_CMD_ICC_ACTIVE;
701
702 writel(cmd, port_mmio + PORT_CMD);
703 readl(port_mmio + PORT_CMD);
704
705 /* wait 10ms to be sure we've come out of LPM state */
706 ata_msleep(ap, 10);
707 } else {
708 cmd |= PORT_CMD_ALPE;
709 if (policy == ATA_LPM_MIN_POWER)
710 cmd |= PORT_CMD_ASP;
711
712 /* write out new cmd value */
713 writel(cmd, port_mmio + PORT_CMD);
714 }
715 }
716
717 /* set aggressive device sleep */
718 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
719 (hpriv->cap2 & HOST_CAP2_SADM) &&
720 (link->device->flags & ATA_DFLAG_DEVSLP)) {
721 if (policy == ATA_LPM_MIN_POWER)
722 ahci_set_aggressive_devslp(ap, true);
723 else
724 ahci_set_aggressive_devslp(ap, false);
725 }
726
727 if (policy == ATA_LPM_MAX_POWER) {
728 sata_link_scr_lpm(link, policy, false);
729
730 /* turn PHYRDY IRQ back on */
731 pp->intr_mask |= PORT_IRQ_PHYRDY;
732 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
733 }
734
735 return 0;
736 }
737
738 #ifdef CONFIG_PM
739 static void ahci_power_down(struct ata_port *ap)
740 {
741 struct ahci_host_priv *hpriv = ap->host->private_data;
742 void __iomem *port_mmio = ahci_port_base(ap);
743 u32 cmd, scontrol;
744
745 if (!(hpriv->cap & HOST_CAP_SSS))
746 return;
747
748 /* put device into listen mode, first set PxSCTL.DET to 0 */
749 scontrol = readl(port_mmio + PORT_SCR_CTL);
750 scontrol &= ~0xf;
751 writel(scontrol, port_mmio + PORT_SCR_CTL);
752
753 /* then set PxCMD.SUD to 0 */
754 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
755 cmd &= ~PORT_CMD_SPIN_UP;
756 writel(cmd, port_mmio + PORT_CMD);
757 }
758 #endif
759
760 static void ahci_start_port(struct ata_port *ap)
761 {
762 struct ahci_host_priv *hpriv = ap->host->private_data;
763 struct ahci_port_priv *pp = ap->private_data;
764 struct ata_link *link;
765 struct ahci_em_priv *emp;
766 ssize_t rc;
767 int i;
768
769 /* enable FIS reception */
770 ahci_start_fis_rx(ap);
771
772 /* enable DMA */
773 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
774 hpriv->start_engine(ap);
775
776 /* turn on LEDs */
777 if (ap->flags & ATA_FLAG_EM) {
778 ata_for_each_link(link, ap, EDGE) {
779 emp = &pp->em_priv[link->pmp];
780
781 /* EM Transmit bit maybe busy during init */
782 for (i = 0; i < EM_MAX_RETRY; i++) {
783 rc = ap->ops->transmit_led_message(ap,
784 emp->led_state,
785 4);
786 /*
787 * If busy, give a breather but do not
788 * release EH ownership by using msleep()
789 * instead of ata_msleep(). EM Transmit
790 * bit is busy for the whole host and
791 * releasing ownership will cause other
792 * ports to fail the same way.
793 */
794 if (rc == -EBUSY)
795 msleep(1);
796 else
797 break;
798 }
799 }
800 }
801
802 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
803 ata_for_each_link(link, ap, EDGE)
804 ahci_init_sw_activity(link);
805
806 }
807
808 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
809 {
810 int rc;
811
812 /* disable DMA */
813 rc = ahci_stop_engine(ap);
814 if (rc) {
815 *emsg = "failed to stop engine";
816 return rc;
817 }
818
819 /* disable FIS reception */
820 rc = ahci_stop_fis_rx(ap);
821 if (rc) {
822 *emsg = "failed stop FIS RX";
823 return rc;
824 }
825
826 return 0;
827 }
828
829 int ahci_reset_controller(struct ata_host *host)
830 {
831 struct ahci_host_priv *hpriv = host->private_data;
832 void __iomem *mmio = hpriv->mmio;
833 u32 tmp;
834
835 /* we must be in AHCI mode, before using anything
836 * AHCI-specific, such as HOST_RESET.
837 */
838 ahci_enable_ahci(mmio);
839
840 /* global controller reset */
841 if (!ahci_skip_host_reset) {
842 tmp = readl(mmio + HOST_CTL);
843 if ((tmp & HOST_RESET) == 0) {
844 writel(tmp | HOST_RESET, mmio + HOST_CTL);
845 readl(mmio + HOST_CTL); /* flush */
846 }
847
848 /*
849 * to perform host reset, OS should set HOST_RESET
850 * and poll until this bit is read to be "0".
851 * reset must complete within 1 second, or
852 * the hardware should be considered fried.
853 */
854 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
855 HOST_RESET, 10, 1000);
856
857 if (tmp & HOST_RESET) {
858 dev_err(host->dev, "controller reset failed (0x%x)\n",
859 tmp);
860 return -EIO;
861 }
862
863 /* turn on AHCI mode */
864 ahci_enable_ahci(mmio);
865
866 /* Some registers might be cleared on reset. Restore
867 * initial values.
868 */
869 ahci_restore_initial_config(host);
870 } else
871 dev_info(host->dev, "skipping global host reset\n");
872
873 return 0;
874 }
875 EXPORT_SYMBOL_GPL(ahci_reset_controller);
876
877 static void ahci_sw_activity(struct ata_link *link)
878 {
879 struct ata_port *ap = link->ap;
880 struct ahci_port_priv *pp = ap->private_data;
881 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
882
883 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
884 return;
885
886 emp->activity++;
887 if (!timer_pending(&emp->timer))
888 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
889 }
890
891 static void ahci_sw_activity_blink(unsigned long arg)
892 {
893 struct ata_link *link = (struct ata_link *)arg;
894 struct ata_port *ap = link->ap;
895 struct ahci_port_priv *pp = ap->private_data;
896 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
897 unsigned long led_message = emp->led_state;
898 u32 activity_led_state;
899 unsigned long flags;
900
901 led_message &= EM_MSG_LED_VALUE;
902 led_message |= ap->port_no | (link->pmp << 8);
903
904 /* check to see if we've had activity. If so,
905 * toggle state of LED and reset timer. If not,
906 * turn LED to desired idle state.
907 */
908 spin_lock_irqsave(ap->lock, flags);
909 if (emp->saved_activity != emp->activity) {
910 emp->saved_activity = emp->activity;
911 /* get the current LED state */
912 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
913
914 if (activity_led_state)
915 activity_led_state = 0;
916 else
917 activity_led_state = 1;
918
919 /* clear old state */
920 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
921
922 /* toggle state */
923 led_message |= (activity_led_state << 16);
924 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
925 } else {
926 /* switch to idle */
927 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
928 if (emp->blink_policy == BLINK_OFF)
929 led_message |= (1 << 16);
930 }
931 spin_unlock_irqrestore(ap->lock, flags);
932 ap->ops->transmit_led_message(ap, led_message, 4);
933 }
934
935 static void ahci_init_sw_activity(struct ata_link *link)
936 {
937 struct ata_port *ap = link->ap;
938 struct ahci_port_priv *pp = ap->private_data;
939 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
940
941 /* init activity stats, setup timer */
942 emp->saved_activity = emp->activity = 0;
943 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
944
945 /* check our blink policy and set flag for link if it's enabled */
946 if (emp->blink_policy)
947 link->flags |= ATA_LFLAG_SW_ACTIVITY;
948 }
949
950 int ahci_reset_em(struct ata_host *host)
951 {
952 struct ahci_host_priv *hpriv = host->private_data;
953 void __iomem *mmio = hpriv->mmio;
954 u32 em_ctl;
955
956 em_ctl = readl(mmio + HOST_EM_CTL);
957 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
958 return -EINVAL;
959
960 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
961 return 0;
962 }
963 EXPORT_SYMBOL_GPL(ahci_reset_em);
964
965 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
966 ssize_t size)
967 {
968 struct ahci_host_priv *hpriv = ap->host->private_data;
969 struct ahci_port_priv *pp = ap->private_data;
970 void __iomem *mmio = hpriv->mmio;
971 u32 em_ctl;
972 u32 message[] = {0, 0};
973 unsigned long flags;
974 int pmp;
975 struct ahci_em_priv *emp;
976
977 /* get the slot number from the message */
978 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
979 if (pmp < EM_MAX_SLOTS)
980 emp = &pp->em_priv[pmp];
981 else
982 return -EINVAL;
983
984 spin_lock_irqsave(ap->lock, flags);
985
986 /*
987 * if we are still busy transmitting a previous message,
988 * do not allow
989 */
990 em_ctl = readl(mmio + HOST_EM_CTL);
991 if (em_ctl & EM_CTL_TM) {
992 spin_unlock_irqrestore(ap->lock, flags);
993 return -EBUSY;
994 }
995
996 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
997 /*
998 * create message header - this is all zero except for
999 * the message size, which is 4 bytes.
1000 */
1001 message[0] |= (4 << 8);
1002
1003 /* ignore 0:4 of byte zero, fill in port info yourself */
1004 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1005
1006 /* write message to EM_LOC */
1007 writel(message[0], mmio + hpriv->em_loc);
1008 writel(message[1], mmio + hpriv->em_loc+4);
1009
1010 /*
1011 * tell hardware to transmit the message
1012 */
1013 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1014 }
1015
1016 /* save off new led state for port/slot */
1017 emp->led_state = state;
1018
1019 spin_unlock_irqrestore(ap->lock, flags);
1020 return size;
1021 }
1022
1023 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1024 {
1025 struct ahci_port_priv *pp = ap->private_data;
1026 struct ata_link *link;
1027 struct ahci_em_priv *emp;
1028 int rc = 0;
1029
1030 ata_for_each_link(link, ap, EDGE) {
1031 emp = &pp->em_priv[link->pmp];
1032 rc += sprintf(buf, "%lx\n", emp->led_state);
1033 }
1034 return rc;
1035 }
1036
1037 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1038 size_t size)
1039 {
1040 unsigned int state;
1041 int pmp;
1042 struct ahci_port_priv *pp = ap->private_data;
1043 struct ahci_em_priv *emp;
1044
1045 if (kstrtouint(buf, 0, &state) < 0)
1046 return -EINVAL;
1047
1048 /* get the slot number from the message */
1049 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1050 if (pmp < EM_MAX_SLOTS)
1051 emp = &pp->em_priv[pmp];
1052 else
1053 return -EINVAL;
1054
1055 /* mask off the activity bits if we are in sw_activity
1056 * mode, user should turn off sw_activity before setting
1057 * activity led through em_message
1058 */
1059 if (emp->blink_policy)
1060 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1061
1062 return ap->ops->transmit_led_message(ap, state, size);
1063 }
1064
1065 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1066 {
1067 struct ata_link *link = dev->link;
1068 struct ata_port *ap = link->ap;
1069 struct ahci_port_priv *pp = ap->private_data;
1070 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1071 u32 port_led_state = emp->led_state;
1072
1073 /* save the desired Activity LED behavior */
1074 if (val == OFF) {
1075 /* clear LFLAG */
1076 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1077
1078 /* set the LED to OFF */
1079 port_led_state &= EM_MSG_LED_VALUE_OFF;
1080 port_led_state |= (ap->port_no | (link->pmp << 8));
1081 ap->ops->transmit_led_message(ap, port_led_state, 4);
1082 } else {
1083 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1084 if (val == BLINK_OFF) {
1085 /* set LED to ON for idle */
1086 port_led_state &= EM_MSG_LED_VALUE_OFF;
1087 port_led_state |= (ap->port_no | (link->pmp << 8));
1088 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1089 ap->ops->transmit_led_message(ap, port_led_state, 4);
1090 }
1091 }
1092 emp->blink_policy = val;
1093 return 0;
1094 }
1095
1096 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1097 {
1098 struct ata_link *link = dev->link;
1099 struct ata_port *ap = link->ap;
1100 struct ahci_port_priv *pp = ap->private_data;
1101 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1102
1103 /* display the saved value of activity behavior for this
1104 * disk.
1105 */
1106 return sprintf(buf, "%d\n", emp->blink_policy);
1107 }
1108
1109 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1110 int port_no, void __iomem *mmio,
1111 void __iomem *port_mmio)
1112 {
1113 const char *emsg = NULL;
1114 int rc;
1115 u32 tmp;
1116
1117 /* make sure port is not active */
1118 rc = ahci_deinit_port(ap, &emsg);
1119 if (rc)
1120 dev_warn(dev, "%s (%d)\n", emsg, rc);
1121
1122 /* clear SError */
1123 tmp = readl(port_mmio + PORT_SCR_ERR);
1124 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1125 writel(tmp, port_mmio + PORT_SCR_ERR);
1126
1127 /* clear port IRQ */
1128 tmp = readl(port_mmio + PORT_IRQ_STAT);
1129 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1130 if (tmp)
1131 writel(tmp, port_mmio + PORT_IRQ_STAT);
1132
1133 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1134 }
1135
1136 void ahci_init_controller(struct ata_host *host)
1137 {
1138 struct ahci_host_priv *hpriv = host->private_data;
1139 void __iomem *mmio = hpriv->mmio;
1140 int i;
1141 void __iomem *port_mmio;
1142 u32 tmp;
1143
1144 for (i = 0; i < host->n_ports; i++) {
1145 struct ata_port *ap = host->ports[i];
1146
1147 port_mmio = ahci_port_base(ap);
1148 if (ata_port_is_dummy(ap))
1149 continue;
1150
1151 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1152 }
1153
1154 tmp = readl(mmio + HOST_CTL);
1155 VPRINTK("HOST_CTL 0x%x\n", tmp);
1156 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1157 tmp = readl(mmio + HOST_CTL);
1158 VPRINTK("HOST_CTL 0x%x\n", tmp);
1159 }
1160 EXPORT_SYMBOL_GPL(ahci_init_controller);
1161
1162 static void ahci_dev_config(struct ata_device *dev)
1163 {
1164 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1165
1166 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1167 dev->max_sectors = 255;
1168 ata_dev_info(dev,
1169 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1170 }
1171 }
1172
1173 unsigned int ahci_dev_classify(struct ata_port *ap)
1174 {
1175 void __iomem *port_mmio = ahci_port_base(ap);
1176 struct ata_taskfile tf;
1177 u32 tmp;
1178
1179 tmp = readl(port_mmio + PORT_SIG);
1180 tf.lbah = (tmp >> 24) & 0xff;
1181 tf.lbam = (tmp >> 16) & 0xff;
1182 tf.lbal = (tmp >> 8) & 0xff;
1183 tf.nsect = (tmp) & 0xff;
1184
1185 return ata_dev_classify(&tf);
1186 }
1187 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1188
1189 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1190 u32 opts)
1191 {
1192 dma_addr_t cmd_tbl_dma;
1193
1194 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1195
1196 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1197 pp->cmd_slot[tag].status = 0;
1198 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1199 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1200 }
1201 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1202
1203 int ahci_kick_engine(struct ata_port *ap)
1204 {
1205 void __iomem *port_mmio = ahci_port_base(ap);
1206 struct ahci_host_priv *hpriv = ap->host->private_data;
1207 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1208 u32 tmp;
1209 int busy, rc;
1210
1211 /* stop engine */
1212 rc = ahci_stop_engine(ap);
1213 if (rc)
1214 goto out_restart;
1215
1216 /* need to do CLO?
1217 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1218 */
1219 busy = status & (ATA_BUSY | ATA_DRQ);
1220 if (!busy && !sata_pmp_attached(ap)) {
1221 rc = 0;
1222 goto out_restart;
1223 }
1224
1225 if (!(hpriv->cap & HOST_CAP_CLO)) {
1226 rc = -EOPNOTSUPP;
1227 goto out_restart;
1228 }
1229
1230 /* perform CLO */
1231 tmp = readl(port_mmio + PORT_CMD);
1232 tmp |= PORT_CMD_CLO;
1233 writel(tmp, port_mmio + PORT_CMD);
1234
1235 rc = 0;
1236 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1237 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1238 if (tmp & PORT_CMD_CLO)
1239 rc = -EIO;
1240
1241 /* restart engine */
1242 out_restart:
1243 hpriv->start_engine(ap);
1244 return rc;
1245 }
1246 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1247
1248 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1249 struct ata_taskfile *tf, int is_cmd, u16 flags,
1250 unsigned long timeout_msec)
1251 {
1252 const u32 cmd_fis_len = 5; /* five dwords */
1253 struct ahci_port_priv *pp = ap->private_data;
1254 void __iomem *port_mmio = ahci_port_base(ap);
1255 u8 *fis = pp->cmd_tbl;
1256 u32 tmp;
1257
1258 /* prep the command */
1259 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1260 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1261
1262 /* issue & wait */
1263 writel(1, port_mmio + PORT_CMD_ISSUE);
1264
1265 if (timeout_msec) {
1266 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1267 0x1, 0x1, 1, timeout_msec);
1268 if (tmp & 0x1) {
1269 ahci_kick_engine(ap);
1270 return -EBUSY;
1271 }
1272 } else
1273 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1274
1275 return 0;
1276 }
1277
1278 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1279 int pmp, unsigned long deadline,
1280 int (*check_ready)(struct ata_link *link))
1281 {
1282 struct ata_port *ap = link->ap;
1283 struct ahci_host_priv *hpriv = ap->host->private_data;
1284 struct ahci_port_priv *pp = ap->private_data;
1285 const char *reason = NULL;
1286 unsigned long now, msecs;
1287 struct ata_taskfile tf;
1288 bool fbs_disabled = false;
1289 int rc;
1290
1291 DPRINTK("ENTER\n");
1292
1293 /* prepare for SRST (AHCI-1.1 10.4.1) */
1294 rc = ahci_kick_engine(ap);
1295 if (rc && rc != -EOPNOTSUPP)
1296 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1297
1298 /*
1299 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1300 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1301 * that is attached to port multiplier.
1302 */
1303 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1304 ahci_disable_fbs(ap);
1305 fbs_disabled = true;
1306 }
1307
1308 ata_tf_init(link->device, &tf);
1309
1310 /* issue the first D2H Register FIS */
1311 msecs = 0;
1312 now = jiffies;
1313 if (time_after(deadline, now))
1314 msecs = jiffies_to_msecs(deadline - now);
1315
1316 tf.ctl |= ATA_SRST;
1317 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1318 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1319 rc = -EIO;
1320 reason = "1st FIS failed";
1321 goto fail;
1322 }
1323
1324 /* spec says at least 5us, but be generous and sleep for 1ms */
1325 ata_msleep(ap, 1);
1326
1327 /* issue the second D2H Register FIS */
1328 tf.ctl &= ~ATA_SRST;
1329 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1330
1331 /* wait for link to become ready */
1332 rc = ata_wait_after_reset(link, deadline, check_ready);
1333 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1334 /*
1335 * Workaround for cases where link online status can't
1336 * be trusted. Treat device readiness timeout as link
1337 * offline.
1338 */
1339 ata_link_info(link, "device not ready, treating as offline\n");
1340 *class = ATA_DEV_NONE;
1341 } else if (rc) {
1342 /* link occupied, -ENODEV too is an error */
1343 reason = "device not ready";
1344 goto fail;
1345 } else
1346 *class = ahci_dev_classify(ap);
1347
1348 /* re-enable FBS if disabled before */
1349 if (fbs_disabled)
1350 ahci_enable_fbs(ap);
1351
1352 DPRINTK("EXIT, class=%u\n", *class);
1353 return 0;
1354
1355 fail:
1356 ata_link_err(link, "softreset failed (%s)\n", reason);
1357 return rc;
1358 }
1359
1360 int ahci_check_ready(struct ata_link *link)
1361 {
1362 void __iomem *port_mmio = ahci_port_base(link->ap);
1363 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1364
1365 return ata_check_ready(status);
1366 }
1367 EXPORT_SYMBOL_GPL(ahci_check_ready);
1368
1369 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1370 unsigned long deadline)
1371 {
1372 int pmp = sata_srst_pmp(link);
1373
1374 DPRINTK("ENTER\n");
1375
1376 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1377 }
1378 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1379
1380 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1381 {
1382 void __iomem *port_mmio = ahci_port_base(link->ap);
1383 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1384 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1385
1386 /*
1387 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1388 * which can save timeout delay.
1389 */
1390 if (irq_status & PORT_IRQ_BAD_PMP)
1391 return -EIO;
1392
1393 return ata_check_ready(status);
1394 }
1395
1396 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1397 unsigned long deadline)
1398 {
1399 struct ata_port *ap = link->ap;
1400 void __iomem *port_mmio = ahci_port_base(ap);
1401 int pmp = sata_srst_pmp(link);
1402 int rc;
1403 u32 irq_sts;
1404
1405 DPRINTK("ENTER\n");
1406
1407 rc = ahci_do_softreset(link, class, pmp, deadline,
1408 ahci_bad_pmp_check_ready);
1409
1410 /*
1411 * Soft reset fails with IPMS set when PMP is enabled but
1412 * SATA HDD/ODD is connected to SATA port, do soft reset
1413 * again to port 0.
1414 */
1415 if (rc == -EIO) {
1416 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1417 if (irq_sts & PORT_IRQ_BAD_PMP) {
1418 ata_link_warn(link,
1419 "applying PMP SRST workaround "
1420 "and retrying\n");
1421 rc = ahci_do_softreset(link, class, 0, deadline,
1422 ahci_check_ready);
1423 }
1424 }
1425
1426 return rc;
1427 }
1428
1429 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1430 unsigned long deadline)
1431 {
1432 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1433 struct ata_port *ap = link->ap;
1434 struct ahci_port_priv *pp = ap->private_data;
1435 struct ahci_host_priv *hpriv = ap->host->private_data;
1436 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1437 struct ata_taskfile tf;
1438 bool online;
1439 int rc;
1440
1441 DPRINTK("ENTER\n");
1442
1443 ahci_stop_engine(ap);
1444
1445 /* clear D2H reception area to properly wait for D2H FIS */
1446 ata_tf_init(link->device, &tf);
1447 tf.command = ATA_BUSY;
1448 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1449
1450 rc = sata_link_hardreset(link, timing, deadline, &online,
1451 ahci_check_ready);
1452
1453 hpriv->start_engine(ap);
1454
1455 if (online)
1456 *class = ahci_dev_classify(ap);
1457
1458 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1459 return rc;
1460 }
1461
1462 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1463 {
1464 struct ata_port *ap = link->ap;
1465 void __iomem *port_mmio = ahci_port_base(ap);
1466 u32 new_tmp, tmp;
1467
1468 ata_std_postreset(link, class);
1469
1470 /* Make sure port's ATAPI bit is set appropriately */
1471 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1472 if (*class == ATA_DEV_ATAPI)
1473 new_tmp |= PORT_CMD_ATAPI;
1474 else
1475 new_tmp &= ~PORT_CMD_ATAPI;
1476 if (new_tmp != tmp) {
1477 writel(new_tmp, port_mmio + PORT_CMD);
1478 readl(port_mmio + PORT_CMD); /* flush */
1479 }
1480 }
1481
1482 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1483 {
1484 struct scatterlist *sg;
1485 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1486 unsigned int si;
1487
1488 VPRINTK("ENTER\n");
1489
1490 /*
1491 * Next, the S/G list.
1492 */
1493 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1494 dma_addr_t addr = sg_dma_address(sg);
1495 u32 sg_len = sg_dma_len(sg);
1496
1497 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1498 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1499 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1500 }
1501
1502 return si;
1503 }
1504
1505 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1506 {
1507 struct ata_port *ap = qc->ap;
1508 struct ahci_port_priv *pp = ap->private_data;
1509
1510 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1511 return ata_std_qc_defer(qc);
1512 else
1513 return sata_pmp_qc_defer_cmd_switch(qc);
1514 }
1515
1516 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1517 {
1518 struct ata_port *ap = qc->ap;
1519 struct ahci_port_priv *pp = ap->private_data;
1520 int is_atapi = ata_is_atapi(qc->tf.protocol);
1521 void *cmd_tbl;
1522 u32 opts;
1523 const u32 cmd_fis_len = 5; /* five dwords */
1524 unsigned int n_elem;
1525
1526 /*
1527 * Fill in command table information. First, the header,
1528 * a SATA Register - Host to Device command FIS.
1529 */
1530 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1531
1532 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1533 if (is_atapi) {
1534 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1535 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1536 }
1537
1538 n_elem = 0;
1539 if (qc->flags & ATA_QCFLAG_DMAMAP)
1540 n_elem = ahci_fill_sg(qc, cmd_tbl);
1541
1542 /*
1543 * Fill in command slot information.
1544 */
1545 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1546 if (qc->tf.flags & ATA_TFLAG_WRITE)
1547 opts |= AHCI_CMD_WRITE;
1548 if (is_atapi)
1549 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1550
1551 ahci_fill_cmd_slot(pp, qc->tag, opts);
1552 }
1553
1554 static void ahci_fbs_dec_intr(struct ata_port *ap)
1555 {
1556 struct ahci_port_priv *pp = ap->private_data;
1557 void __iomem *port_mmio = ahci_port_base(ap);
1558 u32 fbs = readl(port_mmio + PORT_FBS);
1559 int retries = 3;
1560
1561 DPRINTK("ENTER\n");
1562 BUG_ON(!pp->fbs_enabled);
1563
1564 /* time to wait for DEC is not specified by AHCI spec,
1565 * add a retry loop for safety.
1566 */
1567 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1568 fbs = readl(port_mmio + PORT_FBS);
1569 while ((fbs & PORT_FBS_DEC) && retries--) {
1570 udelay(1);
1571 fbs = readl(port_mmio + PORT_FBS);
1572 }
1573
1574 if (fbs & PORT_FBS_DEC)
1575 dev_err(ap->host->dev, "failed to clear device error\n");
1576 }
1577
1578 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1579 {
1580 struct ahci_host_priv *hpriv = ap->host->private_data;
1581 struct ahci_port_priv *pp = ap->private_data;
1582 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1583 struct ata_link *link = NULL;
1584 struct ata_queued_cmd *active_qc;
1585 struct ata_eh_info *active_ehi;
1586 bool fbs_need_dec = false;
1587 u32 serror;
1588
1589 /* determine active link with error */
1590 if (pp->fbs_enabled) {
1591 void __iomem *port_mmio = ahci_port_base(ap);
1592 u32 fbs = readl(port_mmio + PORT_FBS);
1593 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1594
1595 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1596 link = &ap->pmp_link[pmp];
1597 fbs_need_dec = true;
1598 }
1599
1600 } else
1601 ata_for_each_link(link, ap, EDGE)
1602 if (ata_link_active(link))
1603 break;
1604
1605 if (!link)
1606 link = &ap->link;
1607
1608 active_qc = ata_qc_from_tag(ap, link->active_tag);
1609 active_ehi = &link->eh_info;
1610
1611 /* record irq stat */
1612 ata_ehi_clear_desc(host_ehi);
1613 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1614
1615 /* AHCI needs SError cleared; otherwise, it might lock up */
1616 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1617 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1618 host_ehi->serror |= serror;
1619
1620 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1621 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1622 irq_stat &= ~PORT_IRQ_IF_ERR;
1623
1624 if (irq_stat & PORT_IRQ_TF_ERR) {
1625 /* If qc is active, charge it; otherwise, the active
1626 * link. There's no active qc on NCQ errors. It will
1627 * be determined by EH by reading log page 10h.
1628 */
1629 if (active_qc)
1630 active_qc->err_mask |= AC_ERR_DEV;
1631 else
1632 active_ehi->err_mask |= AC_ERR_DEV;
1633
1634 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1635 host_ehi->serror &= ~SERR_INTERNAL;
1636 }
1637
1638 if (irq_stat & PORT_IRQ_UNK_FIS) {
1639 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1640
1641 active_ehi->err_mask |= AC_ERR_HSM;
1642 active_ehi->action |= ATA_EH_RESET;
1643 ata_ehi_push_desc(active_ehi,
1644 "unknown FIS %08x %08x %08x %08x" ,
1645 unk[0], unk[1], unk[2], unk[3]);
1646 }
1647
1648 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1649 active_ehi->err_mask |= AC_ERR_HSM;
1650 active_ehi->action |= ATA_EH_RESET;
1651 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1652 }
1653
1654 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1655 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1656 host_ehi->action |= ATA_EH_RESET;
1657 ata_ehi_push_desc(host_ehi, "host bus error");
1658 }
1659
1660 if (irq_stat & PORT_IRQ_IF_ERR) {
1661 if (fbs_need_dec)
1662 active_ehi->err_mask |= AC_ERR_DEV;
1663 else {
1664 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1665 host_ehi->action |= ATA_EH_RESET;
1666 }
1667
1668 ata_ehi_push_desc(host_ehi, "interface fatal error");
1669 }
1670
1671 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1672 ata_ehi_hotplugged(host_ehi);
1673 ata_ehi_push_desc(host_ehi, "%s",
1674 irq_stat & PORT_IRQ_CONNECT ?
1675 "connection status changed" : "PHY RDY changed");
1676 }
1677
1678 /* okay, let's hand over to EH */
1679
1680 if (irq_stat & PORT_IRQ_FREEZE)
1681 ata_port_freeze(ap);
1682 else if (fbs_need_dec) {
1683 ata_link_abort(link);
1684 ahci_fbs_dec_intr(ap);
1685 } else
1686 ata_port_abort(ap);
1687 }
1688
1689 static void ahci_handle_port_interrupt(struct ata_port *ap,
1690 void __iomem *port_mmio, u32 status)
1691 {
1692 struct ata_eh_info *ehi = &ap->link.eh_info;
1693 struct ahci_port_priv *pp = ap->private_data;
1694 struct ahci_host_priv *hpriv = ap->host->private_data;
1695 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1696 u32 qc_active = 0;
1697 int rc;
1698
1699 /* ignore BAD_PMP while resetting */
1700 if (unlikely(resetting))
1701 status &= ~PORT_IRQ_BAD_PMP;
1702
1703 /* if LPM is enabled, PHYRDY doesn't mean anything */
1704 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) {
1705 status &= ~PORT_IRQ_PHYRDY;
1706 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1707 }
1708
1709 if (unlikely(status & PORT_IRQ_ERROR)) {
1710 ahci_error_intr(ap, status);
1711 return;
1712 }
1713
1714 if (status & PORT_IRQ_SDB_FIS) {
1715 /* If SNotification is available, leave notification
1716 * handling to sata_async_notification(). If not,
1717 * emulate it by snooping SDB FIS RX area.
1718 *
1719 * Snooping FIS RX area is probably cheaper than
1720 * poking SNotification but some constrollers which
1721 * implement SNotification, ICH9 for example, don't
1722 * store AN SDB FIS into receive area.
1723 */
1724 if (hpriv->cap & HOST_CAP_SNTF)
1725 sata_async_notification(ap);
1726 else {
1727 /* If the 'N' bit in word 0 of the FIS is set,
1728 * we just received asynchronous notification.
1729 * Tell libata about it.
1730 *
1731 * Lack of SNotification should not appear in
1732 * ahci 1.2, so the workaround is unnecessary
1733 * when FBS is enabled.
1734 */
1735 if (pp->fbs_enabled)
1736 WARN_ON_ONCE(1);
1737 else {
1738 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1739 u32 f0 = le32_to_cpu(f[0]);
1740 if (f0 & (1 << 15))
1741 sata_async_notification(ap);
1742 }
1743 }
1744 }
1745
1746 /* pp->active_link is not reliable once FBS is enabled, both
1747 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1748 * NCQ and non-NCQ commands may be in flight at the same time.
1749 */
1750 if (pp->fbs_enabled) {
1751 if (ap->qc_active) {
1752 qc_active = readl(port_mmio + PORT_SCR_ACT);
1753 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1754 }
1755 } else {
1756 /* pp->active_link is valid iff any command is in flight */
1757 if (ap->qc_active && pp->active_link->sactive)
1758 qc_active = readl(port_mmio + PORT_SCR_ACT);
1759 else
1760 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1761 }
1762
1763
1764 rc = ata_qc_complete_multiple(ap, qc_active);
1765
1766 /* while resetting, invalid completions are expected */
1767 if (unlikely(rc < 0 && !resetting)) {
1768 ehi->err_mask |= AC_ERR_HSM;
1769 ehi->action |= ATA_EH_RESET;
1770 ata_port_freeze(ap);
1771 }
1772 }
1773
1774 static void ahci_port_intr(struct ata_port *ap)
1775 {
1776 void __iomem *port_mmio = ahci_port_base(ap);
1777 u32 status;
1778
1779 status = readl(port_mmio + PORT_IRQ_STAT);
1780 writel(status, port_mmio + PORT_IRQ_STAT);
1781
1782 ahci_handle_port_interrupt(ap, port_mmio, status);
1783 }
1784
1785 irqreturn_t ahci_thread_fn(int irq, void *dev_instance)
1786 {
1787 struct ata_port *ap = dev_instance;
1788 struct ahci_port_priv *pp = ap->private_data;
1789 void __iomem *port_mmio = ahci_port_base(ap);
1790 unsigned long flags;
1791 u32 status;
1792
1793 spin_lock_irqsave(&ap->host->lock, flags);
1794 status = pp->intr_status;
1795 if (status)
1796 pp->intr_status = 0;
1797 spin_unlock_irqrestore(&ap->host->lock, flags);
1798
1799 spin_lock_bh(ap->lock);
1800 ahci_handle_port_interrupt(ap, port_mmio, status);
1801 spin_unlock_bh(ap->lock);
1802
1803 return IRQ_HANDLED;
1804 }
1805 EXPORT_SYMBOL_GPL(ahci_thread_fn);
1806
1807 static void ahci_hw_port_interrupt(struct ata_port *ap)
1808 {
1809 void __iomem *port_mmio = ahci_port_base(ap);
1810 struct ahci_port_priv *pp = ap->private_data;
1811 u32 status;
1812
1813 status = readl(port_mmio + PORT_IRQ_STAT);
1814 writel(status, port_mmio + PORT_IRQ_STAT);
1815
1816 pp->intr_status |= status;
1817 }
1818
1819 irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance)
1820 {
1821 struct ata_port *ap_this = dev_instance;
1822 struct ahci_port_priv *pp = ap_this->private_data;
1823 struct ata_host *host = ap_this->host;
1824 struct ahci_host_priv *hpriv = host->private_data;
1825 void __iomem *mmio = hpriv->mmio;
1826 unsigned int i;
1827 u32 irq_stat, irq_masked;
1828
1829 VPRINTK("ENTER\n");
1830
1831 spin_lock(&host->lock);
1832
1833 irq_stat = readl(mmio + HOST_IRQ_STAT);
1834
1835 if (!irq_stat) {
1836 u32 status = pp->intr_status;
1837
1838 spin_unlock(&host->lock);
1839
1840 VPRINTK("EXIT\n");
1841
1842 return status ? IRQ_WAKE_THREAD : IRQ_NONE;
1843 }
1844
1845 irq_masked = irq_stat & hpriv->port_map;
1846
1847 for (i = 0; i < host->n_ports; i++) {
1848 struct ata_port *ap;
1849
1850 if (!(irq_masked & (1 << i)))
1851 continue;
1852
1853 ap = host->ports[i];
1854 if (ap) {
1855 ahci_hw_port_interrupt(ap);
1856 VPRINTK("port %u\n", i);
1857 } else {
1858 VPRINTK("port %u (no irq)\n", i);
1859 if (ata_ratelimit())
1860 dev_warn(host->dev,
1861 "interrupt on disabled port %u\n", i);
1862 }
1863 }
1864
1865 writel(irq_stat, mmio + HOST_IRQ_STAT);
1866
1867 spin_unlock(&host->lock);
1868
1869 VPRINTK("EXIT\n");
1870
1871 return IRQ_WAKE_THREAD;
1872 }
1873 EXPORT_SYMBOL_GPL(ahci_hw_interrupt);
1874
1875 irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1876 {
1877 struct ata_host *host = dev_instance;
1878 struct ahci_host_priv *hpriv;
1879 unsigned int i, handled = 0;
1880 void __iomem *mmio;
1881 u32 irq_stat, irq_masked;
1882
1883 VPRINTK("ENTER\n");
1884
1885 hpriv = host->private_data;
1886 mmio = hpriv->mmio;
1887
1888 /* sigh. 0xffffffff is a valid return from h/w */
1889 irq_stat = readl(mmio + HOST_IRQ_STAT);
1890 if (!irq_stat)
1891 return IRQ_NONE;
1892
1893 irq_masked = irq_stat & hpriv->port_map;
1894
1895 spin_lock(&host->lock);
1896
1897 for (i = 0; i < host->n_ports; i++) {
1898 struct ata_port *ap;
1899
1900 if (!(irq_masked & (1 << i)))
1901 continue;
1902
1903 ap = host->ports[i];
1904 if (ap) {
1905 ahci_port_intr(ap);
1906 VPRINTK("port %u\n", i);
1907 } else {
1908 VPRINTK("port %u (no irq)\n", i);
1909 if (ata_ratelimit())
1910 dev_warn(host->dev,
1911 "interrupt on disabled port %u\n", i);
1912 }
1913
1914 handled = 1;
1915 }
1916
1917 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1918 * it should be cleared after all the port events are cleared;
1919 * otherwise, it will raise a spurious interrupt after each
1920 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1921 * information.
1922 *
1923 * Also, use the unmasked value to clear interrupt as spurious
1924 * pending event on a dummy port might cause screaming IRQ.
1925 */
1926 writel(irq_stat, mmio + HOST_IRQ_STAT);
1927
1928 spin_unlock(&host->lock);
1929
1930 VPRINTK("EXIT\n");
1931
1932 return IRQ_RETVAL(handled);
1933 }
1934 EXPORT_SYMBOL_GPL(ahci_interrupt);
1935
1936 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1937 {
1938 struct ata_port *ap = qc->ap;
1939 void __iomem *port_mmio = ahci_port_base(ap);
1940 struct ahci_port_priv *pp = ap->private_data;
1941
1942 /* Keep track of the currently active link. It will be used
1943 * in completion path to determine whether NCQ phase is in
1944 * progress.
1945 */
1946 pp->active_link = qc->dev->link;
1947
1948 if (qc->tf.protocol == ATA_PROT_NCQ)
1949 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1950
1951 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1952 u32 fbs = readl(port_mmio + PORT_FBS);
1953 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1954 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1955 writel(fbs, port_mmio + PORT_FBS);
1956 pp->fbs_last_dev = qc->dev->link->pmp;
1957 }
1958
1959 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1960
1961 ahci_sw_activity(qc->dev->link);
1962
1963 return 0;
1964 }
1965
1966 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1967 {
1968 struct ahci_port_priv *pp = qc->ap->private_data;
1969 u8 *rx_fis = pp->rx_fis;
1970
1971 if (pp->fbs_enabled)
1972 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1973
1974 /*
1975 * After a successful execution of an ATA PIO data-in command,
1976 * the device doesn't send D2H Reg FIS to update the TF and
1977 * the host should take TF and E_Status from the preceding PIO
1978 * Setup FIS.
1979 */
1980 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1981 !(qc->flags & ATA_QCFLAG_FAILED)) {
1982 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1983 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1984 } else
1985 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
1986
1987 return true;
1988 }
1989
1990 static void ahci_freeze(struct ata_port *ap)
1991 {
1992 void __iomem *port_mmio = ahci_port_base(ap);
1993
1994 /* turn IRQ off */
1995 writel(0, port_mmio + PORT_IRQ_MASK);
1996 }
1997
1998 static void ahci_thaw(struct ata_port *ap)
1999 {
2000 struct ahci_host_priv *hpriv = ap->host->private_data;
2001 void __iomem *mmio = hpriv->mmio;
2002 void __iomem *port_mmio = ahci_port_base(ap);
2003 u32 tmp;
2004 struct ahci_port_priv *pp = ap->private_data;
2005
2006 /* clear IRQ */
2007 tmp = readl(port_mmio + PORT_IRQ_STAT);
2008 writel(tmp, port_mmio + PORT_IRQ_STAT);
2009 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2010
2011 /* turn IRQ back on */
2012 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2013 }
2014
2015 void ahci_error_handler(struct ata_port *ap)
2016 {
2017 struct ahci_host_priv *hpriv = ap->host->private_data;
2018
2019 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2020 /* restart engine */
2021 ahci_stop_engine(ap);
2022 hpriv->start_engine(ap);
2023 }
2024
2025 sata_pmp_error_handler(ap);
2026
2027 if (!ata_dev_enabled(ap->link.device))
2028 ahci_stop_engine(ap);
2029 }
2030 EXPORT_SYMBOL_GPL(ahci_error_handler);
2031
2032 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2033 {
2034 struct ata_port *ap = qc->ap;
2035
2036 /* make DMA engine forget about the failed command */
2037 if (qc->flags & ATA_QCFLAG_FAILED)
2038 ahci_kick_engine(ap);
2039 }
2040
2041 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2042 {
2043 struct ahci_host_priv *hpriv = ap->host->private_data;
2044 void __iomem *port_mmio = ahci_port_base(ap);
2045 struct ata_device *dev = ap->link.device;
2046 u32 devslp, dm, dito, mdat, deto;
2047 int rc;
2048 unsigned int err_mask;
2049
2050 devslp = readl(port_mmio + PORT_DEVSLP);
2051 if (!(devslp & PORT_DEVSLP_DSP)) {
2052 dev_err(ap->host->dev, "port does not support device sleep\n");
2053 return;
2054 }
2055
2056 /* disable device sleep */
2057 if (!sleep) {
2058 if (devslp & PORT_DEVSLP_ADSE) {
2059 writel(devslp & ~PORT_DEVSLP_ADSE,
2060 port_mmio + PORT_DEVSLP);
2061 err_mask = ata_dev_set_feature(dev,
2062 SETFEATURES_SATA_DISABLE,
2063 SATA_DEVSLP);
2064 if (err_mask && err_mask != AC_ERR_DEV)
2065 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2066 }
2067 return;
2068 }
2069
2070 /* device sleep was already enabled */
2071 if (devslp & PORT_DEVSLP_ADSE)
2072 return;
2073
2074 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2075 rc = ahci_stop_engine(ap);
2076 if (rc)
2077 return;
2078
2079 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2080 dito = devslp_idle_timeout / (dm + 1);
2081 if (dito > 0x3ff)
2082 dito = 0x3ff;
2083
2084 /* Use the nominal value 10 ms if the read MDAT is zero,
2085 * the nominal value of DETO is 20 ms.
2086 */
2087 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2088 ATA_LOG_DEVSLP_VALID_MASK) {
2089 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2090 ATA_LOG_DEVSLP_MDAT_MASK;
2091 if (!mdat)
2092 mdat = 10;
2093 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2094 if (!deto)
2095 deto = 20;
2096 } else {
2097 mdat = 10;
2098 deto = 20;
2099 }
2100
2101 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2102 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2103 (deto << PORT_DEVSLP_DETO_OFFSET) |
2104 PORT_DEVSLP_ADSE);
2105 writel(devslp, port_mmio + PORT_DEVSLP);
2106
2107 hpriv->start_engine(ap);
2108
2109 /* enable device sleep feature for the drive */
2110 err_mask = ata_dev_set_feature(dev,
2111 SETFEATURES_SATA_ENABLE,
2112 SATA_DEVSLP);
2113 if (err_mask && err_mask != AC_ERR_DEV)
2114 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2115 }
2116
2117 static void ahci_enable_fbs(struct ata_port *ap)
2118 {
2119 struct ahci_host_priv *hpriv = ap->host->private_data;
2120 struct ahci_port_priv *pp = ap->private_data;
2121 void __iomem *port_mmio = ahci_port_base(ap);
2122 u32 fbs;
2123 int rc;
2124
2125 if (!pp->fbs_supported)
2126 return;
2127
2128 fbs = readl(port_mmio + PORT_FBS);
2129 if (fbs & PORT_FBS_EN) {
2130 pp->fbs_enabled = true;
2131 pp->fbs_last_dev = -1; /* initialization */
2132 return;
2133 }
2134
2135 rc = ahci_stop_engine(ap);
2136 if (rc)
2137 return;
2138
2139 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2140 fbs = readl(port_mmio + PORT_FBS);
2141 if (fbs & PORT_FBS_EN) {
2142 dev_info(ap->host->dev, "FBS is enabled\n");
2143 pp->fbs_enabled = true;
2144 pp->fbs_last_dev = -1; /* initialization */
2145 } else
2146 dev_err(ap->host->dev, "Failed to enable FBS\n");
2147
2148 hpriv->start_engine(ap);
2149 }
2150
2151 static void ahci_disable_fbs(struct ata_port *ap)
2152 {
2153 struct ahci_host_priv *hpriv = ap->host->private_data;
2154 struct ahci_port_priv *pp = ap->private_data;
2155 void __iomem *port_mmio = ahci_port_base(ap);
2156 u32 fbs;
2157 int rc;
2158
2159 if (!pp->fbs_supported)
2160 return;
2161
2162 fbs = readl(port_mmio + PORT_FBS);
2163 if ((fbs & PORT_FBS_EN) == 0) {
2164 pp->fbs_enabled = false;
2165 return;
2166 }
2167
2168 rc = ahci_stop_engine(ap);
2169 if (rc)
2170 return;
2171
2172 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2173 fbs = readl(port_mmio + PORT_FBS);
2174 if (fbs & PORT_FBS_EN)
2175 dev_err(ap->host->dev, "Failed to disable FBS\n");
2176 else {
2177 dev_info(ap->host->dev, "FBS is disabled\n");
2178 pp->fbs_enabled = false;
2179 }
2180
2181 hpriv->start_engine(ap);
2182 }
2183
2184 static void ahci_pmp_attach(struct ata_port *ap)
2185 {
2186 void __iomem *port_mmio = ahci_port_base(ap);
2187 struct ahci_port_priv *pp = ap->private_data;
2188 u32 cmd;
2189
2190 cmd = readl(port_mmio + PORT_CMD);
2191 cmd |= PORT_CMD_PMP;
2192 writel(cmd, port_mmio + PORT_CMD);
2193
2194 ahci_enable_fbs(ap);
2195
2196 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2197
2198 /*
2199 * We must not change the port interrupt mask register if the
2200 * port is marked frozen, the value in pp->intr_mask will be
2201 * restored later when the port is thawed.
2202 *
2203 * Note that during initialization, the port is marked as
2204 * frozen since the irq handler is not yet registered.
2205 */
2206 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2207 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2208 }
2209
2210 static void ahci_pmp_detach(struct ata_port *ap)
2211 {
2212 void __iomem *port_mmio = ahci_port_base(ap);
2213 struct ahci_port_priv *pp = ap->private_data;
2214 u32 cmd;
2215
2216 ahci_disable_fbs(ap);
2217
2218 cmd = readl(port_mmio + PORT_CMD);
2219 cmd &= ~PORT_CMD_PMP;
2220 writel(cmd, port_mmio + PORT_CMD);
2221
2222 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2223
2224 /* see comment above in ahci_pmp_attach() */
2225 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2226 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2227 }
2228
2229 int ahci_port_resume(struct ata_port *ap)
2230 {
2231 ahci_power_up(ap);
2232 ahci_start_port(ap);
2233
2234 if (sata_pmp_attached(ap))
2235 ahci_pmp_attach(ap);
2236 else
2237 ahci_pmp_detach(ap);
2238
2239 return 0;
2240 }
2241 EXPORT_SYMBOL_GPL(ahci_port_resume);
2242
2243 #ifdef CONFIG_PM
2244 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2245 {
2246 const char *emsg = NULL;
2247 int rc;
2248
2249 rc = ahci_deinit_port(ap, &emsg);
2250 if (rc == 0)
2251 ahci_power_down(ap);
2252 else {
2253 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2254 ata_port_freeze(ap);
2255 }
2256
2257 return rc;
2258 }
2259 #endif
2260
2261 static int ahci_port_start(struct ata_port *ap)
2262 {
2263 struct ahci_host_priv *hpriv = ap->host->private_data;
2264 struct device *dev = ap->host->dev;
2265 struct ahci_port_priv *pp;
2266 void *mem;
2267 dma_addr_t mem_dma;
2268 size_t dma_sz, rx_fis_sz;
2269
2270 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2271 if (!pp)
2272 return -ENOMEM;
2273
2274 if (ap->host->n_ports > 1) {
2275 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2276 if (!pp->irq_desc) {
2277 devm_kfree(dev, pp);
2278 return -ENOMEM;
2279 }
2280 snprintf(pp->irq_desc, 8,
2281 "%s%d", dev_driver_string(dev), ap->port_no);
2282 }
2283
2284 /* check FBS capability */
2285 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2286 void __iomem *port_mmio = ahci_port_base(ap);
2287 u32 cmd = readl(port_mmio + PORT_CMD);
2288 if (cmd & PORT_CMD_FBSCP)
2289 pp->fbs_supported = true;
2290 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2291 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2292 ap->port_no);
2293 pp->fbs_supported = true;
2294 } else
2295 dev_warn(dev, "port %d is not capable of FBS\n",
2296 ap->port_no);
2297 }
2298
2299 if (pp->fbs_supported) {
2300 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2301 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2302 } else {
2303 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2304 rx_fis_sz = AHCI_RX_FIS_SZ;
2305 }
2306
2307 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2308 if (!mem)
2309 return -ENOMEM;
2310 memset(mem, 0, dma_sz);
2311
2312 /*
2313 * First item in chunk of DMA memory: 32-slot command table,
2314 * 32 bytes each in size
2315 */
2316 pp->cmd_slot = mem;
2317 pp->cmd_slot_dma = mem_dma;
2318
2319 mem += AHCI_CMD_SLOT_SZ;
2320 mem_dma += AHCI_CMD_SLOT_SZ;
2321
2322 /*
2323 * Second item: Received-FIS area
2324 */
2325 pp->rx_fis = mem;
2326 pp->rx_fis_dma = mem_dma;
2327
2328 mem += rx_fis_sz;
2329 mem_dma += rx_fis_sz;
2330
2331 /*
2332 * Third item: data area for storing a single command
2333 * and its scatter-gather table
2334 */
2335 pp->cmd_tbl = mem;
2336 pp->cmd_tbl_dma = mem_dma;
2337
2338 /*
2339 * Save off initial list of interrupts to be enabled.
2340 * This could be changed later
2341 */
2342 pp->intr_mask = DEF_PORT_IRQ;
2343
2344 /*
2345 * Switch to per-port locking in case each port has its own MSI vector.
2346 */
2347 if ((hpriv->flags & AHCI_HFLAG_MULTI_MSI)) {
2348 spin_lock_init(&pp->lock);
2349 ap->lock = &pp->lock;
2350 }
2351
2352 ap->private_data = pp;
2353
2354 /* engage engines, captain */
2355 return ahci_port_resume(ap);
2356 }
2357
2358 static void ahci_port_stop(struct ata_port *ap)
2359 {
2360 const char *emsg = NULL;
2361 int rc;
2362
2363 /* de-initialize port */
2364 rc = ahci_deinit_port(ap, &emsg);
2365 if (rc)
2366 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2367 }
2368
2369 void ahci_print_info(struct ata_host *host, const char *scc_s)
2370 {
2371 struct ahci_host_priv *hpriv = host->private_data;
2372 void __iomem *mmio = hpriv->mmio;
2373 u32 vers, cap, cap2, impl, speed;
2374 const char *speed_s;
2375
2376 vers = readl(mmio + HOST_VERSION);
2377 cap = hpriv->cap;
2378 cap2 = hpriv->cap2;
2379 impl = hpriv->port_map;
2380
2381 speed = (cap >> 20) & 0xf;
2382 if (speed == 1)
2383 speed_s = "1.5";
2384 else if (speed == 2)
2385 speed_s = "3";
2386 else if (speed == 3)
2387 speed_s = "6";
2388 else
2389 speed_s = "?";
2390
2391 dev_info(host->dev,
2392 "AHCI %02x%02x.%02x%02x "
2393 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2394 ,
2395
2396 (vers >> 24) & 0xff,
2397 (vers >> 16) & 0xff,
2398 (vers >> 8) & 0xff,
2399 vers & 0xff,
2400
2401 ((cap >> 8) & 0x1f) + 1,
2402 (cap & 0x1f) + 1,
2403 speed_s,
2404 impl,
2405 scc_s);
2406
2407 dev_info(host->dev,
2408 "flags: "
2409 "%s%s%s%s%s%s%s"
2410 "%s%s%s%s%s%s%s"
2411 "%s%s%s%s%s%s%s"
2412 "%s%s\n"
2413 ,
2414
2415 cap & HOST_CAP_64 ? "64bit " : "",
2416 cap & HOST_CAP_NCQ ? "ncq " : "",
2417 cap & HOST_CAP_SNTF ? "sntf " : "",
2418 cap & HOST_CAP_MPS ? "ilck " : "",
2419 cap & HOST_CAP_SSS ? "stag " : "",
2420 cap & HOST_CAP_ALPM ? "pm " : "",
2421 cap & HOST_CAP_LED ? "led " : "",
2422 cap & HOST_CAP_CLO ? "clo " : "",
2423 cap & HOST_CAP_ONLY ? "only " : "",
2424 cap & HOST_CAP_PMP ? "pmp " : "",
2425 cap & HOST_CAP_FBS ? "fbs " : "",
2426 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2427 cap & HOST_CAP_SSC ? "slum " : "",
2428 cap & HOST_CAP_PART ? "part " : "",
2429 cap & HOST_CAP_CCC ? "ccc " : "",
2430 cap & HOST_CAP_EMS ? "ems " : "",
2431 cap & HOST_CAP_SXS ? "sxs " : "",
2432 cap2 & HOST_CAP2_DESO ? "deso " : "",
2433 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2434 cap2 & HOST_CAP2_SDS ? "sds " : "",
2435 cap2 & HOST_CAP2_APST ? "apst " : "",
2436 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2437 cap2 & HOST_CAP2_BOH ? "boh " : ""
2438 );
2439 }
2440 EXPORT_SYMBOL_GPL(ahci_print_info);
2441
2442 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2443 struct ata_port_info *pi)
2444 {
2445 u8 messages;
2446 void __iomem *mmio = hpriv->mmio;
2447 u32 em_loc = readl(mmio + HOST_EM_LOC);
2448 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2449
2450 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2451 return;
2452
2453 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2454
2455 if (messages) {
2456 /* store em_loc */
2457 hpriv->em_loc = ((em_loc >> 16) * 4);
2458 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2459 hpriv->em_msg_type = messages;
2460 pi->flags |= ATA_FLAG_EM;
2461 if (!(em_ctl & EM_CTL_ALHD))
2462 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2463 }
2464 }
2465 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2466
2467 MODULE_AUTHOR("Jeff Garzik");
2468 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2469 MODULE_LICENSE("GPL");
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