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ahci: Do not export local variable ahci_em_messages
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / libahci.c
1 /*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/nospec.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47 #include <linux/pci.h>
48 #include "ahci.h"
49 #include "libata.h"
50
51 static int ahci_skip_host_reset;
52 int ahci_ignore_sss;
53 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
54
55 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
56 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
57
58 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
59 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
60
61 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
62 unsigned hints);
63 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
64 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
65 size_t size);
66 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
67 ssize_t size);
68
69
70
71 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
72 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74 static int ahci_port_start(struct ata_port *ap);
75 static void ahci_port_stop(struct ata_port *ap);
76 static void ahci_qc_prep(struct ata_queued_cmd *qc);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78 static void ahci_freeze(struct ata_port *ap);
79 static void ahci_thaw(struct ata_port *ap);
80 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
81 static void ahci_enable_fbs(struct ata_port *ap);
82 static void ahci_disable_fbs(struct ata_port *ap);
83 static void ahci_pmp_attach(struct ata_port *ap);
84 static void ahci_pmp_detach(struct ata_port *ap);
85 static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static void ahci_postreset(struct ata_link *link, unsigned int *class);
92 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
93 static void ahci_dev_config(struct ata_device *dev);
94 #ifdef CONFIG_PM
95 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96 #endif
97 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98 static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100 static void ahci_init_sw_activity(struct ata_link *link);
101
102 static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108 static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
110 static ssize_t ahci_read_em_buffer(struct device *dev,
111 struct device_attribute *attr, char *buf);
112 static ssize_t ahci_store_em_buffer(struct device *dev,
113 struct device_attribute *attr,
114 const char *buf, size_t size);
115 static ssize_t ahci_show_em_supported(struct device *dev,
116 struct device_attribute *attr, char *buf);
117 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
118
119 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
120 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
121 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
122 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
123 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
124 ahci_read_em_buffer, ahci_store_em_buffer);
125 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
126
127 struct device_attribute *ahci_shost_attrs[] = {
128 &dev_attr_link_power_management_policy,
129 &dev_attr_em_message_type,
130 &dev_attr_em_message,
131 &dev_attr_ahci_host_caps,
132 &dev_attr_ahci_host_cap2,
133 &dev_attr_ahci_host_version,
134 &dev_attr_ahci_port_cmd,
135 &dev_attr_em_buffer,
136 &dev_attr_em_message_supported,
137 NULL
138 };
139 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
140
141 struct device_attribute *ahci_sdev_attrs[] = {
142 &dev_attr_sw_activity,
143 &dev_attr_unload_heads,
144 &dev_attr_ncq_prio_enable,
145 NULL
146 };
147 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
148
149 struct ata_port_operations ahci_ops = {
150 .inherits = &sata_pmp_port_ops,
151
152 .qc_defer = ahci_pmp_qc_defer,
153 .qc_prep = ahci_qc_prep,
154 .qc_issue = ahci_qc_issue,
155 .qc_fill_rtf = ahci_qc_fill_rtf,
156
157 .freeze = ahci_freeze,
158 .thaw = ahci_thaw,
159 .softreset = ahci_softreset,
160 .hardreset = ahci_hardreset,
161 .postreset = ahci_postreset,
162 .pmp_softreset = ahci_softreset,
163 .error_handler = ahci_error_handler,
164 .post_internal_cmd = ahci_post_internal_cmd,
165 .dev_config = ahci_dev_config,
166
167 .scr_read = ahci_scr_read,
168 .scr_write = ahci_scr_write,
169 .pmp_attach = ahci_pmp_attach,
170 .pmp_detach = ahci_pmp_detach,
171
172 .set_lpm = ahci_set_lpm,
173 .em_show = ahci_led_show,
174 .em_store = ahci_led_store,
175 .sw_activity_show = ahci_activity_show,
176 .sw_activity_store = ahci_activity_store,
177 .transmit_led_message = ahci_transmit_led_message,
178 #ifdef CONFIG_PM
179 .port_suspend = ahci_port_suspend,
180 .port_resume = ahci_port_resume,
181 #endif
182 .port_start = ahci_port_start,
183 .port_stop = ahci_port_stop,
184 };
185 EXPORT_SYMBOL_GPL(ahci_ops);
186
187 struct ata_port_operations ahci_pmp_retry_srst_ops = {
188 .inherits = &ahci_ops,
189 .softreset = ahci_pmp_retry_softreset,
190 };
191 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
192
193 static bool ahci_em_messages __read_mostly = true;
194 module_param(ahci_em_messages, bool, 0444);
195 /* add other LED protocol types when they become supported */
196 MODULE_PARM_DESC(ahci_em_messages,
197 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
198
199 /* device sleep idle timeout in ms */
200 static int devslp_idle_timeout __read_mostly = 1000;
201 module_param(devslp_idle_timeout, int, 0644);
202 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
203
204 static void ahci_enable_ahci(void __iomem *mmio)
205 {
206 int i;
207 u32 tmp;
208
209 /* turn on AHCI_EN */
210 tmp = readl(mmio + HOST_CTL);
211 if (tmp & HOST_AHCI_EN)
212 return;
213
214 /* Some controllers need AHCI_EN to be written multiple times.
215 * Try a few times before giving up.
216 */
217 for (i = 0; i < 5; i++) {
218 tmp |= HOST_AHCI_EN;
219 writel(tmp, mmio + HOST_CTL);
220 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
221 if (tmp & HOST_AHCI_EN)
222 return;
223 msleep(10);
224 }
225
226 WARN_ON(1);
227 }
228
229 /**
230 * ahci_rpm_get_port - Make sure the port is powered on
231 * @ap: Port to power on
232 *
233 * Whenever there is need to access the AHCI host registers outside of
234 * normal execution paths, call this function to make sure the host is
235 * actually powered on.
236 */
237 static int ahci_rpm_get_port(struct ata_port *ap)
238 {
239 return pm_runtime_get_sync(ap->dev);
240 }
241
242 /**
243 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
244 * @ap: Port to power down
245 *
246 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
247 * if it has no more active users.
248 */
249 static void ahci_rpm_put_port(struct ata_port *ap)
250 {
251 pm_runtime_put(ap->dev);
252 }
253
254 static ssize_t ahci_show_host_caps(struct device *dev,
255 struct device_attribute *attr, char *buf)
256 {
257 struct Scsi_Host *shost = class_to_shost(dev);
258 struct ata_port *ap = ata_shost_to_port(shost);
259 struct ahci_host_priv *hpriv = ap->host->private_data;
260
261 return sprintf(buf, "%x\n", hpriv->cap);
262 }
263
264 static ssize_t ahci_show_host_cap2(struct device *dev,
265 struct device_attribute *attr, char *buf)
266 {
267 struct Scsi_Host *shost = class_to_shost(dev);
268 struct ata_port *ap = ata_shost_to_port(shost);
269 struct ahci_host_priv *hpriv = ap->host->private_data;
270
271 return sprintf(buf, "%x\n", hpriv->cap2);
272 }
273
274 static ssize_t ahci_show_host_version(struct device *dev,
275 struct device_attribute *attr, char *buf)
276 {
277 struct Scsi_Host *shost = class_to_shost(dev);
278 struct ata_port *ap = ata_shost_to_port(shost);
279 struct ahci_host_priv *hpriv = ap->host->private_data;
280
281 return sprintf(buf, "%x\n", hpriv->version);
282 }
283
284 static ssize_t ahci_show_port_cmd(struct device *dev,
285 struct device_attribute *attr, char *buf)
286 {
287 struct Scsi_Host *shost = class_to_shost(dev);
288 struct ata_port *ap = ata_shost_to_port(shost);
289 void __iomem *port_mmio = ahci_port_base(ap);
290 ssize_t ret;
291
292 ahci_rpm_get_port(ap);
293 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
294 ahci_rpm_put_port(ap);
295
296 return ret;
297 }
298
299 static ssize_t ahci_read_em_buffer(struct device *dev,
300 struct device_attribute *attr, char *buf)
301 {
302 struct Scsi_Host *shost = class_to_shost(dev);
303 struct ata_port *ap = ata_shost_to_port(shost);
304 struct ahci_host_priv *hpriv = ap->host->private_data;
305 void __iomem *mmio = hpriv->mmio;
306 void __iomem *em_mmio = mmio + hpriv->em_loc;
307 u32 em_ctl, msg;
308 unsigned long flags;
309 size_t count;
310 int i;
311
312 ahci_rpm_get_port(ap);
313 spin_lock_irqsave(ap->lock, flags);
314
315 em_ctl = readl(mmio + HOST_EM_CTL);
316 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
317 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
318 spin_unlock_irqrestore(ap->lock, flags);
319 ahci_rpm_put_port(ap);
320 return -EINVAL;
321 }
322
323 if (!(em_ctl & EM_CTL_MR)) {
324 spin_unlock_irqrestore(ap->lock, flags);
325 ahci_rpm_put_port(ap);
326 return -EAGAIN;
327 }
328
329 if (!(em_ctl & EM_CTL_SMB))
330 em_mmio += hpriv->em_buf_sz;
331
332 count = hpriv->em_buf_sz;
333
334 /* the count should not be larger than PAGE_SIZE */
335 if (count > PAGE_SIZE) {
336 if (printk_ratelimit())
337 ata_port_warn(ap,
338 "EM read buffer size too large: "
339 "buffer size %u, page size %lu\n",
340 hpriv->em_buf_sz, PAGE_SIZE);
341 count = PAGE_SIZE;
342 }
343
344 for (i = 0; i < count; i += 4) {
345 msg = readl(em_mmio + i);
346 buf[i] = msg & 0xff;
347 buf[i + 1] = (msg >> 8) & 0xff;
348 buf[i + 2] = (msg >> 16) & 0xff;
349 buf[i + 3] = (msg >> 24) & 0xff;
350 }
351
352 spin_unlock_irqrestore(ap->lock, flags);
353 ahci_rpm_put_port(ap);
354
355 return i;
356 }
357
358 static ssize_t ahci_store_em_buffer(struct device *dev,
359 struct device_attribute *attr,
360 const char *buf, size_t size)
361 {
362 struct Scsi_Host *shost = class_to_shost(dev);
363 struct ata_port *ap = ata_shost_to_port(shost);
364 struct ahci_host_priv *hpriv = ap->host->private_data;
365 void __iomem *mmio = hpriv->mmio;
366 void __iomem *em_mmio = mmio + hpriv->em_loc;
367 const unsigned char *msg_buf = buf;
368 u32 em_ctl, msg;
369 unsigned long flags;
370 int i;
371
372 /* check size validity */
373 if (!(ap->flags & ATA_FLAG_EM) ||
374 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
375 size % 4 || size > hpriv->em_buf_sz)
376 return -EINVAL;
377
378 ahci_rpm_get_port(ap);
379 spin_lock_irqsave(ap->lock, flags);
380
381 em_ctl = readl(mmio + HOST_EM_CTL);
382 if (em_ctl & EM_CTL_TM) {
383 spin_unlock_irqrestore(ap->lock, flags);
384 ahci_rpm_put_port(ap);
385 return -EBUSY;
386 }
387
388 for (i = 0; i < size; i += 4) {
389 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
390 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
391 writel(msg, em_mmio + i);
392 }
393
394 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
395
396 spin_unlock_irqrestore(ap->lock, flags);
397 ahci_rpm_put_port(ap);
398
399 return size;
400 }
401
402 static ssize_t ahci_show_em_supported(struct device *dev,
403 struct device_attribute *attr, char *buf)
404 {
405 struct Scsi_Host *shost = class_to_shost(dev);
406 struct ata_port *ap = ata_shost_to_port(shost);
407 struct ahci_host_priv *hpriv = ap->host->private_data;
408 void __iomem *mmio = hpriv->mmio;
409 u32 em_ctl;
410
411 ahci_rpm_get_port(ap);
412 em_ctl = readl(mmio + HOST_EM_CTL);
413 ahci_rpm_put_port(ap);
414
415 return sprintf(buf, "%s%s%s%s\n",
416 em_ctl & EM_CTL_LED ? "led " : "",
417 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
418 em_ctl & EM_CTL_SES ? "ses-2 " : "",
419 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
420 }
421
422 /**
423 * ahci_save_initial_config - Save and fixup initial config values
424 * @dev: target AHCI device
425 * @hpriv: host private area to store config values
426 *
427 * Some registers containing configuration info might be setup by
428 * BIOS and might be cleared on reset. This function saves the
429 * initial values of those registers into @hpriv such that they
430 * can be restored after controller reset.
431 *
432 * If inconsistent, config values are fixed up by this function.
433 *
434 * If it is not set already this function sets hpriv->start_engine to
435 * ahci_start_engine.
436 *
437 * LOCKING:
438 * None.
439 */
440 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
441 {
442 void __iomem *mmio = hpriv->mmio;
443 u32 cap, cap2, vers, port_map;
444 int i;
445
446 /* make sure AHCI mode is enabled before accessing CAP */
447 ahci_enable_ahci(mmio);
448
449 /* Values prefixed with saved_ are written back to host after
450 * reset. Values without are used for driver operation.
451 */
452 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
453 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
454
455 /* CAP2 register is only defined for AHCI 1.2 and later */
456 vers = readl(mmio + HOST_VERSION);
457 if ((vers >> 16) > 1 ||
458 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
459 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
460 else
461 hpriv->saved_cap2 = cap2 = 0;
462
463 /* some chips have errata preventing 64bit use */
464 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
465 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
466 cap &= ~HOST_CAP_64;
467 }
468
469 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
470 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
471 cap &= ~HOST_CAP_NCQ;
472 }
473
474 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
475 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
476 cap |= HOST_CAP_NCQ;
477 }
478
479 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
480 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
481 cap &= ~HOST_CAP_PMP;
482 }
483
484 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
485 dev_info(dev,
486 "controller can't do SNTF, turning off CAP_SNTF\n");
487 cap &= ~HOST_CAP_SNTF;
488 }
489
490 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
491 dev_info(dev,
492 "controller can't do DEVSLP, turning off\n");
493 cap2 &= ~HOST_CAP2_SDS;
494 cap2 &= ~HOST_CAP2_SADM;
495 }
496
497 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
498 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
499 cap |= HOST_CAP_FBS;
500 }
501
502 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
503 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
504 cap &= ~HOST_CAP_FBS;
505 }
506
507 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
508 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
509 cap |= HOST_CAP_ALPM;
510 }
511
512 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
513 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
514 port_map, hpriv->force_port_map);
515 port_map = hpriv->force_port_map;
516 hpriv->saved_port_map = port_map;
517 }
518
519 if (hpriv->mask_port_map) {
520 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
521 port_map,
522 port_map & hpriv->mask_port_map);
523 port_map &= hpriv->mask_port_map;
524 }
525
526 /* cross check port_map and cap.n_ports */
527 if (port_map) {
528 int map_ports = 0;
529
530 for (i = 0; i < AHCI_MAX_PORTS; i++)
531 if (port_map & (1 << i))
532 map_ports++;
533
534 /* If PI has more ports than n_ports, whine, clear
535 * port_map and let it be generated from n_ports.
536 */
537 if (map_ports > ahci_nr_ports(cap)) {
538 dev_warn(dev,
539 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
540 port_map, ahci_nr_ports(cap));
541 port_map = 0;
542 }
543 }
544
545 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
546 if (!port_map && vers < 0x10300) {
547 port_map = (1 << ahci_nr_ports(cap)) - 1;
548 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
549
550 /* write the fixed up value to the PI register */
551 hpriv->saved_port_map = port_map;
552 }
553
554 /* record values to use during operation */
555 hpriv->cap = cap;
556 hpriv->cap2 = cap2;
557 hpriv->version = readl(mmio + HOST_VERSION);
558 hpriv->port_map = port_map;
559
560 if (!hpriv->start_engine)
561 hpriv->start_engine = ahci_start_engine;
562
563 if (!hpriv->stop_engine)
564 hpriv->stop_engine = ahci_stop_engine;
565
566 if (!hpriv->irq_handler)
567 hpriv->irq_handler = ahci_single_level_irq_intr;
568 }
569 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
570
571 /**
572 * ahci_restore_initial_config - Restore initial config
573 * @host: target ATA host
574 *
575 * Restore initial config stored by ahci_save_initial_config().
576 *
577 * LOCKING:
578 * None.
579 */
580 static void ahci_restore_initial_config(struct ata_host *host)
581 {
582 struct ahci_host_priv *hpriv = host->private_data;
583 void __iomem *mmio = hpriv->mmio;
584
585 writel(hpriv->saved_cap, mmio + HOST_CAP);
586 if (hpriv->saved_cap2)
587 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
588 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
589 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
590 }
591
592 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
593 {
594 static const int offset[] = {
595 [SCR_STATUS] = PORT_SCR_STAT,
596 [SCR_CONTROL] = PORT_SCR_CTL,
597 [SCR_ERROR] = PORT_SCR_ERR,
598 [SCR_ACTIVE] = PORT_SCR_ACT,
599 [SCR_NOTIFICATION] = PORT_SCR_NTF,
600 };
601 struct ahci_host_priv *hpriv = ap->host->private_data;
602
603 if (sc_reg < ARRAY_SIZE(offset) &&
604 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
605 return offset[sc_reg];
606 return 0;
607 }
608
609 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
610 {
611 void __iomem *port_mmio = ahci_port_base(link->ap);
612 int offset = ahci_scr_offset(link->ap, sc_reg);
613
614 if (offset) {
615 *val = readl(port_mmio + offset);
616 return 0;
617 }
618 return -EINVAL;
619 }
620
621 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
622 {
623 void __iomem *port_mmio = ahci_port_base(link->ap);
624 int offset = ahci_scr_offset(link->ap, sc_reg);
625
626 if (offset) {
627 writel(val, port_mmio + offset);
628 return 0;
629 }
630 return -EINVAL;
631 }
632
633 void ahci_start_engine(struct ata_port *ap)
634 {
635 void __iomem *port_mmio = ahci_port_base(ap);
636 u32 tmp;
637
638 /* start DMA */
639 tmp = readl(port_mmio + PORT_CMD);
640 tmp |= PORT_CMD_START;
641 writel(tmp, port_mmio + PORT_CMD);
642 readl(port_mmio + PORT_CMD); /* flush */
643 }
644 EXPORT_SYMBOL_GPL(ahci_start_engine);
645
646 int ahci_stop_engine(struct ata_port *ap)
647 {
648 void __iomem *port_mmio = ahci_port_base(ap);
649 struct ahci_host_priv *hpriv = ap->host->private_data;
650 u32 tmp;
651
652 /*
653 * On some controllers, stopping a port's DMA engine while the port
654 * is in ALPM state (partial or slumber) results in failures on
655 * subsequent DMA engine starts. For those controllers, put the
656 * port back in active state before stopping its DMA engine.
657 */
658 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
659 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
660 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
661 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
662 return -EIO;
663 }
664
665 tmp = readl(port_mmio + PORT_CMD);
666
667 /* check if the HBA is idle */
668 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
669 return 0;
670
671 /* setting HBA to idle */
672 tmp &= ~PORT_CMD_START;
673 writel(tmp, port_mmio + PORT_CMD);
674
675 /* wait for engine to stop. This could be as long as 500 msec */
676 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
677 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
678 if (tmp & PORT_CMD_LIST_ON)
679 return -EIO;
680
681 return 0;
682 }
683 EXPORT_SYMBOL_GPL(ahci_stop_engine);
684
685 void ahci_start_fis_rx(struct ata_port *ap)
686 {
687 void __iomem *port_mmio = ahci_port_base(ap);
688 struct ahci_host_priv *hpriv = ap->host->private_data;
689 struct ahci_port_priv *pp = ap->private_data;
690 u32 tmp;
691
692 /* set FIS registers */
693 if (hpriv->cap & HOST_CAP_64)
694 writel((pp->cmd_slot_dma >> 16) >> 16,
695 port_mmio + PORT_LST_ADDR_HI);
696 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
697
698 if (hpriv->cap & HOST_CAP_64)
699 writel((pp->rx_fis_dma >> 16) >> 16,
700 port_mmio + PORT_FIS_ADDR_HI);
701 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
702
703 /* enable FIS reception */
704 tmp = readl(port_mmio + PORT_CMD);
705 tmp |= PORT_CMD_FIS_RX;
706 writel(tmp, port_mmio + PORT_CMD);
707
708 /* flush */
709 readl(port_mmio + PORT_CMD);
710 }
711 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
712
713 static int ahci_stop_fis_rx(struct ata_port *ap)
714 {
715 void __iomem *port_mmio = ahci_port_base(ap);
716 u32 tmp;
717
718 /* disable FIS reception */
719 tmp = readl(port_mmio + PORT_CMD);
720 tmp &= ~PORT_CMD_FIS_RX;
721 writel(tmp, port_mmio + PORT_CMD);
722
723 /* wait for completion, spec says 500ms, give it 1000 */
724 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
725 PORT_CMD_FIS_ON, 10, 1000);
726 if (tmp & PORT_CMD_FIS_ON)
727 return -EBUSY;
728
729 return 0;
730 }
731
732 static void ahci_power_up(struct ata_port *ap)
733 {
734 struct ahci_host_priv *hpriv = ap->host->private_data;
735 void __iomem *port_mmio = ahci_port_base(ap);
736 u32 cmd;
737
738 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
739
740 /* spin up device */
741 if (hpriv->cap & HOST_CAP_SSS) {
742 cmd |= PORT_CMD_SPIN_UP;
743 writel(cmd, port_mmio + PORT_CMD);
744 }
745
746 /* wake up link */
747 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
748 }
749
750 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
751 unsigned int hints)
752 {
753 struct ata_port *ap = link->ap;
754 struct ahci_host_priv *hpriv = ap->host->private_data;
755 struct ahci_port_priv *pp = ap->private_data;
756 void __iomem *port_mmio = ahci_port_base(ap);
757
758 if (policy != ATA_LPM_MAX_POWER) {
759 /* wakeup flag only applies to the max power policy */
760 hints &= ~ATA_LPM_WAKE_ONLY;
761
762 /*
763 * Disable interrupts on Phy Ready. This keeps us from
764 * getting woken up due to spurious phy ready
765 * interrupts.
766 */
767 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
768 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
769
770 sata_link_scr_lpm(link, policy, false);
771 }
772
773 if (hpriv->cap & HOST_CAP_ALPM) {
774 u32 cmd = readl(port_mmio + PORT_CMD);
775
776 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
777 if (!(hints & ATA_LPM_WAKE_ONLY))
778 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
779 cmd |= PORT_CMD_ICC_ACTIVE;
780
781 writel(cmd, port_mmio + PORT_CMD);
782 readl(port_mmio + PORT_CMD);
783
784 /* wait 10ms to be sure we've come out of LPM state */
785 ata_msleep(ap, 10);
786
787 if (hints & ATA_LPM_WAKE_ONLY)
788 return 0;
789 } else {
790 cmd |= PORT_CMD_ALPE;
791 if (policy == ATA_LPM_MIN_POWER)
792 cmd |= PORT_CMD_ASP;
793 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
794 cmd &= ~PORT_CMD_ASP;
795
796 /* write out new cmd value */
797 writel(cmd, port_mmio + PORT_CMD);
798 }
799 }
800
801 /* set aggressive device sleep */
802 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
803 (hpriv->cap2 & HOST_CAP2_SADM) &&
804 (link->device->flags & ATA_DFLAG_DEVSLP)) {
805 if (policy == ATA_LPM_MIN_POWER ||
806 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
807 ahci_set_aggressive_devslp(ap, true);
808 else
809 ahci_set_aggressive_devslp(ap, false);
810 }
811
812 if (policy == ATA_LPM_MAX_POWER) {
813 sata_link_scr_lpm(link, policy, false);
814
815 /* turn PHYRDY IRQ back on */
816 pp->intr_mask |= PORT_IRQ_PHYRDY;
817 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
818 }
819
820 return 0;
821 }
822
823 #ifdef CONFIG_PM
824 static void ahci_power_down(struct ata_port *ap)
825 {
826 struct ahci_host_priv *hpriv = ap->host->private_data;
827 void __iomem *port_mmio = ahci_port_base(ap);
828 u32 cmd, scontrol;
829
830 if (!(hpriv->cap & HOST_CAP_SSS))
831 return;
832
833 /* put device into listen mode, first set PxSCTL.DET to 0 */
834 scontrol = readl(port_mmio + PORT_SCR_CTL);
835 scontrol &= ~0xf;
836 writel(scontrol, port_mmio + PORT_SCR_CTL);
837
838 /* then set PxCMD.SUD to 0 */
839 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
840 cmd &= ~PORT_CMD_SPIN_UP;
841 writel(cmd, port_mmio + PORT_CMD);
842 }
843 #endif
844
845 static void ahci_start_port(struct ata_port *ap)
846 {
847 struct ahci_host_priv *hpriv = ap->host->private_data;
848 struct ahci_port_priv *pp = ap->private_data;
849 struct ata_link *link;
850 struct ahci_em_priv *emp;
851 ssize_t rc;
852 int i;
853
854 /* enable FIS reception */
855 ahci_start_fis_rx(ap);
856
857 /* enable DMA */
858 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
859 hpriv->start_engine(ap);
860
861 /* turn on LEDs */
862 if (ap->flags & ATA_FLAG_EM) {
863 ata_for_each_link(link, ap, EDGE) {
864 emp = &pp->em_priv[link->pmp];
865
866 /* EM Transmit bit maybe busy during init */
867 for (i = 0; i < EM_MAX_RETRY; i++) {
868 rc = ap->ops->transmit_led_message(ap,
869 emp->led_state,
870 4);
871 /*
872 * If busy, give a breather but do not
873 * release EH ownership by using msleep()
874 * instead of ata_msleep(). EM Transmit
875 * bit is busy for the whole host and
876 * releasing ownership will cause other
877 * ports to fail the same way.
878 */
879 if (rc == -EBUSY)
880 msleep(1);
881 else
882 break;
883 }
884 }
885 }
886
887 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
888 ata_for_each_link(link, ap, EDGE)
889 ahci_init_sw_activity(link);
890
891 }
892
893 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
894 {
895 int rc;
896 struct ahci_host_priv *hpriv = ap->host->private_data;
897
898 /* disable DMA */
899 rc = hpriv->stop_engine(ap);
900 if (rc) {
901 *emsg = "failed to stop engine";
902 return rc;
903 }
904
905 /* disable FIS reception */
906 rc = ahci_stop_fis_rx(ap);
907 if (rc) {
908 *emsg = "failed stop FIS RX";
909 return rc;
910 }
911
912 return 0;
913 }
914
915 int ahci_reset_controller(struct ata_host *host)
916 {
917 struct ahci_host_priv *hpriv = host->private_data;
918 void __iomem *mmio = hpriv->mmio;
919 u32 tmp;
920
921 /* we must be in AHCI mode, before using anything
922 * AHCI-specific, such as HOST_RESET.
923 */
924 ahci_enable_ahci(mmio);
925
926 /* global controller reset */
927 if (!ahci_skip_host_reset) {
928 tmp = readl(mmio + HOST_CTL);
929 if ((tmp & HOST_RESET) == 0) {
930 writel(tmp | HOST_RESET, mmio + HOST_CTL);
931 readl(mmio + HOST_CTL); /* flush */
932 }
933
934 /*
935 * to perform host reset, OS should set HOST_RESET
936 * and poll until this bit is read to be "0".
937 * reset must complete within 1 second, or
938 * the hardware should be considered fried.
939 */
940 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
941 HOST_RESET, 10, 1000);
942
943 if (tmp & HOST_RESET) {
944 dev_err(host->dev, "controller reset failed (0x%x)\n",
945 tmp);
946 return -EIO;
947 }
948
949 /* turn on AHCI mode */
950 ahci_enable_ahci(mmio);
951
952 /* Some registers might be cleared on reset. Restore
953 * initial values.
954 */
955 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
956 ahci_restore_initial_config(host);
957 } else
958 dev_info(host->dev, "skipping global host reset\n");
959
960 return 0;
961 }
962 EXPORT_SYMBOL_GPL(ahci_reset_controller);
963
964 static void ahci_sw_activity(struct ata_link *link)
965 {
966 struct ata_port *ap = link->ap;
967 struct ahci_port_priv *pp = ap->private_data;
968 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
969
970 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
971 return;
972
973 emp->activity++;
974 if (!timer_pending(&emp->timer))
975 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
976 }
977
978 static void ahci_sw_activity_blink(struct timer_list *t)
979 {
980 struct ahci_em_priv *emp = from_timer(emp, t, timer);
981 struct ata_link *link = emp->link;
982 struct ata_port *ap = link->ap;
983
984 unsigned long led_message = emp->led_state;
985 u32 activity_led_state;
986 unsigned long flags;
987
988 led_message &= EM_MSG_LED_VALUE;
989 led_message |= ap->port_no | (link->pmp << 8);
990
991 /* check to see if we've had activity. If so,
992 * toggle state of LED and reset timer. If not,
993 * turn LED to desired idle state.
994 */
995 spin_lock_irqsave(ap->lock, flags);
996 if (emp->saved_activity != emp->activity) {
997 emp->saved_activity = emp->activity;
998 /* get the current LED state */
999 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1000
1001 if (activity_led_state)
1002 activity_led_state = 0;
1003 else
1004 activity_led_state = 1;
1005
1006 /* clear old state */
1007 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1008
1009 /* toggle state */
1010 led_message |= (activity_led_state << 16);
1011 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1012 } else {
1013 /* switch to idle */
1014 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1015 if (emp->blink_policy == BLINK_OFF)
1016 led_message |= (1 << 16);
1017 }
1018 spin_unlock_irqrestore(ap->lock, flags);
1019 ap->ops->transmit_led_message(ap, led_message, 4);
1020 }
1021
1022 static void ahci_init_sw_activity(struct ata_link *link)
1023 {
1024 struct ata_port *ap = link->ap;
1025 struct ahci_port_priv *pp = ap->private_data;
1026 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1027
1028 /* init activity stats, setup timer */
1029 emp->saved_activity = emp->activity = 0;
1030 emp->link = link;
1031 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1032
1033 /* check our blink policy and set flag for link if it's enabled */
1034 if (emp->blink_policy)
1035 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1036 }
1037
1038 int ahci_reset_em(struct ata_host *host)
1039 {
1040 struct ahci_host_priv *hpriv = host->private_data;
1041 void __iomem *mmio = hpriv->mmio;
1042 u32 em_ctl;
1043
1044 em_ctl = readl(mmio + HOST_EM_CTL);
1045 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1046 return -EINVAL;
1047
1048 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1049 return 0;
1050 }
1051 EXPORT_SYMBOL_GPL(ahci_reset_em);
1052
1053 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1054 ssize_t size)
1055 {
1056 struct ahci_host_priv *hpriv = ap->host->private_data;
1057 struct ahci_port_priv *pp = ap->private_data;
1058 void __iomem *mmio = hpriv->mmio;
1059 u32 em_ctl;
1060 u32 message[] = {0, 0};
1061 unsigned long flags;
1062 int pmp;
1063 struct ahci_em_priv *emp;
1064
1065 /* get the slot number from the message */
1066 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1067 if (pmp < EM_MAX_SLOTS)
1068 emp = &pp->em_priv[pmp];
1069 else
1070 return -EINVAL;
1071
1072 ahci_rpm_get_port(ap);
1073 spin_lock_irqsave(ap->lock, flags);
1074
1075 /*
1076 * if we are still busy transmitting a previous message,
1077 * do not allow
1078 */
1079 em_ctl = readl(mmio + HOST_EM_CTL);
1080 if (em_ctl & EM_CTL_TM) {
1081 spin_unlock_irqrestore(ap->lock, flags);
1082 ahci_rpm_put_port(ap);
1083 return -EBUSY;
1084 }
1085
1086 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1087 /*
1088 * create message header - this is all zero except for
1089 * the message size, which is 4 bytes.
1090 */
1091 message[0] |= (4 << 8);
1092
1093 /* ignore 0:4 of byte zero, fill in port info yourself */
1094 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1095
1096 /* write message to EM_LOC */
1097 writel(message[0], mmio + hpriv->em_loc);
1098 writel(message[1], mmio + hpriv->em_loc+4);
1099
1100 /*
1101 * tell hardware to transmit the message
1102 */
1103 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1104 }
1105
1106 /* save off new led state for port/slot */
1107 emp->led_state = state;
1108
1109 spin_unlock_irqrestore(ap->lock, flags);
1110 ahci_rpm_put_port(ap);
1111
1112 return size;
1113 }
1114
1115 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1116 {
1117 struct ahci_port_priv *pp = ap->private_data;
1118 struct ata_link *link;
1119 struct ahci_em_priv *emp;
1120 int rc = 0;
1121
1122 ata_for_each_link(link, ap, EDGE) {
1123 emp = &pp->em_priv[link->pmp];
1124 rc += sprintf(buf, "%lx\n", emp->led_state);
1125 }
1126 return rc;
1127 }
1128
1129 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1130 size_t size)
1131 {
1132 unsigned int state;
1133 int pmp;
1134 struct ahci_port_priv *pp = ap->private_data;
1135 struct ahci_em_priv *emp;
1136
1137 if (kstrtouint(buf, 0, &state) < 0)
1138 return -EINVAL;
1139
1140 /* get the slot number from the message */
1141 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1142 if (pmp < EM_MAX_SLOTS) {
1143 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1144 emp = &pp->em_priv[pmp];
1145 } else {
1146 return -EINVAL;
1147 }
1148
1149 /* mask off the activity bits if we are in sw_activity
1150 * mode, user should turn off sw_activity before setting
1151 * activity led through em_message
1152 */
1153 if (emp->blink_policy)
1154 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1155
1156 return ap->ops->transmit_led_message(ap, state, size);
1157 }
1158
1159 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1160 {
1161 struct ata_link *link = dev->link;
1162 struct ata_port *ap = link->ap;
1163 struct ahci_port_priv *pp = ap->private_data;
1164 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1165 u32 port_led_state = emp->led_state;
1166
1167 /* save the desired Activity LED behavior */
1168 if (val == OFF) {
1169 /* clear LFLAG */
1170 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1171
1172 /* set the LED to OFF */
1173 port_led_state &= EM_MSG_LED_VALUE_OFF;
1174 port_led_state |= (ap->port_no | (link->pmp << 8));
1175 ap->ops->transmit_led_message(ap, port_led_state, 4);
1176 } else {
1177 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1178 if (val == BLINK_OFF) {
1179 /* set LED to ON for idle */
1180 port_led_state &= EM_MSG_LED_VALUE_OFF;
1181 port_led_state |= (ap->port_no | (link->pmp << 8));
1182 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1183 ap->ops->transmit_led_message(ap, port_led_state, 4);
1184 }
1185 }
1186 emp->blink_policy = val;
1187 return 0;
1188 }
1189
1190 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1191 {
1192 struct ata_link *link = dev->link;
1193 struct ata_port *ap = link->ap;
1194 struct ahci_port_priv *pp = ap->private_data;
1195 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1196
1197 /* display the saved value of activity behavior for this
1198 * disk.
1199 */
1200 return sprintf(buf, "%d\n", emp->blink_policy);
1201 }
1202
1203 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1204 int port_no, void __iomem *mmio,
1205 void __iomem *port_mmio)
1206 {
1207 struct ahci_host_priv *hpriv = ap->host->private_data;
1208 const char *emsg = NULL;
1209 int rc;
1210 u32 tmp;
1211
1212 /* make sure port is not active */
1213 rc = ahci_deinit_port(ap, &emsg);
1214 if (rc)
1215 dev_warn(dev, "%s (%d)\n", emsg, rc);
1216
1217 /* clear SError */
1218 tmp = readl(port_mmio + PORT_SCR_ERR);
1219 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1220 writel(tmp, port_mmio + PORT_SCR_ERR);
1221
1222 /* clear port IRQ */
1223 tmp = readl(port_mmio + PORT_IRQ_STAT);
1224 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1225 if (tmp)
1226 writel(tmp, port_mmio + PORT_IRQ_STAT);
1227
1228 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1229
1230 /* mark esata ports */
1231 tmp = readl(port_mmio + PORT_CMD);
1232 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1233 ap->pflags |= ATA_PFLAG_EXTERNAL;
1234 }
1235
1236 void ahci_init_controller(struct ata_host *host)
1237 {
1238 struct ahci_host_priv *hpriv = host->private_data;
1239 void __iomem *mmio = hpriv->mmio;
1240 int i;
1241 void __iomem *port_mmio;
1242 u32 tmp;
1243
1244 for (i = 0; i < host->n_ports; i++) {
1245 struct ata_port *ap = host->ports[i];
1246
1247 port_mmio = ahci_port_base(ap);
1248 if (ata_port_is_dummy(ap))
1249 continue;
1250
1251 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1252 }
1253
1254 tmp = readl(mmio + HOST_CTL);
1255 VPRINTK("HOST_CTL 0x%x\n", tmp);
1256 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1257 tmp = readl(mmio + HOST_CTL);
1258 VPRINTK("HOST_CTL 0x%x\n", tmp);
1259 }
1260 EXPORT_SYMBOL_GPL(ahci_init_controller);
1261
1262 static void ahci_dev_config(struct ata_device *dev)
1263 {
1264 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1265
1266 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1267 dev->max_sectors = 255;
1268 ata_dev_info(dev,
1269 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1270 }
1271 }
1272
1273 unsigned int ahci_dev_classify(struct ata_port *ap)
1274 {
1275 void __iomem *port_mmio = ahci_port_base(ap);
1276 struct ata_taskfile tf;
1277 u32 tmp;
1278
1279 tmp = readl(port_mmio + PORT_SIG);
1280 tf.lbah = (tmp >> 24) & 0xff;
1281 tf.lbam = (tmp >> 16) & 0xff;
1282 tf.lbal = (tmp >> 8) & 0xff;
1283 tf.nsect = (tmp) & 0xff;
1284
1285 return ata_dev_classify(&tf);
1286 }
1287 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1288
1289 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1290 u32 opts)
1291 {
1292 dma_addr_t cmd_tbl_dma;
1293
1294 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1295
1296 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1297 pp->cmd_slot[tag].status = 0;
1298 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1299 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1300 }
1301 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1302
1303 int ahci_kick_engine(struct ata_port *ap)
1304 {
1305 void __iomem *port_mmio = ahci_port_base(ap);
1306 struct ahci_host_priv *hpriv = ap->host->private_data;
1307 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1308 u32 tmp;
1309 int busy, rc;
1310
1311 /* stop engine */
1312 rc = hpriv->stop_engine(ap);
1313 if (rc)
1314 goto out_restart;
1315
1316 /* need to do CLO?
1317 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1318 */
1319 busy = status & (ATA_BUSY | ATA_DRQ);
1320 if (!busy && !sata_pmp_attached(ap)) {
1321 rc = 0;
1322 goto out_restart;
1323 }
1324
1325 if (!(hpriv->cap & HOST_CAP_CLO)) {
1326 rc = -EOPNOTSUPP;
1327 goto out_restart;
1328 }
1329
1330 /* perform CLO */
1331 tmp = readl(port_mmio + PORT_CMD);
1332 tmp |= PORT_CMD_CLO;
1333 writel(tmp, port_mmio + PORT_CMD);
1334
1335 rc = 0;
1336 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1337 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1338 if (tmp & PORT_CMD_CLO)
1339 rc = -EIO;
1340
1341 /* restart engine */
1342 out_restart:
1343 hpriv->start_engine(ap);
1344 return rc;
1345 }
1346 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1347
1348 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1349 struct ata_taskfile *tf, int is_cmd, u16 flags,
1350 unsigned long timeout_msec)
1351 {
1352 const u32 cmd_fis_len = 5; /* five dwords */
1353 struct ahci_port_priv *pp = ap->private_data;
1354 void __iomem *port_mmio = ahci_port_base(ap);
1355 u8 *fis = pp->cmd_tbl;
1356 u32 tmp;
1357
1358 /* prep the command */
1359 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1360 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1361
1362 /* set port value for softreset of Port Multiplier */
1363 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1364 tmp = readl(port_mmio + PORT_FBS);
1365 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1366 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1367 writel(tmp, port_mmio + PORT_FBS);
1368 pp->fbs_last_dev = pmp;
1369 }
1370
1371 /* issue & wait */
1372 writel(1, port_mmio + PORT_CMD_ISSUE);
1373
1374 if (timeout_msec) {
1375 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1376 0x1, 0x1, 1, timeout_msec);
1377 if (tmp & 0x1) {
1378 ahci_kick_engine(ap);
1379 return -EBUSY;
1380 }
1381 } else
1382 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1383
1384 return 0;
1385 }
1386
1387 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1388 int pmp, unsigned long deadline,
1389 int (*check_ready)(struct ata_link *link))
1390 {
1391 struct ata_port *ap = link->ap;
1392 struct ahci_host_priv *hpriv = ap->host->private_data;
1393 struct ahci_port_priv *pp = ap->private_data;
1394 const char *reason = NULL;
1395 unsigned long now, msecs;
1396 struct ata_taskfile tf;
1397 bool fbs_disabled = false;
1398 int rc;
1399
1400 DPRINTK("ENTER\n");
1401
1402 /* prepare for SRST (AHCI-1.1 10.4.1) */
1403 rc = ahci_kick_engine(ap);
1404 if (rc && rc != -EOPNOTSUPP)
1405 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1406
1407 /*
1408 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1409 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1410 * that is attached to port multiplier.
1411 */
1412 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1413 ahci_disable_fbs(ap);
1414 fbs_disabled = true;
1415 }
1416
1417 ata_tf_init(link->device, &tf);
1418
1419 /* issue the first H2D Register FIS */
1420 msecs = 0;
1421 now = jiffies;
1422 if (time_after(deadline, now))
1423 msecs = jiffies_to_msecs(deadline - now);
1424
1425 tf.ctl |= ATA_SRST;
1426 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1427 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1428 rc = -EIO;
1429 reason = "1st FIS failed";
1430 goto fail;
1431 }
1432
1433 /* spec says at least 5us, but be generous and sleep for 1ms */
1434 ata_msleep(ap, 1);
1435
1436 /* issue the second H2D Register FIS */
1437 tf.ctl &= ~ATA_SRST;
1438 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1439
1440 /* wait for link to become ready */
1441 rc = ata_wait_after_reset(link, deadline, check_ready);
1442 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1443 /*
1444 * Workaround for cases where link online status can't
1445 * be trusted. Treat device readiness timeout as link
1446 * offline.
1447 */
1448 ata_link_info(link, "device not ready, treating as offline\n");
1449 *class = ATA_DEV_NONE;
1450 } else if (rc) {
1451 /* link occupied, -ENODEV too is an error */
1452 reason = "device not ready";
1453 goto fail;
1454 } else
1455 *class = ahci_dev_classify(ap);
1456
1457 /* re-enable FBS if disabled before */
1458 if (fbs_disabled)
1459 ahci_enable_fbs(ap);
1460
1461 DPRINTK("EXIT, class=%u\n", *class);
1462 return 0;
1463
1464 fail:
1465 ata_link_err(link, "softreset failed (%s)\n", reason);
1466 return rc;
1467 }
1468
1469 int ahci_check_ready(struct ata_link *link)
1470 {
1471 void __iomem *port_mmio = ahci_port_base(link->ap);
1472 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1473
1474 return ata_check_ready(status);
1475 }
1476 EXPORT_SYMBOL_GPL(ahci_check_ready);
1477
1478 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1479 unsigned long deadline)
1480 {
1481 int pmp = sata_srst_pmp(link);
1482
1483 DPRINTK("ENTER\n");
1484
1485 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1486 }
1487 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1488
1489 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1490 {
1491 void __iomem *port_mmio = ahci_port_base(link->ap);
1492 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1493 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1494
1495 /*
1496 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1497 * which can save timeout delay.
1498 */
1499 if (irq_status & PORT_IRQ_BAD_PMP)
1500 return -EIO;
1501
1502 return ata_check_ready(status);
1503 }
1504
1505 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1506 unsigned long deadline)
1507 {
1508 struct ata_port *ap = link->ap;
1509 void __iomem *port_mmio = ahci_port_base(ap);
1510 int pmp = sata_srst_pmp(link);
1511 int rc;
1512 u32 irq_sts;
1513
1514 DPRINTK("ENTER\n");
1515
1516 rc = ahci_do_softreset(link, class, pmp, deadline,
1517 ahci_bad_pmp_check_ready);
1518
1519 /*
1520 * Soft reset fails with IPMS set when PMP is enabled but
1521 * SATA HDD/ODD is connected to SATA port, do soft reset
1522 * again to port 0.
1523 */
1524 if (rc == -EIO) {
1525 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1526 if (irq_sts & PORT_IRQ_BAD_PMP) {
1527 ata_link_warn(link,
1528 "applying PMP SRST workaround "
1529 "and retrying\n");
1530 rc = ahci_do_softreset(link, class, 0, deadline,
1531 ahci_check_ready);
1532 }
1533 }
1534
1535 return rc;
1536 }
1537
1538 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1539 unsigned long deadline, bool *online)
1540 {
1541 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1542 struct ata_port *ap = link->ap;
1543 struct ahci_port_priv *pp = ap->private_data;
1544 struct ahci_host_priv *hpriv = ap->host->private_data;
1545 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1546 struct ata_taskfile tf;
1547 int rc;
1548
1549 DPRINTK("ENTER\n");
1550
1551 hpriv->stop_engine(ap);
1552
1553 /* clear D2H reception area to properly wait for D2H FIS */
1554 ata_tf_init(link->device, &tf);
1555 tf.command = ATA_BUSY;
1556 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1557
1558 rc = sata_link_hardreset(link, timing, deadline, online,
1559 ahci_check_ready);
1560
1561 hpriv->start_engine(ap);
1562
1563 if (*online)
1564 *class = ahci_dev_classify(ap);
1565
1566 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1567 return rc;
1568 }
1569 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1570
1571 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1572 unsigned long deadline)
1573 {
1574 bool online;
1575
1576 return ahci_do_hardreset(link, class, deadline, &online);
1577 }
1578
1579 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1580 {
1581 struct ata_port *ap = link->ap;
1582 void __iomem *port_mmio = ahci_port_base(ap);
1583 u32 new_tmp, tmp;
1584
1585 ata_std_postreset(link, class);
1586
1587 /* Make sure port's ATAPI bit is set appropriately */
1588 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1589 if (*class == ATA_DEV_ATAPI)
1590 new_tmp |= PORT_CMD_ATAPI;
1591 else
1592 new_tmp &= ~PORT_CMD_ATAPI;
1593 if (new_tmp != tmp) {
1594 writel(new_tmp, port_mmio + PORT_CMD);
1595 readl(port_mmio + PORT_CMD); /* flush */
1596 }
1597 }
1598
1599 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1600 {
1601 struct scatterlist *sg;
1602 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1603 unsigned int si;
1604
1605 VPRINTK("ENTER\n");
1606
1607 /*
1608 * Next, the S/G list.
1609 */
1610 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1611 dma_addr_t addr = sg_dma_address(sg);
1612 u32 sg_len = sg_dma_len(sg);
1613
1614 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1615 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1616 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1617 }
1618
1619 return si;
1620 }
1621
1622 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1623 {
1624 struct ata_port *ap = qc->ap;
1625 struct ahci_port_priv *pp = ap->private_data;
1626
1627 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1628 return ata_std_qc_defer(qc);
1629 else
1630 return sata_pmp_qc_defer_cmd_switch(qc);
1631 }
1632
1633 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1634 {
1635 struct ata_port *ap = qc->ap;
1636 struct ahci_port_priv *pp = ap->private_data;
1637 int is_atapi = ata_is_atapi(qc->tf.protocol);
1638 void *cmd_tbl;
1639 u32 opts;
1640 const u32 cmd_fis_len = 5; /* five dwords */
1641 unsigned int n_elem;
1642
1643 /*
1644 * Fill in command table information. First, the header,
1645 * a SATA Register - Host to Device command FIS.
1646 */
1647 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1648
1649 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1650 if (is_atapi) {
1651 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1652 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1653 }
1654
1655 n_elem = 0;
1656 if (qc->flags & ATA_QCFLAG_DMAMAP)
1657 n_elem = ahci_fill_sg(qc, cmd_tbl);
1658
1659 /*
1660 * Fill in command slot information.
1661 */
1662 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1663 if (qc->tf.flags & ATA_TFLAG_WRITE)
1664 opts |= AHCI_CMD_WRITE;
1665 if (is_atapi)
1666 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1667
1668 ahci_fill_cmd_slot(pp, qc->tag, opts);
1669 }
1670
1671 static void ahci_fbs_dec_intr(struct ata_port *ap)
1672 {
1673 struct ahci_port_priv *pp = ap->private_data;
1674 void __iomem *port_mmio = ahci_port_base(ap);
1675 u32 fbs = readl(port_mmio + PORT_FBS);
1676 int retries = 3;
1677
1678 DPRINTK("ENTER\n");
1679 BUG_ON(!pp->fbs_enabled);
1680
1681 /* time to wait for DEC is not specified by AHCI spec,
1682 * add a retry loop for safety.
1683 */
1684 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1685 fbs = readl(port_mmio + PORT_FBS);
1686 while ((fbs & PORT_FBS_DEC) && retries--) {
1687 udelay(1);
1688 fbs = readl(port_mmio + PORT_FBS);
1689 }
1690
1691 if (fbs & PORT_FBS_DEC)
1692 dev_err(ap->host->dev, "failed to clear device error\n");
1693 }
1694
1695 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1696 {
1697 struct ahci_host_priv *hpriv = ap->host->private_data;
1698 struct ahci_port_priv *pp = ap->private_data;
1699 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1700 struct ata_link *link = NULL;
1701 struct ata_queued_cmd *active_qc;
1702 struct ata_eh_info *active_ehi;
1703 bool fbs_need_dec = false;
1704 u32 serror;
1705
1706 /* determine active link with error */
1707 if (pp->fbs_enabled) {
1708 void __iomem *port_mmio = ahci_port_base(ap);
1709 u32 fbs = readl(port_mmio + PORT_FBS);
1710 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1711
1712 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1713 link = &ap->pmp_link[pmp];
1714 fbs_need_dec = true;
1715 }
1716
1717 } else
1718 ata_for_each_link(link, ap, EDGE)
1719 if (ata_link_active(link))
1720 break;
1721
1722 if (!link)
1723 link = &ap->link;
1724
1725 active_qc = ata_qc_from_tag(ap, link->active_tag);
1726 active_ehi = &link->eh_info;
1727
1728 /* record irq stat */
1729 ata_ehi_clear_desc(host_ehi);
1730 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1731
1732 /* AHCI needs SError cleared; otherwise, it might lock up */
1733 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1734 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1735 host_ehi->serror |= serror;
1736
1737 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1738 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1739 irq_stat &= ~PORT_IRQ_IF_ERR;
1740
1741 if (irq_stat & PORT_IRQ_TF_ERR) {
1742 /* If qc is active, charge it; otherwise, the active
1743 * link. There's no active qc on NCQ errors. It will
1744 * be determined by EH by reading log page 10h.
1745 */
1746 if (active_qc)
1747 active_qc->err_mask |= AC_ERR_DEV;
1748 else
1749 active_ehi->err_mask |= AC_ERR_DEV;
1750
1751 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1752 host_ehi->serror &= ~SERR_INTERNAL;
1753 }
1754
1755 if (irq_stat & PORT_IRQ_UNK_FIS) {
1756 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1757
1758 active_ehi->err_mask |= AC_ERR_HSM;
1759 active_ehi->action |= ATA_EH_RESET;
1760 ata_ehi_push_desc(active_ehi,
1761 "unknown FIS %08x %08x %08x %08x" ,
1762 unk[0], unk[1], unk[2], unk[3]);
1763 }
1764
1765 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1766 active_ehi->err_mask |= AC_ERR_HSM;
1767 active_ehi->action |= ATA_EH_RESET;
1768 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1769 }
1770
1771 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1772 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1773 host_ehi->action |= ATA_EH_RESET;
1774 ata_ehi_push_desc(host_ehi, "host bus error");
1775 }
1776
1777 if (irq_stat & PORT_IRQ_IF_ERR) {
1778 if (fbs_need_dec)
1779 active_ehi->err_mask |= AC_ERR_DEV;
1780 else {
1781 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1782 host_ehi->action |= ATA_EH_RESET;
1783 }
1784
1785 ata_ehi_push_desc(host_ehi, "interface fatal error");
1786 }
1787
1788 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1789 ata_ehi_hotplugged(host_ehi);
1790 ata_ehi_push_desc(host_ehi, "%s",
1791 irq_stat & PORT_IRQ_CONNECT ?
1792 "connection status changed" : "PHY RDY changed");
1793 }
1794
1795 /* okay, let's hand over to EH */
1796
1797 if (irq_stat & PORT_IRQ_FREEZE)
1798 ata_port_freeze(ap);
1799 else if (fbs_need_dec) {
1800 ata_link_abort(link);
1801 ahci_fbs_dec_intr(ap);
1802 } else
1803 ata_port_abort(ap);
1804 }
1805
1806 static void ahci_handle_port_interrupt(struct ata_port *ap,
1807 void __iomem *port_mmio, u32 status)
1808 {
1809 struct ata_eh_info *ehi = &ap->link.eh_info;
1810 struct ahci_port_priv *pp = ap->private_data;
1811 struct ahci_host_priv *hpriv = ap->host->private_data;
1812 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1813 u32 qc_active = 0;
1814 int rc;
1815
1816 /* ignore BAD_PMP while resetting */
1817 if (unlikely(resetting))
1818 status &= ~PORT_IRQ_BAD_PMP;
1819
1820 if (sata_lpm_ignore_phy_events(&ap->link)) {
1821 status &= ~PORT_IRQ_PHYRDY;
1822 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1823 }
1824
1825 if (unlikely(status & PORT_IRQ_ERROR)) {
1826 ahci_error_intr(ap, status);
1827 return;
1828 }
1829
1830 if (status & PORT_IRQ_SDB_FIS) {
1831 /* If SNotification is available, leave notification
1832 * handling to sata_async_notification(). If not,
1833 * emulate it by snooping SDB FIS RX area.
1834 *
1835 * Snooping FIS RX area is probably cheaper than
1836 * poking SNotification but some constrollers which
1837 * implement SNotification, ICH9 for example, don't
1838 * store AN SDB FIS into receive area.
1839 */
1840 if (hpriv->cap & HOST_CAP_SNTF)
1841 sata_async_notification(ap);
1842 else {
1843 /* If the 'N' bit in word 0 of the FIS is set,
1844 * we just received asynchronous notification.
1845 * Tell libata about it.
1846 *
1847 * Lack of SNotification should not appear in
1848 * ahci 1.2, so the workaround is unnecessary
1849 * when FBS is enabled.
1850 */
1851 if (pp->fbs_enabled)
1852 WARN_ON_ONCE(1);
1853 else {
1854 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1855 u32 f0 = le32_to_cpu(f[0]);
1856 if (f0 & (1 << 15))
1857 sata_async_notification(ap);
1858 }
1859 }
1860 }
1861
1862 /* pp->active_link is not reliable once FBS is enabled, both
1863 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1864 * NCQ and non-NCQ commands may be in flight at the same time.
1865 */
1866 if (pp->fbs_enabled) {
1867 if (ap->qc_active) {
1868 qc_active = readl(port_mmio + PORT_SCR_ACT);
1869 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1870 }
1871 } else {
1872 /* pp->active_link is valid iff any command is in flight */
1873 if (ap->qc_active && pp->active_link->sactive)
1874 qc_active = readl(port_mmio + PORT_SCR_ACT);
1875 else
1876 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1877 }
1878
1879
1880 rc = ata_qc_complete_multiple(ap, qc_active);
1881
1882 /* while resetting, invalid completions are expected */
1883 if (unlikely(rc < 0 && !resetting)) {
1884 ehi->err_mask |= AC_ERR_HSM;
1885 ehi->action |= ATA_EH_RESET;
1886 ata_port_freeze(ap);
1887 }
1888 }
1889
1890 static void ahci_port_intr(struct ata_port *ap)
1891 {
1892 void __iomem *port_mmio = ahci_port_base(ap);
1893 u32 status;
1894
1895 status = readl(port_mmio + PORT_IRQ_STAT);
1896 writel(status, port_mmio + PORT_IRQ_STAT);
1897
1898 ahci_handle_port_interrupt(ap, port_mmio, status);
1899 }
1900
1901 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1902 {
1903 struct ata_port *ap = dev_instance;
1904 void __iomem *port_mmio = ahci_port_base(ap);
1905 u32 status;
1906
1907 VPRINTK("ENTER\n");
1908
1909 status = readl(port_mmio + PORT_IRQ_STAT);
1910 writel(status, port_mmio + PORT_IRQ_STAT);
1911
1912 spin_lock(ap->lock);
1913 ahci_handle_port_interrupt(ap, port_mmio, status);
1914 spin_unlock(ap->lock);
1915
1916 VPRINTK("EXIT\n");
1917
1918 return IRQ_HANDLED;
1919 }
1920
1921 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1922 {
1923 unsigned int i, handled = 0;
1924
1925 for (i = 0; i < host->n_ports; i++) {
1926 struct ata_port *ap;
1927
1928 if (!(irq_masked & (1 << i)))
1929 continue;
1930
1931 ap = host->ports[i];
1932 if (ap) {
1933 ahci_port_intr(ap);
1934 VPRINTK("port %u\n", i);
1935 } else {
1936 VPRINTK("port %u (no irq)\n", i);
1937 if (ata_ratelimit())
1938 dev_warn(host->dev,
1939 "interrupt on disabled port %u\n", i);
1940 }
1941
1942 handled = 1;
1943 }
1944
1945 return handled;
1946 }
1947 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1948
1949 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1950 {
1951 struct ata_host *host = dev_instance;
1952 struct ahci_host_priv *hpriv;
1953 unsigned int rc = 0;
1954 void __iomem *mmio;
1955 u32 irq_stat, irq_masked;
1956
1957 VPRINTK("ENTER\n");
1958
1959 hpriv = host->private_data;
1960 mmio = hpriv->mmio;
1961
1962 /* sigh. 0xffffffff is a valid return from h/w */
1963 irq_stat = readl(mmio + HOST_IRQ_STAT);
1964 if (!irq_stat)
1965 return IRQ_NONE;
1966
1967 irq_masked = irq_stat & hpriv->port_map;
1968
1969 spin_lock(&host->lock);
1970
1971 rc = ahci_handle_port_intr(host, irq_masked);
1972
1973 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1974 * it should be cleared after all the port events are cleared;
1975 * otherwise, it will raise a spurious interrupt after each
1976 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1977 * information.
1978 *
1979 * Also, use the unmasked value to clear interrupt as spurious
1980 * pending event on a dummy port might cause screaming IRQ.
1981 */
1982 writel(irq_stat, mmio + HOST_IRQ_STAT);
1983
1984 spin_unlock(&host->lock);
1985
1986 VPRINTK("EXIT\n");
1987
1988 return IRQ_RETVAL(rc);
1989 }
1990
1991 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1992 {
1993 struct ata_port *ap = qc->ap;
1994 void __iomem *port_mmio = ahci_port_base(ap);
1995 struct ahci_port_priv *pp = ap->private_data;
1996
1997 /* Keep track of the currently active link. It will be used
1998 * in completion path to determine whether NCQ phase is in
1999 * progress.
2000 */
2001 pp->active_link = qc->dev->link;
2002
2003 if (ata_is_ncq(qc->tf.protocol))
2004 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2005
2006 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2007 u32 fbs = readl(port_mmio + PORT_FBS);
2008 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2009 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2010 writel(fbs, port_mmio + PORT_FBS);
2011 pp->fbs_last_dev = qc->dev->link->pmp;
2012 }
2013
2014 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2015
2016 ahci_sw_activity(qc->dev->link);
2017
2018 return 0;
2019 }
2020 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2021
2022 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2023 {
2024 struct ahci_port_priv *pp = qc->ap->private_data;
2025 u8 *rx_fis = pp->rx_fis;
2026
2027 if (pp->fbs_enabled)
2028 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2029
2030 /*
2031 * After a successful execution of an ATA PIO data-in command,
2032 * the device doesn't send D2H Reg FIS to update the TF and
2033 * the host should take TF and E_Status from the preceding PIO
2034 * Setup FIS.
2035 */
2036 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2037 !(qc->flags & ATA_QCFLAG_FAILED)) {
2038 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2039 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2040 } else
2041 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2042
2043 return true;
2044 }
2045
2046 static void ahci_freeze(struct ata_port *ap)
2047 {
2048 void __iomem *port_mmio = ahci_port_base(ap);
2049
2050 /* turn IRQ off */
2051 writel(0, port_mmio + PORT_IRQ_MASK);
2052 }
2053
2054 static void ahci_thaw(struct ata_port *ap)
2055 {
2056 struct ahci_host_priv *hpriv = ap->host->private_data;
2057 void __iomem *mmio = hpriv->mmio;
2058 void __iomem *port_mmio = ahci_port_base(ap);
2059 u32 tmp;
2060 struct ahci_port_priv *pp = ap->private_data;
2061
2062 /* clear IRQ */
2063 tmp = readl(port_mmio + PORT_IRQ_STAT);
2064 writel(tmp, port_mmio + PORT_IRQ_STAT);
2065 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2066
2067 /* turn IRQ back on */
2068 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2069 }
2070
2071 void ahci_error_handler(struct ata_port *ap)
2072 {
2073 struct ahci_host_priv *hpriv = ap->host->private_data;
2074
2075 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2076 /* restart engine */
2077 hpriv->stop_engine(ap);
2078 hpriv->start_engine(ap);
2079 }
2080
2081 sata_pmp_error_handler(ap);
2082
2083 if (!ata_dev_enabled(ap->link.device))
2084 hpriv->stop_engine(ap);
2085 }
2086 EXPORT_SYMBOL_GPL(ahci_error_handler);
2087
2088 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2089 {
2090 struct ata_port *ap = qc->ap;
2091
2092 /* make DMA engine forget about the failed command */
2093 if (qc->flags & ATA_QCFLAG_FAILED)
2094 ahci_kick_engine(ap);
2095 }
2096
2097 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2098 {
2099 struct ahci_host_priv *hpriv = ap->host->private_data;
2100 void __iomem *port_mmio = ahci_port_base(ap);
2101 struct ata_device *dev = ap->link.device;
2102 u32 devslp, dm, dito, mdat, deto, dito_conf;
2103 int rc;
2104 unsigned int err_mask;
2105
2106 devslp = readl(port_mmio + PORT_DEVSLP);
2107 if (!(devslp & PORT_DEVSLP_DSP)) {
2108 dev_info(ap->host->dev, "port does not support device sleep\n");
2109 return;
2110 }
2111
2112 /* disable device sleep */
2113 if (!sleep) {
2114 if (devslp & PORT_DEVSLP_ADSE) {
2115 writel(devslp & ~PORT_DEVSLP_ADSE,
2116 port_mmio + PORT_DEVSLP);
2117 err_mask = ata_dev_set_feature(dev,
2118 SETFEATURES_SATA_DISABLE,
2119 SATA_DEVSLP);
2120 if (err_mask && err_mask != AC_ERR_DEV)
2121 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2122 }
2123 return;
2124 }
2125
2126 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2127 dito = devslp_idle_timeout / (dm + 1);
2128 if (dito > 0x3ff)
2129 dito = 0x3ff;
2130
2131 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2132
2133 /* device sleep was already enabled and same dito */
2134 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2135 return;
2136
2137 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2138 rc = hpriv->stop_engine(ap);
2139 if (rc)
2140 return;
2141
2142 /* Use the nominal value 10 ms if the read MDAT is zero,
2143 * the nominal value of DETO is 20 ms.
2144 */
2145 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2146 ATA_LOG_DEVSLP_VALID_MASK) {
2147 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2148 ATA_LOG_DEVSLP_MDAT_MASK;
2149 if (!mdat)
2150 mdat = 10;
2151 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2152 if (!deto)
2153 deto = 20;
2154 } else {
2155 mdat = 10;
2156 deto = 20;
2157 }
2158
2159 /* Make dito, mdat, deto bits to 0s */
2160 devslp &= ~GENMASK_ULL(24, 2);
2161 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2162 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2163 (deto << PORT_DEVSLP_DETO_OFFSET) |
2164 PORT_DEVSLP_ADSE);
2165 writel(devslp, port_mmio + PORT_DEVSLP);
2166
2167 hpriv->start_engine(ap);
2168
2169 /* enable device sleep feature for the drive */
2170 err_mask = ata_dev_set_feature(dev,
2171 SETFEATURES_SATA_ENABLE,
2172 SATA_DEVSLP);
2173 if (err_mask && err_mask != AC_ERR_DEV)
2174 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2175 }
2176
2177 static void ahci_enable_fbs(struct ata_port *ap)
2178 {
2179 struct ahci_host_priv *hpriv = ap->host->private_data;
2180 struct ahci_port_priv *pp = ap->private_data;
2181 void __iomem *port_mmio = ahci_port_base(ap);
2182 u32 fbs;
2183 int rc;
2184
2185 if (!pp->fbs_supported)
2186 return;
2187
2188 fbs = readl(port_mmio + PORT_FBS);
2189 if (fbs & PORT_FBS_EN) {
2190 pp->fbs_enabled = true;
2191 pp->fbs_last_dev = -1; /* initialization */
2192 return;
2193 }
2194
2195 rc = hpriv->stop_engine(ap);
2196 if (rc)
2197 return;
2198
2199 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2200 fbs = readl(port_mmio + PORT_FBS);
2201 if (fbs & PORT_FBS_EN) {
2202 dev_info(ap->host->dev, "FBS is enabled\n");
2203 pp->fbs_enabled = true;
2204 pp->fbs_last_dev = -1; /* initialization */
2205 } else
2206 dev_err(ap->host->dev, "Failed to enable FBS\n");
2207
2208 hpriv->start_engine(ap);
2209 }
2210
2211 static void ahci_disable_fbs(struct ata_port *ap)
2212 {
2213 struct ahci_host_priv *hpriv = ap->host->private_data;
2214 struct ahci_port_priv *pp = ap->private_data;
2215 void __iomem *port_mmio = ahci_port_base(ap);
2216 u32 fbs;
2217 int rc;
2218
2219 if (!pp->fbs_supported)
2220 return;
2221
2222 fbs = readl(port_mmio + PORT_FBS);
2223 if ((fbs & PORT_FBS_EN) == 0) {
2224 pp->fbs_enabled = false;
2225 return;
2226 }
2227
2228 rc = hpriv->stop_engine(ap);
2229 if (rc)
2230 return;
2231
2232 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2233 fbs = readl(port_mmio + PORT_FBS);
2234 if (fbs & PORT_FBS_EN)
2235 dev_err(ap->host->dev, "Failed to disable FBS\n");
2236 else {
2237 dev_info(ap->host->dev, "FBS is disabled\n");
2238 pp->fbs_enabled = false;
2239 }
2240
2241 hpriv->start_engine(ap);
2242 }
2243
2244 static void ahci_pmp_attach(struct ata_port *ap)
2245 {
2246 void __iomem *port_mmio = ahci_port_base(ap);
2247 struct ahci_port_priv *pp = ap->private_data;
2248 u32 cmd;
2249
2250 cmd = readl(port_mmio + PORT_CMD);
2251 cmd |= PORT_CMD_PMP;
2252 writel(cmd, port_mmio + PORT_CMD);
2253
2254 ahci_enable_fbs(ap);
2255
2256 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2257
2258 /*
2259 * We must not change the port interrupt mask register if the
2260 * port is marked frozen, the value in pp->intr_mask will be
2261 * restored later when the port is thawed.
2262 *
2263 * Note that during initialization, the port is marked as
2264 * frozen since the irq handler is not yet registered.
2265 */
2266 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2267 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2268 }
2269
2270 static void ahci_pmp_detach(struct ata_port *ap)
2271 {
2272 void __iomem *port_mmio = ahci_port_base(ap);
2273 struct ahci_port_priv *pp = ap->private_data;
2274 u32 cmd;
2275
2276 ahci_disable_fbs(ap);
2277
2278 cmd = readl(port_mmio + PORT_CMD);
2279 cmd &= ~PORT_CMD_PMP;
2280 writel(cmd, port_mmio + PORT_CMD);
2281
2282 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2283
2284 /* see comment above in ahci_pmp_attach() */
2285 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2286 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2287 }
2288
2289 int ahci_port_resume(struct ata_port *ap)
2290 {
2291 ahci_rpm_get_port(ap);
2292
2293 ahci_power_up(ap);
2294 ahci_start_port(ap);
2295
2296 if (sata_pmp_attached(ap))
2297 ahci_pmp_attach(ap);
2298 else
2299 ahci_pmp_detach(ap);
2300
2301 return 0;
2302 }
2303 EXPORT_SYMBOL_GPL(ahci_port_resume);
2304
2305 #ifdef CONFIG_PM
2306 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2307 {
2308 const char *emsg = NULL;
2309 int rc;
2310
2311 rc = ahci_deinit_port(ap, &emsg);
2312 if (rc == 0)
2313 ahci_power_down(ap);
2314 else {
2315 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2316 ata_port_freeze(ap);
2317 }
2318
2319 ahci_rpm_put_port(ap);
2320 return rc;
2321 }
2322 #endif
2323
2324 static int ahci_port_start(struct ata_port *ap)
2325 {
2326 struct ahci_host_priv *hpriv = ap->host->private_data;
2327 struct device *dev = ap->host->dev;
2328 struct ahci_port_priv *pp;
2329 void *mem;
2330 dma_addr_t mem_dma;
2331 size_t dma_sz, rx_fis_sz;
2332
2333 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2334 if (!pp)
2335 return -ENOMEM;
2336
2337 if (ap->host->n_ports > 1) {
2338 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2339 if (!pp->irq_desc) {
2340 devm_kfree(dev, pp);
2341 return -ENOMEM;
2342 }
2343 snprintf(pp->irq_desc, 8,
2344 "%s%d", dev_driver_string(dev), ap->port_no);
2345 }
2346
2347 /* check FBS capability */
2348 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2349 void __iomem *port_mmio = ahci_port_base(ap);
2350 u32 cmd = readl(port_mmio + PORT_CMD);
2351 if (cmd & PORT_CMD_FBSCP)
2352 pp->fbs_supported = true;
2353 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2354 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2355 ap->port_no);
2356 pp->fbs_supported = true;
2357 } else
2358 dev_warn(dev, "port %d is not capable of FBS\n",
2359 ap->port_no);
2360 }
2361
2362 if (pp->fbs_supported) {
2363 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2364 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2365 } else {
2366 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2367 rx_fis_sz = AHCI_RX_FIS_SZ;
2368 }
2369
2370 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2371 if (!mem)
2372 return -ENOMEM;
2373 memset(mem, 0, dma_sz);
2374
2375 /*
2376 * First item in chunk of DMA memory: 32-slot command table,
2377 * 32 bytes each in size
2378 */
2379 pp->cmd_slot = mem;
2380 pp->cmd_slot_dma = mem_dma;
2381
2382 mem += AHCI_CMD_SLOT_SZ;
2383 mem_dma += AHCI_CMD_SLOT_SZ;
2384
2385 /*
2386 * Second item: Received-FIS area
2387 */
2388 pp->rx_fis = mem;
2389 pp->rx_fis_dma = mem_dma;
2390
2391 mem += rx_fis_sz;
2392 mem_dma += rx_fis_sz;
2393
2394 /*
2395 * Third item: data area for storing a single command
2396 * and its scatter-gather table
2397 */
2398 pp->cmd_tbl = mem;
2399 pp->cmd_tbl_dma = mem_dma;
2400
2401 /*
2402 * Save off initial list of interrupts to be enabled.
2403 * This could be changed later
2404 */
2405 pp->intr_mask = DEF_PORT_IRQ;
2406
2407 /*
2408 * Switch to per-port locking in case each port has its own MSI vector.
2409 */
2410 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2411 spin_lock_init(&pp->lock);
2412 ap->lock = &pp->lock;
2413 }
2414
2415 ap->private_data = pp;
2416
2417 /* engage engines, captain */
2418 return ahci_port_resume(ap);
2419 }
2420
2421 static void ahci_port_stop(struct ata_port *ap)
2422 {
2423 const char *emsg = NULL;
2424 struct ahci_host_priv *hpriv = ap->host->private_data;
2425 void __iomem *host_mmio = hpriv->mmio;
2426 int rc;
2427
2428 /* de-initialize port */
2429 rc = ahci_deinit_port(ap, &emsg);
2430 if (rc)
2431 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2432
2433 /*
2434 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2435 * re-enabling INTx.
2436 */
2437 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2438 }
2439
2440 void ahci_print_info(struct ata_host *host, const char *scc_s)
2441 {
2442 struct ahci_host_priv *hpriv = host->private_data;
2443 u32 vers, cap, cap2, impl, speed;
2444 const char *speed_s;
2445
2446 vers = hpriv->version;
2447 cap = hpriv->cap;
2448 cap2 = hpriv->cap2;
2449 impl = hpriv->port_map;
2450
2451 speed = (cap >> 20) & 0xf;
2452 if (speed == 1)
2453 speed_s = "1.5";
2454 else if (speed == 2)
2455 speed_s = "3";
2456 else if (speed == 3)
2457 speed_s = "6";
2458 else
2459 speed_s = "?";
2460
2461 dev_info(host->dev,
2462 "AHCI %02x%02x.%02x%02x "
2463 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2464 ,
2465
2466 (vers >> 24) & 0xff,
2467 (vers >> 16) & 0xff,
2468 (vers >> 8) & 0xff,
2469 vers & 0xff,
2470
2471 ((cap >> 8) & 0x1f) + 1,
2472 (cap & 0x1f) + 1,
2473 speed_s,
2474 impl,
2475 scc_s);
2476
2477 dev_info(host->dev,
2478 "flags: "
2479 "%s%s%s%s%s%s%s"
2480 "%s%s%s%s%s%s%s"
2481 "%s%s%s%s%s%s%s"
2482 "%s%s\n"
2483 ,
2484
2485 cap & HOST_CAP_64 ? "64bit " : "",
2486 cap & HOST_CAP_NCQ ? "ncq " : "",
2487 cap & HOST_CAP_SNTF ? "sntf " : "",
2488 cap & HOST_CAP_MPS ? "ilck " : "",
2489 cap & HOST_CAP_SSS ? "stag " : "",
2490 cap & HOST_CAP_ALPM ? "pm " : "",
2491 cap & HOST_CAP_LED ? "led " : "",
2492 cap & HOST_CAP_CLO ? "clo " : "",
2493 cap & HOST_CAP_ONLY ? "only " : "",
2494 cap & HOST_CAP_PMP ? "pmp " : "",
2495 cap & HOST_CAP_FBS ? "fbs " : "",
2496 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2497 cap & HOST_CAP_SSC ? "slum " : "",
2498 cap & HOST_CAP_PART ? "part " : "",
2499 cap & HOST_CAP_CCC ? "ccc " : "",
2500 cap & HOST_CAP_EMS ? "ems " : "",
2501 cap & HOST_CAP_SXS ? "sxs " : "",
2502 cap2 & HOST_CAP2_DESO ? "deso " : "",
2503 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2504 cap2 & HOST_CAP2_SDS ? "sds " : "",
2505 cap2 & HOST_CAP2_APST ? "apst " : "",
2506 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2507 cap2 & HOST_CAP2_BOH ? "boh " : ""
2508 );
2509 }
2510 EXPORT_SYMBOL_GPL(ahci_print_info);
2511
2512 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2513 struct ata_port_info *pi)
2514 {
2515 u8 messages;
2516 void __iomem *mmio = hpriv->mmio;
2517 u32 em_loc = readl(mmio + HOST_EM_LOC);
2518 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2519
2520 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2521 return;
2522
2523 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2524
2525 if (messages) {
2526 /* store em_loc */
2527 hpriv->em_loc = ((em_loc >> 16) * 4);
2528 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2529 hpriv->em_msg_type = messages;
2530 pi->flags |= ATA_FLAG_EM;
2531 if (!(em_ctl & EM_CTL_ALHD))
2532 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2533 }
2534 }
2535 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2536
2537 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2538 struct scsi_host_template *sht)
2539 {
2540 struct ahci_host_priv *hpriv = host->private_data;
2541 int i, rc;
2542
2543 rc = ata_host_start(host);
2544 if (rc)
2545 return rc;
2546 /*
2547 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2548 * allocated. That is one MSI per port, starting from @irq.
2549 */
2550 for (i = 0; i < host->n_ports; i++) {
2551 struct ahci_port_priv *pp = host->ports[i]->private_data;
2552 int irq = hpriv->get_irq_vector(host, i);
2553
2554 /* Do not receive interrupts sent by dummy ports */
2555 if (!pp) {
2556 disable_irq(irq);
2557 continue;
2558 }
2559
2560 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2561 0, pp->irq_desc, host->ports[i]);
2562
2563 if (rc)
2564 return rc;
2565 ata_port_desc(host->ports[i], "irq %d", irq);
2566 }
2567
2568 return ata_host_register(host, sht);
2569 }
2570
2571 /**
2572 * ahci_host_activate - start AHCI host, request IRQs and register it
2573 * @host: target ATA host
2574 * @sht: scsi_host_template to use when registering the host
2575 *
2576 * LOCKING:
2577 * Inherited from calling layer (may sleep).
2578 *
2579 * RETURNS:
2580 * 0 on success, -errno otherwise.
2581 */
2582 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2583 {
2584 struct ahci_host_priv *hpriv = host->private_data;
2585 int irq = hpriv->irq;
2586 int rc;
2587
2588 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2589 if (hpriv->irq_handler)
2590 dev_warn(host->dev,
2591 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2592 if (!hpriv->get_irq_vector) {
2593 dev_err(host->dev,
2594 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2595 return -EIO;
2596 }
2597
2598 rc = ahci_host_activate_multi_irqs(host, sht);
2599 } else {
2600 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2601 IRQF_SHARED, sht);
2602 }
2603
2604
2605 return rc;
2606 }
2607 EXPORT_SYMBOL_GPL(ahci_host_activate);
2608
2609 MODULE_AUTHOR("Jeff Garzik");
2610 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2611 MODULE_LICENSE("GPL");
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