2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include <linux/pci.h>
50 static int ahci_skip_host_reset
;
52 EXPORT_SYMBOL_GPL(ahci_ignore_sss
);
54 module_param_named(skip_host_reset
, ahci_skip_host_reset
, int, 0444);
55 MODULE_PARM_DESC(skip_host_reset
, "skip global host reset (0=don't skip, 1=skip)");
57 module_param_named(ignore_sss
, ahci_ignore_sss
, int, 0444);
58 MODULE_PARM_DESC(ignore_sss
, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
60 static int ahci_set_lpm(struct ata_link
*link
, enum ata_lpm_policy policy
,
62 static ssize_t
ahci_led_show(struct ata_port
*ap
, char *buf
);
63 static ssize_t
ahci_led_store(struct ata_port
*ap
, const char *buf
,
65 static ssize_t
ahci_transmit_led_message(struct ata_port
*ap
, u32 state
,
70 static int ahci_scr_read(struct ata_link
*link
, unsigned int sc_reg
, u32
*val
);
71 static int ahci_scr_write(struct ata_link
*link
, unsigned int sc_reg
, u32 val
);
72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd
*qc
);
73 static int ahci_port_start(struct ata_port
*ap
);
74 static void ahci_port_stop(struct ata_port
*ap
);
75 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
76 static int ahci_pmp_qc_defer(struct ata_queued_cmd
*qc
);
77 static void ahci_freeze(struct ata_port
*ap
);
78 static void ahci_thaw(struct ata_port
*ap
);
79 static void ahci_set_aggressive_devslp(struct ata_port
*ap
, bool sleep
);
80 static void ahci_enable_fbs(struct ata_port
*ap
);
81 static void ahci_disable_fbs(struct ata_port
*ap
);
82 static void ahci_pmp_attach(struct ata_port
*ap
);
83 static void ahci_pmp_detach(struct ata_port
*ap
);
84 static int ahci_softreset(struct ata_link
*link
, unsigned int *class,
85 unsigned long deadline
);
86 static int ahci_pmp_retry_softreset(struct ata_link
*link
, unsigned int *class,
87 unsigned long deadline
);
88 static int ahci_hardreset(struct ata_link
*link
, unsigned int *class,
89 unsigned long deadline
);
90 static void ahci_postreset(struct ata_link
*link
, unsigned int *class);
91 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
);
92 static void ahci_dev_config(struct ata_device
*dev
);
94 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
);
96 static ssize_t
ahci_activity_show(struct ata_device
*dev
, char *buf
);
97 static ssize_t
ahci_activity_store(struct ata_device
*dev
,
98 enum sw_activity val
);
99 static void ahci_init_sw_activity(struct ata_link
*link
);
101 static ssize_t
ahci_show_host_caps(struct device
*dev
,
102 struct device_attribute
*attr
, char *buf
);
103 static ssize_t
ahci_show_host_cap2(struct device
*dev
,
104 struct device_attribute
*attr
, char *buf
);
105 static ssize_t
ahci_show_host_version(struct device
*dev
,
106 struct device_attribute
*attr
, char *buf
);
107 static ssize_t
ahci_show_port_cmd(struct device
*dev
,
108 struct device_attribute
*attr
, char *buf
);
109 static ssize_t
ahci_read_em_buffer(struct device
*dev
,
110 struct device_attribute
*attr
, char *buf
);
111 static ssize_t
ahci_store_em_buffer(struct device
*dev
,
112 struct device_attribute
*attr
,
113 const char *buf
, size_t size
);
114 static ssize_t
ahci_show_em_supported(struct device
*dev
,
115 struct device_attribute
*attr
, char *buf
);
116 static irqreturn_t
ahci_single_level_irq_intr(int irq
, void *dev_instance
);
118 static DEVICE_ATTR(ahci_host_caps
, S_IRUGO
, ahci_show_host_caps
, NULL
);
119 static DEVICE_ATTR(ahci_host_cap2
, S_IRUGO
, ahci_show_host_cap2
, NULL
);
120 static DEVICE_ATTR(ahci_host_version
, S_IRUGO
, ahci_show_host_version
, NULL
);
121 static DEVICE_ATTR(ahci_port_cmd
, S_IRUGO
, ahci_show_port_cmd
, NULL
);
122 static DEVICE_ATTR(em_buffer
, S_IWUSR
| S_IRUGO
,
123 ahci_read_em_buffer
, ahci_store_em_buffer
);
124 static DEVICE_ATTR(em_message_supported
, S_IRUGO
, ahci_show_em_supported
, NULL
);
126 struct device_attribute
*ahci_shost_attrs
[] = {
127 &dev_attr_link_power_management_policy
,
128 &dev_attr_em_message_type
,
129 &dev_attr_em_message
,
130 &dev_attr_ahci_host_caps
,
131 &dev_attr_ahci_host_cap2
,
132 &dev_attr_ahci_host_version
,
133 &dev_attr_ahci_port_cmd
,
135 &dev_attr_em_message_supported
,
138 EXPORT_SYMBOL_GPL(ahci_shost_attrs
);
140 struct device_attribute
*ahci_sdev_attrs
[] = {
141 &dev_attr_sw_activity
,
142 &dev_attr_unload_heads
,
143 &dev_attr_ncq_prio_enable
,
146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs
);
148 struct ata_port_operations ahci_ops
= {
149 .inherits
= &sata_pmp_port_ops
,
151 .qc_defer
= ahci_pmp_qc_defer
,
152 .qc_prep
= ahci_qc_prep
,
153 .qc_issue
= ahci_qc_issue
,
154 .qc_fill_rtf
= ahci_qc_fill_rtf
,
156 .freeze
= ahci_freeze
,
158 .softreset
= ahci_softreset
,
159 .hardreset
= ahci_hardreset
,
160 .postreset
= ahci_postreset
,
161 .pmp_softreset
= ahci_softreset
,
162 .error_handler
= ahci_error_handler
,
163 .post_internal_cmd
= ahci_post_internal_cmd
,
164 .dev_config
= ahci_dev_config
,
166 .scr_read
= ahci_scr_read
,
167 .scr_write
= ahci_scr_write
,
168 .pmp_attach
= ahci_pmp_attach
,
169 .pmp_detach
= ahci_pmp_detach
,
171 .set_lpm
= ahci_set_lpm
,
172 .em_show
= ahci_led_show
,
173 .em_store
= ahci_led_store
,
174 .sw_activity_show
= ahci_activity_show
,
175 .sw_activity_store
= ahci_activity_store
,
176 .transmit_led_message
= ahci_transmit_led_message
,
178 .port_suspend
= ahci_port_suspend
,
179 .port_resume
= ahci_port_resume
,
181 .port_start
= ahci_port_start
,
182 .port_stop
= ahci_port_stop
,
184 EXPORT_SYMBOL_GPL(ahci_ops
);
186 struct ata_port_operations ahci_pmp_retry_srst_ops
= {
187 .inherits
= &ahci_ops
,
188 .softreset
= ahci_pmp_retry_softreset
,
190 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops
);
192 static bool ahci_em_messages __read_mostly
= true;
193 EXPORT_SYMBOL_GPL(ahci_em_messages
);
194 module_param(ahci_em_messages
, bool, 0444);
195 /* add other LED protocol types when they become supported */
196 MODULE_PARM_DESC(ahci_em_messages
,
197 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
199 /* device sleep idle timeout in ms */
200 static int devslp_idle_timeout __read_mostly
= 1000;
201 module_param(devslp_idle_timeout
, int, 0644);
202 MODULE_PARM_DESC(devslp_idle_timeout
, "device sleep idle timeout");
204 static void ahci_enable_ahci(void __iomem
*mmio
)
209 /* turn on AHCI_EN */
210 tmp
= readl(mmio
+ HOST_CTL
);
211 if (tmp
& HOST_AHCI_EN
)
214 /* Some controllers need AHCI_EN to be written multiple times.
215 * Try a few times before giving up.
217 for (i
= 0; i
< 5; i
++) {
219 writel(tmp
, mmio
+ HOST_CTL
);
220 tmp
= readl(mmio
+ HOST_CTL
); /* flush && sanity check */
221 if (tmp
& HOST_AHCI_EN
)
230 * ahci_rpm_get_port - Make sure the port is powered on
231 * @ap: Port to power on
233 * Whenever there is need to access the AHCI host registers outside of
234 * normal execution paths, call this function to make sure the host is
235 * actually powered on.
237 static int ahci_rpm_get_port(struct ata_port
*ap
)
239 return pm_runtime_get_sync(ap
->dev
);
243 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
244 * @ap: Port to power down
246 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
247 * if it has no more active users.
249 static void ahci_rpm_put_port(struct ata_port
*ap
)
251 pm_runtime_put(ap
->dev
);
254 static ssize_t
ahci_show_host_caps(struct device
*dev
,
255 struct device_attribute
*attr
, char *buf
)
257 struct Scsi_Host
*shost
= class_to_shost(dev
);
258 struct ata_port
*ap
= ata_shost_to_port(shost
);
259 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
261 return sprintf(buf
, "%x\n", hpriv
->cap
);
264 static ssize_t
ahci_show_host_cap2(struct device
*dev
,
265 struct device_attribute
*attr
, char *buf
)
267 struct Scsi_Host
*shost
= class_to_shost(dev
);
268 struct ata_port
*ap
= ata_shost_to_port(shost
);
269 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
271 return sprintf(buf
, "%x\n", hpriv
->cap2
);
274 static ssize_t
ahci_show_host_version(struct device
*dev
,
275 struct device_attribute
*attr
, char *buf
)
277 struct Scsi_Host
*shost
= class_to_shost(dev
);
278 struct ata_port
*ap
= ata_shost_to_port(shost
);
279 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
281 return sprintf(buf
, "%x\n", hpriv
->version
);
284 static ssize_t
ahci_show_port_cmd(struct device
*dev
,
285 struct device_attribute
*attr
, char *buf
)
287 struct Scsi_Host
*shost
= class_to_shost(dev
);
288 struct ata_port
*ap
= ata_shost_to_port(shost
);
289 void __iomem
*port_mmio
= ahci_port_base(ap
);
292 ahci_rpm_get_port(ap
);
293 ret
= sprintf(buf
, "%x\n", readl(port_mmio
+ PORT_CMD
));
294 ahci_rpm_put_port(ap
);
299 static ssize_t
ahci_read_em_buffer(struct device
*dev
,
300 struct device_attribute
*attr
, char *buf
)
302 struct Scsi_Host
*shost
= class_to_shost(dev
);
303 struct ata_port
*ap
= ata_shost_to_port(shost
);
304 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
305 void __iomem
*mmio
= hpriv
->mmio
;
306 void __iomem
*em_mmio
= mmio
+ hpriv
->em_loc
;
312 ahci_rpm_get_port(ap
);
313 spin_lock_irqsave(ap
->lock
, flags
);
315 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
316 if (!(ap
->flags
& ATA_FLAG_EM
) || em_ctl
& EM_CTL_XMT
||
317 !(hpriv
->em_msg_type
& EM_MSG_TYPE_SGPIO
)) {
318 spin_unlock_irqrestore(ap
->lock
, flags
);
319 ahci_rpm_put_port(ap
);
323 if (!(em_ctl
& EM_CTL_MR
)) {
324 spin_unlock_irqrestore(ap
->lock
, flags
);
325 ahci_rpm_put_port(ap
);
329 if (!(em_ctl
& EM_CTL_SMB
))
330 em_mmio
+= hpriv
->em_buf_sz
;
332 count
= hpriv
->em_buf_sz
;
334 /* the count should not be larger than PAGE_SIZE */
335 if (count
> PAGE_SIZE
) {
336 if (printk_ratelimit())
338 "EM read buffer size too large: "
339 "buffer size %u, page size %lu\n",
340 hpriv
->em_buf_sz
, PAGE_SIZE
);
344 for (i
= 0; i
< count
; i
+= 4) {
345 msg
= readl(em_mmio
+ i
);
347 buf
[i
+ 1] = (msg
>> 8) & 0xff;
348 buf
[i
+ 2] = (msg
>> 16) & 0xff;
349 buf
[i
+ 3] = (msg
>> 24) & 0xff;
352 spin_unlock_irqrestore(ap
->lock
, flags
);
353 ahci_rpm_put_port(ap
);
358 static ssize_t
ahci_store_em_buffer(struct device
*dev
,
359 struct device_attribute
*attr
,
360 const char *buf
, size_t size
)
362 struct Scsi_Host
*shost
= class_to_shost(dev
);
363 struct ata_port
*ap
= ata_shost_to_port(shost
);
364 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
365 void __iomem
*mmio
= hpriv
->mmio
;
366 void __iomem
*em_mmio
= mmio
+ hpriv
->em_loc
;
367 const unsigned char *msg_buf
= buf
;
372 /* check size validity */
373 if (!(ap
->flags
& ATA_FLAG_EM
) ||
374 !(hpriv
->em_msg_type
& EM_MSG_TYPE_SGPIO
) ||
375 size
% 4 || size
> hpriv
->em_buf_sz
)
378 ahci_rpm_get_port(ap
);
379 spin_lock_irqsave(ap
->lock
, flags
);
381 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
382 if (em_ctl
& EM_CTL_TM
) {
383 spin_unlock_irqrestore(ap
->lock
, flags
);
384 ahci_rpm_put_port(ap
);
388 for (i
= 0; i
< size
; i
+= 4) {
389 msg
= msg_buf
[i
] | msg_buf
[i
+ 1] << 8 |
390 msg_buf
[i
+ 2] << 16 | msg_buf
[i
+ 3] << 24;
391 writel(msg
, em_mmio
+ i
);
394 writel(em_ctl
| EM_CTL_TM
, mmio
+ HOST_EM_CTL
);
396 spin_unlock_irqrestore(ap
->lock
, flags
);
397 ahci_rpm_put_port(ap
);
402 static ssize_t
ahci_show_em_supported(struct device
*dev
,
403 struct device_attribute
*attr
, char *buf
)
405 struct Scsi_Host
*shost
= class_to_shost(dev
);
406 struct ata_port
*ap
= ata_shost_to_port(shost
);
407 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
408 void __iomem
*mmio
= hpriv
->mmio
;
411 ahci_rpm_get_port(ap
);
412 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
413 ahci_rpm_put_port(ap
);
415 return sprintf(buf
, "%s%s%s%s\n",
416 em_ctl
& EM_CTL_LED
? "led " : "",
417 em_ctl
& EM_CTL_SAFTE
? "saf-te " : "",
418 em_ctl
& EM_CTL_SES
? "ses-2 " : "",
419 em_ctl
& EM_CTL_SGPIO
? "sgpio " : "");
423 * ahci_save_initial_config - Save and fixup initial config values
424 * @dev: target AHCI device
425 * @hpriv: host private area to store config values
427 * Some registers containing configuration info might be setup by
428 * BIOS and might be cleared on reset. This function saves the
429 * initial values of those registers into @hpriv such that they
430 * can be restored after controller reset.
432 * If inconsistent, config values are fixed up by this function.
434 * If it is not set already this function sets hpriv->start_engine to
440 void ahci_save_initial_config(struct device
*dev
, struct ahci_host_priv
*hpriv
)
442 void __iomem
*mmio
= hpriv
->mmio
;
443 u32 cap
, cap2
, vers
, port_map
;
446 /* make sure AHCI mode is enabled before accessing CAP */
447 ahci_enable_ahci(mmio
);
449 /* Values prefixed with saved_ are written back to host after
450 * reset. Values without are used for driver operation.
452 hpriv
->saved_cap
= cap
= readl(mmio
+ HOST_CAP
);
453 hpriv
->saved_port_map
= port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
455 /* CAP2 register is only defined for AHCI 1.2 and later */
456 vers
= readl(mmio
+ HOST_VERSION
);
457 if ((vers
>> 16) > 1 ||
458 ((vers
>> 16) == 1 && (vers
& 0xFFFF) >= 0x200))
459 hpriv
->saved_cap2
= cap2
= readl(mmio
+ HOST_CAP2
);
461 hpriv
->saved_cap2
= cap2
= 0;
463 /* some chips have errata preventing 64bit use */
464 if ((cap
& HOST_CAP_64
) && (hpriv
->flags
& AHCI_HFLAG_32BIT_ONLY
)) {
465 dev_info(dev
, "controller can't do 64bit DMA, forcing 32bit\n");
469 if ((cap
& HOST_CAP_NCQ
) && (hpriv
->flags
& AHCI_HFLAG_NO_NCQ
)) {
470 dev_info(dev
, "controller can't do NCQ, turning off CAP_NCQ\n");
471 cap
&= ~HOST_CAP_NCQ
;
474 if (!(cap
& HOST_CAP_NCQ
) && (hpriv
->flags
& AHCI_HFLAG_YES_NCQ
)) {
475 dev_info(dev
, "controller can do NCQ, turning on CAP_NCQ\n");
479 if ((cap
& HOST_CAP_PMP
) && (hpriv
->flags
& AHCI_HFLAG_NO_PMP
)) {
480 dev_info(dev
, "controller can't do PMP, turning off CAP_PMP\n");
481 cap
&= ~HOST_CAP_PMP
;
484 if ((cap
& HOST_CAP_SNTF
) && (hpriv
->flags
& AHCI_HFLAG_NO_SNTF
)) {
486 "controller can't do SNTF, turning off CAP_SNTF\n");
487 cap
&= ~HOST_CAP_SNTF
;
490 if ((cap2
& HOST_CAP2_SDS
) && (hpriv
->flags
& AHCI_HFLAG_NO_DEVSLP
)) {
492 "controller can't do DEVSLP, turning off\n");
493 cap2
&= ~HOST_CAP2_SDS
;
494 cap2
&= ~HOST_CAP2_SADM
;
497 if (!(cap
& HOST_CAP_FBS
) && (hpriv
->flags
& AHCI_HFLAG_YES_FBS
)) {
498 dev_info(dev
, "controller can do FBS, turning on CAP_FBS\n");
502 if ((cap
& HOST_CAP_FBS
) && (hpriv
->flags
& AHCI_HFLAG_NO_FBS
)) {
503 dev_info(dev
, "controller can't do FBS, turning off CAP_FBS\n");
504 cap
&= ~HOST_CAP_FBS
;
507 if (!(cap
& HOST_CAP_ALPM
) && (hpriv
->flags
& AHCI_HFLAG_YES_ALPM
)) {
508 dev_info(dev
, "controller can do ALPM, turning on CAP_ALPM\n");
509 cap
|= HOST_CAP_ALPM
;
512 if (hpriv
->force_port_map
&& port_map
!= hpriv
->force_port_map
) {
513 dev_info(dev
, "forcing port_map 0x%x -> 0x%x\n",
514 port_map
, hpriv
->force_port_map
);
515 port_map
= hpriv
->force_port_map
;
516 hpriv
->saved_port_map
= port_map
;
519 if (hpriv
->mask_port_map
) {
520 dev_warn(dev
, "masking port_map 0x%x -> 0x%x\n",
522 port_map
& hpriv
->mask_port_map
);
523 port_map
&= hpriv
->mask_port_map
;
526 /* cross check port_map and cap.n_ports */
530 for (i
= 0; i
< AHCI_MAX_PORTS
; i
++)
531 if (port_map
& (1 << i
))
534 /* If PI has more ports than n_ports, whine, clear
535 * port_map and let it be generated from n_ports.
537 if (map_ports
> ahci_nr_ports(cap
)) {
539 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
540 port_map
, ahci_nr_ports(cap
));
545 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
546 if (!port_map
&& vers
< 0x10300) {
547 port_map
= (1 << ahci_nr_ports(cap
)) - 1;
548 dev_warn(dev
, "forcing PORTS_IMPL to 0x%x\n", port_map
);
550 /* write the fixed up value to the PI register */
551 hpriv
->saved_port_map
= port_map
;
554 /* record values to use during operation */
557 hpriv
->version
= readl(mmio
+ HOST_VERSION
);
558 hpriv
->port_map
= port_map
;
560 if (!hpriv
->start_engine
)
561 hpriv
->start_engine
= ahci_start_engine
;
563 if (!hpriv
->irq_handler
)
564 hpriv
->irq_handler
= ahci_single_level_irq_intr
;
566 EXPORT_SYMBOL_GPL(ahci_save_initial_config
);
569 * ahci_restore_initial_config - Restore initial config
570 * @host: target ATA host
572 * Restore initial config stored by ahci_save_initial_config().
577 static void ahci_restore_initial_config(struct ata_host
*host
)
579 struct ahci_host_priv
*hpriv
= host
->private_data
;
580 void __iomem
*mmio
= hpriv
->mmio
;
582 writel(hpriv
->saved_cap
, mmio
+ HOST_CAP
);
583 if (hpriv
->saved_cap2
)
584 writel(hpriv
->saved_cap2
, mmio
+ HOST_CAP2
);
585 writel(hpriv
->saved_port_map
, mmio
+ HOST_PORTS_IMPL
);
586 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
589 static unsigned ahci_scr_offset(struct ata_port
*ap
, unsigned int sc_reg
)
591 static const int offset
[] = {
592 [SCR_STATUS
] = PORT_SCR_STAT
,
593 [SCR_CONTROL
] = PORT_SCR_CTL
,
594 [SCR_ERROR
] = PORT_SCR_ERR
,
595 [SCR_ACTIVE
] = PORT_SCR_ACT
,
596 [SCR_NOTIFICATION
] = PORT_SCR_NTF
,
598 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
600 if (sc_reg
< ARRAY_SIZE(offset
) &&
601 (sc_reg
!= SCR_NOTIFICATION
|| (hpriv
->cap
& HOST_CAP_SNTF
)))
602 return offset
[sc_reg
];
606 static int ahci_scr_read(struct ata_link
*link
, unsigned int sc_reg
, u32
*val
)
608 void __iomem
*port_mmio
= ahci_port_base(link
->ap
);
609 int offset
= ahci_scr_offset(link
->ap
, sc_reg
);
612 *val
= readl(port_mmio
+ offset
);
618 static int ahci_scr_write(struct ata_link
*link
, unsigned int sc_reg
, u32 val
)
620 void __iomem
*port_mmio
= ahci_port_base(link
->ap
);
621 int offset
= ahci_scr_offset(link
->ap
, sc_reg
);
624 writel(val
, port_mmio
+ offset
);
630 void ahci_start_engine(struct ata_port
*ap
)
632 void __iomem
*port_mmio
= ahci_port_base(ap
);
636 tmp
= readl(port_mmio
+ PORT_CMD
);
637 tmp
|= PORT_CMD_START
;
638 writel(tmp
, port_mmio
+ PORT_CMD
);
639 readl(port_mmio
+ PORT_CMD
); /* flush */
641 EXPORT_SYMBOL_GPL(ahci_start_engine
);
643 int ahci_stop_engine(struct ata_port
*ap
)
645 void __iomem
*port_mmio
= ahci_port_base(ap
);
646 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
650 * On some controllers, stopping a port's DMA engine while the port
651 * is in ALPM state (partial or slumber) results in failures on
652 * subsequent DMA engine starts. For those controllers, put the
653 * port back in active state before stopping its DMA engine.
655 if ((hpriv
->flags
& AHCI_HFLAG_WAKE_BEFORE_STOP
) &&
656 (ap
->link
.lpm_policy
> ATA_LPM_MAX_POWER
) &&
657 ahci_set_lpm(&ap
->link
, ATA_LPM_MAX_POWER
, ATA_LPM_WAKE_ONLY
)) {
658 dev_err(ap
->host
->dev
, "Failed to wake up port before engine stop\n");
662 tmp
= readl(port_mmio
+ PORT_CMD
);
664 /* check if the HBA is idle */
665 if ((tmp
& (PORT_CMD_START
| PORT_CMD_LIST_ON
)) == 0)
668 /* setting HBA to idle */
669 tmp
&= ~PORT_CMD_START
;
670 writel(tmp
, port_mmio
+ PORT_CMD
);
673 /* Rev Ax of Cavium CN99XX needs a hack for port stop */
674 if (MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(),
675 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM
, BRCM_CPU_PART_VULCAN
),
676 MIDR_CPU_VAR_REV(0, 0),
677 MIDR_CPU_VAR_REV(0, MIDR_REVISION_MASK
))) {
678 tmp
= readl(hpriv
->mmio
+ 0x8000);
679 writel(tmp
| (1 << 26), hpriv
->mmio
+ 0x8000);
681 writel(tmp
& ~(1 << 26), hpriv
->mmio
+ 0x8000);
682 dev_warn(ap
->host
->dev
, "CN99XX stop engine fix applied!\n");
686 /* wait for engine to stop. This could be as long as 500 msec */
687 tmp
= ata_wait_register(ap
, port_mmio
+ PORT_CMD
,
688 PORT_CMD_LIST_ON
, PORT_CMD_LIST_ON
, 1, 500);
689 if (tmp
& PORT_CMD_LIST_ON
)
694 EXPORT_SYMBOL_GPL(ahci_stop_engine
);
696 void ahci_start_fis_rx(struct ata_port
*ap
)
698 void __iomem
*port_mmio
= ahci_port_base(ap
);
699 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
700 struct ahci_port_priv
*pp
= ap
->private_data
;
703 /* set FIS registers */
704 if (hpriv
->cap
& HOST_CAP_64
)
705 writel((pp
->cmd_slot_dma
>> 16) >> 16,
706 port_mmio
+ PORT_LST_ADDR_HI
);
707 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
709 if (hpriv
->cap
& HOST_CAP_64
)
710 writel((pp
->rx_fis_dma
>> 16) >> 16,
711 port_mmio
+ PORT_FIS_ADDR_HI
);
712 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
714 /* enable FIS reception */
715 tmp
= readl(port_mmio
+ PORT_CMD
);
716 tmp
|= PORT_CMD_FIS_RX
;
717 writel(tmp
, port_mmio
+ PORT_CMD
);
720 readl(port_mmio
+ PORT_CMD
);
722 EXPORT_SYMBOL_GPL(ahci_start_fis_rx
);
724 static int ahci_stop_fis_rx(struct ata_port
*ap
)
726 void __iomem
*port_mmio
= ahci_port_base(ap
);
729 /* disable FIS reception */
730 tmp
= readl(port_mmio
+ PORT_CMD
);
731 tmp
&= ~PORT_CMD_FIS_RX
;
732 writel(tmp
, port_mmio
+ PORT_CMD
);
734 /* wait for completion, spec says 500ms, give it 1000 */
735 tmp
= ata_wait_register(ap
, port_mmio
+ PORT_CMD
, PORT_CMD_FIS_ON
,
736 PORT_CMD_FIS_ON
, 10, 1000);
737 if (tmp
& PORT_CMD_FIS_ON
)
743 static void ahci_power_up(struct ata_port
*ap
)
745 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
746 void __iomem
*port_mmio
= ahci_port_base(ap
);
749 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
752 if (hpriv
->cap
& HOST_CAP_SSS
) {
753 cmd
|= PORT_CMD_SPIN_UP
;
754 writel(cmd
, port_mmio
+ PORT_CMD
);
758 writel(cmd
| PORT_CMD_ICC_ACTIVE
, port_mmio
+ PORT_CMD
);
761 static int ahci_set_lpm(struct ata_link
*link
, enum ata_lpm_policy policy
,
764 struct ata_port
*ap
= link
->ap
;
765 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
766 struct ahci_port_priv
*pp
= ap
->private_data
;
767 void __iomem
*port_mmio
= ahci_port_base(ap
);
769 if (policy
!= ATA_LPM_MAX_POWER
) {
770 /* wakeup flag only applies to the max power policy */
771 hints
&= ~ATA_LPM_WAKE_ONLY
;
774 * Disable interrupts on Phy Ready. This keeps us from
775 * getting woken up due to spurious phy ready
778 pp
->intr_mask
&= ~PORT_IRQ_PHYRDY
;
779 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
781 sata_link_scr_lpm(link
, policy
, false);
784 if (hpriv
->cap
& HOST_CAP_ALPM
) {
785 u32 cmd
= readl(port_mmio
+ PORT_CMD
);
787 if (policy
== ATA_LPM_MAX_POWER
|| !(hints
& ATA_LPM_HIPM
)) {
788 if (!(hints
& ATA_LPM_WAKE_ONLY
))
789 cmd
&= ~(PORT_CMD_ASP
| PORT_CMD_ALPE
);
790 cmd
|= PORT_CMD_ICC_ACTIVE
;
792 writel(cmd
, port_mmio
+ PORT_CMD
);
793 readl(port_mmio
+ PORT_CMD
);
795 /* wait 10ms to be sure we've come out of LPM state */
798 if (hints
& ATA_LPM_WAKE_ONLY
)
801 cmd
|= PORT_CMD_ALPE
;
802 if (policy
== ATA_LPM_MIN_POWER
)
805 /* write out new cmd value */
806 writel(cmd
, port_mmio
+ PORT_CMD
);
810 /* set aggressive device sleep */
811 if ((hpriv
->cap2
& HOST_CAP2_SDS
) &&
812 (hpriv
->cap2
& HOST_CAP2_SADM
) &&
813 (link
->device
->flags
& ATA_DFLAG_DEVSLP
)) {
814 if (policy
== ATA_LPM_MIN_POWER
)
815 ahci_set_aggressive_devslp(ap
, true);
817 ahci_set_aggressive_devslp(ap
, false);
820 if (policy
== ATA_LPM_MAX_POWER
) {
821 sata_link_scr_lpm(link
, policy
, false);
823 /* turn PHYRDY IRQ back on */
824 pp
->intr_mask
|= PORT_IRQ_PHYRDY
;
825 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
832 static void ahci_power_down(struct ata_port
*ap
)
834 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
835 void __iomem
*port_mmio
= ahci_port_base(ap
);
838 if (!(hpriv
->cap
& HOST_CAP_SSS
))
841 /* put device into listen mode, first set PxSCTL.DET to 0 */
842 scontrol
= readl(port_mmio
+ PORT_SCR_CTL
);
844 writel(scontrol
, port_mmio
+ PORT_SCR_CTL
);
846 /* then set PxCMD.SUD to 0 */
847 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
848 cmd
&= ~PORT_CMD_SPIN_UP
;
849 writel(cmd
, port_mmio
+ PORT_CMD
);
853 static void ahci_start_port(struct ata_port
*ap
)
855 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
856 struct ahci_port_priv
*pp
= ap
->private_data
;
857 struct ata_link
*link
;
858 struct ahci_em_priv
*emp
;
862 /* enable FIS reception */
863 ahci_start_fis_rx(ap
);
866 if (!(hpriv
->flags
& AHCI_HFLAG_DELAY_ENGINE
))
867 hpriv
->start_engine(ap
);
870 if (ap
->flags
& ATA_FLAG_EM
) {
871 ata_for_each_link(link
, ap
, EDGE
) {
872 emp
= &pp
->em_priv
[link
->pmp
];
874 /* EM Transmit bit maybe busy during init */
875 for (i
= 0; i
< EM_MAX_RETRY
; i
++) {
876 rc
= ap
->ops
->transmit_led_message(ap
,
880 * If busy, give a breather but do not
881 * release EH ownership by using msleep()
882 * instead of ata_msleep(). EM Transmit
883 * bit is busy for the whole host and
884 * releasing ownership will cause other
885 * ports to fail the same way.
895 if (ap
->flags
& ATA_FLAG_SW_ACTIVITY
)
896 ata_for_each_link(link
, ap
, EDGE
)
897 ahci_init_sw_activity(link
);
901 static int ahci_deinit_port(struct ata_port
*ap
, const char **emsg
)
906 rc
= ahci_stop_engine(ap
);
908 *emsg
= "failed to stop engine";
912 /* disable FIS reception */
913 rc
= ahci_stop_fis_rx(ap
);
915 *emsg
= "failed stop FIS RX";
922 int ahci_reset_controller(struct ata_host
*host
)
924 struct ahci_host_priv
*hpriv
= host
->private_data
;
925 void __iomem
*mmio
= hpriv
->mmio
;
928 /* we must be in AHCI mode, before using anything
929 * AHCI-specific, such as HOST_RESET.
931 ahci_enable_ahci(mmio
);
933 /* global controller reset */
934 if (!ahci_skip_host_reset
) {
935 tmp
= readl(mmio
+ HOST_CTL
);
936 if ((tmp
& HOST_RESET
) == 0) {
937 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
938 readl(mmio
+ HOST_CTL
); /* flush */
942 * to perform host reset, OS should set HOST_RESET
943 * and poll until this bit is read to be "0".
944 * reset must complete within 1 second, or
945 * the hardware should be considered fried.
947 tmp
= ata_wait_register(NULL
, mmio
+ HOST_CTL
, HOST_RESET
,
948 HOST_RESET
, 10, 1000);
950 if (tmp
& HOST_RESET
) {
951 dev_err(host
->dev
, "controller reset failed (0x%x)\n",
956 /* turn on AHCI mode */
957 ahci_enable_ahci(mmio
);
959 /* Some registers might be cleared on reset. Restore
962 if (!(hpriv
->flags
& AHCI_HFLAG_NO_WRITE_TO_RO
))
963 ahci_restore_initial_config(host
);
965 dev_info(host
->dev
, "skipping global host reset\n");
969 EXPORT_SYMBOL_GPL(ahci_reset_controller
);
971 static void ahci_sw_activity(struct ata_link
*link
)
973 struct ata_port
*ap
= link
->ap
;
974 struct ahci_port_priv
*pp
= ap
->private_data
;
975 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
977 if (!(link
->flags
& ATA_LFLAG_SW_ACTIVITY
))
981 if (!timer_pending(&emp
->timer
))
982 mod_timer(&emp
->timer
, jiffies
+ msecs_to_jiffies(10));
985 static void ahci_sw_activity_blink(unsigned long arg
)
987 struct ata_link
*link
= (struct ata_link
*)arg
;
988 struct ata_port
*ap
= link
->ap
;
989 struct ahci_port_priv
*pp
= ap
->private_data
;
990 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
991 unsigned long led_message
= emp
->led_state
;
992 u32 activity_led_state
;
995 led_message
&= EM_MSG_LED_VALUE
;
996 led_message
|= ap
->port_no
| (link
->pmp
<< 8);
998 /* check to see if we've had activity. If so,
999 * toggle state of LED and reset timer. If not,
1000 * turn LED to desired idle state.
1002 spin_lock_irqsave(ap
->lock
, flags
);
1003 if (emp
->saved_activity
!= emp
->activity
) {
1004 emp
->saved_activity
= emp
->activity
;
1005 /* get the current LED state */
1006 activity_led_state
= led_message
& EM_MSG_LED_VALUE_ON
;
1008 if (activity_led_state
)
1009 activity_led_state
= 0;
1011 activity_led_state
= 1;
1013 /* clear old state */
1014 led_message
&= ~EM_MSG_LED_VALUE_ACTIVITY
;
1017 led_message
|= (activity_led_state
<< 16);
1018 mod_timer(&emp
->timer
, jiffies
+ msecs_to_jiffies(100));
1020 /* switch to idle */
1021 led_message
&= ~EM_MSG_LED_VALUE_ACTIVITY
;
1022 if (emp
->blink_policy
== BLINK_OFF
)
1023 led_message
|= (1 << 16);
1025 spin_unlock_irqrestore(ap
->lock
, flags
);
1026 ap
->ops
->transmit_led_message(ap
, led_message
, 4);
1029 static void ahci_init_sw_activity(struct ata_link
*link
)
1031 struct ata_port
*ap
= link
->ap
;
1032 struct ahci_port_priv
*pp
= ap
->private_data
;
1033 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
1035 /* init activity stats, setup timer */
1036 emp
->saved_activity
= emp
->activity
= 0;
1037 setup_timer(&emp
->timer
, ahci_sw_activity_blink
, (unsigned long)link
);
1039 /* check our blink policy and set flag for link if it's enabled */
1040 if (emp
->blink_policy
)
1041 link
->flags
|= ATA_LFLAG_SW_ACTIVITY
;
1044 int ahci_reset_em(struct ata_host
*host
)
1046 struct ahci_host_priv
*hpriv
= host
->private_data
;
1047 void __iomem
*mmio
= hpriv
->mmio
;
1050 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
1051 if ((em_ctl
& EM_CTL_TM
) || (em_ctl
& EM_CTL_RST
))
1054 writel(em_ctl
| EM_CTL_RST
, mmio
+ HOST_EM_CTL
);
1057 EXPORT_SYMBOL_GPL(ahci_reset_em
);
1059 static ssize_t
ahci_transmit_led_message(struct ata_port
*ap
, u32 state
,
1062 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1063 struct ahci_port_priv
*pp
= ap
->private_data
;
1064 void __iomem
*mmio
= hpriv
->mmio
;
1066 u32 message
[] = {0, 0};
1067 unsigned long flags
;
1069 struct ahci_em_priv
*emp
;
1071 /* get the slot number from the message */
1072 pmp
= (state
& EM_MSG_LED_PMP_SLOT
) >> 8;
1073 if (pmp
< EM_MAX_SLOTS
)
1074 emp
= &pp
->em_priv
[pmp
];
1078 ahci_rpm_get_port(ap
);
1079 spin_lock_irqsave(ap
->lock
, flags
);
1082 * if we are still busy transmitting a previous message,
1085 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
1086 if (em_ctl
& EM_CTL_TM
) {
1087 spin_unlock_irqrestore(ap
->lock
, flags
);
1088 ahci_rpm_put_port(ap
);
1092 if (hpriv
->em_msg_type
& EM_MSG_TYPE_LED
) {
1094 * create message header - this is all zero except for
1095 * the message size, which is 4 bytes.
1097 message
[0] |= (4 << 8);
1099 /* ignore 0:4 of byte zero, fill in port info yourself */
1100 message
[1] = ((state
& ~EM_MSG_LED_HBA_PORT
) | ap
->port_no
);
1102 /* write message to EM_LOC */
1103 writel(message
[0], mmio
+ hpriv
->em_loc
);
1104 writel(message
[1], mmio
+ hpriv
->em_loc
+4);
1107 * tell hardware to transmit the message
1109 writel(em_ctl
| EM_CTL_TM
, mmio
+ HOST_EM_CTL
);
1112 /* save off new led state for port/slot */
1113 emp
->led_state
= state
;
1115 spin_unlock_irqrestore(ap
->lock
, flags
);
1116 ahci_rpm_put_port(ap
);
1121 static ssize_t
ahci_led_show(struct ata_port
*ap
, char *buf
)
1123 struct ahci_port_priv
*pp
= ap
->private_data
;
1124 struct ata_link
*link
;
1125 struct ahci_em_priv
*emp
;
1128 ata_for_each_link(link
, ap
, EDGE
) {
1129 emp
= &pp
->em_priv
[link
->pmp
];
1130 rc
+= sprintf(buf
, "%lx\n", emp
->led_state
);
1135 static ssize_t
ahci_led_store(struct ata_port
*ap
, const char *buf
,
1140 struct ahci_port_priv
*pp
= ap
->private_data
;
1141 struct ahci_em_priv
*emp
;
1143 if (kstrtouint(buf
, 0, &state
) < 0)
1146 /* get the slot number from the message */
1147 pmp
= (state
& EM_MSG_LED_PMP_SLOT
) >> 8;
1148 if (pmp
< EM_MAX_SLOTS
)
1149 emp
= &pp
->em_priv
[pmp
];
1153 /* mask off the activity bits if we are in sw_activity
1154 * mode, user should turn off sw_activity before setting
1155 * activity led through em_message
1157 if (emp
->blink_policy
)
1158 state
&= ~EM_MSG_LED_VALUE_ACTIVITY
;
1160 return ap
->ops
->transmit_led_message(ap
, state
, size
);
1163 static ssize_t
ahci_activity_store(struct ata_device
*dev
, enum sw_activity val
)
1165 struct ata_link
*link
= dev
->link
;
1166 struct ata_port
*ap
= link
->ap
;
1167 struct ahci_port_priv
*pp
= ap
->private_data
;
1168 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
1169 u32 port_led_state
= emp
->led_state
;
1171 /* save the desired Activity LED behavior */
1174 link
->flags
&= ~(ATA_LFLAG_SW_ACTIVITY
);
1176 /* set the LED to OFF */
1177 port_led_state
&= EM_MSG_LED_VALUE_OFF
;
1178 port_led_state
|= (ap
->port_no
| (link
->pmp
<< 8));
1179 ap
->ops
->transmit_led_message(ap
, port_led_state
, 4);
1181 link
->flags
|= ATA_LFLAG_SW_ACTIVITY
;
1182 if (val
== BLINK_OFF
) {
1183 /* set LED to ON for idle */
1184 port_led_state
&= EM_MSG_LED_VALUE_OFF
;
1185 port_led_state
|= (ap
->port_no
| (link
->pmp
<< 8));
1186 port_led_state
|= EM_MSG_LED_VALUE_ON
; /* check this */
1187 ap
->ops
->transmit_led_message(ap
, port_led_state
, 4);
1190 emp
->blink_policy
= val
;
1194 static ssize_t
ahci_activity_show(struct ata_device
*dev
, char *buf
)
1196 struct ata_link
*link
= dev
->link
;
1197 struct ata_port
*ap
= link
->ap
;
1198 struct ahci_port_priv
*pp
= ap
->private_data
;
1199 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
1201 /* display the saved value of activity behavior for this
1204 return sprintf(buf
, "%d\n", emp
->blink_policy
);
1207 static void ahci_port_init(struct device
*dev
, struct ata_port
*ap
,
1208 int port_no
, void __iomem
*mmio
,
1209 void __iomem
*port_mmio
)
1211 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1212 const char *emsg
= NULL
;
1216 /* make sure port is not active */
1217 rc
= ahci_deinit_port(ap
, &emsg
);
1219 dev_warn(dev
, "%s (%d)\n", emsg
, rc
);
1222 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
1223 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
1224 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
1226 /* clear port IRQ */
1227 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1228 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
1230 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1232 writel(1 << port_no
, mmio
+ HOST_IRQ_STAT
);
1234 /* mark esata ports */
1235 tmp
= readl(port_mmio
+ PORT_CMD
);
1236 if ((tmp
& PORT_CMD_ESP
) && (hpriv
->cap
& HOST_CAP_SXS
))
1237 ap
->pflags
|= ATA_PFLAG_EXTERNAL
;
1240 void ahci_init_controller(struct ata_host
*host
)
1242 struct ahci_host_priv
*hpriv
= host
->private_data
;
1243 void __iomem
*mmio
= hpriv
->mmio
;
1245 void __iomem
*port_mmio
;
1248 for (i
= 0; i
< host
->n_ports
; i
++) {
1249 struct ata_port
*ap
= host
->ports
[i
];
1251 port_mmio
= ahci_port_base(ap
);
1252 if (ata_port_is_dummy(ap
))
1255 ahci_port_init(host
->dev
, ap
, i
, mmio
, port_mmio
);
1258 tmp
= readl(mmio
+ HOST_CTL
);
1259 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1260 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
1261 tmp
= readl(mmio
+ HOST_CTL
);
1262 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1264 EXPORT_SYMBOL_GPL(ahci_init_controller
);
1266 static void ahci_dev_config(struct ata_device
*dev
)
1268 struct ahci_host_priv
*hpriv
= dev
->link
->ap
->host
->private_data
;
1270 if (hpriv
->flags
& AHCI_HFLAG_SECT255
) {
1271 dev
->max_sectors
= 255;
1273 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1277 unsigned int ahci_dev_classify(struct ata_port
*ap
)
1279 void __iomem
*port_mmio
= ahci_port_base(ap
);
1280 struct ata_taskfile tf
;
1283 tmp
= readl(port_mmio
+ PORT_SIG
);
1284 tf
.lbah
= (tmp
>> 24) & 0xff;
1285 tf
.lbam
= (tmp
>> 16) & 0xff;
1286 tf
.lbal
= (tmp
>> 8) & 0xff;
1287 tf
.nsect
= (tmp
) & 0xff;
1289 return ata_dev_classify(&tf
);
1291 EXPORT_SYMBOL_GPL(ahci_dev_classify
);
1293 void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, unsigned int tag
,
1296 dma_addr_t cmd_tbl_dma
;
1298 cmd_tbl_dma
= pp
->cmd_tbl_dma
+ tag
* AHCI_CMD_TBL_SZ
;
1300 pp
->cmd_slot
[tag
].opts
= cpu_to_le32(opts
);
1301 pp
->cmd_slot
[tag
].status
= 0;
1302 pp
->cmd_slot
[tag
].tbl_addr
= cpu_to_le32(cmd_tbl_dma
& 0xffffffff);
1303 pp
->cmd_slot
[tag
].tbl_addr_hi
= cpu_to_le32((cmd_tbl_dma
>> 16) >> 16);
1305 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot
);
1307 int ahci_kick_engine(struct ata_port
*ap
)
1309 void __iomem
*port_mmio
= ahci_port_base(ap
);
1310 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1311 u8 status
= readl(port_mmio
+ PORT_TFDATA
) & 0xFF;
1316 rc
= ahci_stop_engine(ap
);
1321 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1323 busy
= status
& (ATA_BUSY
| ATA_DRQ
);
1324 if (!busy
&& !sata_pmp_attached(ap
)) {
1329 if (!(hpriv
->cap
& HOST_CAP_CLO
)) {
1335 tmp
= readl(port_mmio
+ PORT_CMD
);
1336 tmp
|= PORT_CMD_CLO
;
1337 writel(tmp
, port_mmio
+ PORT_CMD
);
1340 tmp
= ata_wait_register(ap
, port_mmio
+ PORT_CMD
,
1341 PORT_CMD_CLO
, PORT_CMD_CLO
, 1, 500);
1342 if (tmp
& PORT_CMD_CLO
)
1345 /* restart engine */
1347 hpriv
->start_engine(ap
);
1350 EXPORT_SYMBOL_GPL(ahci_kick_engine
);
1352 static int ahci_exec_polled_cmd(struct ata_port
*ap
, int pmp
,
1353 struct ata_taskfile
*tf
, int is_cmd
, u16 flags
,
1354 unsigned long timeout_msec
)
1356 const u32 cmd_fis_len
= 5; /* five dwords */
1357 struct ahci_port_priv
*pp
= ap
->private_data
;
1358 void __iomem
*port_mmio
= ahci_port_base(ap
);
1359 u8
*fis
= pp
->cmd_tbl
;
1362 /* prep the command */
1363 ata_tf_to_fis(tf
, pmp
, is_cmd
, fis
);
1364 ahci_fill_cmd_slot(pp
, 0, cmd_fis_len
| flags
| (pmp
<< 12));
1366 /* set port value for softreset of Port Multiplier */
1367 if (pp
->fbs_enabled
&& pp
->fbs_last_dev
!= pmp
) {
1368 tmp
= readl(port_mmio
+ PORT_FBS
);
1369 tmp
&= ~(PORT_FBS_DEV_MASK
| PORT_FBS_DEC
);
1370 tmp
|= pmp
<< PORT_FBS_DEV_OFFSET
;
1371 writel(tmp
, port_mmio
+ PORT_FBS
);
1372 pp
->fbs_last_dev
= pmp
;
1376 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
1379 tmp
= ata_wait_register(ap
, port_mmio
+ PORT_CMD_ISSUE
,
1380 0x1, 0x1, 1, timeout_msec
);
1382 ahci_kick_engine(ap
);
1386 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
1391 int ahci_do_softreset(struct ata_link
*link
, unsigned int *class,
1392 int pmp
, unsigned long deadline
,
1393 int (*check_ready
)(struct ata_link
*link
))
1395 struct ata_port
*ap
= link
->ap
;
1396 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1397 struct ahci_port_priv
*pp
= ap
->private_data
;
1398 const char *reason
= NULL
;
1399 unsigned long now
, msecs
;
1400 struct ata_taskfile tf
;
1401 bool fbs_disabled
= false;
1406 /* prepare for SRST (AHCI-1.1 10.4.1) */
1407 rc
= ahci_kick_engine(ap
);
1408 if (rc
&& rc
!= -EOPNOTSUPP
)
1409 ata_link_warn(link
, "failed to reset engine (errno=%d)\n", rc
);
1412 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1413 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1414 * that is attached to port multiplier.
1416 if (!ata_is_host_link(link
) && pp
->fbs_enabled
) {
1417 ahci_disable_fbs(ap
);
1418 fbs_disabled
= true;
1421 ata_tf_init(link
->device
, &tf
);
1423 /* issue the first H2D Register FIS */
1426 if (time_after(deadline
, now
))
1427 msecs
= jiffies_to_msecs(deadline
- now
);
1430 if (ahci_exec_polled_cmd(ap
, pmp
, &tf
, 0,
1431 AHCI_CMD_RESET
| AHCI_CMD_CLR_BUSY
, msecs
)) {
1433 reason
= "1st FIS failed";
1437 /* spec says at least 5us, but be generous and sleep for 1ms */
1440 /* issue the second H2D Register FIS */
1441 tf
.ctl
&= ~ATA_SRST
;
1442 ahci_exec_polled_cmd(ap
, pmp
, &tf
, 0, 0, 0);
1444 /* wait for link to become ready */
1445 rc
= ata_wait_after_reset(link
, deadline
, check_ready
);
1446 if (rc
== -EBUSY
&& hpriv
->flags
& AHCI_HFLAG_SRST_TOUT_IS_OFFLINE
) {
1448 * Workaround for cases where link online status can't
1449 * be trusted. Treat device readiness timeout as link
1452 ata_link_info(link
, "device not ready, treating as offline\n");
1453 *class = ATA_DEV_NONE
;
1455 /* link occupied, -ENODEV too is an error */
1456 reason
= "device not ready";
1459 *class = ahci_dev_classify(ap
);
1461 /* re-enable FBS if disabled before */
1463 ahci_enable_fbs(ap
);
1465 DPRINTK("EXIT, class=%u\n", *class);
1469 ata_link_err(link
, "softreset failed (%s)\n", reason
);
1473 int ahci_check_ready(struct ata_link
*link
)
1475 void __iomem
*port_mmio
= ahci_port_base(link
->ap
);
1476 u8 status
= readl(port_mmio
+ PORT_TFDATA
) & 0xFF;
1478 return ata_check_ready(status
);
1480 EXPORT_SYMBOL_GPL(ahci_check_ready
);
1482 static int ahci_softreset(struct ata_link
*link
, unsigned int *class,
1483 unsigned long deadline
)
1485 int pmp
= sata_srst_pmp(link
);
1489 return ahci_do_softreset(link
, class, pmp
, deadline
, ahci_check_ready
);
1491 EXPORT_SYMBOL_GPL(ahci_do_softreset
);
1493 static int ahci_bad_pmp_check_ready(struct ata_link
*link
)
1495 void __iomem
*port_mmio
= ahci_port_base(link
->ap
);
1496 u8 status
= readl(port_mmio
+ PORT_TFDATA
) & 0xFF;
1497 u32 irq_status
= readl(port_mmio
+ PORT_IRQ_STAT
);
1500 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1501 * which can save timeout delay.
1503 if (irq_status
& PORT_IRQ_BAD_PMP
)
1506 return ata_check_ready(status
);
1509 static int ahci_pmp_retry_softreset(struct ata_link
*link
, unsigned int *class,
1510 unsigned long deadline
)
1512 struct ata_port
*ap
= link
->ap
;
1513 void __iomem
*port_mmio
= ahci_port_base(ap
);
1514 int pmp
= sata_srst_pmp(link
);
1520 rc
= ahci_do_softreset(link
, class, pmp
, deadline
,
1521 ahci_bad_pmp_check_ready
);
1524 * Soft reset fails with IPMS set when PMP is enabled but
1525 * SATA HDD/ODD is connected to SATA port, do soft reset
1529 irq_sts
= readl(port_mmio
+ PORT_IRQ_STAT
);
1530 if (irq_sts
& PORT_IRQ_BAD_PMP
) {
1532 "applying PMP SRST workaround "
1534 rc
= ahci_do_softreset(link
, class, 0, deadline
,
1542 int ahci_do_hardreset(struct ata_link
*link
, unsigned int *class,
1543 unsigned long deadline
, bool *online
)
1545 const unsigned long *timing
= sata_ehc_deb_timing(&link
->eh_context
);
1546 struct ata_port
*ap
= link
->ap
;
1547 struct ahci_port_priv
*pp
= ap
->private_data
;
1548 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1549 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
1550 struct ata_taskfile tf
;
1555 ahci_stop_engine(ap
);
1557 /* clear D2H reception area to properly wait for D2H FIS */
1558 ata_tf_init(link
->device
, &tf
);
1559 tf
.command
= ATA_BUSY
;
1560 ata_tf_to_fis(&tf
, 0, 0, d2h_fis
);
1562 rc
= sata_link_hardreset(link
, timing
, deadline
, online
,
1565 hpriv
->start_engine(ap
);
1568 *class = ahci_dev_classify(ap
);
1570 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
1573 EXPORT_SYMBOL_GPL(ahci_do_hardreset
);
1575 static int ahci_hardreset(struct ata_link
*link
, unsigned int *class,
1576 unsigned long deadline
)
1580 return ahci_do_hardreset(link
, class, deadline
, &online
);
1583 static void ahci_postreset(struct ata_link
*link
, unsigned int *class)
1585 struct ata_port
*ap
= link
->ap
;
1586 void __iomem
*port_mmio
= ahci_port_base(ap
);
1589 ata_std_postreset(link
, class);
1591 /* Make sure port's ATAPI bit is set appropriately */
1592 new_tmp
= tmp
= readl(port_mmio
+ PORT_CMD
);
1593 if (*class == ATA_DEV_ATAPI
)
1594 new_tmp
|= PORT_CMD_ATAPI
;
1596 new_tmp
&= ~PORT_CMD_ATAPI
;
1597 if (new_tmp
!= tmp
) {
1598 writel(new_tmp
, port_mmio
+ PORT_CMD
);
1599 readl(port_mmio
+ PORT_CMD
); /* flush */
1603 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_tbl
)
1605 struct scatterlist
*sg
;
1606 struct ahci_sg
*ahci_sg
= cmd_tbl
+ AHCI_CMD_TBL_HDR_SZ
;
1612 * Next, the S/G list.
1614 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
1615 dma_addr_t addr
= sg_dma_address(sg
);
1616 u32 sg_len
= sg_dma_len(sg
);
1618 ahci_sg
[si
].addr
= cpu_to_le32(addr
& 0xffffffff);
1619 ahci_sg
[si
].addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
1620 ahci_sg
[si
].flags_size
= cpu_to_le32(sg_len
- 1);
1626 static int ahci_pmp_qc_defer(struct ata_queued_cmd
*qc
)
1628 struct ata_port
*ap
= qc
->ap
;
1629 struct ahci_port_priv
*pp
= ap
->private_data
;
1631 if (!sata_pmp_attached(ap
) || pp
->fbs_enabled
)
1632 return ata_std_qc_defer(qc
);
1634 return sata_pmp_qc_defer_cmd_switch(qc
);
1637 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
1639 struct ata_port
*ap
= qc
->ap
;
1640 struct ahci_port_priv
*pp
= ap
->private_data
;
1641 int is_atapi
= ata_is_atapi(qc
->tf
.protocol
);
1644 const u32 cmd_fis_len
= 5; /* five dwords */
1645 unsigned int n_elem
;
1648 * Fill in command table information. First, the header,
1649 * a SATA Register - Host to Device command FIS.
1651 cmd_tbl
= pp
->cmd_tbl
+ qc
->tag
* AHCI_CMD_TBL_SZ
;
1653 ata_tf_to_fis(&qc
->tf
, qc
->dev
->link
->pmp
, 1, cmd_tbl
);
1655 memset(cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
1656 memcpy(cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, qc
->dev
->cdb_len
);
1660 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
1661 n_elem
= ahci_fill_sg(qc
, cmd_tbl
);
1664 * Fill in command slot information.
1666 opts
= cmd_fis_len
| n_elem
<< 16 | (qc
->dev
->link
->pmp
<< 12);
1667 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
1668 opts
|= AHCI_CMD_WRITE
;
1670 opts
|= AHCI_CMD_ATAPI
| AHCI_CMD_PREFETCH
;
1672 ahci_fill_cmd_slot(pp
, qc
->tag
, opts
);
1675 static void ahci_fbs_dec_intr(struct ata_port
*ap
)
1677 struct ahci_port_priv
*pp
= ap
->private_data
;
1678 void __iomem
*port_mmio
= ahci_port_base(ap
);
1679 u32 fbs
= readl(port_mmio
+ PORT_FBS
);
1683 BUG_ON(!pp
->fbs_enabled
);
1685 /* time to wait for DEC is not specified by AHCI spec,
1686 * add a retry loop for safety.
1688 writel(fbs
| PORT_FBS_DEC
, port_mmio
+ PORT_FBS
);
1689 fbs
= readl(port_mmio
+ PORT_FBS
);
1690 while ((fbs
& PORT_FBS_DEC
) && retries
--) {
1692 fbs
= readl(port_mmio
+ PORT_FBS
);
1695 if (fbs
& PORT_FBS_DEC
)
1696 dev_err(ap
->host
->dev
, "failed to clear device error\n");
1699 static void ahci_error_intr(struct ata_port
*ap
, u32 irq_stat
)
1701 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1702 struct ahci_port_priv
*pp
= ap
->private_data
;
1703 struct ata_eh_info
*host_ehi
= &ap
->link
.eh_info
;
1704 struct ata_link
*link
= NULL
;
1705 struct ata_queued_cmd
*active_qc
;
1706 struct ata_eh_info
*active_ehi
;
1707 bool fbs_need_dec
= false;
1710 /* determine active link with error */
1711 if (pp
->fbs_enabled
) {
1712 void __iomem
*port_mmio
= ahci_port_base(ap
);
1713 u32 fbs
= readl(port_mmio
+ PORT_FBS
);
1714 int pmp
= fbs
>> PORT_FBS_DWE_OFFSET
;
1716 if ((fbs
& PORT_FBS_SDE
) && (pmp
< ap
->nr_pmp_links
)) {
1717 link
= &ap
->pmp_link
[pmp
];
1718 fbs_need_dec
= true;
1722 ata_for_each_link(link
, ap
, EDGE
)
1723 if (ata_link_active(link
))
1729 active_qc
= ata_qc_from_tag(ap
, link
->active_tag
);
1730 active_ehi
= &link
->eh_info
;
1732 /* record irq stat */
1733 ata_ehi_clear_desc(host_ehi
);
1734 ata_ehi_push_desc(host_ehi
, "irq_stat 0x%08x", irq_stat
);
1736 /* AHCI needs SError cleared; otherwise, it might lock up */
1737 ahci_scr_read(&ap
->link
, SCR_ERROR
, &serror
);
1738 ahci_scr_write(&ap
->link
, SCR_ERROR
, serror
);
1739 host_ehi
->serror
|= serror
;
1741 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1742 if (hpriv
->flags
& AHCI_HFLAG_IGN_IRQ_IF_ERR
)
1743 irq_stat
&= ~PORT_IRQ_IF_ERR
;
1745 if (irq_stat
& PORT_IRQ_TF_ERR
) {
1746 /* If qc is active, charge it; otherwise, the active
1747 * link. There's no active qc on NCQ errors. It will
1748 * be determined by EH by reading log page 10h.
1751 active_qc
->err_mask
|= AC_ERR_DEV
;
1753 active_ehi
->err_mask
|= AC_ERR_DEV
;
1755 if (hpriv
->flags
& AHCI_HFLAG_IGN_SERR_INTERNAL
)
1756 host_ehi
->serror
&= ~SERR_INTERNAL
;
1759 if (irq_stat
& PORT_IRQ_UNK_FIS
) {
1760 u32
*unk
= pp
->rx_fis
+ RX_FIS_UNK
;
1762 active_ehi
->err_mask
|= AC_ERR_HSM
;
1763 active_ehi
->action
|= ATA_EH_RESET
;
1764 ata_ehi_push_desc(active_ehi
,
1765 "unknown FIS %08x %08x %08x %08x" ,
1766 unk
[0], unk
[1], unk
[2], unk
[3]);
1769 if (sata_pmp_attached(ap
) && (irq_stat
& PORT_IRQ_BAD_PMP
)) {
1770 active_ehi
->err_mask
|= AC_ERR_HSM
;
1771 active_ehi
->action
|= ATA_EH_RESET
;
1772 ata_ehi_push_desc(active_ehi
, "incorrect PMP");
1775 if (irq_stat
& (PORT_IRQ_HBUS_ERR
| PORT_IRQ_HBUS_DATA_ERR
)) {
1776 host_ehi
->err_mask
|= AC_ERR_HOST_BUS
;
1777 host_ehi
->action
|= ATA_EH_RESET
;
1778 ata_ehi_push_desc(host_ehi
, "host bus error");
1781 if (irq_stat
& PORT_IRQ_IF_ERR
) {
1783 active_ehi
->err_mask
|= AC_ERR_DEV
;
1785 host_ehi
->err_mask
|= AC_ERR_ATA_BUS
;
1786 host_ehi
->action
|= ATA_EH_RESET
;
1789 ata_ehi_push_desc(host_ehi
, "interface fatal error");
1792 if (irq_stat
& (PORT_IRQ_CONNECT
| PORT_IRQ_PHYRDY
)) {
1793 ata_ehi_hotplugged(host_ehi
);
1794 ata_ehi_push_desc(host_ehi
, "%s",
1795 irq_stat
& PORT_IRQ_CONNECT
?
1796 "connection status changed" : "PHY RDY changed");
1799 /* okay, let's hand over to EH */
1801 if (irq_stat
& PORT_IRQ_FREEZE
)
1802 ata_port_freeze(ap
);
1803 else if (fbs_need_dec
) {
1804 ata_link_abort(link
);
1805 ahci_fbs_dec_intr(ap
);
1810 static void ahci_handle_port_interrupt(struct ata_port
*ap
,
1811 void __iomem
*port_mmio
, u32 status
)
1813 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
1814 struct ahci_port_priv
*pp
= ap
->private_data
;
1815 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1816 int resetting
= !!(ap
->pflags
& ATA_PFLAG_RESETTING
);
1820 /* ignore BAD_PMP while resetting */
1821 if (unlikely(resetting
))
1822 status
&= ~PORT_IRQ_BAD_PMP
;
1824 if (sata_lpm_ignore_phy_events(&ap
->link
)) {
1825 status
&= ~PORT_IRQ_PHYRDY
;
1826 ahci_scr_write(&ap
->link
, SCR_ERROR
, SERR_PHYRDY_CHG
);
1829 if (unlikely(status
& PORT_IRQ_ERROR
)) {
1830 ahci_error_intr(ap
, status
);
1834 if (status
& PORT_IRQ_SDB_FIS
) {
1835 /* If SNotification is available, leave notification
1836 * handling to sata_async_notification(). If not,
1837 * emulate it by snooping SDB FIS RX area.
1839 * Snooping FIS RX area is probably cheaper than
1840 * poking SNotification but some constrollers which
1841 * implement SNotification, ICH9 for example, don't
1842 * store AN SDB FIS into receive area.
1844 if (hpriv
->cap
& HOST_CAP_SNTF
)
1845 sata_async_notification(ap
);
1847 /* If the 'N' bit in word 0 of the FIS is set,
1848 * we just received asynchronous notification.
1849 * Tell libata about it.
1851 * Lack of SNotification should not appear in
1852 * ahci 1.2, so the workaround is unnecessary
1853 * when FBS is enabled.
1855 if (pp
->fbs_enabled
)
1858 const __le32
*f
= pp
->rx_fis
+ RX_FIS_SDB
;
1859 u32 f0
= le32_to_cpu(f
[0]);
1861 sata_async_notification(ap
);
1866 /* pp->active_link is not reliable once FBS is enabled, both
1867 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1868 * NCQ and non-NCQ commands may be in flight at the same time.
1870 if (pp
->fbs_enabled
) {
1871 if (ap
->qc_active
) {
1872 qc_active
= readl(port_mmio
+ PORT_SCR_ACT
);
1873 qc_active
|= readl(port_mmio
+ PORT_CMD_ISSUE
);
1876 /* pp->active_link is valid iff any command is in flight */
1877 if (ap
->qc_active
&& pp
->active_link
->sactive
)
1878 qc_active
= readl(port_mmio
+ PORT_SCR_ACT
);
1880 qc_active
= readl(port_mmio
+ PORT_CMD_ISSUE
);
1884 rc
= ata_qc_complete_multiple(ap
, qc_active
);
1886 /* while resetting, invalid completions are expected */
1887 if (unlikely(rc
< 0 && !resetting
)) {
1888 ehi
->err_mask
|= AC_ERR_HSM
;
1889 ehi
->action
|= ATA_EH_RESET
;
1890 ata_port_freeze(ap
);
1894 static void ahci_port_intr(struct ata_port
*ap
)
1896 void __iomem
*port_mmio
= ahci_port_base(ap
);
1899 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
1900 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
1902 ahci_handle_port_interrupt(ap
, port_mmio
, status
);
1905 static irqreturn_t
ahci_multi_irqs_intr_hard(int irq
, void *dev_instance
)
1907 struct ata_port
*ap
= dev_instance
;
1908 void __iomem
*port_mmio
= ahci_port_base(ap
);
1913 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
1914 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
1916 spin_lock(ap
->lock
);
1917 ahci_handle_port_interrupt(ap
, port_mmio
, status
);
1918 spin_unlock(ap
->lock
);
1925 u32
ahci_handle_port_intr(struct ata_host
*host
, u32 irq_masked
)
1927 unsigned int i
, handled
= 0;
1929 for (i
= 0; i
< host
->n_ports
; i
++) {
1930 struct ata_port
*ap
;
1932 if (!(irq_masked
& (1 << i
)))
1935 ap
= host
->ports
[i
];
1938 VPRINTK("port %u\n", i
);
1940 VPRINTK("port %u (no irq)\n", i
);
1941 if (ata_ratelimit())
1943 "interrupt on disabled port %u\n", i
);
1951 EXPORT_SYMBOL_GPL(ahci_handle_port_intr
);
1953 static irqreturn_t
ahci_single_level_irq_intr(int irq
, void *dev_instance
)
1955 struct ata_host
*host
= dev_instance
;
1956 struct ahci_host_priv
*hpriv
;
1957 unsigned int rc
= 0;
1959 u32 irq_stat
, irq_masked
;
1963 hpriv
= host
->private_data
;
1966 /* sigh. 0xffffffff is a valid return from h/w */
1967 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
1971 irq_masked
= irq_stat
& hpriv
->port_map
;
1973 spin_lock(&host
->lock
);
1975 rc
= ahci_handle_port_intr(host
, irq_masked
);
1977 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1978 * it should be cleared after all the port events are cleared;
1979 * otherwise, it will raise a spurious interrupt after each
1980 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1983 * Also, use the unmasked value to clear interrupt as spurious
1984 * pending event on a dummy port might cause screaming IRQ.
1986 writel(irq_stat
, mmio
+ HOST_IRQ_STAT
);
1988 spin_unlock(&host
->lock
);
1992 return IRQ_RETVAL(rc
);
1995 unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
)
1997 struct ata_port
*ap
= qc
->ap
;
1998 void __iomem
*port_mmio
= ahci_port_base(ap
);
1999 struct ahci_port_priv
*pp
= ap
->private_data
;
2001 /* Keep track of the currently active link. It will be used
2002 * in completion path to determine whether NCQ phase is in
2005 pp
->active_link
= qc
->dev
->link
;
2007 if (ata_is_ncq(qc
->tf
.protocol
))
2008 writel(1 << qc
->tag
, port_mmio
+ PORT_SCR_ACT
);
2010 if (pp
->fbs_enabled
&& pp
->fbs_last_dev
!= qc
->dev
->link
->pmp
) {
2011 u32 fbs
= readl(port_mmio
+ PORT_FBS
);
2012 fbs
&= ~(PORT_FBS_DEV_MASK
| PORT_FBS_DEC
);
2013 fbs
|= qc
->dev
->link
->pmp
<< PORT_FBS_DEV_OFFSET
;
2014 writel(fbs
, port_mmio
+ PORT_FBS
);
2015 pp
->fbs_last_dev
= qc
->dev
->link
->pmp
;
2018 writel(1 << qc
->tag
, port_mmio
+ PORT_CMD_ISSUE
);
2020 ahci_sw_activity(qc
->dev
->link
);
2024 EXPORT_SYMBOL_GPL(ahci_qc_issue
);
2026 static bool ahci_qc_fill_rtf(struct ata_queued_cmd
*qc
)
2028 struct ahci_port_priv
*pp
= qc
->ap
->private_data
;
2029 u8
*rx_fis
= pp
->rx_fis
;
2031 if (pp
->fbs_enabled
)
2032 rx_fis
+= qc
->dev
->link
->pmp
* AHCI_RX_FIS_SZ
;
2035 * After a successful execution of an ATA PIO data-in command,
2036 * the device doesn't send D2H Reg FIS to update the TF and
2037 * the host should take TF and E_Status from the preceding PIO
2040 if (qc
->tf
.protocol
== ATA_PROT_PIO
&& qc
->dma_dir
== DMA_FROM_DEVICE
&&
2041 !(qc
->flags
& ATA_QCFLAG_FAILED
)) {
2042 ata_tf_from_fis(rx_fis
+ RX_FIS_PIO_SETUP
, &qc
->result_tf
);
2043 qc
->result_tf
.command
= (rx_fis
+ RX_FIS_PIO_SETUP
)[15];
2045 ata_tf_from_fis(rx_fis
+ RX_FIS_D2H_REG
, &qc
->result_tf
);
2050 static void ahci_freeze(struct ata_port
*ap
)
2052 void __iomem
*port_mmio
= ahci_port_base(ap
);
2055 writel(0, port_mmio
+ PORT_IRQ_MASK
);
2058 static void ahci_thaw(struct ata_port
*ap
)
2060 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
2061 void __iomem
*mmio
= hpriv
->mmio
;
2062 void __iomem
*port_mmio
= ahci_port_base(ap
);
2064 struct ahci_port_priv
*pp
= ap
->private_data
;
2067 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
2068 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
2069 writel(1 << ap
->port_no
, mmio
+ HOST_IRQ_STAT
);
2071 /* turn IRQ back on */
2072 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
2075 void ahci_error_handler(struct ata_port
*ap
)
2077 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
2079 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
2080 /* restart engine */
2081 ahci_stop_engine(ap
);
2082 hpriv
->start_engine(ap
);
2085 sata_pmp_error_handler(ap
);
2087 if (!ata_dev_enabled(ap
->link
.device
))
2088 ahci_stop_engine(ap
);
2090 EXPORT_SYMBOL_GPL(ahci_error_handler
);
2092 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
)
2094 struct ata_port
*ap
= qc
->ap
;
2096 /* make DMA engine forget about the failed command */
2097 if (qc
->flags
& ATA_QCFLAG_FAILED
)
2098 ahci_kick_engine(ap
);
2101 static void ahci_set_aggressive_devslp(struct ata_port
*ap
, bool sleep
)
2103 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
2104 void __iomem
*port_mmio
= ahci_port_base(ap
);
2105 struct ata_device
*dev
= ap
->link
.device
;
2106 u32 devslp
, dm
, dito
, mdat
, deto
;
2108 unsigned int err_mask
;
2110 devslp
= readl(port_mmio
+ PORT_DEVSLP
);
2111 if (!(devslp
& PORT_DEVSLP_DSP
)) {
2112 dev_info(ap
->host
->dev
, "port does not support device sleep\n");
2116 /* disable device sleep */
2118 if (devslp
& PORT_DEVSLP_ADSE
) {
2119 writel(devslp
& ~PORT_DEVSLP_ADSE
,
2120 port_mmio
+ PORT_DEVSLP
);
2121 err_mask
= ata_dev_set_feature(dev
,
2122 SETFEATURES_SATA_DISABLE
,
2124 if (err_mask
&& err_mask
!= AC_ERR_DEV
)
2125 ata_dev_warn(dev
, "failed to disable DEVSLP\n");
2130 /* device sleep was already enabled */
2131 if (devslp
& PORT_DEVSLP_ADSE
)
2134 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2135 rc
= ahci_stop_engine(ap
);
2139 dm
= (devslp
& PORT_DEVSLP_DM_MASK
) >> PORT_DEVSLP_DM_OFFSET
;
2140 dito
= devslp_idle_timeout
/ (dm
+ 1);
2144 /* Use the nominal value 10 ms if the read MDAT is zero,
2145 * the nominal value of DETO is 20 ms.
2147 if (dev
->devslp_timing
[ATA_LOG_DEVSLP_VALID
] &
2148 ATA_LOG_DEVSLP_VALID_MASK
) {
2149 mdat
= dev
->devslp_timing
[ATA_LOG_DEVSLP_MDAT
] &
2150 ATA_LOG_DEVSLP_MDAT_MASK
;
2153 deto
= dev
->devslp_timing
[ATA_LOG_DEVSLP_DETO
];
2161 devslp
|= ((dito
<< PORT_DEVSLP_DITO_OFFSET
) |
2162 (mdat
<< PORT_DEVSLP_MDAT_OFFSET
) |
2163 (deto
<< PORT_DEVSLP_DETO_OFFSET
) |
2165 writel(devslp
, port_mmio
+ PORT_DEVSLP
);
2167 hpriv
->start_engine(ap
);
2169 /* enable device sleep feature for the drive */
2170 err_mask
= ata_dev_set_feature(dev
,
2171 SETFEATURES_SATA_ENABLE
,
2173 if (err_mask
&& err_mask
!= AC_ERR_DEV
)
2174 ata_dev_warn(dev
, "failed to enable DEVSLP\n");
2177 static void ahci_enable_fbs(struct ata_port
*ap
)
2179 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
2180 struct ahci_port_priv
*pp
= ap
->private_data
;
2181 void __iomem
*port_mmio
= ahci_port_base(ap
);
2185 if (!pp
->fbs_supported
)
2188 fbs
= readl(port_mmio
+ PORT_FBS
);
2189 if (fbs
& PORT_FBS_EN
) {
2190 pp
->fbs_enabled
= true;
2191 pp
->fbs_last_dev
= -1; /* initialization */
2195 rc
= ahci_stop_engine(ap
);
2199 writel(fbs
| PORT_FBS_EN
, port_mmio
+ PORT_FBS
);
2200 fbs
= readl(port_mmio
+ PORT_FBS
);
2201 if (fbs
& PORT_FBS_EN
) {
2202 dev_info(ap
->host
->dev
, "FBS is enabled\n");
2203 pp
->fbs_enabled
= true;
2204 pp
->fbs_last_dev
= -1; /* initialization */
2206 dev_err(ap
->host
->dev
, "Failed to enable FBS\n");
2208 hpriv
->start_engine(ap
);
2211 static void ahci_disable_fbs(struct ata_port
*ap
)
2213 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
2214 struct ahci_port_priv
*pp
= ap
->private_data
;
2215 void __iomem
*port_mmio
= ahci_port_base(ap
);
2219 if (!pp
->fbs_supported
)
2222 fbs
= readl(port_mmio
+ PORT_FBS
);
2223 if ((fbs
& PORT_FBS_EN
) == 0) {
2224 pp
->fbs_enabled
= false;
2228 rc
= ahci_stop_engine(ap
);
2232 writel(fbs
& ~PORT_FBS_EN
, port_mmio
+ PORT_FBS
);
2233 fbs
= readl(port_mmio
+ PORT_FBS
);
2234 if (fbs
& PORT_FBS_EN
)
2235 dev_err(ap
->host
->dev
, "Failed to disable FBS\n");
2237 dev_info(ap
->host
->dev
, "FBS is disabled\n");
2238 pp
->fbs_enabled
= false;
2241 hpriv
->start_engine(ap
);
2244 static void ahci_pmp_attach(struct ata_port
*ap
)
2246 void __iomem
*port_mmio
= ahci_port_base(ap
);
2247 struct ahci_port_priv
*pp
= ap
->private_data
;
2250 cmd
= readl(port_mmio
+ PORT_CMD
);
2251 cmd
|= PORT_CMD_PMP
;
2252 writel(cmd
, port_mmio
+ PORT_CMD
);
2254 ahci_enable_fbs(ap
);
2256 pp
->intr_mask
|= PORT_IRQ_BAD_PMP
;
2259 * We must not change the port interrupt mask register if the
2260 * port is marked frozen, the value in pp->intr_mask will be
2261 * restored later when the port is thawed.
2263 * Note that during initialization, the port is marked as
2264 * frozen since the irq handler is not yet registered.
2266 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
))
2267 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
2270 static void ahci_pmp_detach(struct ata_port
*ap
)
2272 void __iomem
*port_mmio
= ahci_port_base(ap
);
2273 struct ahci_port_priv
*pp
= ap
->private_data
;
2276 ahci_disable_fbs(ap
);
2278 cmd
= readl(port_mmio
+ PORT_CMD
);
2279 cmd
&= ~PORT_CMD_PMP
;
2280 writel(cmd
, port_mmio
+ PORT_CMD
);
2282 pp
->intr_mask
&= ~PORT_IRQ_BAD_PMP
;
2284 /* see comment above in ahci_pmp_attach() */
2285 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
))
2286 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
2289 int ahci_port_resume(struct ata_port
*ap
)
2291 ahci_rpm_get_port(ap
);
2294 ahci_start_port(ap
);
2296 if (sata_pmp_attached(ap
))
2297 ahci_pmp_attach(ap
);
2299 ahci_pmp_detach(ap
);
2303 EXPORT_SYMBOL_GPL(ahci_port_resume
);
2306 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
)
2308 const char *emsg
= NULL
;
2311 rc
= ahci_deinit_port(ap
, &emsg
);
2313 ahci_power_down(ap
);
2315 ata_port_err(ap
, "%s (%d)\n", emsg
, rc
);
2316 ata_port_freeze(ap
);
2319 ahci_rpm_put_port(ap
);
2324 static int ahci_port_start(struct ata_port
*ap
)
2326 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
2327 struct device
*dev
= ap
->host
->dev
;
2328 struct ahci_port_priv
*pp
;
2331 size_t dma_sz
, rx_fis_sz
;
2333 pp
= devm_kzalloc(dev
, sizeof(*pp
), GFP_KERNEL
);
2337 if (ap
->host
->n_ports
> 1) {
2338 pp
->irq_desc
= devm_kzalloc(dev
, 8, GFP_KERNEL
);
2339 if (!pp
->irq_desc
) {
2340 devm_kfree(dev
, pp
);
2343 snprintf(pp
->irq_desc
, 8,
2344 "%s%d", dev_driver_string(dev
), ap
->port_no
);
2347 /* check FBS capability */
2348 if ((hpriv
->cap
& HOST_CAP_FBS
) && sata_pmp_supported(ap
)) {
2349 void __iomem
*port_mmio
= ahci_port_base(ap
);
2350 u32 cmd
= readl(port_mmio
+ PORT_CMD
);
2351 if (cmd
& PORT_CMD_FBSCP
)
2352 pp
->fbs_supported
= true;
2353 else if (hpriv
->flags
& AHCI_HFLAG_YES_FBS
) {
2354 dev_info(dev
, "port %d can do FBS, forcing FBSCP\n",
2356 pp
->fbs_supported
= true;
2358 dev_warn(dev
, "port %d is not capable of FBS\n",
2362 if (pp
->fbs_supported
) {
2363 dma_sz
= AHCI_PORT_PRIV_FBS_DMA_SZ
;
2364 rx_fis_sz
= AHCI_RX_FIS_SZ
* 16;
2366 dma_sz
= AHCI_PORT_PRIV_DMA_SZ
;
2367 rx_fis_sz
= AHCI_RX_FIS_SZ
;
2370 mem
= dmam_alloc_coherent(dev
, dma_sz
, &mem_dma
, GFP_KERNEL
);
2373 memset(mem
, 0, dma_sz
);
2376 * First item in chunk of DMA memory: 32-slot command table,
2377 * 32 bytes each in size
2380 pp
->cmd_slot_dma
= mem_dma
;
2382 mem
+= AHCI_CMD_SLOT_SZ
;
2383 mem_dma
+= AHCI_CMD_SLOT_SZ
;
2386 * Second item: Received-FIS area
2389 pp
->rx_fis_dma
= mem_dma
;
2392 mem_dma
+= rx_fis_sz
;
2395 * Third item: data area for storing a single command
2396 * and its scatter-gather table
2399 pp
->cmd_tbl_dma
= mem_dma
;
2402 * Save off initial list of interrupts to be enabled.
2403 * This could be changed later
2405 pp
->intr_mask
= DEF_PORT_IRQ
;
2408 * Switch to per-port locking in case each port has its own MSI vector.
2410 if (hpriv
->flags
& AHCI_HFLAG_MULTI_MSI
) {
2411 spin_lock_init(&pp
->lock
);
2412 ap
->lock
= &pp
->lock
;
2415 ap
->private_data
= pp
;
2417 /* engage engines, captain */
2418 return ahci_port_resume(ap
);
2421 static void ahci_port_stop(struct ata_port
*ap
)
2423 const char *emsg
= NULL
;
2424 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
2425 void __iomem
*host_mmio
= hpriv
->mmio
;
2428 /* de-initialize port */
2429 rc
= ahci_deinit_port(ap
, &emsg
);
2431 ata_port_warn(ap
, "%s (%d)\n", emsg
, rc
);
2434 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2437 writel(1 << ap
->port_no
, host_mmio
+ HOST_IRQ_STAT
);
2440 void ahci_print_info(struct ata_host
*host
, const char *scc_s
)
2442 struct ahci_host_priv
*hpriv
= host
->private_data
;
2443 u32 vers
, cap
, cap2
, impl
, speed
;
2444 const char *speed_s
;
2446 vers
= hpriv
->version
;
2449 impl
= hpriv
->port_map
;
2451 speed
= (cap
>> 20) & 0xf;
2454 else if (speed
== 2)
2456 else if (speed
== 3)
2462 "AHCI %02x%02x.%02x%02x "
2463 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2466 (vers
>> 24) & 0xff,
2467 (vers
>> 16) & 0xff,
2471 ((cap
>> 8) & 0x1f) + 1,
2485 cap
& HOST_CAP_64
? "64bit " : "",
2486 cap
& HOST_CAP_NCQ
? "ncq " : "",
2487 cap
& HOST_CAP_SNTF
? "sntf " : "",
2488 cap
& HOST_CAP_MPS
? "ilck " : "",
2489 cap
& HOST_CAP_SSS
? "stag " : "",
2490 cap
& HOST_CAP_ALPM
? "pm " : "",
2491 cap
& HOST_CAP_LED
? "led " : "",
2492 cap
& HOST_CAP_CLO
? "clo " : "",
2493 cap
& HOST_CAP_ONLY
? "only " : "",
2494 cap
& HOST_CAP_PMP
? "pmp " : "",
2495 cap
& HOST_CAP_FBS
? "fbs " : "",
2496 cap
& HOST_CAP_PIO_MULTI
? "pio " : "",
2497 cap
& HOST_CAP_SSC
? "slum " : "",
2498 cap
& HOST_CAP_PART
? "part " : "",
2499 cap
& HOST_CAP_CCC
? "ccc " : "",
2500 cap
& HOST_CAP_EMS
? "ems " : "",
2501 cap
& HOST_CAP_SXS
? "sxs " : "",
2502 cap2
& HOST_CAP2_DESO
? "deso " : "",
2503 cap2
& HOST_CAP2_SADM
? "sadm " : "",
2504 cap2
& HOST_CAP2_SDS
? "sds " : "",
2505 cap2
& HOST_CAP2_APST
? "apst " : "",
2506 cap2
& HOST_CAP2_NVMHCI
? "nvmp " : "",
2507 cap2
& HOST_CAP2_BOH
? "boh " : ""
2510 EXPORT_SYMBOL_GPL(ahci_print_info
);
2512 void ahci_set_em_messages(struct ahci_host_priv
*hpriv
,
2513 struct ata_port_info
*pi
)
2516 void __iomem
*mmio
= hpriv
->mmio
;
2517 u32 em_loc
= readl(mmio
+ HOST_EM_LOC
);
2518 u32 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
2520 if (!ahci_em_messages
|| !(hpriv
->cap
& HOST_CAP_EMS
))
2523 messages
= (em_ctl
& EM_CTRL_MSG_TYPE
) >> 16;
2527 hpriv
->em_loc
= ((em_loc
>> 16) * 4);
2528 hpriv
->em_buf_sz
= ((em_loc
& 0xff) * 4);
2529 hpriv
->em_msg_type
= messages
;
2530 pi
->flags
|= ATA_FLAG_EM
;
2531 if (!(em_ctl
& EM_CTL_ALHD
))
2532 pi
->flags
|= ATA_FLAG_SW_ACTIVITY
;
2535 EXPORT_SYMBOL_GPL(ahci_set_em_messages
);
2537 static int ahci_host_activate_multi_irqs(struct ata_host
*host
,
2538 struct scsi_host_template
*sht
)
2540 struct ahci_host_priv
*hpriv
= host
->private_data
;
2543 rc
= ata_host_start(host
);
2547 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2548 * allocated. That is one MSI per port, starting from @irq.
2550 for (i
= 0; i
< host
->n_ports
; i
++) {
2551 struct ahci_port_priv
*pp
= host
->ports
[i
]->private_data
;
2552 int irq
= hpriv
->get_irq_vector(host
, i
);
2554 /* Do not receive interrupts sent by dummy ports */
2560 rc
= devm_request_irq(host
->dev
, irq
, ahci_multi_irqs_intr_hard
,
2561 0, pp
->irq_desc
, host
->ports
[i
]);
2565 ata_port_desc(host
->ports
[i
], "irq %d", irq
);
2568 return ata_host_register(host
, sht
);
2572 * ahci_host_activate - start AHCI host, request IRQs and register it
2573 * @host: target ATA host
2574 * @sht: scsi_host_template to use when registering the host
2577 * Inherited from calling layer (may sleep).
2580 * 0 on success, -errno otherwise.
2582 int ahci_host_activate(struct ata_host
*host
, struct scsi_host_template
*sht
)
2584 struct ahci_host_priv
*hpriv
= host
->private_data
;
2585 int irq
= hpriv
->irq
;
2588 if (hpriv
->flags
& AHCI_HFLAG_MULTI_MSI
) {
2589 if (hpriv
->irq_handler
)
2591 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2592 if (!hpriv
->get_irq_vector
) {
2594 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2598 rc
= ahci_host_activate_multi_irqs(host
, sht
);
2600 rc
= ata_host_activate(host
, irq
, hpriv
->irq_handler
,
2607 EXPORT_SYMBOL_GPL(ahci_host_activate
);
2609 MODULE_AUTHOR("Jeff Garzik");
2610 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2611 MODULE_LICENSE("GPL");