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Merge tag 'spi-fix-v5.3-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
[mirror_ubuntu-focal-kernel.git] / drivers / ata / pata_hpt37x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
4 *
5 * This driver is heavily based upon:
6 *
7 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 *
9 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
10 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
11 * Portions Copyright (C) 2003 Red Hat Inc
12 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
13 *
14 * TODO
15 * Look into engine reset on timeout errors. Should not be required.
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <scsi/scsi_host.h>
26 #include <linux/libata.h>
27
28 #define DRV_NAME "pata_hpt37x"
29 #define DRV_VERSION "0.6.23"
30
31 struct hpt_clock {
32 u8 xfer_speed;
33 u32 timing;
34 };
35
36 struct hpt_chip {
37 const char *name;
38 unsigned int base;
39 struct hpt_clock const *clocks[4];
40 };
41
42 /* key for bus clock timings
43 * bit
44 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
45 * cycles = value + 1
46 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
47 * cycles = value + 1
48 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
49 * register access.
50 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
51 * register access.
52 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
53 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
54 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
55 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
56 * register access.
57 * 28 UDMA enable.
58 * 29 DMA enable.
59 * 30 PIO_MST enable. If set, the chip is in bus master mode during
60 * PIO xfer.
61 * 31 FIFO enable. Only for PIO.
62 */
63
64 static struct hpt_clock hpt37x_timings_33[] = {
65 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
66 { XFER_UDMA_5, 0x12446231 },
67 { XFER_UDMA_4, 0x12446231 },
68 { XFER_UDMA_3, 0x126c6231 },
69 { XFER_UDMA_2, 0x12486231 },
70 { XFER_UDMA_1, 0x124c6233 },
71 { XFER_UDMA_0, 0x12506297 },
72
73 { XFER_MW_DMA_2, 0x22406c31 },
74 { XFER_MW_DMA_1, 0x22406c33 },
75 { XFER_MW_DMA_0, 0x22406c97 },
76
77 { XFER_PIO_4, 0x06414e31 },
78 { XFER_PIO_3, 0x06414e42 },
79 { XFER_PIO_2, 0x06414e53 },
80 { XFER_PIO_1, 0x06814e93 },
81 { XFER_PIO_0, 0x06814ea7 }
82 };
83
84 static struct hpt_clock hpt37x_timings_50[] = {
85 { XFER_UDMA_6, 0x12848242 },
86 { XFER_UDMA_5, 0x12848242 },
87 { XFER_UDMA_4, 0x12ac8242 },
88 { XFER_UDMA_3, 0x128c8242 },
89 { XFER_UDMA_2, 0x120c8242 },
90 { XFER_UDMA_1, 0x12148254 },
91 { XFER_UDMA_0, 0x121882ea },
92
93 { XFER_MW_DMA_2, 0x22808242 },
94 { XFER_MW_DMA_1, 0x22808254 },
95 { XFER_MW_DMA_0, 0x228082ea },
96
97 { XFER_PIO_4, 0x0a81f442 },
98 { XFER_PIO_3, 0x0a81f443 },
99 { XFER_PIO_2, 0x0a81f454 },
100 { XFER_PIO_1, 0x0ac1f465 },
101 { XFER_PIO_0, 0x0ac1f48a }
102 };
103
104 static struct hpt_clock hpt37x_timings_66[] = {
105 { XFER_UDMA_6, 0x1c869c62 },
106 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
107 { XFER_UDMA_4, 0x1c8a9c62 },
108 { XFER_UDMA_3, 0x1c8e9c62 },
109 { XFER_UDMA_2, 0x1c929c62 },
110 { XFER_UDMA_1, 0x1c9a9c62 },
111 { XFER_UDMA_0, 0x1c829c62 },
112
113 { XFER_MW_DMA_2, 0x2c829c62 },
114 { XFER_MW_DMA_1, 0x2c829c66 },
115 { XFER_MW_DMA_0, 0x2c829d2e },
116
117 { XFER_PIO_4, 0x0c829c62 },
118 { XFER_PIO_3, 0x0c829c84 },
119 { XFER_PIO_2, 0x0c829ca6 },
120 { XFER_PIO_1, 0x0d029d26 },
121 { XFER_PIO_0, 0x0d029d5e }
122 };
123
124
125 static const struct hpt_chip hpt370 = {
126 "HPT370",
127 48,
128 {
129 hpt37x_timings_33,
130 NULL,
131 NULL,
132 NULL
133 }
134 };
135
136 static const struct hpt_chip hpt370a = {
137 "HPT370A",
138 48,
139 {
140 hpt37x_timings_33,
141 NULL,
142 hpt37x_timings_50,
143 NULL
144 }
145 };
146
147 static const struct hpt_chip hpt372 = {
148 "HPT372",
149 55,
150 {
151 hpt37x_timings_33,
152 NULL,
153 hpt37x_timings_50,
154 hpt37x_timings_66
155 }
156 };
157
158 static const struct hpt_chip hpt302 = {
159 "HPT302",
160 66,
161 {
162 hpt37x_timings_33,
163 NULL,
164 hpt37x_timings_50,
165 hpt37x_timings_66
166 }
167 };
168
169 static const struct hpt_chip hpt371 = {
170 "HPT371",
171 66,
172 {
173 hpt37x_timings_33,
174 NULL,
175 hpt37x_timings_50,
176 hpt37x_timings_66
177 }
178 };
179
180 static const struct hpt_chip hpt372a = {
181 "HPT372A",
182 66,
183 {
184 hpt37x_timings_33,
185 NULL,
186 hpt37x_timings_50,
187 hpt37x_timings_66
188 }
189 };
190
191 static const struct hpt_chip hpt374 = {
192 "HPT374",
193 48,
194 {
195 hpt37x_timings_33,
196 NULL,
197 NULL,
198 NULL
199 }
200 };
201
202 /**
203 * hpt37x_find_mode - reset the hpt37x bus
204 * @ap: ATA port
205 * @speed: transfer mode
206 *
207 * Return the 32bit register programming information for this channel
208 * that matches the speed provided.
209 */
210
211 static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
212 {
213 struct hpt_clock *clocks = ap->host->private_data;
214
215 while (clocks->xfer_speed) {
216 if (clocks->xfer_speed == speed)
217 return clocks->timing;
218 clocks++;
219 }
220 BUG();
221 return 0xffffffffU; /* silence compiler warning */
222 }
223
224 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
225 const char * const list[])
226 {
227 unsigned char model_num[ATA_ID_PROD_LEN + 1];
228 int i;
229
230 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
231
232 i = match_string(list, -1, model_num);
233 if (i >= 0) {
234 pr_warn("%s is not supported for %s\n", modestr, list[i]);
235 return 1;
236 }
237 return 0;
238 }
239
240 static const char * const bad_ata33[] = {
241 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
242 "Maxtor 90845U3", "Maxtor 90650U2",
243 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
244 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
245 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
246 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
247 "Maxtor 90510D4",
248 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
249 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
250 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
251 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
252 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
253 NULL
254 };
255
256 static const char * const bad_ata100_5[] = {
257 "IBM-DTLA-307075",
258 "IBM-DTLA-307060",
259 "IBM-DTLA-307045",
260 "IBM-DTLA-307030",
261 "IBM-DTLA-307020",
262 "IBM-DTLA-307015",
263 "IBM-DTLA-305040",
264 "IBM-DTLA-305030",
265 "IBM-DTLA-305020",
266 "IC35L010AVER07-0",
267 "IC35L020AVER07-0",
268 "IC35L030AVER07-0",
269 "IC35L040AVER07-0",
270 "IC35L060AVER07-0",
271 "WDC AC310200R",
272 NULL
273 };
274
275 /**
276 * hpt370_filter - mode selection filter
277 * @adev: ATA device
278 *
279 * Block UDMA on devices that cause trouble with this controller.
280 */
281
282 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
283 {
284 if (adev->class == ATA_DEV_ATA) {
285 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
286 mask &= ~ATA_MASK_UDMA;
287 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
288 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
289 }
290 return mask;
291 }
292
293 /**
294 * hpt370a_filter - mode selection filter
295 * @adev: ATA device
296 *
297 * Block UDMA on devices that cause trouble with this controller.
298 */
299
300 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
301 {
302 if (adev->class == ATA_DEV_ATA) {
303 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
304 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
305 }
306 return mask;
307 }
308
309 /**
310 * hpt372_filter - mode selection filter
311 * @adev: ATA device
312 * @mask: mode mask
313 *
314 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
315 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
316 */
317 static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask)
318 {
319 if (ata_id_is_sata(adev->id))
320 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
321
322 return mask;
323 }
324
325 /**
326 * hpt37x_cable_detect - Detect the cable type
327 * @ap: ATA port to detect on
328 *
329 * Return the cable type attached to this port
330 */
331
332 static int hpt37x_cable_detect(struct ata_port *ap)
333 {
334 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
335 u8 scr2, ata66;
336
337 pci_read_config_byte(pdev, 0x5B, &scr2);
338 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
339
340 udelay(10); /* debounce */
341
342 /* Cable register now active */
343 pci_read_config_byte(pdev, 0x5A, &ata66);
344 /* Restore state */
345 pci_write_config_byte(pdev, 0x5B, scr2);
346
347 if (ata66 & (2 >> ap->port_no))
348 return ATA_CBL_PATA40;
349 else
350 return ATA_CBL_PATA80;
351 }
352
353 /**
354 * hpt374_fn1_cable_detect - Detect the cable type
355 * @ap: ATA port to detect on
356 *
357 * Return the cable type attached to this port
358 */
359
360 static int hpt374_fn1_cable_detect(struct ata_port *ap)
361 {
362 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
363 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
364 u16 mcr3;
365 u8 ata66;
366
367 /* Do the extra channel work */
368 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
369 /* Set bit 15 of 0x52 to enable TCBLID as input */
370 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
371 pci_read_config_byte(pdev, 0x5A, &ata66);
372 /* Reset TCBLID/FCBLID to output */
373 pci_write_config_word(pdev, mcrbase + 2, mcr3);
374
375 if (ata66 & (2 >> ap->port_no))
376 return ATA_CBL_PATA40;
377 else
378 return ATA_CBL_PATA80;
379 }
380
381 /**
382 * hpt37x_pre_reset - reset the hpt37x bus
383 * @link: ATA link to reset
384 * @deadline: deadline jiffies for the operation
385 *
386 * Perform the initial reset handling for the HPT37x.
387 */
388
389 static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
390 {
391 struct ata_port *ap = link->ap;
392 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
393 static const struct pci_bits hpt37x_enable_bits[] = {
394 { 0x50, 1, 0x04, 0x04 },
395 { 0x54, 1, 0x04, 0x04 }
396 };
397
398 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
399 return -ENOENT;
400
401 /* Reset the state machine */
402 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
403 udelay(100);
404
405 return ata_sff_prereset(link, deadline);
406 }
407
408 static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev,
409 u8 mode)
410 {
411 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
412 u32 addr1, addr2;
413 u32 reg, timing, mask;
414 u8 fast;
415
416 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
417 addr2 = 0x51 + 4 * ap->port_no;
418
419 /* Fast interrupt prediction disable, hold off interrupt disable */
420 pci_read_config_byte(pdev, addr2, &fast);
421 fast &= ~0x02;
422 fast |= 0x01;
423 pci_write_config_byte(pdev, addr2, fast);
424
425 /* Determine timing mask and find matching mode entry */
426 if (mode < XFER_MW_DMA_0)
427 mask = 0xcfc3ffff;
428 else if (mode < XFER_UDMA_0)
429 mask = 0x31c001ff;
430 else
431 mask = 0x303c0000;
432
433 timing = hpt37x_find_mode(ap, mode);
434
435 pci_read_config_dword(pdev, addr1, &reg);
436 reg = (reg & ~mask) | (timing & mask);
437 pci_write_config_dword(pdev, addr1, reg);
438 }
439 /**
440 * hpt370_set_piomode - PIO setup
441 * @ap: ATA interface
442 * @adev: device on the interface
443 *
444 * Perform PIO mode setup.
445 */
446
447 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
448 {
449 hpt370_set_mode(ap, adev, adev->pio_mode);
450 }
451
452 /**
453 * hpt370_set_dmamode - DMA timing setup
454 * @ap: ATA interface
455 * @adev: Device being configured
456 *
457 * Set up the channel for MWDMA or UDMA modes.
458 */
459
460 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
461 {
462 hpt370_set_mode(ap, adev, adev->dma_mode);
463 }
464
465 /**
466 * hpt370_bmdma_end - DMA engine stop
467 * @qc: ATA command
468 *
469 * Work around the HPT370 DMA engine.
470 */
471
472 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
473 {
474 struct ata_port *ap = qc->ap;
475 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
476 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
477 u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
478 u8 dma_cmd;
479
480 if (dma_stat & ATA_DMA_ACTIVE) {
481 udelay(20);
482 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
483 }
484 if (dma_stat & ATA_DMA_ACTIVE) {
485 /* Clear the engine */
486 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
487 udelay(10);
488 /* Stop DMA */
489 dma_cmd = ioread8(bmdma + ATA_DMA_CMD);
490 iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD);
491 /* Clear Error */
492 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
493 iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR,
494 bmdma + ATA_DMA_STATUS);
495 /* Clear the engine */
496 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
497 udelay(10);
498 }
499 ata_bmdma_stop(qc);
500 }
501
502 static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev,
503 u8 mode)
504 {
505 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
506 u32 addr1, addr2;
507 u32 reg, timing, mask;
508 u8 fast;
509
510 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
511 addr2 = 0x51 + 4 * ap->port_no;
512
513 /* Fast interrupt prediction disable, hold off interrupt disable */
514 pci_read_config_byte(pdev, addr2, &fast);
515 fast &= ~0x07;
516 pci_write_config_byte(pdev, addr2, fast);
517
518 /* Determine timing mask and find matching mode entry */
519 if (mode < XFER_MW_DMA_0)
520 mask = 0xcfc3ffff;
521 else if (mode < XFER_UDMA_0)
522 mask = 0x31c001ff;
523 else
524 mask = 0x303c0000;
525
526 timing = hpt37x_find_mode(ap, mode);
527
528 pci_read_config_dword(pdev, addr1, &reg);
529 reg = (reg & ~mask) | (timing & mask);
530 pci_write_config_dword(pdev, addr1, reg);
531 }
532
533 /**
534 * hpt372_set_piomode - PIO setup
535 * @ap: ATA interface
536 * @adev: device on the interface
537 *
538 * Perform PIO mode setup.
539 */
540
541 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
542 {
543 hpt372_set_mode(ap, adev, adev->pio_mode);
544 }
545
546 /**
547 * hpt372_set_dmamode - DMA timing setup
548 * @ap: ATA interface
549 * @adev: Device being configured
550 *
551 * Set up the channel for MWDMA or UDMA modes.
552 */
553
554 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
555 {
556 hpt372_set_mode(ap, adev, adev->dma_mode);
557 }
558
559 /**
560 * hpt37x_bmdma_end - DMA engine stop
561 * @qc: ATA command
562 *
563 * Clean up after the HPT372 and later DMA engine
564 */
565
566 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
567 {
568 struct ata_port *ap = qc->ap;
569 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
570 int mscreg = 0x50 + 4 * ap->port_no;
571 u8 bwsr_stat, msc_stat;
572
573 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
574 pci_read_config_byte(pdev, mscreg, &msc_stat);
575 if (bwsr_stat & (1 << ap->port_no))
576 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
577 ata_bmdma_stop(qc);
578 }
579
580
581 static struct scsi_host_template hpt37x_sht = {
582 ATA_BMDMA_SHT(DRV_NAME),
583 };
584
585 /*
586 * Configuration for HPT370
587 */
588
589 static struct ata_port_operations hpt370_port_ops = {
590 .inherits = &ata_bmdma_port_ops,
591
592 .bmdma_stop = hpt370_bmdma_stop,
593
594 .mode_filter = hpt370_filter,
595 .cable_detect = hpt37x_cable_detect,
596 .set_piomode = hpt370_set_piomode,
597 .set_dmamode = hpt370_set_dmamode,
598 .prereset = hpt37x_pre_reset,
599 };
600
601 /*
602 * Configuration for HPT370A. Close to 370 but less filters
603 */
604
605 static struct ata_port_operations hpt370a_port_ops = {
606 .inherits = &hpt370_port_ops,
607 .mode_filter = hpt370a_filter,
608 };
609
610 /*
611 * Configuration for HPT371 and HPT302. Slightly different PIO and DMA
612 * mode setting functionality.
613 */
614
615 static struct ata_port_operations hpt302_port_ops = {
616 .inherits = &ata_bmdma_port_ops,
617
618 .bmdma_stop = hpt37x_bmdma_stop,
619
620 .cable_detect = hpt37x_cable_detect,
621 .set_piomode = hpt372_set_piomode,
622 .set_dmamode = hpt372_set_dmamode,
623 .prereset = hpt37x_pre_reset,
624 };
625
626 /*
627 * Configuration for HPT372. Mode setting works like 371 and 302
628 * but we have a mode filter.
629 */
630
631 static struct ata_port_operations hpt372_port_ops = {
632 .inherits = &hpt302_port_ops,
633 .mode_filter = hpt372_filter,
634 };
635
636 /*
637 * Configuration for HPT374. Mode setting and filtering works like 372
638 * but we have a different cable detection procedure for function 1.
639 */
640
641 static struct ata_port_operations hpt374_fn1_port_ops = {
642 .inherits = &hpt372_port_ops,
643 .cable_detect = hpt374_fn1_cable_detect,
644 };
645
646 /**
647 * hpt37x_clock_slot - Turn timing to PC clock entry
648 * @freq: Reported frequency timing
649 * @base: Base timing
650 *
651 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
652 * and 3 for 66Mhz)
653 */
654
655 static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
656 {
657 unsigned int f = (base * freq) / 192; /* Mhz */
658 if (f < 40)
659 return 0; /* 33Mhz slot */
660 if (f < 45)
661 return 1; /* 40Mhz slot */
662 if (f < 55)
663 return 2; /* 50Mhz slot */
664 return 3; /* 60Mhz slot */
665 }
666
667 /**
668 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
669 * @dev: PCI device
670 *
671 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
672 * succeeds
673 */
674
675 static int hpt37x_calibrate_dpll(struct pci_dev *dev)
676 {
677 u8 reg5b;
678 u32 reg5c;
679 int tries;
680
681 for (tries = 0; tries < 0x5000; tries++) {
682 udelay(50);
683 pci_read_config_byte(dev, 0x5b, &reg5b);
684 if (reg5b & 0x80) {
685 /* See if it stays set */
686 for (tries = 0; tries < 0x1000; tries++) {
687 pci_read_config_byte(dev, 0x5b, &reg5b);
688 /* Failed ? */
689 if ((reg5b & 0x80) == 0)
690 return 0;
691 }
692 /* Turn off tuning, we have the DPLL set */
693 pci_read_config_dword(dev, 0x5c, &reg5c);
694 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
695 return 1;
696 }
697 }
698 /* Never went stable */
699 return 0;
700 }
701
702 static u32 hpt374_read_freq(struct pci_dev *pdev)
703 {
704 u32 freq;
705 unsigned long io_base = pci_resource_start(pdev, 4);
706
707 if (PCI_FUNC(pdev->devfn) & 1) {
708 struct pci_dev *pdev_0;
709
710 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
711 /* Someone hot plugged the controller on us ? */
712 if (pdev_0 == NULL)
713 return 0;
714 io_base = pci_resource_start(pdev_0, 4);
715 freq = inl(io_base + 0x90);
716 pci_dev_put(pdev_0);
717 } else
718 freq = inl(io_base + 0x90);
719 return freq;
720 }
721
722 /**
723 * hpt37x_init_one - Initialise an HPT37X/302
724 * @dev: PCI device
725 * @id: Entry in match table
726 *
727 * Initialise an HPT37x device. There are some interesting complications
728 * here. Firstly the chip may report 366 and be one of several variants.
729 * Secondly all the timings depend on the clock for the chip which we must
730 * detect and look up
731 *
732 * This is the known chip mappings. It may be missing a couple of later
733 * releases.
734 *
735 * Chip version PCI Rev Notes
736 * HPT366 4 (HPT366) 0 Other driver
737 * HPT366 4 (HPT366) 1 Other driver
738 * HPT368 4 (HPT366) 2 Other driver
739 * HPT370 4 (HPT366) 3 UDMA100
740 * HPT370A 4 (HPT366) 4 UDMA100
741 * HPT372 4 (HPT366) 5 UDMA133 (1)
742 * HPT372N 4 (HPT366) 6 Other driver
743 * HPT372A 5 (HPT372) 1 UDMA133 (1)
744 * HPT372N 5 (HPT372) 2 Other driver
745 * HPT302 6 (HPT302) 1 UDMA133
746 * HPT302N 6 (HPT302) 2 Other driver
747 * HPT371 7 (HPT371) * UDMA133
748 * HPT374 8 (HPT374) * UDMA133 4 channel
749 * HPT372N 9 (HPT372N) * Other driver
750 *
751 * (1) UDMA133 support depends on the bus clock
752 */
753
754 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
755 {
756 /* HPT370 - UDMA100 */
757 static const struct ata_port_info info_hpt370 = {
758 .flags = ATA_FLAG_SLAVE_POSS,
759 .pio_mask = ATA_PIO4,
760 .mwdma_mask = ATA_MWDMA2,
761 .udma_mask = ATA_UDMA5,
762 .port_ops = &hpt370_port_ops
763 };
764 /* HPT370A - UDMA100 */
765 static const struct ata_port_info info_hpt370a = {
766 .flags = ATA_FLAG_SLAVE_POSS,
767 .pio_mask = ATA_PIO4,
768 .mwdma_mask = ATA_MWDMA2,
769 .udma_mask = ATA_UDMA5,
770 .port_ops = &hpt370a_port_ops
771 };
772 /* HPT370 - UDMA66 */
773 static const struct ata_port_info info_hpt370_33 = {
774 .flags = ATA_FLAG_SLAVE_POSS,
775 .pio_mask = ATA_PIO4,
776 .mwdma_mask = ATA_MWDMA2,
777 .udma_mask = ATA_UDMA4,
778 .port_ops = &hpt370_port_ops
779 };
780 /* HPT370A - UDMA66 */
781 static const struct ata_port_info info_hpt370a_33 = {
782 .flags = ATA_FLAG_SLAVE_POSS,
783 .pio_mask = ATA_PIO4,
784 .mwdma_mask = ATA_MWDMA2,
785 .udma_mask = ATA_UDMA4,
786 .port_ops = &hpt370a_port_ops
787 };
788 /* HPT372 - UDMA133 */
789 static const struct ata_port_info info_hpt372 = {
790 .flags = ATA_FLAG_SLAVE_POSS,
791 .pio_mask = ATA_PIO4,
792 .mwdma_mask = ATA_MWDMA2,
793 .udma_mask = ATA_UDMA6,
794 .port_ops = &hpt372_port_ops
795 };
796 /* HPT371, 302 - UDMA133 */
797 static const struct ata_port_info info_hpt302 = {
798 .flags = ATA_FLAG_SLAVE_POSS,
799 .pio_mask = ATA_PIO4,
800 .mwdma_mask = ATA_MWDMA2,
801 .udma_mask = ATA_UDMA6,
802 .port_ops = &hpt302_port_ops
803 };
804 /* HPT374 - UDMA100, function 1 uses different cable_detect method */
805 static const struct ata_port_info info_hpt374_fn0 = {
806 .flags = ATA_FLAG_SLAVE_POSS,
807 .pio_mask = ATA_PIO4,
808 .mwdma_mask = ATA_MWDMA2,
809 .udma_mask = ATA_UDMA5,
810 .port_ops = &hpt372_port_ops
811 };
812 static const struct ata_port_info info_hpt374_fn1 = {
813 .flags = ATA_FLAG_SLAVE_POSS,
814 .pio_mask = ATA_PIO4,
815 .mwdma_mask = ATA_MWDMA2,
816 .udma_mask = ATA_UDMA5,
817 .port_ops = &hpt374_fn1_port_ops
818 };
819
820 static const int MHz[4] = { 33, 40, 50, 66 };
821 void *private_data = NULL;
822 const struct ata_port_info *ppi[] = { NULL, NULL };
823 u8 rev = dev->revision;
824 u8 irqmask;
825 u8 mcr1;
826 u32 freq;
827 int prefer_dpll = 1;
828
829 unsigned long iobase = pci_resource_start(dev, 4);
830
831 const struct hpt_chip *chip_table;
832 int clock_slot;
833 int rc;
834
835 rc = pcim_enable_device(dev);
836 if (rc)
837 return rc;
838
839 switch (dev->device) {
840 case PCI_DEVICE_ID_TTI_HPT366:
841 /* May be a later chip in disguise. Check */
842 /* Older chips are in the HPT366 driver. Ignore them */
843 if (rev < 3)
844 return -ENODEV;
845 /* N series chips have their own driver. Ignore */
846 if (rev == 6)
847 return -ENODEV;
848
849 switch (rev) {
850 case 3:
851 ppi[0] = &info_hpt370;
852 chip_table = &hpt370;
853 prefer_dpll = 0;
854 break;
855 case 4:
856 ppi[0] = &info_hpt370a;
857 chip_table = &hpt370a;
858 prefer_dpll = 0;
859 break;
860 case 5:
861 ppi[0] = &info_hpt372;
862 chip_table = &hpt372;
863 break;
864 default:
865 pr_err("Unknown HPT366 subtype, please report (%d)\n",
866 rev);
867 return -ENODEV;
868 }
869 break;
870 case PCI_DEVICE_ID_TTI_HPT372:
871 /* 372N if rev >= 2 */
872 if (rev >= 2)
873 return -ENODEV;
874 ppi[0] = &info_hpt372;
875 chip_table = &hpt372a;
876 break;
877 case PCI_DEVICE_ID_TTI_HPT302:
878 /* 302N if rev > 1 */
879 if (rev > 1)
880 return -ENODEV;
881 ppi[0] = &info_hpt302;
882 /* Check this */
883 chip_table = &hpt302;
884 break;
885 case PCI_DEVICE_ID_TTI_HPT371:
886 if (rev > 1)
887 return -ENODEV;
888 ppi[0] = &info_hpt302;
889 chip_table = &hpt371;
890 /*
891 * Single channel device, master is not present but the BIOS
892 * (or us for non x86) must mark it absent
893 */
894 pci_read_config_byte(dev, 0x50, &mcr1);
895 mcr1 &= ~0x04;
896 pci_write_config_byte(dev, 0x50, mcr1);
897 break;
898 case PCI_DEVICE_ID_TTI_HPT374:
899 chip_table = &hpt374;
900 if (!(PCI_FUNC(dev->devfn) & 1))
901 *ppi = &info_hpt374_fn0;
902 else
903 *ppi = &info_hpt374_fn1;
904 break;
905 default:
906 pr_err("PCI table is bogus, please report (%d)\n", dev->device);
907 return -ENODEV;
908 }
909 /* Ok so this is a chip we support */
910
911 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
912 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
913 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
914 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
915
916 pci_read_config_byte(dev, 0x5A, &irqmask);
917 irqmask &= ~0x10;
918 pci_write_config_byte(dev, 0x5a, irqmask);
919
920 /*
921 * default to pci clock. make sure MA15/16 are set to output
922 * to prevent drives having problems with 40-pin cables. Needed
923 * for some drives such as IBM-DTLA which will not enter ready
924 * state on reset when PDIAG is a input.
925 */
926
927 pci_write_config_byte(dev, 0x5b, 0x23);
928
929 /*
930 * HighPoint does this for HPT372A.
931 * NOTE: This register is only writeable via I/O space.
932 */
933 if (chip_table == &hpt372a)
934 outb(0x0e, iobase + 0x9c);
935
936 /*
937 * Some devices do not let this value be accessed via PCI space
938 * according to the old driver. In addition we must use the value
939 * from FN 0 on the HPT374.
940 */
941
942 if (chip_table == &hpt374) {
943 freq = hpt374_read_freq(dev);
944 if (freq == 0)
945 return -ENODEV;
946 } else
947 freq = inl(iobase + 0x90);
948
949 if ((freq >> 12) != 0xABCDE) {
950 int i;
951 u8 sr;
952 u32 total = 0;
953
954 pr_warn("BIOS has not set timing clocks\n");
955
956 /* This is the process the HPT371 BIOS is reported to use */
957 for (i = 0; i < 128; i++) {
958 pci_read_config_byte(dev, 0x78, &sr);
959 total += sr & 0x1FF;
960 udelay(15);
961 }
962 freq = total / 128;
963 }
964 freq &= 0x1FF;
965
966 /*
967 * Turn the frequency check into a band and then find a timing
968 * table to match it.
969 */
970
971 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
972 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
973 /*
974 * We need to try PLL mode instead
975 *
976 * For non UDMA133 capable devices we should
977 * use a 50MHz DPLL by choice
978 */
979 unsigned int f_low, f_high;
980 int dpll, adjust;
981
982 /* Compute DPLL */
983 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
984
985 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
986 f_high = f_low + 2;
987 if (clock_slot > 1)
988 f_high += 2;
989
990 /* Select the DPLL clock. */
991 pci_write_config_byte(dev, 0x5b, 0x21);
992 pci_write_config_dword(dev, 0x5C,
993 (f_high << 16) | f_low | 0x100);
994
995 for (adjust = 0; adjust < 8; adjust++) {
996 if (hpt37x_calibrate_dpll(dev))
997 break;
998 /*
999 * See if it'll settle at a fractionally
1000 * different clock
1001 */
1002 if (adjust & 1)
1003 f_low -= adjust >> 1;
1004 else
1005 f_high += adjust >> 1;
1006 pci_write_config_dword(dev, 0x5C,
1007 (f_high << 16) | f_low | 0x100);
1008 }
1009 if (adjust == 8) {
1010 pr_err("DPLL did not stabilize!\n");
1011 return -ENODEV;
1012 }
1013 if (dpll == 3)
1014 private_data = (void *)hpt37x_timings_66;
1015 else
1016 private_data = (void *)hpt37x_timings_50;
1017
1018 pr_info("bus clock %dMHz, using %dMHz DPLL\n",
1019 MHz[clock_slot], MHz[dpll]);
1020 } else {
1021 private_data = (void *)chip_table->clocks[clock_slot];
1022 /*
1023 * Perform a final fixup. Note that we will have used the
1024 * DPLL on the HPT372 which means we don't have to worry
1025 * about lack of UDMA133 support on lower clocks
1026 */
1027
1028 if (clock_slot < 2 && ppi[0] == &info_hpt370)
1029 ppi[0] = &info_hpt370_33;
1030 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
1031 ppi[0] = &info_hpt370a_33;
1032
1033 pr_info("%s using %dMHz bus clock\n",
1034 chip_table->name, MHz[clock_slot]);
1035 }
1036
1037 /* Now kick off ATA set up */
1038 return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
1039 }
1040
1041 static const struct pci_device_id hpt37x[] = {
1042 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1043 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1044 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1045 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1046 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1047
1048 { },
1049 };
1050
1051 static struct pci_driver hpt37x_pci_driver = {
1052 .name = DRV_NAME,
1053 .id_table = hpt37x,
1054 .probe = hpt37x_init_one,
1055 .remove = ata_pci_remove_one
1056 };
1057
1058 module_pci_driver(hpt37x_pci_driver);
1059
1060 MODULE_AUTHOR("Alan Cox");
1061 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1062 MODULE_LICENSE("GPL");
1063 MODULE_DEVICE_TABLE(pci, hpt37x);
1064 MODULE_VERSION(DRV_VERSION);
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