drivers/ata/pata_ninja32.c

   1 /*
   2  * pata_ninja32.c       - Ninja32 PATA for new ATA layer
   3  *                        (C) 2007 Red Hat Inc
   4  *                        Alan Cox <alan@redhat.com>
   5  *
   6  * Note: The controller like many controllers has shared timings for
   7  * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
   8  * in the dma_stop function. Thus we actually don't need a set_dmamode
   9  * method as the PIO method is always called and will set the right PIO
  10  * timing parameters.
  11  *
  12  * The Ninja32 Cardbus is not a generic SFF controller. Instead it is
  13  * laid out as follows off BAR 0. This is based upon Mark Lord's delkin
  14  * driver and the extensive analysis done by the BSD developers, notably
  15  * ITOH Yasufumi.
  16  *
  17  *      Base + 0x00 IRQ Status
  18  *      Base + 0x01 IRQ control
  19  *      Base + 0x02 Chipset control
  20  *      Base + 0x03 Unknown
  21  *      Base + 0x04 VDMA and reset control + wait bits
  22  *      Base + 0x08 BMIMBA
  23  *      Base + 0x0C DMA Length
  24  *      Base + 0x10 Taskfile
  25  *      Base + 0x18 BMDMA Status ?
  26  *      Base + 0x1C
  27  *      Base + 0x1D Bus master control
  28  *              bit 0 = enable
  29  *              bit 1 = 0 write/1 read
  30  *              bit 2 = 1 sgtable
  31  *              bit 3 = go
  32  *              bit 4-6 wait bits
  33  *              bit 7 = done
  34  *      Base + 0x1E AltStatus
  35  *      Base + 0x1F timing register
  36  */
  37
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/pci.h>
  41 #include <linux/init.h>
  42 #include <linux/blkdev.h>
  43 #include <linux/delay.h>
  44 #include <scsi/scsi_host.h>
  45 #include <linux/libata.h>
  46
  47 #define DRV_NAME "pata_ninja32"
  48 #define DRV_VERSION "0.0.1"
  49
  50
  51 /**
  52  *      ninja32_set_piomode     -       set initial PIO mode data
  53  *      @ap: ATA interface
  54  *      @adev: ATA device
  55  *
  56  *      Called to do the PIO mode setup. Our timing registers are shared
  57  *      but we want to set the PIO timing by default.
  58  */
  59
  60 static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev)
  61 {
  62         static u16 pio_timing[5] = {
  63                 0xd6, 0x85, 0x44, 0x33, 0x13
  64         };
  65         iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0],
  66                  ap->ioaddr.bmdma_addr + 0x1f);
  67         ap->private_data = adev;
  68 }
  69
  70
  71 static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
  72 {
  73         struct ata_device *adev = &ap->link.device[device];
  74         if (ap->private_data != adev) {
  75                 iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f);
  76                 ata_std_dev_select(ap, device);
  77                 ninja32_set_piomode(ap, adev);
  78         }
  79 }
  80
  81 static struct scsi_host_template ninja32_sht = {
  82         ATA_BMDMA_SHT(DRV_NAME),
  83 };
  84
  85 static struct ata_port_operations ninja32_port_ops = {
  86         .set_piomode    = ninja32_set_piomode,
  87         .mode_filter    = ata_pci_default_filter,
  88
  89         .tf_load        = ata_tf_load,
  90         .tf_read        = ata_tf_read,
  91         .check_status   = ata_check_status,
  92         .exec_command   = ata_exec_command,
  93         .dev_select     = ninja32_dev_select,
  94
  95         .freeze         = ata_bmdma_freeze,
  96         .thaw           = ata_bmdma_thaw,
  97         .error_handler  = ata_bmdma_error_handler,
  98         .post_internal_cmd = ata_bmdma_post_internal_cmd,
  99         .cable_detect   = ata_cable_40wire,
 100
 101         .bmdma_setup    = ata_bmdma_setup,
 102         .bmdma_start    = ata_bmdma_start,
 103         .bmdma_stop     = ata_bmdma_stop,
 104         .bmdma_status   = ata_bmdma_status,
 105
 106         .qc_prep        = ata_qc_prep,
 107         .qc_issue       = ata_qc_issue_prot,
 108
 109         .data_xfer      = ata_data_xfer,
 110
 111         .irq_handler    = ata_interrupt,
 112         .irq_clear      = ata_bmdma_irq_clear,
 113         .irq_on         = ata_irq_on,
 114
 115         .port_start     = ata_sff_port_start,
 116 };
 117
 118 static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 119 {
 120         struct ata_host *host;
 121         struct ata_port *ap;
 122         void __iomem *base;
 123         int rc;
 124
 125         host = ata_host_alloc(&dev->dev, 1);
 126         if (!host)
 127                 return -ENOMEM;
 128         ap = host->ports[0];
 129
 130         /* Set up the PCI device */
 131         rc = pcim_enable_device(dev);
 132         if (rc)
 133                 return rc;
 134         rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME);
 135         if (rc == -EBUSY)
 136                 pcim_pin_device(dev);
 137         if (rc)
 138                 return rc;
 139
 140         host->iomap = pcim_iomap_table(dev);
 141         rc = pci_set_dma_mask(dev, ATA_DMA_MASK);
 142         if (rc)
 143                 return rc;
 144         rc = pci_set_consistent_dma_mask(dev, ATA_DMA_MASK);
 145         if (rc)
 146                 return rc;
 147         pci_set_master(dev);
 148
 149         /* Set up the register mappings */
 150         base = host->iomap[0];
 151         if (!base)
 152                 return -ENOMEM;
 153         ap->ops = &ninja32_port_ops;
 154         ap->pio_mask = 0x1F;
 155         ap->flags |= ATA_FLAG_SLAVE_POSS;
 156
 157         ap->ioaddr.cmd_addr = base + 0x10;
 158         ap->ioaddr.ctl_addr = base + 0x1E;
 159         ap->ioaddr.altstatus_addr = base + 0x1E;
 160         ap->ioaddr.bmdma_addr = base;
 161         ata_std_ports(&ap->ioaddr);
 162
 163         iowrite8(0x05, base + 0x01);    /* Enable interrupt lines */
 164         iowrite8(0xBE, base + 0x02);    /* Burst, ?? setup */
 165         iowrite8(0x01, base + 0x03);    /* Unknown */
 166         iowrite8(0x20, base + 0x04);    /* WAIT0 */
 167         iowrite8(0x8f, base + 0x05);    /* Unknown */
 168         iowrite8(0xa4, base + 0x1c);    /* Unknown */
 169         iowrite8(0x83, base + 0x1d);    /* BMDMA control: WAIT0 */
 170         /* FIXME: Should we disable them at remove ? */
 171         return ata_host_activate(host, dev->irq, ata_interrupt,
 172                                  IRQF_SHARED, &ninja32_sht);
 173 }
 174
 175 static const struct pci_device_id ninja32[] = {
 176         { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 177         { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 178         { },
 179 };
 180
 181 static struct pci_driver ninja32_pci_driver = {
 182         .name           = DRV_NAME,
 183         .id_table       = ninja32,
 184         .probe          = ninja32_init_one,
 185         .remove         = ata_pci_remove_one
 186 };
 187
 188 static int __init ninja32_init(void)
 189 {
 190         return pci_register_driver(&ninja32_pci_driver);
 191 }
 192
 193 static void __exit ninja32_exit(void)
 194 {
 195         pci_unregister_driver(&ninja32_pci_driver);
 196 }
 197
 198 MODULE_AUTHOR("Alan Cox");
 199 MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
 200 MODULE_LICENSE("GPL");
 201 MODULE_DEVICE_TABLE(pci, ninja32);
 202 MODULE_VERSION(DRV_VERSION);
 203
 204 module_init(ninja32_init);
 205 module_exit(ninja32_exit);