2 * pata_ninja32.c - Ninja32 PATA for new ATA layer
4 * Alan Cox <alan@redhat.com>
6 * Note: The controller like many controllers has shared timings for
7 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
8 * in the dma_stop function. Thus we actually don't need a set_dmamode
9 * method as the PIO method is always called and will set the right PIO
12 * The Ninja32 Cardbus is not a generic SFF controller. Instead it is
13 * laid out as follows off BAR 0. This is based upon Mark Lord's delkin
14 * driver and the extensive analysis done by the BSD developers, notably
17 * Base + 0x00 IRQ Status
18 * Base + 0x01 IRQ control
19 * Base + 0x02 Chipset control
20 * Base + 0x04 VDMA and reset control + wait bits
22 * Base + 0x0C DMA Length
23 * Base + 0x10 Taskfile
24 * Base + 0x18 BMDMA Status ?
26 * Base + 0x1D Bus master control
28 * bit 1 = 0 write/1 read
33 * Base + 0x1E AltStatus
34 * Base + 0x1F timing register
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
46 #define DRV_NAME "pata_ninja32"
47 #define DRV_VERSION "0.0.1"
51 * ninja32_set_piomode - set initial PIO mode data
55 * Called to do the PIO mode setup. Our timing registers are shared
56 * but we want to set the PIO timing by default.
59 static void ninja32_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
61 static u16 pio_timing
[5] = {
62 0xd6, 0x85, 0x44, 0x33, 0x13
64 iowrite8(pio_timing
[adev
->pio_mode
- XFER_PIO_0
], ap
->ioaddr
.bmdma_addr
+ 0x1f);
65 ap
->private_data
= adev
;
69 static void ninja32_dev_select(struct ata_port
*ap
, unsigned int device
)
71 struct ata_device
*adev
= &ap
->link
.device
[device
];
72 if (ap
->private_data
!= adev
) {
73 iowrite8(0xd6, ap
->ioaddr
.bmdma_addr
+ 0x1f);
74 ata_std_dev_select(ap
, device
);
75 ninja32_set_piomode(ap
, adev
);
79 static struct scsi_host_template ninja32_sht
= {
80 .module
= THIS_MODULE
,
82 .ioctl
= ata_scsi_ioctl
,
83 .queuecommand
= ata_scsi_queuecmd
,
84 .can_queue
= ATA_DEF_QUEUE
,
85 .this_id
= ATA_SHT_THIS_ID
,
86 .sg_tablesize
= LIBATA_MAX_PRD
,
87 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
88 .emulated
= ATA_SHT_EMULATED
,
89 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
90 .proc_name
= DRV_NAME
,
91 .dma_boundary
= ATA_DMA_BOUNDARY
,
92 .slave_configure
= ata_scsi_slave_config
,
93 .slave_destroy
= ata_scsi_slave_destroy
,
94 .bios_param
= ata_std_bios_param
,
97 static struct ata_port_operations ninja32_port_ops
= {
98 .set_piomode
= ninja32_set_piomode
,
99 .mode_filter
= ata_pci_default_filter
,
101 .tf_load
= ata_tf_load
,
102 .tf_read
= ata_tf_read
,
103 .check_status
= ata_check_status
,
104 .exec_command
= ata_exec_command
,
105 .dev_select
= ninja32_dev_select
,
107 .freeze
= ata_bmdma_freeze
,
108 .thaw
= ata_bmdma_thaw
,
109 .error_handler
= ata_bmdma_error_handler
,
110 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
111 .cable_detect
= ata_cable_40wire
,
113 .bmdma_setup
= ata_bmdma_setup
,
114 .bmdma_start
= ata_bmdma_start
,
115 .bmdma_stop
= ata_bmdma_stop
,
116 .bmdma_status
= ata_bmdma_status
,
118 .qc_prep
= ata_qc_prep
,
119 .qc_issue
= ata_qc_issue_prot
,
121 .data_xfer
= ata_data_xfer
,
123 .irq_handler
= ata_interrupt
,
124 .irq_clear
= ata_bmdma_irq_clear
,
125 .irq_on
= ata_irq_on
,
127 .port_start
= ata_sff_port_start
,
130 static int ninja32_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
132 struct ata_host
*host
;
137 host
= ata_host_alloc(&dev
->dev
, 1);
142 /* Set up the PCI device */
143 rc
= pcim_enable_device(dev
);
146 rc
= pcim_iomap_regions(dev
, 1 << 0, DRV_NAME
);
148 pcim_pin_device(dev
);
152 host
->iomap
= pcim_iomap_table(dev
);
153 rc
= pci_set_dma_mask(dev
, ATA_DMA_MASK
);
156 rc
= pci_set_consistent_dma_mask(dev
, ATA_DMA_MASK
);
161 /* Set up the register mappings */
162 base
= host
->iomap
[0];
165 ap
->ops
= &ninja32_port_ops
;
167 ap
->flags
|= ATA_FLAG_SLAVE_POSS
;
169 ap
->ioaddr
.cmd_addr
= base
+ 0x10;
170 ap
->ioaddr
.ctl_addr
= base
+ 0x1E;
171 ap
->ioaddr
.altstatus_addr
= base
+ 0x1E;
172 ap
->ioaddr
.bmdma_addr
= base
;
173 ata_std_ports(&ap
->ioaddr
);
175 iowrite8(0x05, base
+ 0x01); /* Enable interrupt lines */
176 iowrite8(0xB3, base
+ 0x02); /* Burst, ?? setup */
177 iowrite8(0x00, base
+ 0x04); /* WAIT0 ? */
178 /* FIXME: Should we disable them at remove ? */
179 return ata_host_activate(host
, dev
->irq
, ata_interrupt
, IRQF_SHARED
, &ninja32_sht
);
182 static const struct pci_device_id ninja32
[] = {
183 { 0x1145, 0xf021, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
184 { 0x1145, 0xf024, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
188 static struct pci_driver ninja32_pci_driver
= {
191 .probe
= ninja32_init_one
,
192 .remove
= ata_pci_remove_one
195 static int __init
ninja32_init(void)
197 return pci_register_driver(&ninja32_pci_driver
);
200 static void __exit
ninja32_exit(void)
202 pci_unregister_driver(&ninja32_pci_driver
);
205 MODULE_AUTHOR("Alan Cox");
206 MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
207 MODULE_LICENSE("GPL");
208 MODULE_DEVICE_TABLE(pci
, ninja32
);
209 MODULE_VERSION(DRV_VERSION
);
211 module_init(ninja32_init
);
212 module_exit(ninja32_exit
);