2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
22 * Hardware information only available under NDA.
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <scsi/scsi.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
37 #define DRV_NAME "pata_pdc2027x"
38 #define DRV_VERSION "0.74-ac5"
42 #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
44 #define PDPRINTK(fmt, args...)
53 PDC_100_MHZ
= 100000000,
54 PDC_133_MHZ
= 133333333,
58 PDC_GLOBAL_CTL
= 0x1108,
61 PDC_BYTE_COUNT
= 0x1120,
65 static int pdc2027x_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
66 static void pdc2027x_error_handler(struct ata_port
*ap
);
67 static void pdc2027x_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
);
68 static void pdc2027x_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
);
69 static void pdc2027x_post_set_mode(struct ata_port
*ap
);
70 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd
*qc
);
73 * ATA Timing Tables based on 133MHz controller clock.
74 * These tables are only used when the controller is in 133MHz clock.
75 * If the controller is in 100MHz clock, the ASIC hardware will
76 * set the timing registers automatically when "set feature" command
77 * is issued to the device. However, if the controller clock is 133MHz,
78 * the following tables must be used.
80 static struct pdc2027x_pio_timing
{
81 u8 value0
, value1
, value2
;
82 } pdc2027x_pio_timing_tbl
[] = {
83 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
84 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
85 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
86 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
87 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
90 static struct pdc2027x_mdma_timing
{
92 } pdc2027x_mdma_timing_tbl
[] = {
93 { 0xdf, 0x5f }, /* MDMA mode 0 */
94 { 0x6b, 0x27 }, /* MDMA mode 1 */
95 { 0x69, 0x25 }, /* MDMA mode 2 */
98 static struct pdc2027x_udma_timing
{
99 u8 value0
, value1
, value2
;
100 } pdc2027x_udma_timing_tbl
[] = {
101 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
102 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
103 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
104 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
105 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
106 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
107 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
110 static const struct pci_device_id pdc2027x_pci_tbl
[] = {
111 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20268
), PDC_UDMA_100
},
112 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20269
), PDC_UDMA_133
},
113 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20270
), PDC_UDMA_100
},
114 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20271
), PDC_UDMA_133
},
115 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20275
), PDC_UDMA_133
},
116 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20276
), PDC_UDMA_133
},
117 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20277
), PDC_UDMA_133
},
119 { } /* terminate list */
122 static struct pci_driver pdc2027x_pci_driver
= {
124 .id_table
= pdc2027x_pci_tbl
,
125 .probe
= pdc2027x_init_one
,
126 .remove
= ata_pci_remove_one
,
129 static struct scsi_host_template pdc2027x_sht
= {
130 .module
= THIS_MODULE
,
132 .ioctl
= ata_scsi_ioctl
,
133 .queuecommand
= ata_scsi_queuecmd
,
134 .can_queue
= ATA_DEF_QUEUE
,
135 .this_id
= ATA_SHT_THIS_ID
,
136 .sg_tablesize
= LIBATA_MAX_PRD
,
137 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
138 .emulated
= ATA_SHT_EMULATED
,
139 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
140 .proc_name
= DRV_NAME
,
141 .dma_boundary
= ATA_DMA_BOUNDARY
,
142 .slave_configure
= ata_scsi_slave_config
,
143 .slave_destroy
= ata_scsi_slave_destroy
,
144 .bios_param
= ata_std_bios_param
,
147 static struct ata_port_operations pdc2027x_pata100_ops
= {
148 .port_disable
= ata_port_disable
,
150 .tf_load
= ata_tf_load
,
151 .tf_read
= ata_tf_read
,
152 .check_status
= ata_check_status
,
153 .exec_command
= ata_exec_command
,
154 .dev_select
= ata_std_dev_select
,
156 .check_atapi_dma
= pdc2027x_check_atapi_dma
,
157 .bmdma_setup
= ata_bmdma_setup
,
158 .bmdma_start
= ata_bmdma_start
,
159 .bmdma_stop
= ata_bmdma_stop
,
160 .bmdma_status
= ata_bmdma_status
,
161 .qc_prep
= ata_qc_prep
,
162 .qc_issue
= ata_qc_issue_prot
,
163 .data_xfer
= ata_data_xfer
,
165 .freeze
= ata_bmdma_freeze
,
166 .thaw
= ata_bmdma_thaw
,
167 .error_handler
= pdc2027x_error_handler
,
168 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
170 .irq_handler
= ata_interrupt
,
171 .irq_clear
= ata_bmdma_irq_clear
,
173 .port_start
= ata_port_start
,
176 static struct ata_port_operations pdc2027x_pata133_ops
= {
177 .port_disable
= ata_port_disable
,
178 .set_piomode
= pdc2027x_set_piomode
,
179 .set_dmamode
= pdc2027x_set_dmamode
,
180 .post_set_mode
= pdc2027x_post_set_mode
,
182 .tf_load
= ata_tf_load
,
183 .tf_read
= ata_tf_read
,
184 .check_status
= ata_check_status
,
185 .exec_command
= ata_exec_command
,
186 .dev_select
= ata_std_dev_select
,
188 .check_atapi_dma
= pdc2027x_check_atapi_dma
,
189 .bmdma_setup
= ata_bmdma_setup
,
190 .bmdma_start
= ata_bmdma_start
,
191 .bmdma_stop
= ata_bmdma_stop
,
192 .bmdma_status
= ata_bmdma_status
,
193 .qc_prep
= ata_qc_prep
,
194 .qc_issue
= ata_qc_issue_prot
,
195 .data_xfer
= ata_data_xfer
,
197 .freeze
= ata_bmdma_freeze
,
198 .thaw
= ata_bmdma_thaw
,
199 .error_handler
= pdc2027x_error_handler
,
200 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
202 .irq_handler
= ata_interrupt
,
203 .irq_clear
= ata_bmdma_irq_clear
,
205 .port_start
= ata_port_start
,
208 static struct ata_port_info pdc2027x_port_info
[] = {
211 .sht
= &pdc2027x_sht
,
212 .flags
= ATA_FLAG_NO_LEGACY
| ATA_FLAG_SLAVE_POSS
|
214 .pio_mask
= 0x1f, /* pio0-4 */
215 .mwdma_mask
= 0x07, /* mwdma0-2 */
216 .udma_mask
= ATA_UDMA5
, /* udma0-5 */
217 .port_ops
= &pdc2027x_pata100_ops
,
221 .sht
= &pdc2027x_sht
,
222 .flags
= ATA_FLAG_NO_LEGACY
| ATA_FLAG_SLAVE_POSS
|
224 .pio_mask
= 0x1f, /* pio0-4 */
225 .mwdma_mask
= 0x07, /* mwdma0-2 */
226 .udma_mask
= ATA_UDMA6
, /* udma0-6 */
227 .port_ops
= &pdc2027x_pata133_ops
,
231 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
232 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
233 MODULE_LICENSE("GPL");
234 MODULE_VERSION(DRV_VERSION
);
235 MODULE_DEVICE_TABLE(pci
, pdc2027x_pci_tbl
);
238 * port_mmio - Get the MMIO address of PDC2027x extended registers
240 * @offset: offset from mmio base
242 static inline void __iomem
*port_mmio(struct ata_port
*ap
, unsigned int offset
)
244 return ap
->host
->iomap
[PDC_MMIO_BAR
] + ap
->port_no
* 0x100 + offset
;
248 * dev_mmio - Get the MMIO address of PDC2027x extended registers
251 * @offset: offset from mmio base
253 static inline void __iomem
*dev_mmio(struct ata_port
*ap
, struct ata_device
*adev
, unsigned int offset
)
255 u8 adj
= (adev
->devno
) ? 0x08 : 0x00;
256 return port_mmio(ap
, offset
) + adj
;
260 * pdc2027x_pata_cbl_detect - Probe host controller cable detect info
261 * @ap: Port for which cable detect info is desired
263 * Read 80c cable indicator from Promise extended register.
264 * This register is latched when the system is reset.
267 * None (inherited from caller).
269 static void pdc2027x_cbl_detect(struct ata_port
*ap
)
273 /* check cable detect results */
274 cgcr
= readl(port_mmio(ap
, PDC_GLOBAL_CTL
));
275 if (cgcr
& (1 << 26))
278 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap
->port_no
);
280 ap
->cbl
= ATA_CBL_PATA80
;
284 printk(KERN_INFO DRV_NAME
": 40-conductor cable detected on port %d\n", ap
->port_no
);
285 ap
->cbl
= ATA_CBL_PATA40
;
286 ap
->udma_mask
&= ATA_UDMA_MASK_40C
;
290 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
293 static inline int pdc2027x_port_enabled(struct ata_port
*ap
)
295 return readb(port_mmio(ap
, PDC_ATA_CTL
)) & 0x02;
299 * pdc2027x_prereset - prereset for PATA host controller
302 * Probeinit including cable detection.
305 * None (inherited from caller).
308 static int pdc2027x_prereset(struct ata_port
*ap
)
310 /* Check whether port enabled */
311 if (!pdc2027x_port_enabled(ap
))
313 pdc2027x_cbl_detect(ap
);
314 return ata_std_prereset(ap
);
318 * pdc2027x_error_handler - Perform reset on PATA port and classify
321 * Reset PATA phy and classify attached devices.
324 * None (inherited from caller).
327 static void pdc2027x_error_handler(struct ata_port
*ap
)
329 ata_bmdma_drive_eh(ap
, pdc2027x_prereset
, ata_std_softreset
, NULL
, ata_std_postreset
);
333 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
334 * @ap: Port to configure
336 * @pio: PIO mode, 0 - 4
338 * Set PIO mode for device.
341 * None (inherited from caller).
344 static void pdc2027x_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
346 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
349 PDPRINTK("adev->pio_mode[%X]\n", adev
->pio_mode
);
353 printk(KERN_ERR DRV_NAME
": Unknown pio mode [%d] ignored\n", pio
);
358 /* Set the PIO timing registers using value table for 133MHz */
359 PDPRINTK("Set pio regs... \n");
361 ctcr0
= readl(dev_mmio(ap
, adev
, PDC_CTCR0
));
363 ctcr0
|= pdc2027x_pio_timing_tbl
[pio
].value0
|
364 (pdc2027x_pio_timing_tbl
[pio
].value1
<< 8);
365 writel(ctcr0
, dev_mmio(ap
, adev
, PDC_CTCR0
));
367 ctcr1
= readl(dev_mmio(ap
, adev
, PDC_CTCR1
));
369 ctcr1
|= (pdc2027x_pio_timing_tbl
[pio
].value2
<< 24);
370 writel(ctcr1
, dev_mmio(ap
, adev
, PDC_CTCR1
));
372 PDPRINTK("Set pio regs done\n");
374 PDPRINTK("Set to pio mode[%u] \n", pio
);
378 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
379 * @ap: Port to configure
381 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
383 * Set UDMA mode for device.
386 * None (inherited from caller).
388 static void pdc2027x_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
390 unsigned int dma_mode
= adev
->dma_mode
;
393 if ((dma_mode
>= XFER_UDMA_0
) &&
394 (dma_mode
<= XFER_UDMA_6
)) {
395 /* Set the UDMA timing registers with value table for 133MHz */
396 unsigned int udma_mode
= dma_mode
& 0x07;
398 if (dma_mode
== XFER_UDMA_2
) {
401 * If tHOLD is '1', the hardware will add half clock for data hold time.
402 * This code segment seems to be no effect. tHOLD will be overwritten below.
404 ctcr1
= readl(dev_mmio(ap
, adev
, PDC_CTCR1
));
405 writel(ctcr1
& ~(1 << 7), dev_mmio(ap
, adev
, PDC_CTCR1
));
408 PDPRINTK("Set udma regs... \n");
410 ctcr1
= readl(dev_mmio(ap
, adev
, PDC_CTCR1
));
412 ctcr1
|= pdc2027x_udma_timing_tbl
[udma_mode
].value0
|
413 (pdc2027x_udma_timing_tbl
[udma_mode
].value1
<< 8) |
414 (pdc2027x_udma_timing_tbl
[udma_mode
].value2
<< 16);
415 writel(ctcr1
, dev_mmio(ap
, adev
, PDC_CTCR1
));
417 PDPRINTK("Set udma regs done\n");
419 PDPRINTK("Set to udma mode[%u] \n", udma_mode
);
421 } else if ((dma_mode
>= XFER_MW_DMA_0
) &&
422 (dma_mode
<= XFER_MW_DMA_2
)) {
423 /* Set the MDMA timing registers with value table for 133MHz */
424 unsigned int mdma_mode
= dma_mode
& 0x07;
426 PDPRINTK("Set mdma regs... \n");
427 ctcr0
= readl(dev_mmio(ap
, adev
, PDC_CTCR0
));
430 ctcr0
|= (pdc2027x_mdma_timing_tbl
[mdma_mode
].value0
<< 16) |
431 (pdc2027x_mdma_timing_tbl
[mdma_mode
].value1
<< 24);
433 writel(ctcr0
, dev_mmio(ap
, adev
, PDC_CTCR0
));
434 PDPRINTK("Set mdma regs done\n");
436 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode
);
438 printk(KERN_ERR DRV_NAME
": Unknown dma mode [%u] ignored\n", dma_mode
);
443 * pdc2027x_post_set_mode - Set the timing registers back to correct values.
444 * @ap: Port to configure
446 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
447 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
448 * This function overwrites the possibly incorrect values set by the hardware to be correct.
450 static void pdc2027x_post_set_mode(struct ata_port
*ap
)
454 for (i
= 0; i
< ATA_MAX_DEVICES
; i
++) {
455 struct ata_device
*dev
= &ap
->device
[i
];
457 if (ata_dev_enabled(dev
)) {
459 pdc2027x_set_piomode(ap
, dev
);
462 * Enable prefetch if the device support PIO only.
464 if (dev
->xfer_shift
== ATA_SHIFT_PIO
) {
465 u32 ctcr1
= readl(dev_mmio(ap
, dev
, PDC_CTCR1
));
467 writel(ctcr1
, dev_mmio(ap
, dev
, PDC_CTCR1
));
469 PDPRINTK("Turn on prefetch\n");
471 pdc2027x_set_dmamode(ap
, dev
);
478 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
479 * @qc: Metadata associated with taskfile to check
482 * None (inherited from caller).
484 * RETURNS: 0 when ATAPI DMA can be used
487 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd
*qc
)
489 struct scsi_cmnd
*cmd
= qc
->scsicmd
;
490 u8
*scsicmd
= cmd
->cmnd
;
491 int rc
= 1; /* atapi dma off by default */
494 * This workaround is from Promise's GPL driver.
495 * If ATAPI DMA is used for commands not in the
496 * following white list, say MODE_SENSE and REQUEST_SENSE,
497 * pdc2027x might hit the irq lost problem.
499 switch (scsicmd
[0]) {
506 case 0xad: /* READ_DVD_STRUCTURE */
507 case 0xbe: /* READ_CD */
508 /* ATAPI DMA is ok */
519 * pdc_read_counter - Read the ctr counter
520 * @probe_ent: for the port address
523 static long pdc_read_counter(struct ata_probe_ent
*probe_ent
)
525 void __iomem
*mmio_base
= probe_ent
->iomap
[PDC_MMIO_BAR
];
528 u32 bccrl
, bccrh
, bccrlv
, bccrhv
;
531 bccrl
= readl(mmio_base
+ PDC_BYTE_COUNT
) & 0xffff;
532 bccrh
= readl(mmio_base
+ PDC_BYTE_COUNT
+ 0x100) & 0xffff;
535 /* Read the counter values again for verification */
536 bccrlv
= readl(mmio_base
+ PDC_BYTE_COUNT
) & 0xffff;
537 bccrhv
= readl(mmio_base
+ PDC_BYTE_COUNT
+ 0x100) & 0xffff;
540 counter
= (bccrh
<< 15) | bccrl
;
542 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh
, bccrl
);
543 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv
, bccrlv
);
546 * The 30-bit decreasing counter are read by 2 pieces.
547 * Incorrect value may be read when both bccrh and bccrl are changing.
548 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
550 if (retry
&& !(bccrh
== bccrhv
&& bccrl
>= bccrlv
)) {
552 PDPRINTK("rereading counter\n");
560 * adjust_pll - Adjust the PLL input clock in Hz.
562 * @pdc_controller: controller specific information
563 * @probe_ent: For the port address
564 * @pll_clock: The input of PLL in HZ
566 static void pdc_adjust_pll(struct ata_probe_ent
*probe_ent
, long pll_clock
, unsigned int board_idx
)
568 void __iomem
*mmio_base
= probe_ent
->iomap
[PDC_MMIO_BAR
];
570 long pll_clock_khz
= pll_clock
/ 1000;
571 long pout_required
= board_idx
? PDC_133_MHZ
:PDC_100_MHZ
;
572 long ratio
= pout_required
/ pll_clock_khz
;
576 if (unlikely(pll_clock_khz
< 5000L || pll_clock_khz
> 70000L)) {
577 printk(KERN_ERR DRV_NAME
": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz
);
582 PDPRINTK("pout_required is %ld\n", pout_required
);
584 /* Show the current clock value of PLL control register
585 * (maybe already configured by the firmware)
587 pll_ctl
= readw(mmio_base
+ PDC_PLL_CTL
);
589 PDPRINTK("pll_ctl[%X]\n", pll_ctl
);
593 * Calculate the ratio of F, R and OD
594 * POUT = (F + 2) / (( R + 2) * NO)
596 if (ratio
< 8600L) { /* 8.6x */
597 /* Using NO = 0x01, R = 0x0D */
599 } else if (ratio
< 12900L) { /* 12.9x */
600 /* Using NO = 0x01, R = 0x08 */
602 } else if (ratio
< 16100L) { /* 16.1x */
603 /* Using NO = 0x01, R = 0x06 */
605 } else if (ratio
< 64000L) { /* 64x */
609 printk(KERN_ERR DRV_NAME
": Invalid ratio %ld, give up!\n", ratio
);
613 F
= (ratio
* (R
+2)) / 1000 - 2;
615 if (unlikely(F
< 0 || F
> 127)) {
617 printk(KERN_ERR DRV_NAME
": F[%d] invalid!\n", F
);
621 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F
, R
, ratio
);
623 pll_ctl
= (R
<< 8) | F
;
625 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl
);
627 writew(pll_ctl
, mmio_base
+ PDC_PLL_CTL
);
628 readw(mmio_base
+ PDC_PLL_CTL
); /* flush */
630 /* Wait the PLL circuit to be stable */
635 * Show the current clock value of PLL control register
636 * (maybe configured by the firmware)
638 pll_ctl
= readw(mmio_base
+ PDC_PLL_CTL
);
640 PDPRINTK("pll_ctl[%X]\n", pll_ctl
);
647 * detect_pll_input_clock - Detect the PLL input clock in Hz.
648 * @probe_ent: for the port address
649 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
650 * Half of the PCI clock.
652 static long pdc_detect_pll_input_clock(struct ata_probe_ent
*probe_ent
)
654 void __iomem
*mmio_base
= probe_ent
->iomap
[PDC_MMIO_BAR
];
656 long start_count
, end_count
;
659 /* Read current counter value */
660 start_count
= pdc_read_counter(probe_ent
);
662 /* Start the test mode */
663 scr
= readl(mmio_base
+ PDC_SYS_CTL
);
664 PDPRINTK("scr[%X]\n", scr
);
665 writel(scr
| (0x01 << 14), mmio_base
+ PDC_SYS_CTL
);
666 readl(mmio_base
+ PDC_SYS_CTL
); /* flush */
668 /* Let the counter run for 100 ms. */
671 /* Read the counter values again */
672 end_count
= pdc_read_counter(probe_ent
);
674 /* Stop the test mode */
675 scr
= readl(mmio_base
+ PDC_SYS_CTL
);
676 PDPRINTK("scr[%X]\n", scr
);
677 writel(scr
& ~(0x01 << 14), mmio_base
+ PDC_SYS_CTL
);
678 readl(mmio_base
+ PDC_SYS_CTL
); /* flush */
680 /* calculate the input clock in Hz */
681 pll_clock
= (start_count
- end_count
) * 10;
683 PDPRINTK("start[%ld] end[%ld] \n", start_count
, end_count
);
684 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock
);
690 * pdc_hardware_init - Initialize the hardware.
691 * @pdev: instance of pci_dev found
692 * @pdc_controller: controller specific information
693 * @pe: for the port address
695 static int pdc_hardware_init(struct pci_dev
*pdev
, struct ata_probe_ent
*pe
, unsigned int board_idx
)
700 * Detect PLL input clock rate.
701 * On some system, where PCI bus is running at non-standard clock rate.
702 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
703 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
705 pll_clock
= pdc_detect_pll_input_clock(pe
);
707 if (pll_clock
< 0) /* counter overflow? Try again. */
708 pll_clock
= pdc_detect_pll_input_clock(pe
);
710 dev_printk(KERN_INFO
, &pdev
->dev
, "PLL input clock %ld kHz\n", pll_clock
/1000);
712 /* Adjust PLL control register */
713 pdc_adjust_pll(pe
, pll_clock
, board_idx
);
719 * pdc_ata_setup_port - setup the mmio address
720 * @port: ata ioports to setup
721 * @base: base address
723 static void pdc_ata_setup_port(struct ata_ioports
*port
, void __iomem
*base
)
726 port
->data_addr
= base
;
728 port
->error_addr
= base
+ 0x05;
729 port
->nsect_addr
= base
+ 0x0a;
730 port
->lbal_addr
= base
+ 0x0f;
731 port
->lbam_addr
= base
+ 0x10;
732 port
->lbah_addr
= base
+ 0x15;
733 port
->device_addr
= base
+ 0x1a;
735 port
->status_addr
= base
+ 0x1f;
736 port
->altstatus_addr
=
737 port
->ctl_addr
= base
+ 0x81a;
741 * pdc2027x_init_one - PCI probe function
742 * Called when an instance of PCI adapter is inserted.
743 * This function checks whether the hardware is supported,
744 * initialize hardware and register an instance of ata_host to
745 * libata by providing struct ata_probe_ent and ata_device_add().
746 * (implements struct pci_driver.probe() )
748 * @pdev: instance of pci_dev found
749 * @ent: matching entry in the id_tbl[]
751 static int __devinit
pdc2027x_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
753 static int printed_version
;
754 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
756 struct ata_probe_ent
*probe_ent
;
757 void __iomem
*mmio_base
;
760 if (!printed_version
++)
761 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
763 rc
= pcim_enable_device(pdev
);
767 rc
= pcim_iomap_regions(pdev
, 1 << PDC_MMIO_BAR
, DRV_NAME
);
771 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
775 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
779 /* Prepare the probe entry */
780 probe_ent
= devm_kzalloc(&pdev
->dev
, sizeof(*probe_ent
), GFP_KERNEL
);
781 if (probe_ent
== NULL
)
784 probe_ent
->dev
= pci_dev_to_dev(pdev
);
785 INIT_LIST_HEAD(&probe_ent
->node
);
787 probe_ent
->sht
= pdc2027x_port_info
[board_idx
].sht
;
788 probe_ent
->port_flags
= pdc2027x_port_info
[board_idx
].flags
;
789 probe_ent
->pio_mask
= pdc2027x_port_info
[board_idx
].pio_mask
;
790 probe_ent
->mwdma_mask
= pdc2027x_port_info
[board_idx
].mwdma_mask
;
791 probe_ent
->udma_mask
= pdc2027x_port_info
[board_idx
].udma_mask
;
792 probe_ent
->port_ops
= pdc2027x_port_info
[board_idx
].port_ops
;
794 probe_ent
->irq
= pdev
->irq
;
795 probe_ent
->irq_flags
= SA_SHIRQ
;
796 probe_ent
->iomap
= pcim_iomap_table(pdev
);
798 mmio_base
= probe_ent
->iomap
[PDC_MMIO_BAR
];
800 pdc_ata_setup_port(&probe_ent
->port
[0], mmio_base
+ 0x17c0);
801 probe_ent
->port
[0].bmdma_addr
= mmio_base
+ 0x1000;
802 pdc_ata_setup_port(&probe_ent
->port
[1], mmio_base
+ 0x15c0);
803 probe_ent
->port
[1].bmdma_addr
= mmio_base
+ 0x1008;
805 probe_ent
->n_ports
= 2;
807 pci_set_master(pdev
);
808 //pci_enable_intx(pdev);
810 /* initialize adapter */
811 if (pdc_hardware_init(pdev
, probe_ent
, board_idx
) != 0)
814 if (!ata_device_add(probe_ent
))
817 devm_kfree(&pdev
->dev
, probe_ent
);
822 * pdc2027x_init - Called after this module is loaded into the kernel.
824 static int __init
pdc2027x_init(void)
826 return pci_register_driver(&pdc2027x_pci_driver
);
830 * pdc2027x_exit - Called before this module unloaded from the kernel
832 static void __exit
pdc2027x_exit(void)
834 pci_unregister_driver(&pdc2027x_pci_driver
);
837 module_init(pdc2027x_init
);
838 module_exit(pdc2027x_exit
);