drivers/ata/pdc_adma.c

   1 /*
   2  *  pdc_adma.c - Pacific Digital Corporation ADMA
   3  *
   4  *  Maintained by:  Mark Lord <mlord@pobox.com>
   5  *
   6  *  Copyright 2005 Mark Lord
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2, or (at your option)
  11  *  any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; see the file COPYING.  If not, write to
  20  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  *
  23  *  libata documentation is available via 'make {ps|pdf}docs',
  24  *  as Documentation/DocBook/libata.*
  25  *
  26  *
  27  *  Supports ATA disks in single-packet ADMA mode.
  28  *  Uses PIO for everything else.
  29  *
  30  *  TODO:  Use ADMA transfers for ATAPI devices, when possible.
  31  *  This requires careful attention to a number of quirks of the chip.
  32  *
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/pci.h>
  38 #include <linux/init.h>
  39 #include <linux/blkdev.h>
  40 #include <linux/delay.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/device.h>
  43 #include <scsi/scsi_host.h>
  44 #include <linux/libata.h>
  45
  46 #define DRV_NAME        "pdc_adma"
  47 #define DRV_VERSION     "1.0"
  48
  49 /* macro to calculate base address for ATA regs */
  50 #define ADMA_ATA_REGS(base,port_no)     ((base) + ((port_no) * 0x40))
  51
  52 /* macro to calculate base address for ADMA regs */
  53 #define ADMA_REGS(base,port_no)         ((base) + 0x80 + ((port_no) * 0x20))
  54
  55 /* macro to obtain addresses from ata_port */
  56 #define ADMA_PORT_REGS(ap) \
  57         ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
  58
  59 enum {
  60         ADMA_MMIO_BAR           = 4,
  61
  62         ADMA_PORTS              = 2,
  63         ADMA_CPB_BYTES          = 40,
  64         ADMA_PRD_BYTES          = LIBATA_MAX_PRD * 16,
  65         ADMA_PKT_BYTES          = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
  66
  67         ADMA_DMA_BOUNDARY       = 0xffffffff,
  68
  69         /* global register offsets */
  70         ADMA_MODE_LOCK          = 0x00c7,
  71
  72         /* per-channel register offsets */
  73         ADMA_CONTROL            = 0x0000, /* ADMA control */
  74         ADMA_STATUS             = 0x0002, /* ADMA status */
  75         ADMA_CPB_COUNT          = 0x0004, /* CPB count */
  76         ADMA_CPB_CURRENT        = 0x000c, /* current CPB address */
  77         ADMA_CPB_NEXT           = 0x000c, /* next CPB address */
  78         ADMA_CPB_LOOKUP         = 0x0010, /* CPB lookup table */
  79         ADMA_FIFO_IN            = 0x0014, /* input FIFO threshold */
  80         ADMA_FIFO_OUT           = 0x0016, /* output FIFO threshold */
  81
  82         /* ADMA_CONTROL register bits */
  83         aNIEN                   = (1 << 8), /* irq mask: 1==masked */
  84         aGO                     = (1 << 7), /* packet trigger ("Go!") */
  85         aRSTADM                 = (1 << 5), /* ADMA logic reset */
  86         aPIOMD4                 = 0x0003,   /* PIO mode 4 */
  87
  88         /* ADMA_STATUS register bits */
  89         aPSD                    = (1 << 6),
  90         aUIRQ                   = (1 << 4),
  91         aPERR                   = (1 << 0),
  92
  93         /* CPB bits */
  94         cDONE                   = (1 << 0),
  95         cATERR                  = (1 << 3),
  96
  97         cVLD                    = (1 << 0),
  98         cDAT                    = (1 << 2),
  99         cIEN                    = (1 << 3),
 100
 101         /* PRD bits */
 102         pORD                    = (1 << 4),
 103         pDIRO                   = (1 << 5),
 104         pEND                    = (1 << 7),
 105
 106         /* ATA register flags */
 107         rIGN                    = (1 << 5),
 108         rEND                    = (1 << 7),
 109
 110         /* ATA register addresses */
 111         ADMA_REGS_CONTROL       = 0x0e,
 112         ADMA_REGS_SECTOR_COUNT  = 0x12,
 113         ADMA_REGS_LBA_LOW       = 0x13,
 114         ADMA_REGS_LBA_MID       = 0x14,
 115         ADMA_REGS_LBA_HIGH      = 0x15,
 116         ADMA_REGS_DEVICE        = 0x16,
 117         ADMA_REGS_COMMAND       = 0x17,
 118
 119         /* PCI device IDs */
 120         board_1841_idx          = 0,    /* ADMA 2-port controller */
 121 };
 122
 123 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
 124
 125 struct adma_port_priv {
 126         u8                      *pkt;
 127         dma_addr_t              pkt_dma;
 128         adma_state_t            state;
 129 };
 130
 131 static int adma_ata_init_one (struct pci_dev *pdev,
 132                                 const struct pci_device_id *ent);
 133 static int adma_port_start(struct ata_port *ap);
 134 static void adma_host_stop(struct ata_host *host);
 135 static void adma_port_stop(struct ata_port *ap);
 136 static void adma_qc_prep(struct ata_queued_cmd *qc);
 137 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
 138 static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
 139 static void adma_bmdma_stop(struct ata_queued_cmd *qc);
 140 static u8 adma_bmdma_status(struct ata_port *ap);
 141 static void adma_irq_clear(struct ata_port *ap);
 142 static void adma_freeze(struct ata_port *ap);
 143 static void adma_thaw(struct ata_port *ap);
 144 static void adma_error_handler(struct ata_port *ap);
 145
 146 static struct scsi_host_template adma_ata_sht = {
 147         .module                 = THIS_MODULE,
 148         .name                   = DRV_NAME,
 149         .ioctl                  = ata_scsi_ioctl,
 150         .queuecommand           = ata_scsi_queuecmd,
 151         .slave_configure        = ata_scsi_slave_config,
 152         .slave_destroy          = ata_scsi_slave_destroy,
 153         .bios_param             = ata_std_bios_param,
 154         .proc_name              = DRV_NAME,
 155         .can_queue              = ATA_DEF_QUEUE,
 156         .this_id                = ATA_SHT_THIS_ID,
 157         .sg_tablesize           = LIBATA_MAX_PRD,
 158         .dma_boundary           = ADMA_DMA_BOUNDARY,
 159         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 160         .use_clustering         = ENABLE_CLUSTERING,
 161         .emulated               = ATA_SHT_EMULATED,
 162 };
 163
 164 static const struct ata_port_operations adma_ata_ops = {
 165         .tf_load                = ata_tf_load,
 166         .tf_read                = ata_tf_read,
 167         .exec_command           = ata_exec_command,
 168         .check_status           = ata_check_status,
 169         .dev_select             = ata_std_dev_select,
 170         .check_atapi_dma        = adma_check_atapi_dma,
 171         .data_xfer              = ata_data_xfer,
 172         .qc_prep                = adma_qc_prep,
 173         .qc_issue               = adma_qc_issue,
 174         .freeze                 = adma_freeze,
 175         .thaw                   = adma_thaw,
 176         .error_handler          = adma_error_handler,
 177         .irq_clear              = adma_irq_clear,
 178         .irq_on                 = ata_irq_on,
 179         .port_start             = adma_port_start,
 180         .port_stop              = adma_port_stop,
 181         .host_stop              = adma_host_stop,
 182         .bmdma_stop             = adma_bmdma_stop,
 183         .bmdma_status           = adma_bmdma_status,
 184 };
 185
 186 static struct ata_port_info adma_port_info[] = {
 187         /* board_1841_idx */
 188         {
 189                 .flags          = ATA_FLAG_SLAVE_POSS |
 190                                   ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
 191                                   ATA_FLAG_PIO_POLLING,
 192                 .pio_mask       = 0x10, /* pio4 */
 193                 .udma_mask      = ATA_UDMA4,
 194                 .port_ops       = &adma_ata_ops,
 195         },
 196 };
 197
 198 static const struct pci_device_id adma_ata_pci_tbl[] = {
 199         { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
 200
 201         { }     /* terminate list */
 202 };
 203
 204 static struct pci_driver adma_ata_pci_driver = {
 205         .name                   = DRV_NAME,
 206         .id_table               = adma_ata_pci_tbl,
 207         .probe                  = adma_ata_init_one,
 208         .remove                 = ata_pci_remove_one,
 209 };
 210
 211 static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
 212 {
 213         return 1;       /* ATAPI DMA not yet supported */
 214 }
 215
 216 static void adma_bmdma_stop(struct ata_queued_cmd *qc)
 217 {
 218         /* nothing */
 219 }
 220
 221 static u8 adma_bmdma_status(struct ata_port *ap)
 222 {
 223         return 0;
 224 }
 225
 226 static void adma_irq_clear(struct ata_port *ap)
 227 {
 228         /* nothing */
 229 }
 230
 231 static void adma_reset_engine(struct ata_port *ap)
 232 {
 233         void __iomem *chan = ADMA_PORT_REGS(ap);
 234
 235         /* reset ADMA to idle state */
 236         writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
 237         udelay(2);
 238         writew(aPIOMD4, chan + ADMA_CONTROL);
 239         udelay(2);
 240 }
 241
 242 static void adma_reinit_engine(struct ata_port *ap)
 243 {
 244         struct adma_port_priv *pp = ap->private_data;
 245         void __iomem *chan = ADMA_PORT_REGS(ap);
 246
 247         /* mask/clear ATA interrupts */
 248         writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
 249         ata_check_status(ap);
 250
 251         /* reset the ADMA engine */
 252         adma_reset_engine(ap);
 253
 254         /* set in-FIFO threshold to 0x100 */
 255         writew(0x100, chan + ADMA_FIFO_IN);
 256
 257         /* set CPB pointer */
 258         writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
 259
 260         /* set out-FIFO threshold to 0x100 */
 261         writew(0x100, chan + ADMA_FIFO_OUT);
 262
 263         /* set CPB count */
 264         writew(1, chan + ADMA_CPB_COUNT);
 265
 266         /* read/discard ADMA status */
 267         readb(chan + ADMA_STATUS);
 268 }
 269
 270 static inline void adma_enter_reg_mode(struct ata_port *ap)
 271 {
 272         void __iomem *chan = ADMA_PORT_REGS(ap);
 273
 274         writew(aPIOMD4, chan + ADMA_CONTROL);
 275         readb(chan + ADMA_STATUS);      /* flush */
 276 }
 277
 278 static void adma_freeze(struct ata_port *ap)
 279 {
 280         void __iomem *chan = ADMA_PORT_REGS(ap);
 281
 282         /* mask/clear ATA interrupts */
 283         writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
 284         ata_check_status(ap);
 285
 286         /* reset ADMA to idle state */
 287         writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
 288         udelay(2);
 289         writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
 290         udelay(2);
 291 }
 292
 293 static void adma_thaw(struct ata_port *ap)
 294 {
 295         adma_reinit_engine(ap);
 296 }
 297
 298 static int adma_prereset(struct ata_link *link, unsigned long deadline)
 299 {
 300         struct ata_port *ap = link->ap;
 301         struct adma_port_priv *pp = ap->private_data;
 302
 303         if (pp->state != adma_state_idle) /* healthy paranoia */
 304                 pp->state = adma_state_mmio;
 305         adma_reinit_engine(ap);
 306
 307         return ata_std_prereset(link, deadline);
 308 }
 309
 310 static void adma_error_handler(struct ata_port *ap)
 311 {
 312         ata_do_eh(ap, adma_prereset, ata_std_softreset, NULL,
 313                   ata_std_postreset);
 314 }
 315
 316 static int adma_fill_sg(struct ata_queued_cmd *qc)
 317 {
 318         struct scatterlist *sg;
 319         struct ata_port *ap = qc->ap;
 320         struct adma_port_priv *pp = ap->private_data;
 321         u8  *buf = pp->pkt;
 322         int i = (2 + buf[3]) * 8;
 323         u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
 324
 325         ata_for_each_sg(sg, qc) {
 326                 u32 addr;
 327                 u32 len;
 328
 329                 addr = (u32)sg_dma_address(sg);
 330                 *(__le32 *)(buf + i) = cpu_to_le32(addr);
 331                 i += 4;
 332
 333                 len = sg_dma_len(sg) >> 3;
 334                 *(__le32 *)(buf + i) = cpu_to_le32(len);
 335                 i += 4;
 336
 337                 if (ata_sg_is_last(sg, qc))
 338                         pFLAGS |= pEND;
 339                 buf[i++] = pFLAGS;
 340                 buf[i++] = qc->dev->dma_mode & 0xf;
 341                 buf[i++] = 0;   /* pPKLW */
 342                 buf[i++] = 0;   /* reserved */
 343
 344                 *(__le32 *)(buf + i)
 345                         = (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
 346                 i += 4;
 347
 348                 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
 349                                         (unsigned long)addr, len);
 350         }
 351         return i;
 352 }
 353
 354 static void adma_qc_prep(struct ata_queued_cmd *qc)
 355 {
 356         struct adma_port_priv *pp = qc->ap->private_data;
 357         u8  *buf = pp->pkt;
 358         u32 pkt_dma = (u32)pp->pkt_dma;
 359         int i = 0;
 360
 361         VPRINTK("ENTER\n");
 362
 363         adma_enter_reg_mode(qc->ap);
 364         if (qc->tf.protocol != ATA_PROT_DMA) {
 365                 ata_qc_prep(qc);
 366                 return;
 367         }
 368
 369         buf[i++] = 0;   /* Response flags */
 370         buf[i++] = 0;   /* reserved */
 371         buf[i++] = cVLD | cDAT | cIEN;
 372         i++;            /* cLEN, gets filled in below */
 373
 374         *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma);      /* cNCPB */
 375         i += 4;         /* cNCPB */
 376         i += 4;         /* cPRD, gets filled in below */
 377
 378         buf[i++] = 0;   /* reserved */
 379         buf[i++] = 0;   /* reserved */
 380         buf[i++] = 0;   /* reserved */
 381         buf[i++] = 0;   /* reserved */
 382
 383         /* ATA registers; must be a multiple of 4 */
 384         buf[i++] = qc->tf.device;
 385         buf[i++] = ADMA_REGS_DEVICE;
 386         if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
 387                 buf[i++] = qc->tf.hob_nsect;
 388                 buf[i++] = ADMA_REGS_SECTOR_COUNT;
 389                 buf[i++] = qc->tf.hob_lbal;
 390                 buf[i++] = ADMA_REGS_LBA_LOW;
 391                 buf[i++] = qc->tf.hob_lbam;
 392                 buf[i++] = ADMA_REGS_LBA_MID;
 393                 buf[i++] = qc->tf.hob_lbah;
 394                 buf[i++] = ADMA_REGS_LBA_HIGH;
 395         }
 396         buf[i++] = qc->tf.nsect;
 397         buf[i++] = ADMA_REGS_SECTOR_COUNT;
 398         buf[i++] = qc->tf.lbal;
 399         buf[i++] = ADMA_REGS_LBA_LOW;
 400         buf[i++] = qc->tf.lbam;
 401         buf[i++] = ADMA_REGS_LBA_MID;
 402         buf[i++] = qc->tf.lbah;
 403         buf[i++] = ADMA_REGS_LBA_HIGH;
 404         buf[i++] = 0;
 405         buf[i++] = ADMA_REGS_CONTROL;
 406         buf[i++] = rIGN;
 407         buf[i++] = 0;
 408         buf[i++] = qc->tf.command;
 409         buf[i++] = ADMA_REGS_COMMAND | rEND;
 410
 411         buf[3] = (i >> 3) - 2;                          /* cLEN */
 412         *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i);  /* cPRD */
 413
 414         i = adma_fill_sg(qc);
 415         wmb();  /* flush PRDs and pkt to memory */
 416 #if 0
 417         /* dump out CPB + PRDs for debug */
 418         {
 419                 int j, len = 0;
 420                 static char obuf[2048];
 421                 for (j = 0; j < i; ++j) {
 422                         len += sprintf(obuf+len, "%02x ", buf[j]);
 423                         if ((j & 7) == 7) {
 424                                 printk("%s\n", obuf);
 425                                 len = 0;
 426                         }
 427                 }
 428                 if (len)
 429                         printk("%s\n", obuf);
 430         }
 431 #endif
 432 }
 433
 434 static inline void adma_packet_start(struct ata_queued_cmd *qc)
 435 {
 436         struct ata_port *ap = qc->ap;
 437         void __iomem *chan = ADMA_PORT_REGS(ap);
 438
 439         VPRINTK("ENTER, ap %p\n", ap);
 440
 441         /* fire up the ADMA engine */
 442         writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
 443 }
 444
 445 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
 446 {
 447         struct adma_port_priv *pp = qc->ap->private_data;
 448
 449         switch (qc->tf.protocol) {
 450         case ATA_PROT_DMA:
 451                 pp->state = adma_state_pkt;
 452                 adma_packet_start(qc);
 453                 return 0;
 454
 455         case ATA_PROT_ATAPI_DMA:
 456                 BUG();
 457                 break;
 458
 459         default:
 460                 break;
 461         }
 462
 463         pp->state = adma_state_mmio;
 464         return ata_qc_issue_prot(qc);
 465 }
 466
 467 static inline unsigned int adma_intr_pkt(struct ata_host *host)
 468 {
 469         unsigned int handled = 0, port_no;
 470
 471         for (port_no = 0; port_no < host->n_ports; ++port_no) {
 472                 struct ata_port *ap = host->ports[port_no];
 473                 struct adma_port_priv *pp;
 474                 struct ata_queued_cmd *qc;
 475                 void __iomem *chan = ADMA_PORT_REGS(ap);
 476                 u8 status = readb(chan + ADMA_STATUS);
 477
 478                 if (status == 0)
 479                         continue;
 480                 handled = 1;
 481                 adma_enter_reg_mode(ap);
 482                 if (ap->flags & ATA_FLAG_DISABLED)
 483                         continue;
 484                 pp = ap->private_data;
 485                 if (!pp || pp->state != adma_state_pkt)
 486                         continue;
 487                 qc = ata_qc_from_tag(ap, ap->link.active_tag);
 488                 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
 489                         if (status & aPERR)
 490                                 qc->err_mask |= AC_ERR_HOST_BUS;
 491                         else if ((status & (aPSD | aUIRQ)))
 492                                 qc->err_mask |= AC_ERR_OTHER;
 493
 494                         if (pp->pkt[0] & cATERR)
 495                                 qc->err_mask |= AC_ERR_DEV;
 496                         else if (pp->pkt[0] != cDONE)
 497                                 qc->err_mask |= AC_ERR_OTHER;
 498
 499                         if (!qc->err_mask)
 500                                 ata_qc_complete(qc);
 501                         else {
 502                                 struct ata_eh_info *ehi = &ap->link.eh_info;
 503                                 ata_ehi_clear_desc(ehi);
 504                                 ata_ehi_push_desc(ehi,
 505                                         "ADMA-status 0x%02X", status);
 506                                 ata_ehi_push_desc(ehi,
 507                                         "pkt[0] 0x%02X", pp->pkt[0]);
 508
 509                                 if (qc->err_mask == AC_ERR_DEV)
 510                                         ata_port_abort(ap);
 511                                 else
 512                                         ata_port_freeze(ap);
 513                         }
 514                 }
 515         }
 516         return handled;
 517 }
 518
 519 static inline unsigned int adma_intr_mmio(struct ata_host *host)
 520 {
 521         unsigned int handled = 0, port_no;
 522
 523         for (port_no = 0; port_no < host->n_ports; ++port_no) {
 524                 struct ata_port *ap;
 525                 ap = host->ports[port_no];
 526                 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
 527                         struct ata_queued_cmd *qc;
 528                         struct adma_port_priv *pp = ap->private_data;
 529                         if (!pp || pp->state != adma_state_mmio)
 530                                 continue;
 531                         qc = ata_qc_from_tag(ap, ap->link.active_tag);
 532                         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
 533
 534                                 /* check main status, clearing INTRQ */
 535                                 u8 status = ata_check_status(ap);
 536                                 if ((status & ATA_BUSY))
 537                                         continue;
 538                                 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
 539                                         ap->print_id, qc->tf.protocol, status);
 540
 541                                 /* complete taskfile transaction */
 542                                 pp->state = adma_state_idle;
 543                                 qc->err_mask |= ac_err_mask(status);
 544                                 if (!qc->err_mask)
 545                                         ata_qc_complete(qc);
 546                                 else {
 547                                         struct ata_eh_info *ehi =
 548                                                 &ap->link.eh_info;
 549                                         ata_ehi_clear_desc(ehi);
 550                                         ata_ehi_push_desc(ehi,
 551                                                 "status 0x%02X", status);
 552
 553                                         if (qc->err_mask == AC_ERR_DEV)
 554                                                 ata_port_abort(ap);
 555                                         else
 556                                                 ata_port_freeze(ap);
 557                                 }
 558                                 handled = 1;
 559                         }
 560                 }
 561         }
 562         return handled;
 563 }
 564
 565 static irqreturn_t adma_intr(int irq, void *dev_instance)
 566 {
 567         struct ata_host *host = dev_instance;
 568         unsigned int handled = 0;
 569
 570         VPRINTK("ENTER\n");
 571
 572         spin_lock(&host->lock);
 573         handled  = adma_intr_pkt(host) | adma_intr_mmio(host);
 574         spin_unlock(&host->lock);
 575
 576         VPRINTK("EXIT\n");
 577
 578         return IRQ_RETVAL(handled);
 579 }
 580
 581 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
 582 {
 583         port->cmd_addr          =
 584         port->data_addr         = base + 0x000;
 585         port->error_addr        =
 586         port->feature_addr      = base + 0x004;
 587         port->nsect_addr        = base + 0x008;
 588         port->lbal_addr         = base + 0x00c;
 589         port->lbam_addr         = base + 0x010;
 590         port->lbah_addr         = base + 0x014;
 591         port->device_addr       = base + 0x018;
 592         port->status_addr       =
 593         port->command_addr      = base + 0x01c;
 594         port->altstatus_addr    =
 595         port->ctl_addr          = base + 0x038;
 596 }
 597
 598 static int adma_port_start(struct ata_port *ap)
 599 {
 600         struct device *dev = ap->host->dev;
 601         struct adma_port_priv *pp;
 602         int rc;
 603
 604         rc = ata_port_start(ap);
 605         if (rc)
 606                 return rc;
 607         adma_enter_reg_mode(ap);
 608         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
 609         if (!pp)
 610                 return -ENOMEM;
 611         pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
 612                                       GFP_KERNEL);
 613         if (!pp->pkt)
 614                 return -ENOMEM;
 615         /* paranoia? */
 616         if ((pp->pkt_dma & 7) != 0) {
 617                 printk("bad alignment for pp->pkt_dma: %08x\n",
 618                                                 (u32)pp->pkt_dma);
 619                 return -ENOMEM;
 620         }
 621         memset(pp->pkt, 0, ADMA_PKT_BYTES);
 622         ap->private_data = pp;
 623         adma_reinit_engine(ap);
 624         return 0;
 625 }
 626
 627 static void adma_port_stop(struct ata_port *ap)
 628 {
 629         adma_reset_engine(ap);
 630 }
 631
 632 static void adma_host_stop(struct ata_host *host)
 633 {
 634         unsigned int port_no;
 635
 636         for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
 637                 adma_reset_engine(host->ports[port_no]);
 638 }
 639
 640 static void adma_host_init(struct ata_host *host, unsigned int chip_id)
 641 {
 642         unsigned int port_no;
 643
 644         /* enable/lock aGO operation */
 645         writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
 646
 647         /* reset the ADMA logic */
 648         for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
 649                 adma_reset_engine(host->ports[port_no]);
 650 }
 651
 652 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
 653 {
 654         int rc;
 655
 656         rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 657         if (rc) {
 658                 dev_printk(KERN_ERR, &pdev->dev,
 659                         "32-bit DMA enable failed\n");
 660                 return rc;
 661         }
 662         rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 663         if (rc) {
 664                 dev_printk(KERN_ERR, &pdev->dev,
 665                         "32-bit consistent DMA enable failed\n");
 666                 return rc;
 667         }
 668         return 0;
 669 }
 670
 671 static int adma_ata_init_one(struct pci_dev *pdev,
 672                              const struct pci_device_id *ent)
 673 {
 674         static int printed_version;
 675         unsigned int board_idx = (unsigned int) ent->driver_data;
 676         const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
 677         struct ata_host *host;
 678         void __iomem *mmio_base;
 679         int rc, port_no;
 680
 681         if (!printed_version++)
 682                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
 683
 684         /* alloc host */
 685         host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
 686         if (!host)
 687                 return -ENOMEM;
 688
 689         /* acquire resources and fill host */
 690         rc = pcim_enable_device(pdev);
 691         if (rc)
 692                 return rc;
 693
 694         if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
 695                 return -ENODEV;
 696
 697         rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
 698         if (rc)
 699                 return rc;
 700         host->iomap = pcim_iomap_table(pdev);
 701         mmio_base = host->iomap[ADMA_MMIO_BAR];
 702
 703         rc = adma_set_dma_masks(pdev, mmio_base);
 704         if (rc)
 705                 return rc;
 706
 707         for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
 708                 struct ata_port *ap = host->ports[port_no];
 709                 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
 710                 unsigned int offset = port_base - mmio_base;
 711
 712                 adma_ata_setup_port(&ap->ioaddr, port_base);
 713
 714                 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
 715                 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
 716         }
 717
 718         /* initialize adapter */
 719         adma_host_init(host, board_idx);
 720
 721         pci_set_master(pdev);
 722         return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
 723                                  &adma_ata_sht);
 724 }
 725
 726 static int __init adma_ata_init(void)
 727 {
 728         return pci_register_driver(&adma_ata_pci_driver);
 729 }
 730
 731 static void __exit adma_ata_exit(void)
 732 {
 733         pci_unregister_driver(&adma_ata_pci_driver);
 734 }
 735
 736 MODULE_AUTHOR("Mark Lord");
 737 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
 738 MODULE_LICENSE("GPL");
 739 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
 740 MODULE_VERSION(DRV_VERSION);
 741
 742 module_init(adma_ata_init);
 743 module_exit(adma_ata_exit);