]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/ata/sata_mv.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'for-upstream/pvhvm' of git://xenbits.xensource.com/people/ianc/linux-2.6
[mirror_ubuntu-artful-kernel.git] / drivers / ata / sata_mv.c
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28 /*
29 * sata_mv TODO list:
30 *
31 * --> Develop a low-power-consumption strategy, and implement it.
32 *
33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
34 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
42
43 /*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
52 #include <linux/kernel.h>
53 #include <linux/module.h>
54 #include <linux/pci.h>
55 #include <linux/init.h>
56 #include <linux/blkdev.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <linux/dmapool.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/device.h>
62 #include <linux/clk.h>
63 #include <linux/platform_device.h>
64 #include <linux/ata_platform.h>
65 #include <linux/mbus.h>
66 #include <linux/bitops.h>
67 #include <linux/gfp.h>
68 #include <scsi/scsi_host.h>
69 #include <scsi/scsi_cmnd.h>
70 #include <scsi/scsi_device.h>
71 #include <linux/libata.h>
72
73 #define DRV_NAME "sata_mv"
74 #define DRV_VERSION "1.28"
75
76 /*
77 * module options
78 */
79
80 static int msi;
81 #ifdef CONFIG_PCI
82 module_param(msi, int, S_IRUGO);
83 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
84 #endif
85
86 static int irq_coalescing_io_count;
87 module_param(irq_coalescing_io_count, int, S_IRUGO);
88 MODULE_PARM_DESC(irq_coalescing_io_count,
89 "IRQ coalescing I/O count threshold (0..255)");
90
91 static int irq_coalescing_usecs;
92 module_param(irq_coalescing_usecs, int, S_IRUGO);
93 MODULE_PARM_DESC(irq_coalescing_usecs,
94 "IRQ coalescing time threshold in usecs");
95
96 enum {
97 /* BAR's are enumerated in terms of pci_resource_start() terms */
98 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
99 MV_IO_BAR = 2, /* offset 0x18: IO space */
100 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
101
102 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
103 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
104
105 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
106 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
107 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
108 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
109
110 MV_PCI_REG_BASE = 0,
111
112 /*
113 * Per-chip ("all ports") interrupt coalescing feature.
114 * This is only for GEN_II / GEN_IIE hardware.
115 *
116 * Coalescing defers the interrupt until either the IO_THRESHOLD
117 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
118 */
119 COAL_REG_BASE = 0x18000,
120 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
121 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
122
123 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
124 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
125
126 /*
127 * Registers for the (unused here) transaction coalescing feature:
128 */
129 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
130 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
131
132 SATAHC0_REG_BASE = 0x20000,
133 FLASH_CTL = 0x1046c,
134 GPIO_PORT_CTL = 0x104f0,
135 RESET_CFG = 0x180d8,
136
137 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
138 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
139 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
140 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
141
142 MV_MAX_Q_DEPTH = 32,
143 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
144
145 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
146 * CRPB needs alignment on a 256B boundary. Size == 256B
147 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
148 */
149 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
150 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
151 MV_MAX_SG_CT = 256,
152 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
153
154 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
155 MV_PORT_HC_SHIFT = 2,
156 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
157 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
158 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
159
160 /* Host Flags */
161 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
162
163 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
164 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
165
166 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
167
168 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
169 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
170
171 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
172
173 CRQB_FLAG_READ = (1 << 0),
174 CRQB_TAG_SHIFT = 1,
175 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
176 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
177 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
178 CRQB_CMD_ADDR_SHIFT = 8,
179 CRQB_CMD_CS = (0x2 << 11),
180 CRQB_CMD_LAST = (1 << 15),
181
182 CRPB_FLAG_STATUS_SHIFT = 8,
183 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
184 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
185
186 EPRD_FLAG_END_OF_TBL = (1 << 31),
187
188 /* PCI interface registers */
189
190 MV_PCI_COMMAND = 0xc00,
191 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
192 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
193
194 PCI_MAIN_CMD_STS = 0xd30,
195 STOP_PCI_MASTER = (1 << 2),
196 PCI_MASTER_EMPTY = (1 << 3),
197 GLOB_SFT_RST = (1 << 4),
198
199 MV_PCI_MODE = 0xd00,
200 MV_PCI_MODE_MASK = 0x30,
201
202 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
203 MV_PCI_DISC_TIMER = 0xd04,
204 MV_PCI_MSI_TRIGGER = 0xc38,
205 MV_PCI_SERR_MASK = 0xc28,
206 MV_PCI_XBAR_TMOUT = 0x1d04,
207 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
208 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
209 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
210 MV_PCI_ERR_COMMAND = 0x1d50,
211
212 PCI_IRQ_CAUSE = 0x1d58,
213 PCI_IRQ_MASK = 0x1d5c,
214 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
215
216 PCIE_IRQ_CAUSE = 0x1900,
217 PCIE_IRQ_MASK = 0x1910,
218 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
219
220 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
221 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
222 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
223 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
224 SOC_HC_MAIN_IRQ_MASK = 0x20024,
225 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
226 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
227 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
228 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
229 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
230 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
231 PCI_ERR = (1 << 18),
232 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
233 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
234 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
235 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
236 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
237 GPIO_INT = (1 << 22),
238 SELF_INT = (1 << 23),
239 TWSI_INT = (1 << 24),
240 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
241 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
242 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
243
244 /* SATAHC registers */
245 HC_CFG = 0x00,
246
247 HC_IRQ_CAUSE = 0x14,
248 DMA_IRQ = (1 << 0), /* shift by port # */
249 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
250 DEV_IRQ = (1 << 8), /* shift by port # */
251
252 /*
253 * Per-HC (Host-Controller) interrupt coalescing feature.
254 * This is present on all chip generations.
255 *
256 * Coalescing defers the interrupt until either the IO_THRESHOLD
257 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
258 */
259 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
260 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
261
262 SOC_LED_CTRL = 0x2c,
263 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
264 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
265 /* with dev activity LED */
266
267 /* Shadow block registers */
268 SHD_BLK = 0x100,
269 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
270
271 /* SATA registers */
272 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
273 SATA_ACTIVE = 0x350,
274 FIS_IRQ_CAUSE = 0x364,
275 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
276
277 LTMODE = 0x30c, /* requires read-after-write */
278 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
279
280 PHY_MODE2 = 0x330,
281 PHY_MODE3 = 0x310,
282
283 PHY_MODE4 = 0x314, /* requires read-after-write */
284 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
285 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
286 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
287 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
288
289 SATA_IFCTL = 0x344,
290 SATA_TESTCTL = 0x348,
291 SATA_IFSTAT = 0x34c,
292 VENDOR_UNIQUE_FIS = 0x35c,
293
294 FISCFG = 0x360,
295 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
296 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
297
298 PHY_MODE9_GEN2 = 0x398,
299 PHY_MODE9_GEN1 = 0x39c,
300 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
301
302 MV5_PHY_MODE = 0x74,
303 MV5_LTMODE = 0x30,
304 MV5_PHY_CTL = 0x0C,
305 SATA_IFCFG = 0x050,
306
307 MV_M2_PREAMP_MASK = 0x7e0,
308
309 /* Port registers */
310 EDMA_CFG = 0,
311 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
312 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
313 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
314 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
315 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
316 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
317 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
318
319 EDMA_ERR_IRQ_CAUSE = 0x8,
320 EDMA_ERR_IRQ_MASK = 0xc,
321 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
322 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
323 EDMA_ERR_DEV = (1 << 2), /* device error */
324 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
325 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
326 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
327 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
328 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
329 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
330 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
331 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
332 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
333 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
334 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
335
336 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
337 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
338 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
339 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
340 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
341
342 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
343
344 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
345 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
346 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
347 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
348 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
349 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
350
351 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
352
353 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
354 EDMA_ERR_OVERRUN_5 = (1 << 5),
355 EDMA_ERR_UNDERRUN_5 = (1 << 6),
356
357 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
358 EDMA_ERR_LNK_CTRL_RX_1 |
359 EDMA_ERR_LNK_CTRL_RX_3 |
360 EDMA_ERR_LNK_CTRL_TX,
361
362 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
363 EDMA_ERR_PRD_PAR |
364 EDMA_ERR_DEV_DCON |
365 EDMA_ERR_DEV_CON |
366 EDMA_ERR_SERR |
367 EDMA_ERR_SELF_DIS |
368 EDMA_ERR_CRQB_PAR |
369 EDMA_ERR_CRPB_PAR |
370 EDMA_ERR_INTRL_PAR |
371 EDMA_ERR_IORDY |
372 EDMA_ERR_LNK_CTRL_RX_2 |
373 EDMA_ERR_LNK_DATA_RX |
374 EDMA_ERR_LNK_DATA_TX |
375 EDMA_ERR_TRANS_PROTO,
376
377 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
378 EDMA_ERR_PRD_PAR |
379 EDMA_ERR_DEV_DCON |
380 EDMA_ERR_DEV_CON |
381 EDMA_ERR_OVERRUN_5 |
382 EDMA_ERR_UNDERRUN_5 |
383 EDMA_ERR_SELF_DIS_5 |
384 EDMA_ERR_CRQB_PAR |
385 EDMA_ERR_CRPB_PAR |
386 EDMA_ERR_INTRL_PAR |
387 EDMA_ERR_IORDY,
388
389 EDMA_REQ_Q_BASE_HI = 0x10,
390 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
391
392 EDMA_REQ_Q_OUT_PTR = 0x18,
393 EDMA_REQ_Q_PTR_SHIFT = 5,
394
395 EDMA_RSP_Q_BASE_HI = 0x1c,
396 EDMA_RSP_Q_IN_PTR = 0x20,
397 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
398 EDMA_RSP_Q_PTR_SHIFT = 3,
399
400 EDMA_CMD = 0x28, /* EDMA command register */
401 EDMA_EN = (1 << 0), /* enable EDMA */
402 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
403 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
404
405 EDMA_STATUS = 0x30, /* EDMA engine status */
406 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
407 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
408
409 EDMA_IORDY_TMOUT = 0x34,
410 EDMA_ARB_CFG = 0x38,
411
412 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
413 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
414
415 BMDMA_CMD = 0x224, /* bmdma command register */
416 BMDMA_STATUS = 0x228, /* bmdma status register */
417 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
418 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
419
420 /* Host private flags (hp_flags) */
421 MV_HP_FLAG_MSI = (1 << 0),
422 MV_HP_ERRATA_50XXB0 = (1 << 1),
423 MV_HP_ERRATA_50XXB2 = (1 << 2),
424 MV_HP_ERRATA_60X1B2 = (1 << 3),
425 MV_HP_ERRATA_60X1C0 = (1 << 4),
426 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
427 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
428 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
429 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
430 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
431 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
432 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
433
434 /* Port private flags (pp_flags) */
435 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
436 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
437 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
438 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
439 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
440 };
441
442 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
443 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
444 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
445 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
446 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
447
448 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
449 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
450
451 enum {
452 /* DMA boundary 0xffff is required by the s/g splitting
453 * we need on /length/ in mv_fill-sg().
454 */
455 MV_DMA_BOUNDARY = 0xffffU,
456
457 /* mask of register bits containing lower 32 bits
458 * of EDMA request queue DMA address
459 */
460 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
461
462 /* ditto, for response queue */
463 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
464 };
465
466 enum chip_type {
467 chip_504x,
468 chip_508x,
469 chip_5080,
470 chip_604x,
471 chip_608x,
472 chip_6042,
473 chip_7042,
474 chip_soc,
475 };
476
477 /* Command ReQuest Block: 32B */
478 struct mv_crqb {
479 __le32 sg_addr;
480 __le32 sg_addr_hi;
481 __le16 ctrl_flags;
482 __le16 ata_cmd[11];
483 };
484
485 struct mv_crqb_iie {
486 __le32 addr;
487 __le32 addr_hi;
488 __le32 flags;
489 __le32 len;
490 __le32 ata_cmd[4];
491 };
492
493 /* Command ResPonse Block: 8B */
494 struct mv_crpb {
495 __le16 id;
496 __le16 flags;
497 __le32 tmstmp;
498 };
499
500 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
501 struct mv_sg {
502 __le32 addr;
503 __le32 flags_size;
504 __le32 addr_hi;
505 __le32 reserved;
506 };
507
508 /*
509 * We keep a local cache of a few frequently accessed port
510 * registers here, to avoid having to read them (very slow)
511 * when switching between EDMA and non-EDMA modes.
512 */
513 struct mv_cached_regs {
514 u32 fiscfg;
515 u32 ltmode;
516 u32 haltcond;
517 u32 unknown_rsvd;
518 };
519
520 struct mv_port_priv {
521 struct mv_crqb *crqb;
522 dma_addr_t crqb_dma;
523 struct mv_crpb *crpb;
524 dma_addr_t crpb_dma;
525 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
526 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
527
528 unsigned int req_idx;
529 unsigned int resp_idx;
530
531 u32 pp_flags;
532 struct mv_cached_regs cached;
533 unsigned int delayed_eh_pmp_map;
534 };
535
536 struct mv_port_signal {
537 u32 amps;
538 u32 pre;
539 };
540
541 struct mv_host_priv {
542 u32 hp_flags;
543 unsigned int board_idx;
544 u32 main_irq_mask;
545 struct mv_port_signal signal[8];
546 const struct mv_hw_ops *ops;
547 int n_ports;
548 void __iomem *base;
549 void __iomem *main_irq_cause_addr;
550 void __iomem *main_irq_mask_addr;
551 u32 irq_cause_offset;
552 u32 irq_mask_offset;
553 u32 unmask_all_irqs;
554
555 #if defined(CONFIG_HAVE_CLK)
556 struct clk *clk;
557 #endif
558 /*
559 * These consistent DMA memory pools give us guaranteed
560 * alignment for hardware-accessed data structures,
561 * and less memory waste in accomplishing the alignment.
562 */
563 struct dma_pool *crqb_pool;
564 struct dma_pool *crpb_pool;
565 struct dma_pool *sg_tbl_pool;
566 };
567
568 struct mv_hw_ops {
569 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
570 unsigned int port);
571 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
572 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
573 void __iomem *mmio);
574 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
575 unsigned int n_hc);
576 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
577 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
578 };
579
580 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
581 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
582 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
583 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
584 static int mv_port_start(struct ata_port *ap);
585 static void mv_port_stop(struct ata_port *ap);
586 static int mv_qc_defer(struct ata_queued_cmd *qc);
587 static void mv_qc_prep(struct ata_queued_cmd *qc);
588 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
589 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
590 static int mv_hardreset(struct ata_link *link, unsigned int *class,
591 unsigned long deadline);
592 static void mv_eh_freeze(struct ata_port *ap);
593 static void mv_eh_thaw(struct ata_port *ap);
594 static void mv6_dev_config(struct ata_device *dev);
595
596 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
597 unsigned int port);
598 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
599 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
600 void __iomem *mmio);
601 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
602 unsigned int n_hc);
603 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
604 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
605
606 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
607 unsigned int port);
608 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
609 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
610 void __iomem *mmio);
611 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
612 unsigned int n_hc);
613 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
614 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
615 void __iomem *mmio);
616 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
617 void __iomem *mmio);
618 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
619 void __iomem *mmio, unsigned int n_hc);
620 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
621 void __iomem *mmio);
622 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
623 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
624 void __iomem *mmio, unsigned int port);
625 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
626 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
627 unsigned int port_no);
628 static int mv_stop_edma(struct ata_port *ap);
629 static int mv_stop_edma_engine(void __iomem *port_mmio);
630 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
631
632 static void mv_pmp_select(struct ata_port *ap, int pmp);
633 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
634 unsigned long deadline);
635 static int mv_softreset(struct ata_link *link, unsigned int *class,
636 unsigned long deadline);
637 static void mv_pmp_error_handler(struct ata_port *ap);
638 static void mv_process_crpb_entries(struct ata_port *ap,
639 struct mv_port_priv *pp);
640
641 static void mv_sff_irq_clear(struct ata_port *ap);
642 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
643 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
644 static void mv_bmdma_start(struct ata_queued_cmd *qc);
645 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
646 static u8 mv_bmdma_status(struct ata_port *ap);
647 static u8 mv_sff_check_status(struct ata_port *ap);
648
649 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
650 * because we have to allow room for worst case splitting of
651 * PRDs for 64K boundaries in mv_fill_sg().
652 */
653 static struct scsi_host_template mv5_sht = {
654 ATA_BASE_SHT(DRV_NAME),
655 .sg_tablesize = MV_MAX_SG_CT / 2,
656 .dma_boundary = MV_DMA_BOUNDARY,
657 };
658
659 static struct scsi_host_template mv6_sht = {
660 ATA_NCQ_SHT(DRV_NAME),
661 .can_queue = MV_MAX_Q_DEPTH - 1,
662 .sg_tablesize = MV_MAX_SG_CT / 2,
663 .dma_boundary = MV_DMA_BOUNDARY,
664 };
665
666 static struct ata_port_operations mv5_ops = {
667 .inherits = &ata_sff_port_ops,
668
669 .lost_interrupt = ATA_OP_NULL,
670
671 .qc_defer = mv_qc_defer,
672 .qc_prep = mv_qc_prep,
673 .qc_issue = mv_qc_issue,
674
675 .freeze = mv_eh_freeze,
676 .thaw = mv_eh_thaw,
677 .hardreset = mv_hardreset,
678
679 .scr_read = mv5_scr_read,
680 .scr_write = mv5_scr_write,
681
682 .port_start = mv_port_start,
683 .port_stop = mv_port_stop,
684 };
685
686 static struct ata_port_operations mv6_ops = {
687 .inherits = &ata_bmdma_port_ops,
688
689 .lost_interrupt = ATA_OP_NULL,
690
691 .qc_defer = mv_qc_defer,
692 .qc_prep = mv_qc_prep,
693 .qc_issue = mv_qc_issue,
694
695 .dev_config = mv6_dev_config,
696
697 .freeze = mv_eh_freeze,
698 .thaw = mv_eh_thaw,
699 .hardreset = mv_hardreset,
700 .softreset = mv_softreset,
701 .pmp_hardreset = mv_pmp_hardreset,
702 .pmp_softreset = mv_softreset,
703 .error_handler = mv_pmp_error_handler,
704
705 .scr_read = mv_scr_read,
706 .scr_write = mv_scr_write,
707
708 .sff_check_status = mv_sff_check_status,
709 .sff_irq_clear = mv_sff_irq_clear,
710 .check_atapi_dma = mv_check_atapi_dma,
711 .bmdma_setup = mv_bmdma_setup,
712 .bmdma_start = mv_bmdma_start,
713 .bmdma_stop = mv_bmdma_stop,
714 .bmdma_status = mv_bmdma_status,
715
716 .port_start = mv_port_start,
717 .port_stop = mv_port_stop,
718 };
719
720 static struct ata_port_operations mv_iie_ops = {
721 .inherits = &mv6_ops,
722 .dev_config = ATA_OP_NULL,
723 .qc_prep = mv_qc_prep_iie,
724 };
725
726 static const struct ata_port_info mv_port_info[] = {
727 { /* chip_504x */
728 .flags = MV_GEN_I_FLAGS,
729 .pio_mask = ATA_PIO4,
730 .udma_mask = ATA_UDMA6,
731 .port_ops = &mv5_ops,
732 },
733 { /* chip_508x */
734 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
735 .pio_mask = ATA_PIO4,
736 .udma_mask = ATA_UDMA6,
737 .port_ops = &mv5_ops,
738 },
739 { /* chip_5080 */
740 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
741 .pio_mask = ATA_PIO4,
742 .udma_mask = ATA_UDMA6,
743 .port_ops = &mv5_ops,
744 },
745 { /* chip_604x */
746 .flags = MV_GEN_II_FLAGS,
747 .pio_mask = ATA_PIO4,
748 .udma_mask = ATA_UDMA6,
749 .port_ops = &mv6_ops,
750 },
751 { /* chip_608x */
752 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
753 .pio_mask = ATA_PIO4,
754 .udma_mask = ATA_UDMA6,
755 .port_ops = &mv6_ops,
756 },
757 { /* chip_6042 */
758 .flags = MV_GEN_IIE_FLAGS,
759 .pio_mask = ATA_PIO4,
760 .udma_mask = ATA_UDMA6,
761 .port_ops = &mv_iie_ops,
762 },
763 { /* chip_7042 */
764 .flags = MV_GEN_IIE_FLAGS,
765 .pio_mask = ATA_PIO4,
766 .udma_mask = ATA_UDMA6,
767 .port_ops = &mv_iie_ops,
768 },
769 { /* chip_soc */
770 .flags = MV_GEN_IIE_FLAGS,
771 .pio_mask = ATA_PIO4,
772 .udma_mask = ATA_UDMA6,
773 .port_ops = &mv_iie_ops,
774 },
775 };
776
777 static const struct pci_device_id mv_pci_tbl[] = {
778 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
779 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
780 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
781 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
782 /* RocketRAID 1720/174x have different identifiers */
783 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
784 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
785 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
786
787 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
788 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
789 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
790 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
791 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
792
793 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
794
795 /* Adaptec 1430SA */
796 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
797
798 /* Marvell 7042 support */
799 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
800
801 /* Highpoint RocketRAID PCIe series */
802 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
803 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
804
805 { } /* terminate list */
806 };
807
808 static const struct mv_hw_ops mv5xxx_ops = {
809 .phy_errata = mv5_phy_errata,
810 .enable_leds = mv5_enable_leds,
811 .read_preamp = mv5_read_preamp,
812 .reset_hc = mv5_reset_hc,
813 .reset_flash = mv5_reset_flash,
814 .reset_bus = mv5_reset_bus,
815 };
816
817 static const struct mv_hw_ops mv6xxx_ops = {
818 .phy_errata = mv6_phy_errata,
819 .enable_leds = mv6_enable_leds,
820 .read_preamp = mv6_read_preamp,
821 .reset_hc = mv6_reset_hc,
822 .reset_flash = mv6_reset_flash,
823 .reset_bus = mv_reset_pci_bus,
824 };
825
826 static const struct mv_hw_ops mv_soc_ops = {
827 .phy_errata = mv6_phy_errata,
828 .enable_leds = mv_soc_enable_leds,
829 .read_preamp = mv_soc_read_preamp,
830 .reset_hc = mv_soc_reset_hc,
831 .reset_flash = mv_soc_reset_flash,
832 .reset_bus = mv_soc_reset_bus,
833 };
834
835 static const struct mv_hw_ops mv_soc_65n_ops = {
836 .phy_errata = mv_soc_65n_phy_errata,
837 .enable_leds = mv_soc_enable_leds,
838 .reset_hc = mv_soc_reset_hc,
839 .reset_flash = mv_soc_reset_flash,
840 .reset_bus = mv_soc_reset_bus,
841 };
842
843 /*
844 * Functions
845 */
846
847 static inline void writelfl(unsigned long data, void __iomem *addr)
848 {
849 writel(data, addr);
850 (void) readl(addr); /* flush to avoid PCI posted write */
851 }
852
853 static inline unsigned int mv_hc_from_port(unsigned int port)
854 {
855 return port >> MV_PORT_HC_SHIFT;
856 }
857
858 static inline unsigned int mv_hardport_from_port(unsigned int port)
859 {
860 return port & MV_PORT_MASK;
861 }
862
863 /*
864 * Consolidate some rather tricky bit shift calculations.
865 * This is hot-path stuff, so not a function.
866 * Simple code, with two return values, so macro rather than inline.
867 *
868 * port is the sole input, in range 0..7.
869 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
870 * hardport is the other output, in range 0..3.
871 *
872 * Note that port and hardport may be the same variable in some cases.
873 */
874 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
875 { \
876 shift = mv_hc_from_port(port) * HC_SHIFT; \
877 hardport = mv_hardport_from_port(port); \
878 shift += hardport * 2; \
879 }
880
881 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
882 {
883 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
884 }
885
886 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
887 unsigned int port)
888 {
889 return mv_hc_base(base, mv_hc_from_port(port));
890 }
891
892 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
893 {
894 return mv_hc_base_from_port(base, port) +
895 MV_SATAHC_ARBTR_REG_SZ +
896 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
897 }
898
899 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
900 {
901 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
902 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
903
904 return hc_mmio + ofs;
905 }
906
907 static inline void __iomem *mv_host_base(struct ata_host *host)
908 {
909 struct mv_host_priv *hpriv = host->private_data;
910 return hpriv->base;
911 }
912
913 static inline void __iomem *mv_ap_base(struct ata_port *ap)
914 {
915 return mv_port_base(mv_host_base(ap->host), ap->port_no);
916 }
917
918 static inline int mv_get_hc_count(unsigned long port_flags)
919 {
920 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
921 }
922
923 /**
924 * mv_save_cached_regs - (re-)initialize cached port registers
925 * @ap: the port whose registers we are caching
926 *
927 * Initialize the local cache of port registers,
928 * so that reading them over and over again can
929 * be avoided on the hotter paths of this driver.
930 * This saves a few microseconds each time we switch
931 * to/from EDMA mode to perform (eg.) a drive cache flush.
932 */
933 static void mv_save_cached_regs(struct ata_port *ap)
934 {
935 void __iomem *port_mmio = mv_ap_base(ap);
936 struct mv_port_priv *pp = ap->private_data;
937
938 pp->cached.fiscfg = readl(port_mmio + FISCFG);
939 pp->cached.ltmode = readl(port_mmio + LTMODE);
940 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
941 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
942 }
943
944 /**
945 * mv_write_cached_reg - write to a cached port register
946 * @addr: hardware address of the register
947 * @old: pointer to cached value of the register
948 * @new: new value for the register
949 *
950 * Write a new value to a cached register,
951 * but only if the value is different from before.
952 */
953 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
954 {
955 if (new != *old) {
956 unsigned long laddr;
957 *old = new;
958 /*
959 * Workaround for 88SX60x1-B2 FEr SATA#13:
960 * Read-after-write is needed to prevent generating 64-bit
961 * write cycles on the PCI bus for SATA interface registers
962 * at offsets ending in 0x4 or 0xc.
963 *
964 * Looks like a lot of fuss, but it avoids an unnecessary
965 * +1 usec read-after-write delay for unaffected registers.
966 */
967 laddr = (long)addr & 0xffff;
968 if (laddr >= 0x300 && laddr <= 0x33c) {
969 laddr &= 0x000f;
970 if (laddr == 0x4 || laddr == 0xc) {
971 writelfl(new, addr); /* read after write */
972 return;
973 }
974 }
975 writel(new, addr); /* unaffected by the errata */
976 }
977 }
978
979 static void mv_set_edma_ptrs(void __iomem *port_mmio,
980 struct mv_host_priv *hpriv,
981 struct mv_port_priv *pp)
982 {
983 u32 index;
984
985 /*
986 * initialize request queue
987 */
988 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
989 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
990
991 WARN_ON(pp->crqb_dma & 0x3ff);
992 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
993 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
994 port_mmio + EDMA_REQ_Q_IN_PTR);
995 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
996
997 /*
998 * initialize response queue
999 */
1000 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
1001 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
1002
1003 WARN_ON(pp->crpb_dma & 0xff);
1004 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
1005 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
1006 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
1007 port_mmio + EDMA_RSP_Q_OUT_PTR);
1008 }
1009
1010 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1011 {
1012 /*
1013 * When writing to the main_irq_mask in hardware,
1014 * we must ensure exclusivity between the interrupt coalescing bits
1015 * and the corresponding individual port DONE_IRQ bits.
1016 *
1017 * Note that this register is really an "IRQ enable" register,
1018 * not an "IRQ mask" register as Marvell's naming might suggest.
1019 */
1020 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1021 mask &= ~DONE_IRQ_0_3;
1022 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1023 mask &= ~DONE_IRQ_4_7;
1024 writelfl(mask, hpriv->main_irq_mask_addr);
1025 }
1026
1027 static void mv_set_main_irq_mask(struct ata_host *host,
1028 u32 disable_bits, u32 enable_bits)
1029 {
1030 struct mv_host_priv *hpriv = host->private_data;
1031 u32 old_mask, new_mask;
1032
1033 old_mask = hpriv->main_irq_mask;
1034 new_mask = (old_mask & ~disable_bits) | enable_bits;
1035 if (new_mask != old_mask) {
1036 hpriv->main_irq_mask = new_mask;
1037 mv_write_main_irq_mask(new_mask, hpriv);
1038 }
1039 }
1040
1041 static void mv_enable_port_irqs(struct ata_port *ap,
1042 unsigned int port_bits)
1043 {
1044 unsigned int shift, hardport, port = ap->port_no;
1045 u32 disable_bits, enable_bits;
1046
1047 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1048
1049 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1050 enable_bits = port_bits << shift;
1051 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1052 }
1053
1054 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1055 void __iomem *port_mmio,
1056 unsigned int port_irqs)
1057 {
1058 struct mv_host_priv *hpriv = ap->host->private_data;
1059 int hardport = mv_hardport_from_port(ap->port_no);
1060 void __iomem *hc_mmio = mv_hc_base_from_port(
1061 mv_host_base(ap->host), ap->port_no);
1062 u32 hc_irq_cause;
1063
1064 /* clear EDMA event indicators, if any */
1065 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
1066
1067 /* clear pending irq events */
1068 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1069 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
1070
1071 /* clear FIS IRQ Cause */
1072 if (IS_GEN_IIE(hpriv))
1073 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
1074
1075 mv_enable_port_irqs(ap, port_irqs);
1076 }
1077
1078 static void mv_set_irq_coalescing(struct ata_host *host,
1079 unsigned int count, unsigned int usecs)
1080 {
1081 struct mv_host_priv *hpriv = host->private_data;
1082 void __iomem *mmio = hpriv->base, *hc_mmio;
1083 u32 coal_enable = 0;
1084 unsigned long flags;
1085 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1086 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1087 ALL_PORTS_COAL_DONE;
1088
1089 /* Disable IRQ coalescing if either threshold is zero */
1090 if (!usecs || !count) {
1091 clks = count = 0;
1092 } else {
1093 /* Respect maximum limits of the hardware */
1094 clks = usecs * COAL_CLOCKS_PER_USEC;
1095 if (clks > MAX_COAL_TIME_THRESHOLD)
1096 clks = MAX_COAL_TIME_THRESHOLD;
1097 if (count > MAX_COAL_IO_COUNT)
1098 count = MAX_COAL_IO_COUNT;
1099 }
1100
1101 spin_lock_irqsave(&host->lock, flags);
1102 mv_set_main_irq_mask(host, coal_disable, 0);
1103
1104 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1105 /*
1106 * GEN_II/GEN_IIE with dual host controllers:
1107 * one set of global thresholds for the entire chip.
1108 */
1109 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1110 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
1111 /* clear leftover coal IRQ bit */
1112 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
1113 if (count)
1114 coal_enable = ALL_PORTS_COAL_DONE;
1115 clks = count = 0; /* force clearing of regular regs below */
1116 }
1117
1118 /*
1119 * All chips: independent thresholds for each HC on the chip.
1120 */
1121 hc_mmio = mv_hc_base_from_port(mmio, 0);
1122 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1123 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1124 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1125 if (count)
1126 coal_enable |= PORTS_0_3_COAL_DONE;
1127 if (is_dual_hc) {
1128 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1129 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1130 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1131 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1132 if (count)
1133 coal_enable |= PORTS_4_7_COAL_DONE;
1134 }
1135
1136 mv_set_main_irq_mask(host, 0, coal_enable);
1137 spin_unlock_irqrestore(&host->lock, flags);
1138 }
1139
1140 /**
1141 * mv_start_edma - Enable eDMA engine
1142 * @base: port base address
1143 * @pp: port private data
1144 *
1145 * Verify the local cache of the eDMA state is accurate with a
1146 * WARN_ON.
1147 *
1148 * LOCKING:
1149 * Inherited from caller.
1150 */
1151 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1152 struct mv_port_priv *pp, u8 protocol)
1153 {
1154 int want_ncq = (protocol == ATA_PROT_NCQ);
1155
1156 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1157 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1158 if (want_ncq != using_ncq)
1159 mv_stop_edma(ap);
1160 }
1161 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1162 struct mv_host_priv *hpriv = ap->host->private_data;
1163
1164 mv_edma_cfg(ap, want_ncq, 1);
1165
1166 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1167 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1168
1169 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
1170 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1171 }
1172 }
1173
1174 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1175 {
1176 void __iomem *port_mmio = mv_ap_base(ap);
1177 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1178 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1179 int i;
1180
1181 /*
1182 * Wait for the EDMA engine to finish transactions in progress.
1183 * No idea what a good "timeout" value might be, but measurements
1184 * indicate that it often requires hundreds of microseconds
1185 * with two drives in-use. So we use the 15msec value above
1186 * as a rough guess at what even more drives might require.
1187 */
1188 for (i = 0; i < timeout; ++i) {
1189 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
1190 if ((edma_stat & empty_idle) == empty_idle)
1191 break;
1192 udelay(per_loop);
1193 }
1194 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1195 }
1196
1197 /**
1198 * mv_stop_edma_engine - Disable eDMA engine
1199 * @port_mmio: io base address
1200 *
1201 * LOCKING:
1202 * Inherited from caller.
1203 */
1204 static int mv_stop_edma_engine(void __iomem *port_mmio)
1205 {
1206 int i;
1207
1208 /* Disable eDMA. The disable bit auto clears. */
1209 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
1210
1211 /* Wait for the chip to confirm eDMA is off. */
1212 for (i = 10000; i > 0; i--) {
1213 u32 reg = readl(port_mmio + EDMA_CMD);
1214 if (!(reg & EDMA_EN))
1215 return 0;
1216 udelay(10);
1217 }
1218 return -EIO;
1219 }
1220
1221 static int mv_stop_edma(struct ata_port *ap)
1222 {
1223 void __iomem *port_mmio = mv_ap_base(ap);
1224 struct mv_port_priv *pp = ap->private_data;
1225 int err = 0;
1226
1227 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1228 return 0;
1229 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1230 mv_wait_for_edma_empty_idle(ap);
1231 if (mv_stop_edma_engine(port_mmio)) {
1232 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
1233 err = -EIO;
1234 }
1235 mv_edma_cfg(ap, 0, 0);
1236 return err;
1237 }
1238
1239 #ifdef ATA_DEBUG
1240 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1241 {
1242 int b, w;
1243 for (b = 0; b < bytes; ) {
1244 DPRINTK("%p: ", start + b);
1245 for (w = 0; b < bytes && w < 4; w++) {
1246 printk("%08x ", readl(start + b));
1247 b += sizeof(u32);
1248 }
1249 printk("\n");
1250 }
1251 }
1252 #endif
1253
1254 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1255 {
1256 #ifdef ATA_DEBUG
1257 int b, w;
1258 u32 dw;
1259 for (b = 0; b < bytes; ) {
1260 DPRINTK("%02x: ", b);
1261 for (w = 0; b < bytes && w < 4; w++) {
1262 (void) pci_read_config_dword(pdev, b, &dw);
1263 printk("%08x ", dw);
1264 b += sizeof(u32);
1265 }
1266 printk("\n");
1267 }
1268 #endif
1269 }
1270 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1271 struct pci_dev *pdev)
1272 {
1273 #ifdef ATA_DEBUG
1274 void __iomem *hc_base = mv_hc_base(mmio_base,
1275 port >> MV_PORT_HC_SHIFT);
1276 void __iomem *port_base;
1277 int start_port, num_ports, p, start_hc, num_hcs, hc;
1278
1279 if (0 > port) {
1280 start_hc = start_port = 0;
1281 num_ports = 8; /* shld be benign for 4 port devs */
1282 num_hcs = 2;
1283 } else {
1284 start_hc = port >> MV_PORT_HC_SHIFT;
1285 start_port = port;
1286 num_ports = num_hcs = 1;
1287 }
1288 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1289 num_ports > 1 ? num_ports - 1 : start_port);
1290
1291 if (NULL != pdev) {
1292 DPRINTK("PCI config space regs:\n");
1293 mv_dump_pci_cfg(pdev, 0x68);
1294 }
1295 DPRINTK("PCI regs:\n");
1296 mv_dump_mem(mmio_base+0xc00, 0x3c);
1297 mv_dump_mem(mmio_base+0xd00, 0x34);
1298 mv_dump_mem(mmio_base+0xf00, 0x4);
1299 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1300 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1301 hc_base = mv_hc_base(mmio_base, hc);
1302 DPRINTK("HC regs (HC %i):\n", hc);
1303 mv_dump_mem(hc_base, 0x1c);
1304 }
1305 for (p = start_port; p < start_port + num_ports; p++) {
1306 port_base = mv_port_base(mmio_base, p);
1307 DPRINTK("EDMA regs (port %i):\n", p);
1308 mv_dump_mem(port_base, 0x54);
1309 DPRINTK("SATA regs (port %i):\n", p);
1310 mv_dump_mem(port_base+0x300, 0x60);
1311 }
1312 #endif
1313 }
1314
1315 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1316 {
1317 unsigned int ofs;
1318
1319 switch (sc_reg_in) {
1320 case SCR_STATUS:
1321 case SCR_CONTROL:
1322 case SCR_ERROR:
1323 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
1324 break;
1325 case SCR_ACTIVE:
1326 ofs = SATA_ACTIVE; /* active is not with the others */
1327 break;
1328 default:
1329 ofs = 0xffffffffU;
1330 break;
1331 }
1332 return ofs;
1333 }
1334
1335 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1336 {
1337 unsigned int ofs = mv_scr_offset(sc_reg_in);
1338
1339 if (ofs != 0xffffffffU) {
1340 *val = readl(mv_ap_base(link->ap) + ofs);
1341 return 0;
1342 } else
1343 return -EINVAL;
1344 }
1345
1346 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1347 {
1348 unsigned int ofs = mv_scr_offset(sc_reg_in);
1349
1350 if (ofs != 0xffffffffU) {
1351 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1352 if (sc_reg_in == SCR_CONTROL) {
1353 /*
1354 * Workaround for 88SX60x1 FEr SATA#26:
1355 *
1356 * COMRESETs have to take care not to accidently
1357 * put the drive to sleep when writing SCR_CONTROL.
1358 * Setting bits 12..15 prevents this problem.
1359 *
1360 * So if we see an outbound COMMRESET, set those bits.
1361 * Ditto for the followup write that clears the reset.
1362 *
1363 * The proprietary driver does this for
1364 * all chip versions, and so do we.
1365 */
1366 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1367 val |= 0xf000;
1368 }
1369 writelfl(val, addr);
1370 return 0;
1371 } else
1372 return -EINVAL;
1373 }
1374
1375 static void mv6_dev_config(struct ata_device *adev)
1376 {
1377 /*
1378 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1379 *
1380 * Gen-II does not support NCQ over a port multiplier
1381 * (no FIS-based switching).
1382 */
1383 if (adev->flags & ATA_DFLAG_NCQ) {
1384 if (sata_pmp_attached(adev->link->ap)) {
1385 adev->flags &= ~ATA_DFLAG_NCQ;
1386 ata_dev_printk(adev, KERN_INFO,
1387 "NCQ disabled for command-based switching\n");
1388 }
1389 }
1390 }
1391
1392 static int mv_qc_defer(struct ata_queued_cmd *qc)
1393 {
1394 struct ata_link *link = qc->dev->link;
1395 struct ata_port *ap = link->ap;
1396 struct mv_port_priv *pp = ap->private_data;
1397
1398 /*
1399 * Don't allow new commands if we're in a delayed EH state
1400 * for NCQ and/or FIS-based switching.
1401 */
1402 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1403 return ATA_DEFER_PORT;
1404
1405 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1406 * can run concurrently.
1407 * set excl_link when we want to send a PIO command in DMA mode
1408 * or a non-NCQ command in NCQ mode.
1409 * When we receive a command from that link, and there are no
1410 * outstanding commands, mark a flag to clear excl_link and let
1411 * the command go through.
1412 */
1413 if (unlikely(ap->excl_link)) {
1414 if (link == ap->excl_link) {
1415 if (ap->nr_active_links)
1416 return ATA_DEFER_PORT;
1417 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1418 return 0;
1419 } else
1420 return ATA_DEFER_PORT;
1421 }
1422
1423 /*
1424 * If the port is completely idle, then allow the new qc.
1425 */
1426 if (ap->nr_active_links == 0)
1427 return 0;
1428
1429 /*
1430 * The port is operating in host queuing mode (EDMA) with NCQ
1431 * enabled, allow multiple NCQ commands. EDMA also allows
1432 * queueing multiple DMA commands but libata core currently
1433 * doesn't allow it.
1434 */
1435 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1436 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1437 if (ata_is_ncq(qc->tf.protocol))
1438 return 0;
1439 else {
1440 ap->excl_link = link;
1441 return ATA_DEFER_PORT;
1442 }
1443 }
1444
1445 return ATA_DEFER_PORT;
1446 }
1447
1448 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1449 {
1450 struct mv_port_priv *pp = ap->private_data;
1451 void __iomem *port_mmio;
1452
1453 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1454 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1455 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1456
1457 ltmode = *old_ltmode & ~LTMODE_BIT8;
1458 haltcond = *old_haltcond | EDMA_ERR_DEV;
1459
1460 if (want_fbs) {
1461 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1462 ltmode = *old_ltmode | LTMODE_BIT8;
1463 if (want_ncq)
1464 haltcond &= ~EDMA_ERR_DEV;
1465 else
1466 fiscfg |= FISCFG_WAIT_DEV_ERR;
1467 } else {
1468 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1469 }
1470
1471 port_mmio = mv_ap_base(ap);
1472 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1473 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1474 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
1475 }
1476
1477 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1478 {
1479 struct mv_host_priv *hpriv = ap->host->private_data;
1480 u32 old, new;
1481
1482 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1483 old = readl(hpriv->base + GPIO_PORT_CTL);
1484 if (want_ncq)
1485 new = old | (1 << 22);
1486 else
1487 new = old & ~(1 << 22);
1488 if (new != old)
1489 writel(new, hpriv->base + GPIO_PORT_CTL);
1490 }
1491
1492 /**
1493 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1494 * @ap: Port being initialized
1495 *
1496 * There are two DMA modes on these chips: basic DMA, and EDMA.
1497 *
1498 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1499 * of basic DMA on the GEN_IIE versions of the chips.
1500 *
1501 * This bit survives EDMA resets, and must be set for basic DMA
1502 * to function, and should be cleared when EDMA is active.
1503 */
1504 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1505 {
1506 struct mv_port_priv *pp = ap->private_data;
1507 u32 new, *old = &pp->cached.unknown_rsvd;
1508
1509 if (enable_bmdma)
1510 new = *old | 1;
1511 else
1512 new = *old & ~1;
1513 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
1514 }
1515
1516 /*
1517 * SOC chips have an issue whereby the HDD LEDs don't always blink
1518 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1519 * of the SOC takes care of it, generating a steady blink rate when
1520 * any drive on the chip is active.
1521 *
1522 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1523 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1524 *
1525 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1526 * LED operation works then, and provides better (more accurate) feedback.
1527 *
1528 * Note that this code assumes that an SOC never has more than one HC onboard.
1529 */
1530 static void mv_soc_led_blink_enable(struct ata_port *ap)
1531 {
1532 struct ata_host *host = ap->host;
1533 struct mv_host_priv *hpriv = host->private_data;
1534 void __iomem *hc_mmio;
1535 u32 led_ctrl;
1536
1537 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1538 return;
1539 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1540 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1541 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1542 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1543 }
1544
1545 static void mv_soc_led_blink_disable(struct ata_port *ap)
1546 {
1547 struct ata_host *host = ap->host;
1548 struct mv_host_priv *hpriv = host->private_data;
1549 void __iomem *hc_mmio;
1550 u32 led_ctrl;
1551 unsigned int port;
1552
1553 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1554 return;
1555
1556 /* disable led-blink only if no ports are using NCQ */
1557 for (port = 0; port < hpriv->n_ports; port++) {
1558 struct ata_port *this_ap = host->ports[port];
1559 struct mv_port_priv *pp = this_ap->private_data;
1560
1561 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1562 return;
1563 }
1564
1565 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1566 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1567 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1568 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1569 }
1570
1571 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1572 {
1573 u32 cfg;
1574 struct mv_port_priv *pp = ap->private_data;
1575 struct mv_host_priv *hpriv = ap->host->private_data;
1576 void __iomem *port_mmio = mv_ap_base(ap);
1577
1578 /* set up non-NCQ EDMA configuration */
1579 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1580 pp->pp_flags &=
1581 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1582
1583 if (IS_GEN_I(hpriv))
1584 cfg |= (1 << 8); /* enab config burst size mask */
1585
1586 else if (IS_GEN_II(hpriv)) {
1587 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1588 mv_60x1_errata_sata25(ap, want_ncq);
1589
1590 } else if (IS_GEN_IIE(hpriv)) {
1591 int want_fbs = sata_pmp_attached(ap);
1592 /*
1593 * Possible future enhancement:
1594 *
1595 * The chip can use FBS with non-NCQ, if we allow it,
1596 * But first we need to have the error handling in place
1597 * for this mode (datasheet section 7.3.15.4.2.3).
1598 * So disallow non-NCQ FBS for now.
1599 */
1600 want_fbs &= want_ncq;
1601
1602 mv_config_fbs(ap, want_ncq, want_fbs);
1603
1604 if (want_fbs) {
1605 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1606 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1607 }
1608
1609 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1610 if (want_edma) {
1611 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1612 if (!IS_SOC(hpriv))
1613 cfg |= (1 << 18); /* enab early completion */
1614 }
1615 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1616 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1617 mv_bmdma_enable_iie(ap, !want_edma);
1618
1619 if (IS_SOC(hpriv)) {
1620 if (want_ncq)
1621 mv_soc_led_blink_enable(ap);
1622 else
1623 mv_soc_led_blink_disable(ap);
1624 }
1625 }
1626
1627 if (want_ncq) {
1628 cfg |= EDMA_CFG_NCQ;
1629 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1630 }
1631
1632 writelfl(cfg, port_mmio + EDMA_CFG);
1633 }
1634
1635 static void mv_port_free_dma_mem(struct ata_port *ap)
1636 {
1637 struct mv_host_priv *hpriv = ap->host->private_data;
1638 struct mv_port_priv *pp = ap->private_data;
1639 int tag;
1640
1641 if (pp->crqb) {
1642 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1643 pp->crqb = NULL;
1644 }
1645 if (pp->crpb) {
1646 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1647 pp->crpb = NULL;
1648 }
1649 /*
1650 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1651 * For later hardware, we have one unique sg_tbl per NCQ tag.
1652 */
1653 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1654 if (pp->sg_tbl[tag]) {
1655 if (tag == 0 || !IS_GEN_I(hpriv))
1656 dma_pool_free(hpriv->sg_tbl_pool,
1657 pp->sg_tbl[tag],
1658 pp->sg_tbl_dma[tag]);
1659 pp->sg_tbl[tag] = NULL;
1660 }
1661 }
1662 }
1663
1664 /**
1665 * mv_port_start - Port specific init/start routine.
1666 * @ap: ATA channel to manipulate
1667 *
1668 * Allocate and point to DMA memory, init port private memory,
1669 * zero indices.
1670 *
1671 * LOCKING:
1672 * Inherited from caller.
1673 */
1674 static int mv_port_start(struct ata_port *ap)
1675 {
1676 struct device *dev = ap->host->dev;
1677 struct mv_host_priv *hpriv = ap->host->private_data;
1678 struct mv_port_priv *pp;
1679 unsigned long flags;
1680 int tag;
1681
1682 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1683 if (!pp)
1684 return -ENOMEM;
1685 ap->private_data = pp;
1686
1687 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1688 if (!pp->crqb)
1689 return -ENOMEM;
1690 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1691
1692 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1693 if (!pp->crpb)
1694 goto out_port_free_dma_mem;
1695 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1696
1697 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1698 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1699 ap->flags |= ATA_FLAG_AN;
1700 /*
1701 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1702 * For later hardware, we need one unique sg_tbl per NCQ tag.
1703 */
1704 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1705 if (tag == 0 || !IS_GEN_I(hpriv)) {
1706 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1707 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1708 if (!pp->sg_tbl[tag])
1709 goto out_port_free_dma_mem;
1710 } else {
1711 pp->sg_tbl[tag] = pp->sg_tbl[0];
1712 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1713 }
1714 }
1715
1716 spin_lock_irqsave(ap->lock, flags);
1717 mv_save_cached_regs(ap);
1718 mv_edma_cfg(ap, 0, 0);
1719 spin_unlock_irqrestore(ap->lock, flags);
1720
1721 return 0;
1722
1723 out_port_free_dma_mem:
1724 mv_port_free_dma_mem(ap);
1725 return -ENOMEM;
1726 }
1727
1728 /**
1729 * mv_port_stop - Port specific cleanup/stop routine.
1730 * @ap: ATA channel to manipulate
1731 *
1732 * Stop DMA, cleanup port memory.
1733 *
1734 * LOCKING:
1735 * This routine uses the host lock to protect the DMA stop.
1736 */
1737 static void mv_port_stop(struct ata_port *ap)
1738 {
1739 unsigned long flags;
1740
1741 spin_lock_irqsave(ap->lock, flags);
1742 mv_stop_edma(ap);
1743 mv_enable_port_irqs(ap, 0);
1744 spin_unlock_irqrestore(ap->lock, flags);
1745 mv_port_free_dma_mem(ap);
1746 }
1747
1748 /**
1749 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1750 * @qc: queued command whose SG list to source from
1751 *
1752 * Populate the SG list and mark the last entry.
1753 *
1754 * LOCKING:
1755 * Inherited from caller.
1756 */
1757 static void mv_fill_sg(struct ata_queued_cmd *qc)
1758 {
1759 struct mv_port_priv *pp = qc->ap->private_data;
1760 struct scatterlist *sg;
1761 struct mv_sg *mv_sg, *last_sg = NULL;
1762 unsigned int si;
1763
1764 mv_sg = pp->sg_tbl[qc->tag];
1765 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1766 dma_addr_t addr = sg_dma_address(sg);
1767 u32 sg_len = sg_dma_len(sg);
1768
1769 while (sg_len) {
1770 u32 offset = addr & 0xffff;
1771 u32 len = sg_len;
1772
1773 if (offset + len > 0x10000)
1774 len = 0x10000 - offset;
1775
1776 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1777 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1778 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1779 mv_sg->reserved = 0;
1780
1781 sg_len -= len;
1782 addr += len;
1783
1784 last_sg = mv_sg;
1785 mv_sg++;
1786 }
1787 }
1788
1789 if (likely(last_sg))
1790 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1791 mb(); /* ensure data structure is visible to the chipset */
1792 }
1793
1794 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1795 {
1796 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1797 (last ? CRQB_CMD_LAST : 0);
1798 *cmdw = cpu_to_le16(tmp);
1799 }
1800
1801 /**
1802 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1803 * @ap: Port associated with this ATA transaction.
1804 *
1805 * We need this only for ATAPI bmdma transactions,
1806 * as otherwise we experience spurious interrupts
1807 * after libata-sff handles the bmdma interrupts.
1808 */
1809 static void mv_sff_irq_clear(struct ata_port *ap)
1810 {
1811 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1812 }
1813
1814 /**
1815 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1816 * @qc: queued command to check for chipset/DMA compatibility.
1817 *
1818 * The bmdma engines cannot handle speculative data sizes
1819 * (bytecount under/over flow). So only allow DMA for
1820 * data transfer commands with known data sizes.
1821 *
1822 * LOCKING:
1823 * Inherited from caller.
1824 */
1825 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1826 {
1827 struct scsi_cmnd *scmd = qc->scsicmd;
1828
1829 if (scmd) {
1830 switch (scmd->cmnd[0]) {
1831 case READ_6:
1832 case READ_10:
1833 case READ_12:
1834 case WRITE_6:
1835 case WRITE_10:
1836 case WRITE_12:
1837 case GPCMD_READ_CD:
1838 case GPCMD_SEND_DVD_STRUCTURE:
1839 case GPCMD_SEND_CUE_SHEET:
1840 return 0; /* DMA is safe */
1841 }
1842 }
1843 return -EOPNOTSUPP; /* use PIO instead */
1844 }
1845
1846 /**
1847 * mv_bmdma_setup - Set up BMDMA transaction
1848 * @qc: queued command to prepare DMA for.
1849 *
1850 * LOCKING:
1851 * Inherited from caller.
1852 */
1853 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1854 {
1855 struct ata_port *ap = qc->ap;
1856 void __iomem *port_mmio = mv_ap_base(ap);
1857 struct mv_port_priv *pp = ap->private_data;
1858
1859 mv_fill_sg(qc);
1860
1861 /* clear all DMA cmd bits */
1862 writel(0, port_mmio + BMDMA_CMD);
1863
1864 /* load PRD table addr. */
1865 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1866 port_mmio + BMDMA_PRD_HIGH);
1867 writelfl(pp->sg_tbl_dma[qc->tag],
1868 port_mmio + BMDMA_PRD_LOW);
1869
1870 /* issue r/w command */
1871 ap->ops->sff_exec_command(ap, &qc->tf);
1872 }
1873
1874 /**
1875 * mv_bmdma_start - Start a BMDMA transaction
1876 * @qc: queued command to start DMA on.
1877 *
1878 * LOCKING:
1879 * Inherited from caller.
1880 */
1881 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1882 {
1883 struct ata_port *ap = qc->ap;
1884 void __iomem *port_mmio = mv_ap_base(ap);
1885 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1886 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1887
1888 /* start host DMA transaction */
1889 writelfl(cmd, port_mmio + BMDMA_CMD);
1890 }
1891
1892 /**
1893 * mv_bmdma_stop - Stop BMDMA transfer
1894 * @qc: queued command to stop DMA on.
1895 *
1896 * Clears the ATA_DMA_START flag in the bmdma control register
1897 *
1898 * LOCKING:
1899 * Inherited from caller.
1900 */
1901 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1902 {
1903 struct ata_port *ap = qc->ap;
1904 void __iomem *port_mmio = mv_ap_base(ap);
1905 u32 cmd;
1906
1907 /* clear start/stop bit */
1908 cmd = readl(port_mmio + BMDMA_CMD);
1909 cmd &= ~ATA_DMA_START;
1910 writelfl(cmd, port_mmio + BMDMA_CMD);
1911
1912 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1913 ata_sff_dma_pause(ap);
1914 }
1915
1916 /**
1917 * mv_bmdma_status - Read BMDMA status
1918 * @ap: port for which to retrieve DMA status.
1919 *
1920 * Read and return equivalent of the sff BMDMA status register.
1921 *
1922 * LOCKING:
1923 * Inherited from caller.
1924 */
1925 static u8 mv_bmdma_status(struct ata_port *ap)
1926 {
1927 void __iomem *port_mmio = mv_ap_base(ap);
1928 u32 reg, status;
1929
1930 /*
1931 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1932 * and the ATA_DMA_INTR bit doesn't exist.
1933 */
1934 reg = readl(port_mmio + BMDMA_STATUS);
1935 if (reg & ATA_DMA_ACTIVE)
1936 status = ATA_DMA_ACTIVE;
1937 else
1938 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1939 return status;
1940 }
1941
1942 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1943 {
1944 struct ata_taskfile *tf = &qc->tf;
1945 /*
1946 * Workaround for 88SX60x1 FEr SATA#24.
1947 *
1948 * Chip may corrupt WRITEs if multi_count >= 4kB.
1949 * Note that READs are unaffected.
1950 *
1951 * It's not clear if this errata really means "4K bytes",
1952 * or if it always happens for multi_count > 7
1953 * regardless of device sector_size.
1954 *
1955 * So, for safety, any write with multi_count > 7
1956 * gets converted here into a regular PIO write instead:
1957 */
1958 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1959 if (qc->dev->multi_count > 7) {
1960 switch (tf->command) {
1961 case ATA_CMD_WRITE_MULTI:
1962 tf->command = ATA_CMD_PIO_WRITE;
1963 break;
1964 case ATA_CMD_WRITE_MULTI_FUA_EXT:
1965 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1966 /* fall through */
1967 case ATA_CMD_WRITE_MULTI_EXT:
1968 tf->command = ATA_CMD_PIO_WRITE_EXT;
1969 break;
1970 }
1971 }
1972 }
1973 }
1974
1975 /**
1976 * mv_qc_prep - Host specific command preparation.
1977 * @qc: queued command to prepare
1978 *
1979 * This routine simply redirects to the general purpose routine
1980 * if command is not DMA. Else, it handles prep of the CRQB
1981 * (command request block), does some sanity checking, and calls
1982 * the SG load routine.
1983 *
1984 * LOCKING:
1985 * Inherited from caller.
1986 */
1987 static void mv_qc_prep(struct ata_queued_cmd *qc)
1988 {
1989 struct ata_port *ap = qc->ap;
1990 struct mv_port_priv *pp = ap->private_data;
1991 __le16 *cw;
1992 struct ata_taskfile *tf = &qc->tf;
1993 u16 flags = 0;
1994 unsigned in_index;
1995
1996 switch (tf->protocol) {
1997 case ATA_PROT_DMA:
1998 case ATA_PROT_NCQ:
1999 break; /* continue below */
2000 case ATA_PROT_PIO:
2001 mv_rw_multi_errata_sata24(qc);
2002 return;
2003 default:
2004 return;
2005 }
2006
2007 /* Fill in command request block
2008 */
2009 if (!(tf->flags & ATA_TFLAG_WRITE))
2010 flags |= CRQB_FLAG_READ;
2011 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2012 flags |= qc->tag << CRQB_TAG_SHIFT;
2013 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2014
2015 /* get current queue index from software */
2016 in_index = pp->req_idx;
2017
2018 pp->crqb[in_index].sg_addr =
2019 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2020 pp->crqb[in_index].sg_addr_hi =
2021 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2022 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2023
2024 cw = &pp->crqb[in_index].ata_cmd[0];
2025
2026 /* Sadly, the CRQB cannot accomodate all registers--there are
2027 * only 11 bytes...so we must pick and choose required
2028 * registers based on the command. So, we drop feature and
2029 * hob_feature for [RW] DMA commands, but they are needed for
2030 * NCQ. NCQ will drop hob_nsect, which is not needed there
2031 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
2032 */
2033 switch (tf->command) {
2034 case ATA_CMD_READ:
2035 case ATA_CMD_READ_EXT:
2036 case ATA_CMD_WRITE:
2037 case ATA_CMD_WRITE_EXT:
2038 case ATA_CMD_WRITE_FUA_EXT:
2039 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2040 break;
2041 case ATA_CMD_FPDMA_READ:
2042 case ATA_CMD_FPDMA_WRITE:
2043 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
2044 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2045 break;
2046 default:
2047 /* The only other commands EDMA supports in non-queued and
2048 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2049 * of which are defined/used by Linux. If we get here, this
2050 * driver needs work.
2051 *
2052 * FIXME: modify libata to give qc_prep a return value and
2053 * return error here.
2054 */
2055 BUG_ON(tf->command);
2056 break;
2057 }
2058 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2059 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2060 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2061 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2062 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2063 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2064 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2065 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2066 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2067
2068 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2069 return;
2070 mv_fill_sg(qc);
2071 }
2072
2073 /**
2074 * mv_qc_prep_iie - Host specific command preparation.
2075 * @qc: queued command to prepare
2076 *
2077 * This routine simply redirects to the general purpose routine
2078 * if command is not DMA. Else, it handles prep of the CRQB
2079 * (command request block), does some sanity checking, and calls
2080 * the SG load routine.
2081 *
2082 * LOCKING:
2083 * Inherited from caller.
2084 */
2085 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2086 {
2087 struct ata_port *ap = qc->ap;
2088 struct mv_port_priv *pp = ap->private_data;
2089 struct mv_crqb_iie *crqb;
2090 struct ata_taskfile *tf = &qc->tf;
2091 unsigned in_index;
2092 u32 flags = 0;
2093
2094 if ((tf->protocol != ATA_PROT_DMA) &&
2095 (tf->protocol != ATA_PROT_NCQ))
2096 return;
2097
2098 /* Fill in Gen IIE command request block */
2099 if (!(tf->flags & ATA_TFLAG_WRITE))
2100 flags |= CRQB_FLAG_READ;
2101
2102 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2103 flags |= qc->tag << CRQB_TAG_SHIFT;
2104 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
2105 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2106
2107 /* get current queue index from software */
2108 in_index = pp->req_idx;
2109
2110 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2111 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2112 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2113 crqb->flags = cpu_to_le32(flags);
2114
2115 crqb->ata_cmd[0] = cpu_to_le32(
2116 (tf->command << 16) |
2117 (tf->feature << 24)
2118 );
2119 crqb->ata_cmd[1] = cpu_to_le32(
2120 (tf->lbal << 0) |
2121 (tf->lbam << 8) |
2122 (tf->lbah << 16) |
2123 (tf->device << 24)
2124 );
2125 crqb->ata_cmd[2] = cpu_to_le32(
2126 (tf->hob_lbal << 0) |
2127 (tf->hob_lbam << 8) |
2128 (tf->hob_lbah << 16) |
2129 (tf->hob_feature << 24)
2130 );
2131 crqb->ata_cmd[3] = cpu_to_le32(
2132 (tf->nsect << 0) |
2133 (tf->hob_nsect << 8)
2134 );
2135
2136 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2137 return;
2138 mv_fill_sg(qc);
2139 }
2140
2141 /**
2142 * mv_sff_check_status - fetch device status, if valid
2143 * @ap: ATA port to fetch status from
2144 *
2145 * When using command issue via mv_qc_issue_fis(),
2146 * the initial ATA_BUSY state does not show up in the
2147 * ATA status (shadow) register. This can confuse libata!
2148 *
2149 * So we have a hook here to fake ATA_BUSY for that situation,
2150 * until the first time a BUSY, DRQ, or ERR bit is seen.
2151 *
2152 * The rest of the time, it simply returns the ATA status register.
2153 */
2154 static u8 mv_sff_check_status(struct ata_port *ap)
2155 {
2156 u8 stat = ioread8(ap->ioaddr.status_addr);
2157 struct mv_port_priv *pp = ap->private_data;
2158
2159 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2160 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2161 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2162 else
2163 stat = ATA_BUSY;
2164 }
2165 return stat;
2166 }
2167
2168 /**
2169 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2170 * @fis: fis to be sent
2171 * @nwords: number of 32-bit words in the fis
2172 */
2173 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2174 {
2175 void __iomem *port_mmio = mv_ap_base(ap);
2176 u32 ifctl, old_ifctl, ifstat;
2177 int i, timeout = 200, final_word = nwords - 1;
2178
2179 /* Initiate FIS transmission mode */
2180 old_ifctl = readl(port_mmio + SATA_IFCTL);
2181 ifctl = 0x100 | (old_ifctl & 0xf);
2182 writelfl(ifctl, port_mmio + SATA_IFCTL);
2183
2184 /* Send all words of the FIS except for the final word */
2185 for (i = 0; i < final_word; ++i)
2186 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
2187
2188 /* Flag end-of-transmission, and then send the final word */
2189 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2190 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
2191
2192 /*
2193 * Wait for FIS transmission to complete.
2194 * This typically takes just a single iteration.
2195 */
2196 do {
2197 ifstat = readl(port_mmio + SATA_IFSTAT);
2198 } while (!(ifstat & 0x1000) && --timeout);
2199
2200 /* Restore original port configuration */
2201 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
2202
2203 /* See if it worked */
2204 if ((ifstat & 0x3000) != 0x1000) {
2205 ata_port_printk(ap, KERN_WARNING,
2206 "%s transmission error, ifstat=%08x\n",
2207 __func__, ifstat);
2208 return AC_ERR_OTHER;
2209 }
2210 return 0;
2211 }
2212
2213 /**
2214 * mv_qc_issue_fis - Issue a command directly as a FIS
2215 * @qc: queued command to start
2216 *
2217 * Note that the ATA shadow registers are not updated
2218 * after command issue, so the device will appear "READY"
2219 * if polled, even while it is BUSY processing the command.
2220 *
2221 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2222 *
2223 * Note: we don't get updated shadow regs on *completion*
2224 * of non-data commands. So avoid sending them via this function,
2225 * as they will appear to have completed immediately.
2226 *
2227 * GEN_IIE has special registers that we could get the result tf from,
2228 * but earlier chipsets do not. For now, we ignore those registers.
2229 */
2230 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2231 {
2232 struct ata_port *ap = qc->ap;
2233 struct mv_port_priv *pp = ap->private_data;
2234 struct ata_link *link = qc->dev->link;
2235 u32 fis[5];
2236 int err = 0;
2237
2238 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2239 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
2240 if (err)
2241 return err;
2242
2243 switch (qc->tf.protocol) {
2244 case ATAPI_PROT_PIO:
2245 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2246 /* fall through */
2247 case ATAPI_PROT_NODATA:
2248 ap->hsm_task_state = HSM_ST_FIRST;
2249 break;
2250 case ATA_PROT_PIO:
2251 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2252 if (qc->tf.flags & ATA_TFLAG_WRITE)
2253 ap->hsm_task_state = HSM_ST_FIRST;
2254 else
2255 ap->hsm_task_state = HSM_ST;
2256 break;
2257 default:
2258 ap->hsm_task_state = HSM_ST_LAST;
2259 break;
2260 }
2261
2262 if (qc->tf.flags & ATA_TFLAG_POLLING)
2263 ata_sff_queue_pio_task(ap, 0);
2264 return 0;
2265 }
2266
2267 /**
2268 * mv_qc_issue - Initiate a command to the host
2269 * @qc: queued command to start
2270 *
2271 * This routine simply redirects to the general purpose routine
2272 * if command is not DMA. Else, it sanity checks our local
2273 * caches of the request producer/consumer indices then enables
2274 * DMA and bumps the request producer index.
2275 *
2276 * LOCKING:
2277 * Inherited from caller.
2278 */
2279 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2280 {
2281 static int limit_warnings = 10;
2282 struct ata_port *ap = qc->ap;
2283 void __iomem *port_mmio = mv_ap_base(ap);
2284 struct mv_port_priv *pp = ap->private_data;
2285 u32 in_index;
2286 unsigned int port_irqs;
2287
2288 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2289
2290 switch (qc->tf.protocol) {
2291 case ATA_PROT_DMA:
2292 case ATA_PROT_NCQ:
2293 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2294 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2295 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2296
2297 /* Write the request in pointer to kick the EDMA to life */
2298 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2299 port_mmio + EDMA_REQ_Q_IN_PTR);
2300 return 0;
2301
2302 case ATA_PROT_PIO:
2303 /*
2304 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2305 *
2306 * Someday, we might implement special polling workarounds
2307 * for these, but it all seems rather unnecessary since we
2308 * normally use only DMA for commands which transfer more
2309 * than a single block of data.
2310 *
2311 * Much of the time, this could just work regardless.
2312 * So for now, just log the incident, and allow the attempt.
2313 */
2314 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2315 --limit_warnings;
2316 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2317 ": attempting PIO w/multiple DRQ: "
2318 "this may fail due to h/w errata\n");
2319 }
2320 /* drop through */
2321 case ATA_PROT_NODATA:
2322 case ATAPI_PROT_PIO:
2323 case ATAPI_PROT_NODATA:
2324 if (ap->flags & ATA_FLAG_PIO_POLLING)
2325 qc->tf.flags |= ATA_TFLAG_POLLING;
2326 break;
2327 }
2328
2329 if (qc->tf.flags & ATA_TFLAG_POLLING)
2330 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2331 else
2332 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2333
2334 /*
2335 * We're about to send a non-EDMA capable command to the
2336 * port. Turn off EDMA so there won't be problems accessing
2337 * shadow block, etc registers.
2338 */
2339 mv_stop_edma(ap);
2340 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2341 mv_pmp_select(ap, qc->dev->link->pmp);
2342
2343 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2344 struct mv_host_priv *hpriv = ap->host->private_data;
2345 /*
2346 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2347 *
2348 * After any NCQ error, the READ_LOG_EXT command
2349 * from libata-eh *must* use mv_qc_issue_fis().
2350 * Otherwise it might fail, due to chip errata.
2351 *
2352 * Rather than special-case it, we'll just *always*
2353 * use this method here for READ_LOG_EXT, making for
2354 * easier testing.
2355 */
2356 if (IS_GEN_II(hpriv))
2357 return mv_qc_issue_fis(qc);
2358 }
2359 return ata_bmdma_qc_issue(qc);
2360 }
2361
2362 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2363 {
2364 struct mv_port_priv *pp = ap->private_data;
2365 struct ata_queued_cmd *qc;
2366
2367 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2368 return NULL;
2369 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2370 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2371 return qc;
2372 return NULL;
2373 }
2374
2375 static void mv_pmp_error_handler(struct ata_port *ap)
2376 {
2377 unsigned int pmp, pmp_map;
2378 struct mv_port_priv *pp = ap->private_data;
2379
2380 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2381 /*
2382 * Perform NCQ error analysis on failed PMPs
2383 * before we freeze the port entirely.
2384 *
2385 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2386 */
2387 pmp_map = pp->delayed_eh_pmp_map;
2388 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2389 for (pmp = 0; pmp_map != 0; pmp++) {
2390 unsigned int this_pmp = (1 << pmp);
2391 if (pmp_map & this_pmp) {
2392 struct ata_link *link = &ap->pmp_link[pmp];
2393 pmp_map &= ~this_pmp;
2394 ata_eh_analyze_ncq_error(link);
2395 }
2396 }
2397 ata_port_freeze(ap);
2398 }
2399 sata_pmp_error_handler(ap);
2400 }
2401
2402 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2403 {
2404 void __iomem *port_mmio = mv_ap_base(ap);
2405
2406 return readl(port_mmio + SATA_TESTCTL) >> 16;
2407 }
2408
2409 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2410 {
2411 struct ata_eh_info *ehi;
2412 unsigned int pmp;
2413
2414 /*
2415 * Initialize EH info for PMPs which saw device errors
2416 */
2417 ehi = &ap->link.eh_info;
2418 for (pmp = 0; pmp_map != 0; pmp++) {
2419 unsigned int this_pmp = (1 << pmp);
2420 if (pmp_map & this_pmp) {
2421 struct ata_link *link = &ap->pmp_link[pmp];
2422
2423 pmp_map &= ~this_pmp;
2424 ehi = &link->eh_info;
2425 ata_ehi_clear_desc(ehi);
2426 ata_ehi_push_desc(ehi, "dev err");
2427 ehi->err_mask |= AC_ERR_DEV;
2428 ehi->action |= ATA_EH_RESET;
2429 ata_link_abort(link);
2430 }
2431 }
2432 }
2433
2434 static int mv_req_q_empty(struct ata_port *ap)
2435 {
2436 void __iomem *port_mmio = mv_ap_base(ap);
2437 u32 in_ptr, out_ptr;
2438
2439 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
2440 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2441 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
2442 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2443 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2444 }
2445
2446 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2447 {
2448 struct mv_port_priv *pp = ap->private_data;
2449 int failed_links;
2450 unsigned int old_map, new_map;
2451
2452 /*
2453 * Device error during FBS+NCQ operation:
2454 *
2455 * Set a port flag to prevent further I/O being enqueued.
2456 * Leave the EDMA running to drain outstanding commands from this port.
2457 * Perform the post-mortem/EH only when all responses are complete.
2458 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2459 */
2460 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2461 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2462 pp->delayed_eh_pmp_map = 0;
2463 }
2464 old_map = pp->delayed_eh_pmp_map;
2465 new_map = old_map | mv_get_err_pmp_map(ap);
2466
2467 if (old_map != new_map) {
2468 pp->delayed_eh_pmp_map = new_map;
2469 mv_pmp_eh_prep(ap, new_map & ~old_map);
2470 }
2471 failed_links = hweight16(new_map);
2472
2473 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2474 "failed_links=%d nr_active_links=%d\n",
2475 __func__, pp->delayed_eh_pmp_map,
2476 ap->qc_active, failed_links,
2477 ap->nr_active_links);
2478
2479 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2480 mv_process_crpb_entries(ap, pp);
2481 mv_stop_edma(ap);
2482 mv_eh_freeze(ap);
2483 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2484 return 1; /* handled */
2485 }
2486 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2487 return 1; /* handled */
2488 }
2489
2490 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2491 {
2492 /*
2493 * Possible future enhancement:
2494 *
2495 * FBS+non-NCQ operation is not yet implemented.
2496 * See related notes in mv_edma_cfg().
2497 *
2498 * Device error during FBS+non-NCQ operation:
2499 *
2500 * We need to snapshot the shadow registers for each failed command.
2501 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2502 */
2503 return 0; /* not handled */
2504 }
2505
2506 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2507 {
2508 struct mv_port_priv *pp = ap->private_data;
2509
2510 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2511 return 0; /* EDMA was not active: not handled */
2512 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2513 return 0; /* FBS was not active: not handled */
2514
2515 if (!(edma_err_cause & EDMA_ERR_DEV))
2516 return 0; /* non DEV error: not handled */
2517 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2518 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2519 return 0; /* other problems: not handled */
2520
2521 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2522 /*
2523 * EDMA should NOT have self-disabled for this case.
2524 * If it did, then something is wrong elsewhere,
2525 * and we cannot handle it here.
2526 */
2527 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2528 ata_port_printk(ap, KERN_WARNING,
2529 "%s: err_cause=0x%x pp_flags=0x%x\n",
2530 __func__, edma_err_cause, pp->pp_flags);
2531 return 0; /* not handled */
2532 }
2533 return mv_handle_fbs_ncq_dev_err(ap);
2534 } else {
2535 /*
2536 * EDMA should have self-disabled for this case.
2537 * If it did not, then something is wrong elsewhere,
2538 * and we cannot handle it here.
2539 */
2540 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2541 ata_port_printk(ap, KERN_WARNING,
2542 "%s: err_cause=0x%x pp_flags=0x%x\n",
2543 __func__, edma_err_cause, pp->pp_flags);
2544 return 0; /* not handled */
2545 }
2546 return mv_handle_fbs_non_ncq_dev_err(ap);
2547 }
2548 return 0; /* not handled */
2549 }
2550
2551 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2552 {
2553 struct ata_eh_info *ehi = &ap->link.eh_info;
2554 char *when = "idle";
2555
2556 ata_ehi_clear_desc(ehi);
2557 if (edma_was_enabled) {
2558 when = "EDMA enabled";
2559 } else {
2560 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2561 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2562 when = "polling";
2563 }
2564 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2565 ehi->err_mask |= AC_ERR_OTHER;
2566 ehi->action |= ATA_EH_RESET;
2567 ata_port_freeze(ap);
2568 }
2569
2570 /**
2571 * mv_err_intr - Handle error interrupts on the port
2572 * @ap: ATA channel to manipulate
2573 *
2574 * Most cases require a full reset of the chip's state machine,
2575 * which also performs a COMRESET.
2576 * Also, if the port disabled DMA, update our cached copy to match.
2577 *
2578 * LOCKING:
2579 * Inherited from caller.
2580 */
2581 static void mv_err_intr(struct ata_port *ap)
2582 {
2583 void __iomem *port_mmio = mv_ap_base(ap);
2584 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2585 u32 fis_cause = 0;
2586 struct mv_port_priv *pp = ap->private_data;
2587 struct mv_host_priv *hpriv = ap->host->private_data;
2588 unsigned int action = 0, err_mask = 0;
2589 struct ata_eh_info *ehi = &ap->link.eh_info;
2590 struct ata_queued_cmd *qc;
2591 int abort = 0;
2592
2593 /*
2594 * Read and clear the SError and err_cause bits.
2595 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2596 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2597 */
2598 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2599 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2600
2601 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
2602 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2603 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2604 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
2605 }
2606 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
2607
2608 if (edma_err_cause & EDMA_ERR_DEV) {
2609 /*
2610 * Device errors during FIS-based switching operation
2611 * require special handling.
2612 */
2613 if (mv_handle_dev_err(ap, edma_err_cause))
2614 return;
2615 }
2616
2617 qc = mv_get_active_qc(ap);
2618 ata_ehi_clear_desc(ehi);
2619 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2620 edma_err_cause, pp->pp_flags);
2621
2622 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2623 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2624 if (fis_cause & FIS_IRQ_CAUSE_AN) {
2625 u32 ec = edma_err_cause &
2626 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2627 sata_async_notification(ap);
2628 if (!ec)
2629 return; /* Just an AN; no need for the nukes */
2630 ata_ehi_push_desc(ehi, "SDB notify");
2631 }
2632 }
2633 /*
2634 * All generations share these EDMA error cause bits:
2635 */
2636 if (edma_err_cause & EDMA_ERR_DEV) {
2637 err_mask |= AC_ERR_DEV;
2638 action |= ATA_EH_RESET;
2639 ata_ehi_push_desc(ehi, "dev error");
2640 }
2641 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2642 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2643 EDMA_ERR_INTRL_PAR)) {
2644 err_mask |= AC_ERR_ATA_BUS;
2645 action |= ATA_EH_RESET;
2646 ata_ehi_push_desc(ehi, "parity error");
2647 }
2648 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2649 ata_ehi_hotplugged(ehi);
2650 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2651 "dev disconnect" : "dev connect");
2652 action |= ATA_EH_RESET;
2653 }
2654
2655 /*
2656 * Gen-I has a different SELF_DIS bit,
2657 * different FREEZE bits, and no SERR bit:
2658 */
2659 if (IS_GEN_I(hpriv)) {
2660 eh_freeze_mask = EDMA_EH_FREEZE_5;
2661 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2662 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2663 ata_ehi_push_desc(ehi, "EDMA self-disable");
2664 }
2665 } else {
2666 eh_freeze_mask = EDMA_EH_FREEZE;
2667 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2668 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2669 ata_ehi_push_desc(ehi, "EDMA self-disable");
2670 }
2671 if (edma_err_cause & EDMA_ERR_SERR) {
2672 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2673 err_mask |= AC_ERR_ATA_BUS;
2674 action |= ATA_EH_RESET;
2675 }
2676 }
2677
2678 if (!err_mask) {
2679 err_mask = AC_ERR_OTHER;
2680 action |= ATA_EH_RESET;
2681 }
2682
2683 ehi->serror |= serr;
2684 ehi->action |= action;
2685
2686 if (qc)
2687 qc->err_mask |= err_mask;
2688 else
2689 ehi->err_mask |= err_mask;
2690
2691 if (err_mask == AC_ERR_DEV) {
2692 /*
2693 * Cannot do ata_port_freeze() here,
2694 * because it would kill PIO access,
2695 * which is needed for further diagnosis.
2696 */
2697 mv_eh_freeze(ap);
2698 abort = 1;
2699 } else if (edma_err_cause & eh_freeze_mask) {
2700 /*
2701 * Note to self: ata_port_freeze() calls ata_port_abort()
2702 */
2703 ata_port_freeze(ap);
2704 } else {
2705 abort = 1;
2706 }
2707
2708 if (abort) {
2709 if (qc)
2710 ata_link_abort(qc->dev->link);
2711 else
2712 ata_port_abort(ap);
2713 }
2714 }
2715
2716 static void mv_process_crpb_response(struct ata_port *ap,
2717 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2718 {
2719 u8 ata_status;
2720 u16 edma_status = le16_to_cpu(response->flags);
2721 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2722
2723 if (unlikely(!qc)) {
2724 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2725 __func__, tag);
2726 return;
2727 }
2728
2729 /*
2730 * edma_status from a response queue entry:
2731 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2732 * MSB is saved ATA status from command completion.
2733 */
2734 if (!ncq_enabled) {
2735 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2736 if (err_cause) {
2737 /*
2738 * Error will be seen/handled by
2739 * mv_err_intr(). So do nothing at all here.
2740 */
2741 return;
2742 }
2743 }
2744 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2745 if (!ac_err_mask(ata_status))
2746 ata_qc_complete(qc);
2747 /* else: leave it for mv_err_intr() */
2748 }
2749
2750 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2751 {
2752 void __iomem *port_mmio = mv_ap_base(ap);
2753 struct mv_host_priv *hpriv = ap->host->private_data;
2754 u32 in_index;
2755 bool work_done = false;
2756 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2757
2758 /* Get the hardware queue position index */
2759 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
2760 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2761
2762 /* Process new responses from since the last time we looked */
2763 while (in_index != pp->resp_idx) {
2764 unsigned int tag;
2765 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2766
2767 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2768
2769 if (IS_GEN_I(hpriv)) {
2770 /* 50xx: no NCQ, only one command active at a time */
2771 tag = ap->link.active_tag;
2772 } else {
2773 /* Gen II/IIE: get command tag from CRPB entry */
2774 tag = le16_to_cpu(response->id) & 0x1f;
2775 }
2776 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2777 work_done = true;
2778 }
2779
2780 /* Update the software queue position index in hardware */
2781 if (work_done)
2782 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2783 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2784 port_mmio + EDMA_RSP_Q_OUT_PTR);
2785 }
2786
2787 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2788 {
2789 struct mv_port_priv *pp;
2790 int edma_was_enabled;
2791
2792 /*
2793 * Grab a snapshot of the EDMA_EN flag setting,
2794 * so that we have a consistent view for this port,
2795 * even if something we call of our routines changes it.
2796 */
2797 pp = ap->private_data;
2798 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2799 /*
2800 * Process completed CRPB response(s) before other events.
2801 */
2802 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2803 mv_process_crpb_entries(ap, pp);
2804 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2805 mv_handle_fbs_ncq_dev_err(ap);
2806 }
2807 /*
2808 * Handle chip-reported errors, or continue on to handle PIO.
2809 */
2810 if (unlikely(port_cause & ERR_IRQ)) {
2811 mv_err_intr(ap);
2812 } else if (!edma_was_enabled) {
2813 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2814 if (qc)
2815 ata_bmdma_port_intr(ap, qc);
2816 else
2817 mv_unexpected_intr(ap, edma_was_enabled);
2818 }
2819 }
2820
2821 /**
2822 * mv_host_intr - Handle all interrupts on the given host controller
2823 * @host: host specific structure
2824 * @main_irq_cause: Main interrupt cause register for the chip.
2825 *
2826 * LOCKING:
2827 * Inherited from caller.
2828 */
2829 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2830 {
2831 struct mv_host_priv *hpriv = host->private_data;
2832 void __iomem *mmio = hpriv->base, *hc_mmio;
2833 unsigned int handled = 0, port;
2834
2835 /* If asserted, clear the "all ports" IRQ coalescing bit */
2836 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2837 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2838
2839 for (port = 0; port < hpriv->n_ports; port++) {
2840 struct ata_port *ap = host->ports[port];
2841 unsigned int p, shift, hardport, port_cause;
2842
2843 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2844 /*
2845 * Each hc within the host has its own hc_irq_cause register,
2846 * where the interrupting ports bits get ack'd.
2847 */
2848 if (hardport == 0) { /* first port on this hc ? */
2849 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2850 u32 port_mask, ack_irqs;
2851 /*
2852 * Skip this entire hc if nothing pending for any ports
2853 */
2854 if (!hc_cause) {
2855 port += MV_PORTS_PER_HC - 1;
2856 continue;
2857 }
2858 /*
2859 * We don't need/want to read the hc_irq_cause register,
2860 * because doing so hurts performance, and
2861 * main_irq_cause already gives us everything we need.
2862 *
2863 * But we do have to *write* to the hc_irq_cause to ack
2864 * the ports that we are handling this time through.
2865 *
2866 * This requires that we create a bitmap for those
2867 * ports which interrupted us, and use that bitmap
2868 * to ack (only) those ports via hc_irq_cause.
2869 */
2870 ack_irqs = 0;
2871 if (hc_cause & PORTS_0_3_COAL_DONE)
2872 ack_irqs = HC_COAL_IRQ;
2873 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2874 if ((port + p) >= hpriv->n_ports)
2875 break;
2876 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2877 if (hc_cause & port_mask)
2878 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2879 }
2880 hc_mmio = mv_hc_base_from_port(mmio, port);
2881 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
2882 handled = 1;
2883 }
2884 /*
2885 * Handle interrupts signalled for this port:
2886 */
2887 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2888 if (port_cause)
2889 mv_port_intr(ap, port_cause);
2890 }
2891 return handled;
2892 }
2893
2894 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2895 {
2896 struct mv_host_priv *hpriv = host->private_data;
2897 struct ata_port *ap;
2898 struct ata_queued_cmd *qc;
2899 struct ata_eh_info *ehi;
2900 unsigned int i, err_mask, printed = 0;
2901 u32 err_cause;
2902
2903 err_cause = readl(mmio + hpriv->irq_cause_offset);
2904
2905 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2906 err_cause);
2907
2908 DPRINTK("All regs @ PCI error\n");
2909 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2910
2911 writelfl(0, mmio + hpriv->irq_cause_offset);
2912
2913 for (i = 0; i < host->n_ports; i++) {
2914 ap = host->ports[i];
2915 if (!ata_link_offline(&ap->link)) {
2916 ehi = &ap->link.eh_info;
2917 ata_ehi_clear_desc(ehi);
2918 if (!printed++)
2919 ata_ehi_push_desc(ehi,
2920 "PCI err cause 0x%08x", err_cause);
2921 err_mask = AC_ERR_HOST_BUS;
2922 ehi->action = ATA_EH_RESET;
2923 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2924 if (qc)
2925 qc->err_mask |= err_mask;
2926 else
2927 ehi->err_mask |= err_mask;
2928
2929 ata_port_freeze(ap);
2930 }
2931 }
2932 return 1; /* handled */
2933 }
2934
2935 /**
2936 * mv_interrupt - Main interrupt event handler
2937 * @irq: unused
2938 * @dev_instance: private data; in this case the host structure
2939 *
2940 * Read the read only register to determine if any host
2941 * controllers have pending interrupts. If so, call lower level
2942 * routine to handle. Also check for PCI errors which are only
2943 * reported here.
2944 *
2945 * LOCKING:
2946 * This routine holds the host lock while processing pending
2947 * interrupts.
2948 */
2949 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2950 {
2951 struct ata_host *host = dev_instance;
2952 struct mv_host_priv *hpriv = host->private_data;
2953 unsigned int handled = 0;
2954 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2955 u32 main_irq_cause, pending_irqs;
2956
2957 spin_lock(&host->lock);
2958
2959 /* for MSI: block new interrupts while in here */
2960 if (using_msi)
2961 mv_write_main_irq_mask(0, hpriv);
2962
2963 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2964 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2965 /*
2966 * Deal with cases where we either have nothing pending, or have read
2967 * a bogus register value which can indicate HW removal or PCI fault.
2968 */
2969 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2970 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2971 handled = mv_pci_error(host, hpriv->base);
2972 else
2973 handled = mv_host_intr(host, pending_irqs);
2974 }
2975
2976 /* for MSI: unmask; interrupt cause bits will retrigger now */
2977 if (using_msi)
2978 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
2979
2980 spin_unlock(&host->lock);
2981
2982 return IRQ_RETVAL(handled);
2983 }
2984
2985 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2986 {
2987 unsigned int ofs;
2988
2989 switch (sc_reg_in) {
2990 case SCR_STATUS:
2991 case SCR_ERROR:
2992 case SCR_CONTROL:
2993 ofs = sc_reg_in * sizeof(u32);
2994 break;
2995 default:
2996 ofs = 0xffffffffU;
2997 break;
2998 }
2999 return ofs;
3000 }
3001
3002 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
3003 {
3004 struct mv_host_priv *hpriv = link->ap->host->private_data;
3005 void __iomem *mmio = hpriv->base;
3006 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3007 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3008
3009 if (ofs != 0xffffffffU) {
3010 *val = readl(addr + ofs);
3011 return 0;
3012 } else
3013 return -EINVAL;
3014 }
3015
3016 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
3017 {
3018 struct mv_host_priv *hpriv = link->ap->host->private_data;
3019 void __iomem *mmio = hpriv->base;
3020 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3021 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3022
3023 if (ofs != 0xffffffffU) {
3024 writelfl(val, addr + ofs);
3025 return 0;
3026 } else
3027 return -EINVAL;
3028 }
3029
3030 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
3031 {
3032 struct pci_dev *pdev = to_pci_dev(host->dev);
3033 int early_5080;
3034
3035 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
3036
3037 if (!early_5080) {
3038 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3039 tmp |= (1 << 0);
3040 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3041 }
3042
3043 mv_reset_pci_bus(host, mmio);
3044 }
3045
3046 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3047 {
3048 writel(0x0fcfffff, mmio + FLASH_CTL);
3049 }
3050
3051 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
3052 void __iomem *mmio)
3053 {
3054 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3055 u32 tmp;
3056
3057 tmp = readl(phy_mmio + MV5_PHY_MODE);
3058
3059 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3060 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3061 }
3062
3063 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3064 {
3065 u32 tmp;
3066
3067 writel(0, mmio + GPIO_PORT_CTL);
3068
3069 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3070
3071 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3072 tmp |= ~(1 << 0);
3073 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3074 }
3075
3076 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3077 unsigned int port)
3078 {
3079 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3080 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3081 u32 tmp;
3082 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3083
3084 if (fix_apm_sq) {
3085 tmp = readl(phy_mmio + MV5_LTMODE);
3086 tmp |= (1 << 19);
3087 writel(tmp, phy_mmio + MV5_LTMODE);
3088
3089 tmp = readl(phy_mmio + MV5_PHY_CTL);
3090 tmp &= ~0x3;
3091 tmp |= 0x1;
3092 writel(tmp, phy_mmio + MV5_PHY_CTL);
3093 }
3094
3095 tmp = readl(phy_mmio + MV5_PHY_MODE);
3096 tmp &= ~mask;
3097 tmp |= hpriv->signal[port].pre;
3098 tmp |= hpriv->signal[port].amps;
3099 writel(tmp, phy_mmio + MV5_PHY_MODE);
3100 }
3101
3102
3103 #undef ZERO
3104 #define ZERO(reg) writel(0, port_mmio + (reg))
3105 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3106 unsigned int port)
3107 {
3108 void __iomem *port_mmio = mv_port_base(mmio, port);
3109
3110 mv_reset_channel(hpriv, mmio, port);
3111
3112 ZERO(0x028); /* command */
3113 writel(0x11f, port_mmio + EDMA_CFG);
3114 ZERO(0x004); /* timer */
3115 ZERO(0x008); /* irq err cause */
3116 ZERO(0x00c); /* irq err mask */
3117 ZERO(0x010); /* rq bah */
3118 ZERO(0x014); /* rq inp */
3119 ZERO(0x018); /* rq outp */
3120 ZERO(0x01c); /* respq bah */
3121 ZERO(0x024); /* respq outp */
3122 ZERO(0x020); /* respq inp */
3123 ZERO(0x02c); /* test control */
3124 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
3125 }
3126 #undef ZERO
3127
3128 #define ZERO(reg) writel(0, hc_mmio + (reg))
3129 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3130 unsigned int hc)
3131 {
3132 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3133 u32 tmp;
3134
3135 ZERO(0x00c);
3136 ZERO(0x010);
3137 ZERO(0x014);
3138 ZERO(0x018);
3139
3140 tmp = readl(hc_mmio + 0x20);
3141 tmp &= 0x1c1c1c1c;
3142 tmp |= 0x03030303;
3143 writel(tmp, hc_mmio + 0x20);
3144 }
3145 #undef ZERO
3146
3147 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3148 unsigned int n_hc)
3149 {
3150 unsigned int hc, port;
3151
3152 for (hc = 0; hc < n_hc; hc++) {
3153 for (port = 0; port < MV_PORTS_PER_HC; port++)
3154 mv5_reset_hc_port(hpriv, mmio,
3155 (hc * MV_PORTS_PER_HC) + port);
3156
3157 mv5_reset_one_hc(hpriv, mmio, hc);
3158 }
3159
3160 return 0;
3161 }
3162
3163 #undef ZERO
3164 #define ZERO(reg) writel(0, mmio + (reg))
3165 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3166 {
3167 struct mv_host_priv *hpriv = host->private_data;
3168 u32 tmp;
3169
3170 tmp = readl(mmio + MV_PCI_MODE);
3171 tmp &= 0xff00ffff;
3172 writel(tmp, mmio + MV_PCI_MODE);
3173
3174 ZERO(MV_PCI_DISC_TIMER);
3175 ZERO(MV_PCI_MSI_TRIGGER);
3176 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
3177 ZERO(MV_PCI_SERR_MASK);
3178 ZERO(hpriv->irq_cause_offset);
3179 ZERO(hpriv->irq_mask_offset);
3180 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3181 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3182 ZERO(MV_PCI_ERR_ATTRIBUTE);
3183 ZERO(MV_PCI_ERR_COMMAND);
3184 }
3185 #undef ZERO
3186
3187 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3188 {
3189 u32 tmp;
3190
3191 mv5_reset_flash(hpriv, mmio);
3192
3193 tmp = readl(mmio + GPIO_PORT_CTL);
3194 tmp &= 0x3;
3195 tmp |= (1 << 5) | (1 << 6);
3196 writel(tmp, mmio + GPIO_PORT_CTL);
3197 }
3198
3199 /**
3200 * mv6_reset_hc - Perform the 6xxx global soft reset
3201 * @mmio: base address of the HBA
3202 *
3203 * This routine only applies to 6xxx parts.
3204 *
3205 * LOCKING:
3206 * Inherited from caller.
3207 */
3208 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3209 unsigned int n_hc)
3210 {
3211 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
3212 int i, rc = 0;
3213 u32 t;
3214
3215 /* Following procedure defined in PCI "main command and status
3216 * register" table.
3217 */
3218 t = readl(reg);
3219 writel(t | STOP_PCI_MASTER, reg);
3220
3221 for (i = 0; i < 1000; i++) {
3222 udelay(1);
3223 t = readl(reg);
3224 if (PCI_MASTER_EMPTY & t)
3225 break;
3226 }
3227 if (!(PCI_MASTER_EMPTY & t)) {
3228 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3229 rc = 1;
3230 goto done;
3231 }
3232
3233 /* set reset */
3234 i = 5;
3235 do {
3236 writel(t | GLOB_SFT_RST, reg);
3237 t = readl(reg);
3238 udelay(1);
3239 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3240
3241 if (!(GLOB_SFT_RST & t)) {
3242 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3243 rc = 1;
3244 goto done;
3245 }
3246
3247 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3248 i = 5;
3249 do {
3250 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3251 t = readl(reg);
3252 udelay(1);
3253 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3254
3255 if (GLOB_SFT_RST & t) {
3256 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3257 rc = 1;
3258 }
3259 done:
3260 return rc;
3261 }
3262
3263 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3264 void __iomem *mmio)
3265 {
3266 void __iomem *port_mmio;
3267 u32 tmp;
3268
3269 tmp = readl(mmio + RESET_CFG);
3270 if ((tmp & (1 << 0)) == 0) {
3271 hpriv->signal[idx].amps = 0x7 << 8;
3272 hpriv->signal[idx].pre = 0x1 << 5;
3273 return;
3274 }
3275
3276 port_mmio = mv_port_base(mmio, idx);
3277 tmp = readl(port_mmio + PHY_MODE2);
3278
3279 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3280 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3281 }
3282
3283 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3284 {
3285 writel(0x00000060, mmio + GPIO_PORT_CTL);
3286 }
3287
3288 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3289 unsigned int port)
3290 {
3291 void __iomem *port_mmio = mv_port_base(mmio, port);
3292
3293 u32 hp_flags = hpriv->hp_flags;
3294 int fix_phy_mode2 =
3295 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3296 int fix_phy_mode4 =
3297 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3298 u32 m2, m3;
3299
3300 if (fix_phy_mode2) {
3301 m2 = readl(port_mmio + PHY_MODE2);
3302 m2 &= ~(1 << 16);
3303 m2 |= (1 << 31);
3304 writel(m2, port_mmio + PHY_MODE2);
3305
3306 udelay(200);
3307
3308 m2 = readl(port_mmio + PHY_MODE2);
3309 m2 &= ~((1 << 16) | (1 << 31));
3310 writel(m2, port_mmio + PHY_MODE2);
3311
3312 udelay(200);
3313 }
3314
3315 /*
3316 * Gen-II/IIe PHY_MODE3 errata RM#2:
3317 * Achieves better receiver noise performance than the h/w default:
3318 */
3319 m3 = readl(port_mmio + PHY_MODE3);
3320 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3321
3322 /* Guideline 88F5182 (GL# SATA-S11) */
3323 if (IS_SOC(hpriv))
3324 m3 &= ~0x1c;
3325
3326 if (fix_phy_mode4) {
3327 u32 m4 = readl(port_mmio + PHY_MODE4);
3328 /*
3329 * Enforce reserved-bit restrictions on GenIIe devices only.
3330 * For earlier chipsets, force only the internal config field
3331 * (workaround for errata FEr SATA#10 part 1).
3332 */
3333 if (IS_GEN_IIE(hpriv))
3334 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3335 else
3336 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3337 writel(m4, port_mmio + PHY_MODE4);
3338 }
3339 /*
3340 * Workaround for 60x1-B2 errata SATA#13:
3341 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3342 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3343 * Or ensure we use writelfl() when writing PHY_MODE4.
3344 */
3345 writel(m3, port_mmio + PHY_MODE3);
3346
3347 /* Revert values of pre-emphasis and signal amps to the saved ones */
3348 m2 = readl(port_mmio + PHY_MODE2);
3349
3350 m2 &= ~MV_M2_PREAMP_MASK;
3351 m2 |= hpriv->signal[port].amps;
3352 m2 |= hpriv->signal[port].pre;
3353 m2 &= ~(1 << 16);
3354
3355 /* according to mvSata 3.6.1, some IIE values are fixed */
3356 if (IS_GEN_IIE(hpriv)) {
3357 m2 &= ~0xC30FF01F;
3358 m2 |= 0x0000900F;
3359 }
3360
3361 writel(m2, port_mmio + PHY_MODE2);
3362 }
3363
3364 /* TODO: use the generic LED interface to configure the SATA Presence */
3365 /* & Acitivy LEDs on the board */
3366 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3367 void __iomem *mmio)
3368 {
3369 return;
3370 }
3371
3372 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3373 void __iomem *mmio)
3374 {
3375 void __iomem *port_mmio;
3376 u32 tmp;
3377
3378 port_mmio = mv_port_base(mmio, idx);
3379 tmp = readl(port_mmio + PHY_MODE2);
3380
3381 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3382 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3383 }
3384
3385 #undef ZERO
3386 #define ZERO(reg) writel(0, port_mmio + (reg))
3387 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3388 void __iomem *mmio, unsigned int port)
3389 {
3390 void __iomem *port_mmio = mv_port_base(mmio, port);
3391
3392 mv_reset_channel(hpriv, mmio, port);
3393
3394 ZERO(0x028); /* command */
3395 writel(0x101f, port_mmio + EDMA_CFG);
3396 ZERO(0x004); /* timer */
3397 ZERO(0x008); /* irq err cause */
3398 ZERO(0x00c); /* irq err mask */
3399 ZERO(0x010); /* rq bah */
3400 ZERO(0x014); /* rq inp */
3401 ZERO(0x018); /* rq outp */
3402 ZERO(0x01c); /* respq bah */
3403 ZERO(0x024); /* respq outp */
3404 ZERO(0x020); /* respq inp */
3405 ZERO(0x02c); /* test control */
3406 writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
3407 }
3408
3409 #undef ZERO
3410
3411 #define ZERO(reg) writel(0, hc_mmio + (reg))
3412 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3413 void __iomem *mmio)
3414 {
3415 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3416
3417 ZERO(0x00c);
3418 ZERO(0x010);
3419 ZERO(0x014);
3420
3421 }
3422
3423 #undef ZERO
3424
3425 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3426 void __iomem *mmio, unsigned int n_hc)
3427 {
3428 unsigned int port;
3429
3430 for (port = 0; port < hpriv->n_ports; port++)
3431 mv_soc_reset_hc_port(hpriv, mmio, port);
3432
3433 mv_soc_reset_one_hc(hpriv, mmio);
3434
3435 return 0;
3436 }
3437
3438 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3439 void __iomem *mmio)
3440 {
3441 return;
3442 }
3443
3444 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3445 {
3446 return;
3447 }
3448
3449 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3450 void __iomem *mmio, unsigned int port)
3451 {
3452 void __iomem *port_mmio = mv_port_base(mmio, port);
3453 u32 reg;
3454
3455 reg = readl(port_mmio + PHY_MODE3);
3456 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3457 reg |= (0x1 << 27);
3458 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3459 reg |= (0x1 << 29);
3460 writel(reg, port_mmio + PHY_MODE3);
3461
3462 reg = readl(port_mmio + PHY_MODE4);
3463 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3464 reg |= (0x1 << 16);
3465 writel(reg, port_mmio + PHY_MODE4);
3466
3467 reg = readl(port_mmio + PHY_MODE9_GEN2);
3468 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3469 reg |= 0x8;
3470 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3471 writel(reg, port_mmio + PHY_MODE9_GEN2);
3472
3473 reg = readl(port_mmio + PHY_MODE9_GEN1);
3474 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3475 reg |= 0x8;
3476 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3477 writel(reg, port_mmio + PHY_MODE9_GEN1);
3478 }
3479
3480 /**
3481 * soc_is_65 - check if the soc is 65 nano device
3482 *
3483 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3484 * register, this register should contain non-zero value and it exists only
3485 * in the 65 nano devices, when reading it from older devices we get 0.
3486 */
3487 static bool soc_is_65n(struct mv_host_priv *hpriv)
3488 {
3489 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3490
3491 if (readl(port0_mmio + PHYCFG_OFS))
3492 return true;
3493 return false;
3494 }
3495
3496 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3497 {
3498 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
3499
3500 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
3501 if (want_gen2i)
3502 ifcfg |= (1 << 7); /* enable gen2i speed */
3503 writelfl(ifcfg, port_mmio + SATA_IFCFG);
3504 }
3505
3506 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3507 unsigned int port_no)
3508 {
3509 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3510
3511 /*
3512 * The datasheet warns against setting EDMA_RESET when EDMA is active
3513 * (but doesn't say what the problem might be). So we first try
3514 * to disable the EDMA engine before doing the EDMA_RESET operation.
3515 */
3516 mv_stop_edma_engine(port_mmio);
3517 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3518
3519 if (!IS_GEN_I(hpriv)) {
3520 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3521 mv_setup_ifcfg(port_mmio, 1);
3522 }
3523 /*
3524 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3525 * link, and physical layers. It resets all SATA interface registers
3526 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
3527 */
3528 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3529 udelay(25); /* allow reset propagation */
3530 writelfl(0, port_mmio + EDMA_CMD);
3531
3532 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3533
3534 if (IS_GEN_I(hpriv))
3535 mdelay(1);
3536 }
3537
3538 static void mv_pmp_select(struct ata_port *ap, int pmp)
3539 {
3540 if (sata_pmp_supported(ap)) {
3541 void __iomem *port_mmio = mv_ap_base(ap);
3542 u32 reg = readl(port_mmio + SATA_IFCTL);
3543 int old = reg & 0xf;
3544
3545 if (old != pmp) {
3546 reg = (reg & ~0xf) | pmp;
3547 writelfl(reg, port_mmio + SATA_IFCTL);
3548 }
3549 }
3550 }
3551
3552 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3553 unsigned long deadline)
3554 {
3555 mv_pmp_select(link->ap, sata_srst_pmp(link));
3556 return sata_std_hardreset(link, class, deadline);
3557 }
3558
3559 static int mv_softreset(struct ata_link *link, unsigned int *class,
3560 unsigned long deadline)
3561 {
3562 mv_pmp_select(link->ap, sata_srst_pmp(link));
3563 return ata_sff_softreset(link, class, deadline);
3564 }
3565
3566 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3567 unsigned long deadline)
3568 {
3569 struct ata_port *ap = link->ap;
3570 struct mv_host_priv *hpriv = ap->host->private_data;
3571 struct mv_port_priv *pp = ap->private_data;
3572 void __iomem *mmio = hpriv->base;
3573 int rc, attempts = 0, extra = 0;
3574 u32 sstatus;
3575 bool online;
3576
3577 mv_reset_channel(hpriv, mmio, ap->port_no);
3578 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3579 pp->pp_flags &=
3580 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3581
3582 /* Workaround for errata FEr SATA#10 (part 2) */
3583 do {
3584 const unsigned long *timing =
3585 sata_ehc_deb_timing(&link->eh_context);
3586
3587 rc = sata_link_hardreset(link, timing, deadline + extra,
3588 &online, NULL);
3589 rc = online ? -EAGAIN : rc;
3590 if (rc)
3591 return rc;
3592 sata_scr_read(link, SCR_STATUS, &sstatus);
3593 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3594 /* Force 1.5gb/s link speed and try again */
3595 mv_setup_ifcfg(mv_ap_base(ap), 0);
3596 if (time_after(jiffies + HZ, deadline))
3597 extra = HZ; /* only extend it once, max */
3598 }
3599 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3600 mv_save_cached_regs(ap);
3601 mv_edma_cfg(ap, 0, 0);
3602
3603 return rc;
3604 }
3605
3606 static void mv_eh_freeze(struct ata_port *ap)
3607 {
3608 mv_stop_edma(ap);
3609 mv_enable_port_irqs(ap, 0);
3610 }
3611
3612 static void mv_eh_thaw(struct ata_port *ap)
3613 {
3614 struct mv_host_priv *hpriv = ap->host->private_data;
3615 unsigned int port = ap->port_no;
3616 unsigned int hardport = mv_hardport_from_port(port);
3617 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3618 void __iomem *port_mmio = mv_ap_base(ap);
3619 u32 hc_irq_cause;
3620
3621 /* clear EDMA errors on this port */
3622 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3623
3624 /* clear pending irq events */
3625 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3626 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
3627
3628 mv_enable_port_irqs(ap, ERR_IRQ);
3629 }
3630
3631 /**
3632 * mv_port_init - Perform some early initialization on a single port.
3633 * @port: libata data structure storing shadow register addresses
3634 * @port_mmio: base address of the port
3635 *
3636 * Initialize shadow register mmio addresses, clear outstanding
3637 * interrupts on the port, and unmask interrupts for the future
3638 * start of the port.
3639 *
3640 * LOCKING:
3641 * Inherited from caller.
3642 */
3643 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3644 {
3645 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
3646
3647 /* PIO related setup
3648 */
3649 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3650 port->error_addr =
3651 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3652 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3653 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3654 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3655 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3656 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3657 port->status_addr =
3658 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3659 /* special case: control/altstatus doesn't have ATA_REG_ address */
3660 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
3661
3662 /* Clear any currently outstanding port interrupt conditions */
3663 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3664 writelfl(readl(serr), serr);
3665 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3666
3667 /* unmask all non-transient EDMA error interrupts */
3668 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
3669
3670 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3671 readl(port_mmio + EDMA_CFG),
3672 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3673 readl(port_mmio + EDMA_ERR_IRQ_MASK));
3674 }
3675
3676 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3677 {
3678 struct mv_host_priv *hpriv = host->private_data;
3679 void __iomem *mmio = hpriv->base;
3680 u32 reg;
3681
3682 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3683 return 0; /* not PCI-X capable */
3684 reg = readl(mmio + MV_PCI_MODE);
3685 if ((reg & MV_PCI_MODE_MASK) == 0)
3686 return 0; /* conventional PCI mode */
3687 return 1; /* chip is in PCI-X mode */
3688 }
3689
3690 static int mv_pci_cut_through_okay(struct ata_host *host)
3691 {
3692 struct mv_host_priv *hpriv = host->private_data;
3693 void __iomem *mmio = hpriv->base;
3694 u32 reg;
3695
3696 if (!mv_in_pcix_mode(host)) {
3697 reg = readl(mmio + MV_PCI_COMMAND);
3698 if (reg & MV_PCI_COMMAND_MRDTRIG)
3699 return 0; /* not okay */
3700 }
3701 return 1; /* okay */
3702 }
3703
3704 static void mv_60x1b2_errata_pci7(struct ata_host *host)
3705 {
3706 struct mv_host_priv *hpriv = host->private_data;
3707 void __iomem *mmio = hpriv->base;
3708
3709 /* workaround for 60x1-B2 errata PCI#7 */
3710 if (mv_in_pcix_mode(host)) {
3711 u32 reg = readl(mmio + MV_PCI_COMMAND);
3712 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
3713 }
3714 }
3715
3716 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3717 {
3718 struct pci_dev *pdev = to_pci_dev(host->dev);
3719 struct mv_host_priv *hpriv = host->private_data;
3720 u32 hp_flags = hpriv->hp_flags;
3721
3722 switch (board_idx) {
3723 case chip_5080:
3724 hpriv->ops = &mv5xxx_ops;
3725 hp_flags |= MV_HP_GEN_I;
3726
3727 switch (pdev->revision) {
3728 case 0x1:
3729 hp_flags |= MV_HP_ERRATA_50XXB0;
3730 break;
3731 case 0x3:
3732 hp_flags |= MV_HP_ERRATA_50XXB2;
3733 break;
3734 default:
3735 dev_printk(KERN_WARNING, &pdev->dev,
3736 "Applying 50XXB2 workarounds to unknown rev\n");
3737 hp_flags |= MV_HP_ERRATA_50XXB2;
3738 break;
3739 }
3740 break;
3741
3742 case chip_504x:
3743 case chip_508x:
3744 hpriv->ops = &mv5xxx_ops;
3745 hp_flags |= MV_HP_GEN_I;
3746
3747 switch (pdev->revision) {
3748 case 0x0:
3749 hp_flags |= MV_HP_ERRATA_50XXB0;
3750 break;
3751 case 0x3:
3752 hp_flags |= MV_HP_ERRATA_50XXB2;
3753 break;
3754 default:
3755 dev_printk(KERN_WARNING, &pdev->dev,
3756 "Applying B2 workarounds to unknown rev\n");
3757 hp_flags |= MV_HP_ERRATA_50XXB2;
3758 break;
3759 }
3760 break;
3761
3762 case chip_604x:
3763 case chip_608x:
3764 hpriv->ops = &mv6xxx_ops;
3765 hp_flags |= MV_HP_GEN_II;
3766
3767 switch (pdev->revision) {
3768 case 0x7:
3769 mv_60x1b2_errata_pci7(host);
3770 hp_flags |= MV_HP_ERRATA_60X1B2;
3771 break;
3772 case 0x9:
3773 hp_flags |= MV_HP_ERRATA_60X1C0;
3774 break;
3775 default:
3776 dev_printk(KERN_WARNING, &pdev->dev,
3777 "Applying B2 workarounds to unknown rev\n");
3778 hp_flags |= MV_HP_ERRATA_60X1B2;
3779 break;
3780 }
3781 break;
3782
3783 case chip_7042:
3784 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3785 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3786 (pdev->device == 0x2300 || pdev->device == 0x2310))
3787 {
3788 /*
3789 * Highpoint RocketRAID PCIe 23xx series cards:
3790 *
3791 * Unconfigured drives are treated as "Legacy"
3792 * by the BIOS, and it overwrites sector 8 with
3793 * a "Lgcy" metadata block prior to Linux boot.
3794 *
3795 * Configured drives (RAID or JBOD) leave sector 8
3796 * alone, but instead overwrite a high numbered
3797 * sector for the RAID metadata. This sector can
3798 * be determined exactly, by truncating the physical
3799 * drive capacity to a nice even GB value.
3800 *
3801 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3802 *
3803 * Warn the user, lest they think we're just buggy.
3804 */
3805 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3806 " BIOS CORRUPTS DATA on all attached drives,"
3807 " regardless of if/how they are configured."
3808 " BEWARE!\n");
3809 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3810 " use sectors 8-9 on \"Legacy\" drives,"
3811 " and avoid the final two gigabytes on"
3812 " all RocketRAID BIOS initialized drives.\n");
3813 }
3814 /* drop through */
3815 case chip_6042:
3816 hpriv->ops = &mv6xxx_ops;
3817 hp_flags |= MV_HP_GEN_IIE;
3818 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3819 hp_flags |= MV_HP_CUT_THROUGH;
3820
3821 switch (pdev->revision) {
3822 case 0x2: /* Rev.B0: the first/only public release */
3823 hp_flags |= MV_HP_ERRATA_60X1C0;
3824 break;
3825 default:
3826 dev_printk(KERN_WARNING, &pdev->dev,
3827 "Applying 60X1C0 workarounds to unknown rev\n");
3828 hp_flags |= MV_HP_ERRATA_60X1C0;
3829 break;
3830 }
3831 break;
3832 case chip_soc:
3833 if (soc_is_65n(hpriv))
3834 hpriv->ops = &mv_soc_65n_ops;
3835 else
3836 hpriv->ops = &mv_soc_ops;
3837 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3838 MV_HP_ERRATA_60X1C0;
3839 break;
3840
3841 default:
3842 dev_printk(KERN_ERR, host->dev,
3843 "BUG: invalid board index %u\n", board_idx);
3844 return 1;
3845 }
3846
3847 hpriv->hp_flags = hp_flags;
3848 if (hp_flags & MV_HP_PCIE) {
3849 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3850 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
3851 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3852 } else {
3853 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3854 hpriv->irq_mask_offset = PCI_IRQ_MASK;
3855 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3856 }
3857
3858 return 0;
3859 }
3860
3861 /**
3862 * mv_init_host - Perform some early initialization of the host.
3863 * @host: ATA host to initialize
3864 *
3865 * If possible, do an early global reset of the host. Then do
3866 * our port init and clear/unmask all/relevant host interrupts.
3867 *
3868 * LOCKING:
3869 * Inherited from caller.
3870 */
3871 static int mv_init_host(struct ata_host *host)
3872 {
3873 int rc = 0, n_hc, port, hc;
3874 struct mv_host_priv *hpriv = host->private_data;
3875 void __iomem *mmio = hpriv->base;
3876
3877 rc = mv_chip_id(host, hpriv->board_idx);
3878 if (rc)
3879 goto done;
3880
3881 if (IS_SOC(hpriv)) {
3882 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3883 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
3884 } else {
3885 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3886 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
3887 }
3888
3889 /* initialize shadow irq mask with register's value */
3890 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3891
3892 /* global interrupt mask: 0 == mask everything */
3893 mv_set_main_irq_mask(host, ~0, 0);
3894
3895 n_hc = mv_get_hc_count(host->ports[0]->flags);
3896
3897 for (port = 0; port < host->n_ports; port++)
3898 if (hpriv->ops->read_preamp)
3899 hpriv->ops->read_preamp(hpriv, port, mmio);
3900
3901 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3902 if (rc)
3903 goto done;
3904
3905 hpriv->ops->reset_flash(hpriv, mmio);
3906 hpriv->ops->reset_bus(host, mmio);
3907 hpriv->ops->enable_leds(hpriv, mmio);
3908
3909 for (port = 0; port < host->n_ports; port++) {
3910 struct ata_port *ap = host->ports[port];
3911 void __iomem *port_mmio = mv_port_base(mmio, port);
3912
3913 mv_port_init(&ap->ioaddr, port_mmio);
3914 }
3915
3916 for (hc = 0; hc < n_hc; hc++) {
3917 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3918
3919 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3920 "(before clear)=0x%08x\n", hc,
3921 readl(hc_mmio + HC_CFG),
3922 readl(hc_mmio + HC_IRQ_CAUSE));
3923
3924 /* Clear any currently outstanding hc interrupt conditions */
3925 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
3926 }
3927
3928 if (!IS_SOC(hpriv)) {
3929 /* Clear any currently outstanding host interrupt conditions */
3930 writelfl(0, mmio + hpriv->irq_cause_offset);
3931
3932 /* and unmask interrupt generation for host regs */
3933 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
3934 }
3935
3936 /*
3937 * enable only global host interrupts for now.
3938 * The per-port interrupts get done later as ports are set up.
3939 */
3940 mv_set_main_irq_mask(host, 0, PCI_ERR);
3941 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3942 irq_coalescing_usecs);
3943 done:
3944 return rc;
3945 }
3946
3947 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3948 {
3949 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3950 MV_CRQB_Q_SZ, 0);
3951 if (!hpriv->crqb_pool)
3952 return -ENOMEM;
3953
3954 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3955 MV_CRPB_Q_SZ, 0);
3956 if (!hpriv->crpb_pool)
3957 return -ENOMEM;
3958
3959 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3960 MV_SG_TBL_SZ, 0);
3961 if (!hpriv->sg_tbl_pool)
3962 return -ENOMEM;
3963
3964 return 0;
3965 }
3966
3967 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3968 struct mbus_dram_target_info *dram)
3969 {
3970 int i;
3971
3972 for (i = 0; i < 4; i++) {
3973 writel(0, hpriv->base + WINDOW_CTRL(i));
3974 writel(0, hpriv->base + WINDOW_BASE(i));
3975 }
3976
3977 for (i = 0; i < dram->num_cs; i++) {
3978 struct mbus_dram_window *cs = dram->cs + i;
3979
3980 writel(((cs->size - 1) & 0xffff0000) |
3981 (cs->mbus_attr << 8) |
3982 (dram->mbus_dram_target_id << 4) | 1,
3983 hpriv->base + WINDOW_CTRL(i));
3984 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3985 }
3986 }
3987
3988 /**
3989 * mv_platform_probe - handle a positive probe of an soc Marvell
3990 * host
3991 * @pdev: platform device found
3992 *
3993 * LOCKING:
3994 * Inherited from caller.
3995 */
3996 static int mv_platform_probe(struct platform_device *pdev)
3997 {
3998 static int printed_version;
3999 const struct mv_sata_platform_data *mv_platform_data;
4000 const struct ata_port_info *ppi[] =
4001 { &mv_port_info[chip_soc], NULL };
4002 struct ata_host *host;
4003 struct mv_host_priv *hpriv;
4004 struct resource *res;
4005 int n_ports, rc;
4006
4007 if (!printed_version++)
4008 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4009
4010 /*
4011 * Simple resource validation ..
4012 */
4013 if (unlikely(pdev->num_resources != 2)) {
4014 dev_err(&pdev->dev, "invalid number of resources\n");
4015 return -EINVAL;
4016 }
4017
4018 /*
4019 * Get the register base first
4020 */
4021 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4022 if (res == NULL)
4023 return -EINVAL;
4024
4025 /* allocate host */
4026 mv_platform_data = pdev->dev.platform_data;
4027 n_ports = mv_platform_data->n_ports;
4028
4029 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4030 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4031
4032 if (!host || !hpriv)
4033 return -ENOMEM;
4034 host->private_data = hpriv;
4035 hpriv->n_ports = n_ports;
4036 hpriv->board_idx = chip_soc;
4037
4038 host->iomap = NULL;
4039 hpriv->base = devm_ioremap(&pdev->dev, res->start,
4040 resource_size(res));
4041 hpriv->base -= SATAHC0_REG_BASE;
4042
4043 #if defined(CONFIG_HAVE_CLK)
4044 hpriv->clk = clk_get(&pdev->dev, NULL);
4045 if (IS_ERR(hpriv->clk))
4046 dev_notice(&pdev->dev, "cannot get clkdev\n");
4047 else
4048 clk_enable(hpriv->clk);
4049 #endif
4050
4051 /*
4052 * (Re-)program MBUS remapping windows if we are asked to.
4053 */
4054 if (mv_platform_data->dram != NULL)
4055 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4056
4057 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4058 if (rc)
4059 goto err;
4060
4061 /* initialize adapter */
4062 rc = mv_init_host(host);
4063 if (rc)
4064 goto err;
4065
4066 dev_printk(KERN_INFO, &pdev->dev,
4067 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
4068 host->n_ports);
4069
4070 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
4071 IRQF_SHARED, &mv6_sht);
4072 err:
4073 #if defined(CONFIG_HAVE_CLK)
4074 if (!IS_ERR(hpriv->clk)) {
4075 clk_disable(hpriv->clk);
4076 clk_put(hpriv->clk);
4077 }
4078 #endif
4079
4080 return rc;
4081 }
4082
4083 /*
4084 *
4085 * mv_platform_remove - unplug a platform interface
4086 * @pdev: platform device
4087 *
4088 * A platform bus SATA device has been unplugged. Perform the needed
4089 * cleanup. Also called on module unload for any active devices.
4090 */
4091 static int __devexit mv_platform_remove(struct platform_device *pdev)
4092 {
4093 struct device *dev = &pdev->dev;
4094 struct ata_host *host = dev_get_drvdata(dev);
4095 #if defined(CONFIG_HAVE_CLK)
4096 struct mv_host_priv *hpriv = host->private_data;
4097 #endif
4098 ata_host_detach(host);
4099
4100 #if defined(CONFIG_HAVE_CLK)
4101 if (!IS_ERR(hpriv->clk)) {
4102 clk_disable(hpriv->clk);
4103 clk_put(hpriv->clk);
4104 }
4105 #endif
4106 return 0;
4107 }
4108
4109 #ifdef CONFIG_PM
4110 static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4111 {
4112 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4113 if (host)
4114 return ata_host_suspend(host, state);
4115 else
4116 return 0;
4117 }
4118
4119 static int mv_platform_resume(struct platform_device *pdev)
4120 {
4121 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4122 int ret;
4123
4124 if (host) {
4125 struct mv_host_priv *hpriv = host->private_data;
4126 const struct mv_sata_platform_data *mv_platform_data = \
4127 pdev->dev.platform_data;
4128 /*
4129 * (Re-)program MBUS remapping windows if we are asked to.
4130 */
4131 if (mv_platform_data->dram != NULL)
4132 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4133
4134 /* initialize adapter */
4135 ret = mv_init_host(host);
4136 if (ret) {
4137 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4138 return ret;
4139 }
4140 ata_host_resume(host);
4141 }
4142
4143 return 0;
4144 }
4145 #else
4146 #define mv_platform_suspend NULL
4147 #define mv_platform_resume NULL
4148 #endif
4149
4150 static struct platform_driver mv_platform_driver = {
4151 .probe = mv_platform_probe,
4152 .remove = __devexit_p(mv_platform_remove),
4153 .suspend = mv_platform_suspend,
4154 .resume = mv_platform_resume,
4155 .driver = {
4156 .name = DRV_NAME,
4157 .owner = THIS_MODULE,
4158 },
4159 };
4160
4161
4162 #ifdef CONFIG_PCI
4163 static int mv_pci_init_one(struct pci_dev *pdev,
4164 const struct pci_device_id *ent);
4165 #ifdef CONFIG_PM
4166 static int mv_pci_device_resume(struct pci_dev *pdev);
4167 #endif
4168
4169
4170 static struct pci_driver mv_pci_driver = {
4171 .name = DRV_NAME,
4172 .id_table = mv_pci_tbl,
4173 .probe = mv_pci_init_one,
4174 .remove = ata_pci_remove_one,
4175 #ifdef CONFIG_PM
4176 .suspend = ata_pci_device_suspend,
4177 .resume = mv_pci_device_resume,
4178 #endif
4179
4180 };
4181
4182 /* move to PCI layer or libata core? */
4183 static int pci_go_64(struct pci_dev *pdev)
4184 {
4185 int rc;
4186
4187 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4188 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4189 if (rc) {
4190 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4191 if (rc) {
4192 dev_printk(KERN_ERR, &pdev->dev,
4193 "64-bit DMA enable failed\n");
4194 return rc;
4195 }
4196 }
4197 } else {
4198 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4199 if (rc) {
4200 dev_printk(KERN_ERR, &pdev->dev,
4201 "32-bit DMA enable failed\n");
4202 return rc;
4203 }
4204 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4205 if (rc) {
4206 dev_printk(KERN_ERR, &pdev->dev,
4207 "32-bit consistent DMA enable failed\n");
4208 return rc;
4209 }
4210 }
4211
4212 return rc;
4213 }
4214
4215 /**
4216 * mv_print_info - Dump key info to kernel log for perusal.
4217 * @host: ATA host to print info about
4218 *
4219 * FIXME: complete this.
4220 *
4221 * LOCKING:
4222 * Inherited from caller.
4223 */
4224 static void mv_print_info(struct ata_host *host)
4225 {
4226 struct pci_dev *pdev = to_pci_dev(host->dev);
4227 struct mv_host_priv *hpriv = host->private_data;
4228 u8 scc;
4229 const char *scc_s, *gen;
4230
4231 /* Use this to determine the HW stepping of the chip so we know
4232 * what errata to workaround
4233 */
4234 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4235 if (scc == 0)
4236 scc_s = "SCSI";
4237 else if (scc == 0x01)
4238 scc_s = "RAID";
4239 else
4240 scc_s = "?";
4241
4242 if (IS_GEN_I(hpriv))
4243 gen = "I";
4244 else if (IS_GEN_II(hpriv))
4245 gen = "II";
4246 else if (IS_GEN_IIE(hpriv))
4247 gen = "IIE";
4248 else
4249 gen = "?";
4250
4251 dev_printk(KERN_INFO, &pdev->dev,
4252 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4253 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4254 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4255 }
4256
4257 /**
4258 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4259 * @pdev: PCI device found
4260 * @ent: PCI device ID entry for the matched host
4261 *
4262 * LOCKING:
4263 * Inherited from caller.
4264 */
4265 static int mv_pci_init_one(struct pci_dev *pdev,
4266 const struct pci_device_id *ent)
4267 {
4268 static int printed_version;
4269 unsigned int board_idx = (unsigned int)ent->driver_data;
4270 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4271 struct ata_host *host;
4272 struct mv_host_priv *hpriv;
4273 int n_ports, port, rc;
4274
4275 if (!printed_version++)
4276 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4277
4278 /* allocate host */
4279 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4280
4281 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4282 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4283 if (!host || !hpriv)
4284 return -ENOMEM;
4285 host->private_data = hpriv;
4286 hpriv->n_ports = n_ports;
4287 hpriv->board_idx = board_idx;
4288
4289 /* acquire resources */
4290 rc = pcim_enable_device(pdev);
4291 if (rc)
4292 return rc;
4293
4294 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4295 if (rc == -EBUSY)
4296 pcim_pin_device(pdev);
4297 if (rc)
4298 return rc;
4299 host->iomap = pcim_iomap_table(pdev);
4300 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4301
4302 rc = pci_go_64(pdev);
4303 if (rc)
4304 return rc;
4305
4306 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4307 if (rc)
4308 return rc;
4309
4310 for (port = 0; port < host->n_ports; port++) {
4311 struct ata_port *ap = host->ports[port];
4312 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4313 unsigned int offset = port_mmio - hpriv->base;
4314
4315 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4316 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4317 }
4318
4319 /* initialize adapter */
4320 rc = mv_init_host(host);
4321 if (rc)
4322 return rc;
4323
4324 /* Enable message-switched interrupts, if requested */
4325 if (msi && pci_enable_msi(pdev) == 0)
4326 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4327
4328 mv_dump_pci_cfg(pdev, 0x68);
4329 mv_print_info(host);
4330
4331 pci_set_master(pdev);
4332 pci_try_set_mwi(pdev);
4333 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4334 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4335 }
4336
4337 #ifdef CONFIG_PM
4338 static int mv_pci_device_resume(struct pci_dev *pdev)
4339 {
4340 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4341 int rc;
4342
4343 rc = ata_pci_device_do_resume(pdev);
4344 if (rc)
4345 return rc;
4346
4347 /* initialize adapter */
4348 rc = mv_init_host(host);
4349 if (rc)
4350 return rc;
4351
4352 ata_host_resume(host);
4353
4354 return 0;
4355 }
4356 #endif
4357 #endif
4358
4359 static int mv_platform_probe(struct platform_device *pdev);
4360 static int __devexit mv_platform_remove(struct platform_device *pdev);
4361
4362 static int __init mv_init(void)
4363 {
4364 int rc = -ENODEV;
4365 #ifdef CONFIG_PCI
4366 rc = pci_register_driver(&mv_pci_driver);
4367 if (rc < 0)
4368 return rc;
4369 #endif
4370 rc = platform_driver_register(&mv_platform_driver);
4371
4372 #ifdef CONFIG_PCI
4373 if (rc < 0)
4374 pci_unregister_driver(&mv_pci_driver);
4375 #endif
4376 return rc;
4377 }
4378
4379 static void __exit mv_exit(void)
4380 {
4381 #ifdef CONFIG_PCI
4382 pci_unregister_driver(&mv_pci_driver);
4383 #endif
4384 platform_driver_unregister(&mv_platform_driver);
4385 }
4386
4387 MODULE_AUTHOR("Brett Russ");
4388 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4389 MODULE_LICENSE("GPL");
4390 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4391 MODULE_VERSION(DRV_VERSION);
4392 MODULE_ALIAS("platform:" DRV_NAME);
4393
4394 module_init(mv_init);
4395 module_exit(mv_exit);
Ubuntu Artful kernel mirror