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[mirror_ubuntu-bionic-kernel.git] / drivers / ata / sata_mv.c
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28 /*
29 * sata_mv TODO list:
30 *
31 * --> Develop a low-power-consumption strategy, and implement it.
32 *
33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
34 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
42
43 /*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
52 #include <linux/kernel.h>
53 #include <linux/module.h>
54 #include <linux/pci.h>
55 #include <linux/init.h>
56 #include <linux/blkdev.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <linux/dmapool.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/device.h>
62 #include <linux/clk.h>
63 #include <linux/platform_device.h>
64 #include <linux/ata_platform.h>
65 #include <linux/mbus.h>
66 #include <linux/bitops.h>
67 #include <linux/gfp.h>
68 #include <scsi/scsi_host.h>
69 #include <scsi/scsi_cmnd.h>
70 #include <scsi/scsi_device.h>
71 #include <linux/libata.h>
72
73 #define DRV_NAME "sata_mv"
74 #define DRV_VERSION "1.28"
75
76 /*
77 * module options
78 */
79
80 static int msi;
81 #ifdef CONFIG_PCI
82 module_param(msi, int, S_IRUGO);
83 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
84 #endif
85
86 static int irq_coalescing_io_count;
87 module_param(irq_coalescing_io_count, int, S_IRUGO);
88 MODULE_PARM_DESC(irq_coalescing_io_count,
89 "IRQ coalescing I/O count threshold (0..255)");
90
91 static int irq_coalescing_usecs;
92 module_param(irq_coalescing_usecs, int, S_IRUGO);
93 MODULE_PARM_DESC(irq_coalescing_usecs,
94 "IRQ coalescing time threshold in usecs");
95
96 enum {
97 /* BAR's are enumerated in terms of pci_resource_start() terms */
98 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
99 MV_IO_BAR = 2, /* offset 0x18: IO space */
100 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
101
102 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
103 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
104
105 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
106 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
107 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
108 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
109
110 MV_PCI_REG_BASE = 0,
111
112 /*
113 * Per-chip ("all ports") interrupt coalescing feature.
114 * This is only for GEN_II / GEN_IIE hardware.
115 *
116 * Coalescing defers the interrupt until either the IO_THRESHOLD
117 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
118 */
119 COAL_REG_BASE = 0x18000,
120 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
121 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
122
123 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
124 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
125
126 /*
127 * Registers for the (unused here) transaction coalescing feature:
128 */
129 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
130 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
131
132 SATAHC0_REG_BASE = 0x20000,
133 FLASH_CTL = 0x1046c,
134 GPIO_PORT_CTL = 0x104f0,
135 RESET_CFG = 0x180d8,
136
137 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
138 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
139 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
140 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
141
142 MV_MAX_Q_DEPTH = 32,
143 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
144
145 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
146 * CRPB needs alignment on a 256B boundary. Size == 256B
147 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
148 */
149 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
150 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
151 MV_MAX_SG_CT = 256,
152 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
153
154 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
155 MV_PORT_HC_SHIFT = 2,
156 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
157 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
158 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
159
160 /* Host Flags */
161 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
162
163 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
164 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
165
166 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
167
168 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
169 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
170
171 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
172
173 CRQB_FLAG_READ = (1 << 0),
174 CRQB_TAG_SHIFT = 1,
175 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
176 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
177 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
178 CRQB_CMD_ADDR_SHIFT = 8,
179 CRQB_CMD_CS = (0x2 << 11),
180 CRQB_CMD_LAST = (1 << 15),
181
182 CRPB_FLAG_STATUS_SHIFT = 8,
183 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
184 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
185
186 EPRD_FLAG_END_OF_TBL = (1 << 31),
187
188 /* PCI interface registers */
189
190 MV_PCI_COMMAND = 0xc00,
191 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
192 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
193
194 PCI_MAIN_CMD_STS = 0xd30,
195 STOP_PCI_MASTER = (1 << 2),
196 PCI_MASTER_EMPTY = (1 << 3),
197 GLOB_SFT_RST = (1 << 4),
198
199 MV_PCI_MODE = 0xd00,
200 MV_PCI_MODE_MASK = 0x30,
201
202 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
203 MV_PCI_DISC_TIMER = 0xd04,
204 MV_PCI_MSI_TRIGGER = 0xc38,
205 MV_PCI_SERR_MASK = 0xc28,
206 MV_PCI_XBAR_TMOUT = 0x1d04,
207 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
208 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
209 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
210 MV_PCI_ERR_COMMAND = 0x1d50,
211
212 PCI_IRQ_CAUSE = 0x1d58,
213 PCI_IRQ_MASK = 0x1d5c,
214 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
215
216 PCIE_IRQ_CAUSE = 0x1900,
217 PCIE_IRQ_MASK = 0x1910,
218 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
219
220 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
221 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
222 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
223 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
224 SOC_HC_MAIN_IRQ_MASK = 0x20024,
225 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
226 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
227 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
228 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
229 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
230 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
231 PCI_ERR = (1 << 18),
232 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
233 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
234 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
235 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
236 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
237 GPIO_INT = (1 << 22),
238 SELF_INT = (1 << 23),
239 TWSI_INT = (1 << 24),
240 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
241 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
242 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
243
244 /* SATAHC registers */
245 HC_CFG = 0x00,
246
247 HC_IRQ_CAUSE = 0x14,
248 DMA_IRQ = (1 << 0), /* shift by port # */
249 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
250 DEV_IRQ = (1 << 8), /* shift by port # */
251
252 /*
253 * Per-HC (Host-Controller) interrupt coalescing feature.
254 * This is present on all chip generations.
255 *
256 * Coalescing defers the interrupt until either the IO_THRESHOLD
257 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
258 */
259 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
260 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
261
262 SOC_LED_CTRL = 0x2c,
263 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
264 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
265 /* with dev activity LED */
266
267 /* Shadow block registers */
268 SHD_BLK = 0x100,
269 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
270
271 /* SATA registers */
272 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
273 SATA_ACTIVE = 0x350,
274 FIS_IRQ_CAUSE = 0x364,
275 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
276
277 LTMODE = 0x30c, /* requires read-after-write */
278 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
279
280 PHY_MODE2 = 0x330,
281 PHY_MODE3 = 0x310,
282
283 PHY_MODE4 = 0x314, /* requires read-after-write */
284 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
285 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
286 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
287 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
288
289 SATA_IFCTL = 0x344,
290 SATA_TESTCTL = 0x348,
291 SATA_IFSTAT = 0x34c,
292 VENDOR_UNIQUE_FIS = 0x35c,
293
294 FISCFG = 0x360,
295 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
296 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
297
298 PHY_MODE9_GEN2 = 0x398,
299 PHY_MODE9_GEN1 = 0x39c,
300 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
301
302 MV5_PHY_MODE = 0x74,
303 MV5_LTMODE = 0x30,
304 MV5_PHY_CTL = 0x0C,
305 SATA_IFCFG = 0x050,
306
307 MV_M2_PREAMP_MASK = 0x7e0,
308
309 /* Port registers */
310 EDMA_CFG = 0,
311 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
312 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
313 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
314 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
315 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
316 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
317 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
318
319 EDMA_ERR_IRQ_CAUSE = 0x8,
320 EDMA_ERR_IRQ_MASK = 0xc,
321 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
322 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
323 EDMA_ERR_DEV = (1 << 2), /* device error */
324 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
325 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
326 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
327 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
328 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
329 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
330 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
331 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
332 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
333 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
334 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
335
336 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
337 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
338 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
339 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
340 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
341
342 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
343
344 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
345 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
346 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
347 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
348 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
349 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
350
351 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
352
353 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
354 EDMA_ERR_OVERRUN_5 = (1 << 5),
355 EDMA_ERR_UNDERRUN_5 = (1 << 6),
356
357 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
358 EDMA_ERR_LNK_CTRL_RX_1 |
359 EDMA_ERR_LNK_CTRL_RX_3 |
360 EDMA_ERR_LNK_CTRL_TX,
361
362 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
363 EDMA_ERR_PRD_PAR |
364 EDMA_ERR_DEV_DCON |
365 EDMA_ERR_DEV_CON |
366 EDMA_ERR_SERR |
367 EDMA_ERR_SELF_DIS |
368 EDMA_ERR_CRQB_PAR |
369 EDMA_ERR_CRPB_PAR |
370 EDMA_ERR_INTRL_PAR |
371 EDMA_ERR_IORDY |
372 EDMA_ERR_LNK_CTRL_RX_2 |
373 EDMA_ERR_LNK_DATA_RX |
374 EDMA_ERR_LNK_DATA_TX |
375 EDMA_ERR_TRANS_PROTO,
376
377 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
378 EDMA_ERR_PRD_PAR |
379 EDMA_ERR_DEV_DCON |
380 EDMA_ERR_DEV_CON |
381 EDMA_ERR_OVERRUN_5 |
382 EDMA_ERR_UNDERRUN_5 |
383 EDMA_ERR_SELF_DIS_5 |
384 EDMA_ERR_CRQB_PAR |
385 EDMA_ERR_CRPB_PAR |
386 EDMA_ERR_INTRL_PAR |
387 EDMA_ERR_IORDY,
388
389 EDMA_REQ_Q_BASE_HI = 0x10,
390 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
391
392 EDMA_REQ_Q_OUT_PTR = 0x18,
393 EDMA_REQ_Q_PTR_SHIFT = 5,
394
395 EDMA_RSP_Q_BASE_HI = 0x1c,
396 EDMA_RSP_Q_IN_PTR = 0x20,
397 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
398 EDMA_RSP_Q_PTR_SHIFT = 3,
399
400 EDMA_CMD = 0x28, /* EDMA command register */
401 EDMA_EN = (1 << 0), /* enable EDMA */
402 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
403 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
404
405 EDMA_STATUS = 0x30, /* EDMA engine status */
406 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
407 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
408
409 EDMA_IORDY_TMOUT = 0x34,
410 EDMA_ARB_CFG = 0x38,
411
412 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
413 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
414
415 BMDMA_CMD = 0x224, /* bmdma command register */
416 BMDMA_STATUS = 0x228, /* bmdma status register */
417 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
418 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
419
420 /* Host private flags (hp_flags) */
421 MV_HP_FLAG_MSI = (1 << 0),
422 MV_HP_ERRATA_50XXB0 = (1 << 1),
423 MV_HP_ERRATA_50XXB2 = (1 << 2),
424 MV_HP_ERRATA_60X1B2 = (1 << 3),
425 MV_HP_ERRATA_60X1C0 = (1 << 4),
426 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
427 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
428 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
429 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
430 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
431 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
432 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
433
434 /* Port private flags (pp_flags) */
435 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
436 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
437 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
438 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
439 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
440 };
441
442 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
443 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
444 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
445 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
446 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
447
448 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
449 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
450
451 enum {
452 /* DMA boundary 0xffff is required by the s/g splitting
453 * we need on /length/ in mv_fill-sg().
454 */
455 MV_DMA_BOUNDARY = 0xffffU,
456
457 /* mask of register bits containing lower 32 bits
458 * of EDMA request queue DMA address
459 */
460 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
461
462 /* ditto, for response queue */
463 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
464 };
465
466 enum chip_type {
467 chip_504x,
468 chip_508x,
469 chip_5080,
470 chip_604x,
471 chip_608x,
472 chip_6042,
473 chip_7042,
474 chip_soc,
475 };
476
477 /* Command ReQuest Block: 32B */
478 struct mv_crqb {
479 __le32 sg_addr;
480 __le32 sg_addr_hi;
481 __le16 ctrl_flags;
482 __le16 ata_cmd[11];
483 };
484
485 struct mv_crqb_iie {
486 __le32 addr;
487 __le32 addr_hi;
488 __le32 flags;
489 __le32 len;
490 __le32 ata_cmd[4];
491 };
492
493 /* Command ResPonse Block: 8B */
494 struct mv_crpb {
495 __le16 id;
496 __le16 flags;
497 __le32 tmstmp;
498 };
499
500 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
501 struct mv_sg {
502 __le32 addr;
503 __le32 flags_size;
504 __le32 addr_hi;
505 __le32 reserved;
506 };
507
508 /*
509 * We keep a local cache of a few frequently accessed port
510 * registers here, to avoid having to read them (very slow)
511 * when switching between EDMA and non-EDMA modes.
512 */
513 struct mv_cached_regs {
514 u32 fiscfg;
515 u32 ltmode;
516 u32 haltcond;
517 u32 unknown_rsvd;
518 };
519
520 struct mv_port_priv {
521 struct mv_crqb *crqb;
522 dma_addr_t crqb_dma;
523 struct mv_crpb *crpb;
524 dma_addr_t crpb_dma;
525 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
526 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
527
528 unsigned int req_idx;
529 unsigned int resp_idx;
530
531 u32 pp_flags;
532 struct mv_cached_regs cached;
533 unsigned int delayed_eh_pmp_map;
534 };
535
536 struct mv_port_signal {
537 u32 amps;
538 u32 pre;
539 };
540
541 struct mv_host_priv {
542 u32 hp_flags;
543 unsigned int board_idx;
544 u32 main_irq_mask;
545 struct mv_port_signal signal[8];
546 const struct mv_hw_ops *ops;
547 int n_ports;
548 void __iomem *base;
549 void __iomem *main_irq_cause_addr;
550 void __iomem *main_irq_mask_addr;
551 u32 irq_cause_offset;
552 u32 irq_mask_offset;
553 u32 unmask_all_irqs;
554
555 #if defined(CONFIG_HAVE_CLK)
556 struct clk *clk;
557 #endif
558 /*
559 * These consistent DMA memory pools give us guaranteed
560 * alignment for hardware-accessed data structures,
561 * and less memory waste in accomplishing the alignment.
562 */
563 struct dma_pool *crqb_pool;
564 struct dma_pool *crpb_pool;
565 struct dma_pool *sg_tbl_pool;
566 };
567
568 struct mv_hw_ops {
569 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
570 unsigned int port);
571 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
572 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
573 void __iomem *mmio);
574 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
575 unsigned int n_hc);
576 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
577 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
578 };
579
580 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
581 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
582 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
583 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
584 static int mv_port_start(struct ata_port *ap);
585 static void mv_port_stop(struct ata_port *ap);
586 static int mv_qc_defer(struct ata_queued_cmd *qc);
587 static void mv_qc_prep(struct ata_queued_cmd *qc);
588 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
589 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
590 static int mv_hardreset(struct ata_link *link, unsigned int *class,
591 unsigned long deadline);
592 static void mv_eh_freeze(struct ata_port *ap);
593 static void mv_eh_thaw(struct ata_port *ap);
594 static void mv6_dev_config(struct ata_device *dev);
595
596 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
597 unsigned int port);
598 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
599 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
600 void __iomem *mmio);
601 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
602 unsigned int n_hc);
603 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
604 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
605
606 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
607 unsigned int port);
608 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
609 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
610 void __iomem *mmio);
611 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
612 unsigned int n_hc);
613 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
614 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
615 void __iomem *mmio);
616 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
617 void __iomem *mmio);
618 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
619 void __iomem *mmio, unsigned int n_hc);
620 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
621 void __iomem *mmio);
622 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
623 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
624 void __iomem *mmio, unsigned int port);
625 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
626 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
627 unsigned int port_no);
628 static int mv_stop_edma(struct ata_port *ap);
629 static int mv_stop_edma_engine(void __iomem *port_mmio);
630 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
631
632 static void mv_pmp_select(struct ata_port *ap, int pmp);
633 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
634 unsigned long deadline);
635 static int mv_softreset(struct ata_link *link, unsigned int *class,
636 unsigned long deadline);
637 static void mv_pmp_error_handler(struct ata_port *ap);
638 static void mv_process_crpb_entries(struct ata_port *ap,
639 struct mv_port_priv *pp);
640
641 static void mv_sff_irq_clear(struct ata_port *ap);
642 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
643 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
644 static void mv_bmdma_start(struct ata_queued_cmd *qc);
645 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
646 static u8 mv_bmdma_status(struct ata_port *ap);
647 static u8 mv_sff_check_status(struct ata_port *ap);
648
649 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
650 * because we have to allow room for worst case splitting of
651 * PRDs for 64K boundaries in mv_fill_sg().
652 */
653 static struct scsi_host_template mv5_sht = {
654 ATA_BASE_SHT(DRV_NAME),
655 .sg_tablesize = MV_MAX_SG_CT / 2,
656 .dma_boundary = MV_DMA_BOUNDARY,
657 };
658
659 static struct scsi_host_template mv6_sht = {
660 ATA_NCQ_SHT(DRV_NAME),
661 .can_queue = MV_MAX_Q_DEPTH - 1,
662 .sg_tablesize = MV_MAX_SG_CT / 2,
663 .dma_boundary = MV_DMA_BOUNDARY,
664 };
665
666 static struct ata_port_operations mv5_ops = {
667 .inherits = &ata_sff_port_ops,
668
669 .lost_interrupt = ATA_OP_NULL,
670
671 .qc_defer = mv_qc_defer,
672 .qc_prep = mv_qc_prep,
673 .qc_issue = mv_qc_issue,
674
675 .freeze = mv_eh_freeze,
676 .thaw = mv_eh_thaw,
677 .hardreset = mv_hardreset,
678 .error_handler = ata_std_error_handler, /* avoid SFF EH */
679 .post_internal_cmd = ATA_OP_NULL,
680
681 .scr_read = mv5_scr_read,
682 .scr_write = mv5_scr_write,
683
684 .port_start = mv_port_start,
685 .port_stop = mv_port_stop,
686 };
687
688 static struct ata_port_operations mv6_ops = {
689 .inherits = &ata_bmdma_port_ops,
690
691 .lost_interrupt = ATA_OP_NULL,
692
693 .qc_defer = mv_qc_defer,
694 .qc_prep = mv_qc_prep,
695 .qc_issue = mv_qc_issue,
696
697 .dev_config = mv6_dev_config,
698
699 .freeze = mv_eh_freeze,
700 .thaw = mv_eh_thaw,
701 .hardreset = mv_hardreset,
702 .softreset = mv_softreset,
703 .pmp_hardreset = mv_pmp_hardreset,
704 .pmp_softreset = mv_softreset,
705 .error_handler = mv_pmp_error_handler,
706
707 .scr_read = mv_scr_read,
708 .scr_write = mv_scr_write,
709
710 .sff_check_status = mv_sff_check_status,
711 .sff_irq_clear = mv_sff_irq_clear,
712 .check_atapi_dma = mv_check_atapi_dma,
713 .bmdma_setup = mv_bmdma_setup,
714 .bmdma_start = mv_bmdma_start,
715 .bmdma_stop = mv_bmdma_stop,
716 .bmdma_status = mv_bmdma_status,
717
718 .port_start = mv_port_start,
719 .port_stop = mv_port_stop,
720
721 .mode_filter = ATA_OP_NULL, /* will be removed soon */
722 };
723
724 static struct ata_port_operations mv_iie_ops = {
725 .inherits = &mv6_ops,
726 .dev_config = ATA_OP_NULL,
727 .qc_prep = mv_qc_prep_iie,
728 };
729
730 static const struct ata_port_info mv_port_info[] = {
731 { /* chip_504x */
732 .flags = MV_GEN_I_FLAGS,
733 .pio_mask = ATA_PIO4,
734 .udma_mask = ATA_UDMA6,
735 .port_ops = &mv5_ops,
736 },
737 { /* chip_508x */
738 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
739 .pio_mask = ATA_PIO4,
740 .udma_mask = ATA_UDMA6,
741 .port_ops = &mv5_ops,
742 },
743 { /* chip_5080 */
744 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
745 .pio_mask = ATA_PIO4,
746 .udma_mask = ATA_UDMA6,
747 .port_ops = &mv5_ops,
748 },
749 { /* chip_604x */
750 .flags = MV_GEN_II_FLAGS,
751 .pio_mask = ATA_PIO4,
752 .udma_mask = ATA_UDMA6,
753 .port_ops = &mv6_ops,
754 },
755 { /* chip_608x */
756 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
757 .pio_mask = ATA_PIO4,
758 .udma_mask = ATA_UDMA6,
759 .port_ops = &mv6_ops,
760 },
761 { /* chip_6042 */
762 .flags = MV_GEN_IIE_FLAGS,
763 .pio_mask = ATA_PIO4,
764 .udma_mask = ATA_UDMA6,
765 .port_ops = &mv_iie_ops,
766 },
767 { /* chip_7042 */
768 .flags = MV_GEN_IIE_FLAGS,
769 .pio_mask = ATA_PIO4,
770 .udma_mask = ATA_UDMA6,
771 .port_ops = &mv_iie_ops,
772 },
773 { /* chip_soc */
774 .flags = MV_GEN_IIE_FLAGS,
775 .pio_mask = ATA_PIO4,
776 .udma_mask = ATA_UDMA6,
777 .port_ops = &mv_iie_ops,
778 },
779 };
780
781 static const struct pci_device_id mv_pci_tbl[] = {
782 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
783 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
784 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
785 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
786 /* RocketRAID 1720/174x have different identifiers */
787 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
788 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
789 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
790
791 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
792 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
793 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
794 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
795 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
796
797 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
798
799 /* Adaptec 1430SA */
800 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
801
802 /* Marvell 7042 support */
803 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
804
805 /* Highpoint RocketRAID PCIe series */
806 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
807 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
808
809 { } /* terminate list */
810 };
811
812 static const struct mv_hw_ops mv5xxx_ops = {
813 .phy_errata = mv5_phy_errata,
814 .enable_leds = mv5_enable_leds,
815 .read_preamp = mv5_read_preamp,
816 .reset_hc = mv5_reset_hc,
817 .reset_flash = mv5_reset_flash,
818 .reset_bus = mv5_reset_bus,
819 };
820
821 static const struct mv_hw_ops mv6xxx_ops = {
822 .phy_errata = mv6_phy_errata,
823 .enable_leds = mv6_enable_leds,
824 .read_preamp = mv6_read_preamp,
825 .reset_hc = mv6_reset_hc,
826 .reset_flash = mv6_reset_flash,
827 .reset_bus = mv_reset_pci_bus,
828 };
829
830 static const struct mv_hw_ops mv_soc_ops = {
831 .phy_errata = mv6_phy_errata,
832 .enable_leds = mv_soc_enable_leds,
833 .read_preamp = mv_soc_read_preamp,
834 .reset_hc = mv_soc_reset_hc,
835 .reset_flash = mv_soc_reset_flash,
836 .reset_bus = mv_soc_reset_bus,
837 };
838
839 static const struct mv_hw_ops mv_soc_65n_ops = {
840 .phy_errata = mv_soc_65n_phy_errata,
841 .enable_leds = mv_soc_enable_leds,
842 .reset_hc = mv_soc_reset_hc,
843 .reset_flash = mv_soc_reset_flash,
844 .reset_bus = mv_soc_reset_bus,
845 };
846
847 /*
848 * Functions
849 */
850
851 static inline void writelfl(unsigned long data, void __iomem *addr)
852 {
853 writel(data, addr);
854 (void) readl(addr); /* flush to avoid PCI posted write */
855 }
856
857 static inline unsigned int mv_hc_from_port(unsigned int port)
858 {
859 return port >> MV_PORT_HC_SHIFT;
860 }
861
862 static inline unsigned int mv_hardport_from_port(unsigned int port)
863 {
864 return port & MV_PORT_MASK;
865 }
866
867 /*
868 * Consolidate some rather tricky bit shift calculations.
869 * This is hot-path stuff, so not a function.
870 * Simple code, with two return values, so macro rather than inline.
871 *
872 * port is the sole input, in range 0..7.
873 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
874 * hardport is the other output, in range 0..3.
875 *
876 * Note that port and hardport may be the same variable in some cases.
877 */
878 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
879 { \
880 shift = mv_hc_from_port(port) * HC_SHIFT; \
881 hardport = mv_hardport_from_port(port); \
882 shift += hardport * 2; \
883 }
884
885 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
886 {
887 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
888 }
889
890 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
891 unsigned int port)
892 {
893 return mv_hc_base(base, mv_hc_from_port(port));
894 }
895
896 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
897 {
898 return mv_hc_base_from_port(base, port) +
899 MV_SATAHC_ARBTR_REG_SZ +
900 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
901 }
902
903 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
904 {
905 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
906 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
907
908 return hc_mmio + ofs;
909 }
910
911 static inline void __iomem *mv_host_base(struct ata_host *host)
912 {
913 struct mv_host_priv *hpriv = host->private_data;
914 return hpriv->base;
915 }
916
917 static inline void __iomem *mv_ap_base(struct ata_port *ap)
918 {
919 return mv_port_base(mv_host_base(ap->host), ap->port_no);
920 }
921
922 static inline int mv_get_hc_count(unsigned long port_flags)
923 {
924 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
925 }
926
927 /**
928 * mv_save_cached_regs - (re-)initialize cached port registers
929 * @ap: the port whose registers we are caching
930 *
931 * Initialize the local cache of port registers,
932 * so that reading them over and over again can
933 * be avoided on the hotter paths of this driver.
934 * This saves a few microseconds each time we switch
935 * to/from EDMA mode to perform (eg.) a drive cache flush.
936 */
937 static void mv_save_cached_regs(struct ata_port *ap)
938 {
939 void __iomem *port_mmio = mv_ap_base(ap);
940 struct mv_port_priv *pp = ap->private_data;
941
942 pp->cached.fiscfg = readl(port_mmio + FISCFG);
943 pp->cached.ltmode = readl(port_mmio + LTMODE);
944 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
945 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
946 }
947
948 /**
949 * mv_write_cached_reg - write to a cached port register
950 * @addr: hardware address of the register
951 * @old: pointer to cached value of the register
952 * @new: new value for the register
953 *
954 * Write a new value to a cached register,
955 * but only if the value is different from before.
956 */
957 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
958 {
959 if (new != *old) {
960 unsigned long laddr;
961 *old = new;
962 /*
963 * Workaround for 88SX60x1-B2 FEr SATA#13:
964 * Read-after-write is needed to prevent generating 64-bit
965 * write cycles on the PCI bus for SATA interface registers
966 * at offsets ending in 0x4 or 0xc.
967 *
968 * Looks like a lot of fuss, but it avoids an unnecessary
969 * +1 usec read-after-write delay for unaffected registers.
970 */
971 laddr = (long)addr & 0xffff;
972 if (laddr >= 0x300 && laddr <= 0x33c) {
973 laddr &= 0x000f;
974 if (laddr == 0x4 || laddr == 0xc) {
975 writelfl(new, addr); /* read after write */
976 return;
977 }
978 }
979 writel(new, addr); /* unaffected by the errata */
980 }
981 }
982
983 static void mv_set_edma_ptrs(void __iomem *port_mmio,
984 struct mv_host_priv *hpriv,
985 struct mv_port_priv *pp)
986 {
987 u32 index;
988
989 /*
990 * initialize request queue
991 */
992 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
993 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
994
995 WARN_ON(pp->crqb_dma & 0x3ff);
996 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
997 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
998 port_mmio + EDMA_REQ_Q_IN_PTR);
999 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
1000
1001 /*
1002 * initialize response queue
1003 */
1004 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
1005 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
1006
1007 WARN_ON(pp->crpb_dma & 0xff);
1008 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
1009 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
1010 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
1011 port_mmio + EDMA_RSP_Q_OUT_PTR);
1012 }
1013
1014 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1015 {
1016 /*
1017 * When writing to the main_irq_mask in hardware,
1018 * we must ensure exclusivity between the interrupt coalescing bits
1019 * and the corresponding individual port DONE_IRQ bits.
1020 *
1021 * Note that this register is really an "IRQ enable" register,
1022 * not an "IRQ mask" register as Marvell's naming might suggest.
1023 */
1024 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1025 mask &= ~DONE_IRQ_0_3;
1026 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1027 mask &= ~DONE_IRQ_4_7;
1028 writelfl(mask, hpriv->main_irq_mask_addr);
1029 }
1030
1031 static void mv_set_main_irq_mask(struct ata_host *host,
1032 u32 disable_bits, u32 enable_bits)
1033 {
1034 struct mv_host_priv *hpriv = host->private_data;
1035 u32 old_mask, new_mask;
1036
1037 old_mask = hpriv->main_irq_mask;
1038 new_mask = (old_mask & ~disable_bits) | enable_bits;
1039 if (new_mask != old_mask) {
1040 hpriv->main_irq_mask = new_mask;
1041 mv_write_main_irq_mask(new_mask, hpriv);
1042 }
1043 }
1044
1045 static void mv_enable_port_irqs(struct ata_port *ap,
1046 unsigned int port_bits)
1047 {
1048 unsigned int shift, hardport, port = ap->port_no;
1049 u32 disable_bits, enable_bits;
1050
1051 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1052
1053 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1054 enable_bits = port_bits << shift;
1055 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1056 }
1057
1058 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1059 void __iomem *port_mmio,
1060 unsigned int port_irqs)
1061 {
1062 struct mv_host_priv *hpriv = ap->host->private_data;
1063 int hardport = mv_hardport_from_port(ap->port_no);
1064 void __iomem *hc_mmio = mv_hc_base_from_port(
1065 mv_host_base(ap->host), ap->port_no);
1066 u32 hc_irq_cause;
1067
1068 /* clear EDMA event indicators, if any */
1069 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
1070
1071 /* clear pending irq events */
1072 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1073 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
1074
1075 /* clear FIS IRQ Cause */
1076 if (IS_GEN_IIE(hpriv))
1077 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
1078
1079 mv_enable_port_irqs(ap, port_irqs);
1080 }
1081
1082 static void mv_set_irq_coalescing(struct ata_host *host,
1083 unsigned int count, unsigned int usecs)
1084 {
1085 struct mv_host_priv *hpriv = host->private_data;
1086 void __iomem *mmio = hpriv->base, *hc_mmio;
1087 u32 coal_enable = 0;
1088 unsigned long flags;
1089 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1090 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1091 ALL_PORTS_COAL_DONE;
1092
1093 /* Disable IRQ coalescing if either threshold is zero */
1094 if (!usecs || !count) {
1095 clks = count = 0;
1096 } else {
1097 /* Respect maximum limits of the hardware */
1098 clks = usecs * COAL_CLOCKS_PER_USEC;
1099 if (clks > MAX_COAL_TIME_THRESHOLD)
1100 clks = MAX_COAL_TIME_THRESHOLD;
1101 if (count > MAX_COAL_IO_COUNT)
1102 count = MAX_COAL_IO_COUNT;
1103 }
1104
1105 spin_lock_irqsave(&host->lock, flags);
1106 mv_set_main_irq_mask(host, coal_disable, 0);
1107
1108 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1109 /*
1110 * GEN_II/GEN_IIE with dual host controllers:
1111 * one set of global thresholds for the entire chip.
1112 */
1113 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1114 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
1115 /* clear leftover coal IRQ bit */
1116 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
1117 if (count)
1118 coal_enable = ALL_PORTS_COAL_DONE;
1119 clks = count = 0; /* force clearing of regular regs below */
1120 }
1121
1122 /*
1123 * All chips: independent thresholds for each HC on the chip.
1124 */
1125 hc_mmio = mv_hc_base_from_port(mmio, 0);
1126 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1127 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1128 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1129 if (count)
1130 coal_enable |= PORTS_0_3_COAL_DONE;
1131 if (is_dual_hc) {
1132 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1133 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1134 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1135 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1136 if (count)
1137 coal_enable |= PORTS_4_7_COAL_DONE;
1138 }
1139
1140 mv_set_main_irq_mask(host, 0, coal_enable);
1141 spin_unlock_irqrestore(&host->lock, flags);
1142 }
1143
1144 /**
1145 * mv_start_edma - Enable eDMA engine
1146 * @base: port base address
1147 * @pp: port private data
1148 *
1149 * Verify the local cache of the eDMA state is accurate with a
1150 * WARN_ON.
1151 *
1152 * LOCKING:
1153 * Inherited from caller.
1154 */
1155 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1156 struct mv_port_priv *pp, u8 protocol)
1157 {
1158 int want_ncq = (protocol == ATA_PROT_NCQ);
1159
1160 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1161 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1162 if (want_ncq != using_ncq)
1163 mv_stop_edma(ap);
1164 }
1165 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1166 struct mv_host_priv *hpriv = ap->host->private_data;
1167
1168 mv_edma_cfg(ap, want_ncq, 1);
1169
1170 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1171 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1172
1173 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
1174 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1175 }
1176 }
1177
1178 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1179 {
1180 void __iomem *port_mmio = mv_ap_base(ap);
1181 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1182 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1183 int i;
1184
1185 /*
1186 * Wait for the EDMA engine to finish transactions in progress.
1187 * No idea what a good "timeout" value might be, but measurements
1188 * indicate that it often requires hundreds of microseconds
1189 * with two drives in-use. So we use the 15msec value above
1190 * as a rough guess at what even more drives might require.
1191 */
1192 for (i = 0; i < timeout; ++i) {
1193 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
1194 if ((edma_stat & empty_idle) == empty_idle)
1195 break;
1196 udelay(per_loop);
1197 }
1198 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1199 }
1200
1201 /**
1202 * mv_stop_edma_engine - Disable eDMA engine
1203 * @port_mmio: io base address
1204 *
1205 * LOCKING:
1206 * Inherited from caller.
1207 */
1208 static int mv_stop_edma_engine(void __iomem *port_mmio)
1209 {
1210 int i;
1211
1212 /* Disable eDMA. The disable bit auto clears. */
1213 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
1214
1215 /* Wait for the chip to confirm eDMA is off. */
1216 for (i = 10000; i > 0; i--) {
1217 u32 reg = readl(port_mmio + EDMA_CMD);
1218 if (!(reg & EDMA_EN))
1219 return 0;
1220 udelay(10);
1221 }
1222 return -EIO;
1223 }
1224
1225 static int mv_stop_edma(struct ata_port *ap)
1226 {
1227 void __iomem *port_mmio = mv_ap_base(ap);
1228 struct mv_port_priv *pp = ap->private_data;
1229 int err = 0;
1230
1231 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1232 return 0;
1233 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1234 mv_wait_for_edma_empty_idle(ap);
1235 if (mv_stop_edma_engine(port_mmio)) {
1236 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
1237 err = -EIO;
1238 }
1239 mv_edma_cfg(ap, 0, 0);
1240 return err;
1241 }
1242
1243 #ifdef ATA_DEBUG
1244 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1245 {
1246 int b, w;
1247 for (b = 0; b < bytes; ) {
1248 DPRINTK("%p: ", start + b);
1249 for (w = 0; b < bytes && w < 4; w++) {
1250 printk("%08x ", readl(start + b));
1251 b += sizeof(u32);
1252 }
1253 printk("\n");
1254 }
1255 }
1256 #endif
1257
1258 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1259 {
1260 #ifdef ATA_DEBUG
1261 int b, w;
1262 u32 dw;
1263 for (b = 0; b < bytes; ) {
1264 DPRINTK("%02x: ", b);
1265 for (w = 0; b < bytes && w < 4; w++) {
1266 (void) pci_read_config_dword(pdev, b, &dw);
1267 printk("%08x ", dw);
1268 b += sizeof(u32);
1269 }
1270 printk("\n");
1271 }
1272 #endif
1273 }
1274 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1275 struct pci_dev *pdev)
1276 {
1277 #ifdef ATA_DEBUG
1278 void __iomem *hc_base = mv_hc_base(mmio_base,
1279 port >> MV_PORT_HC_SHIFT);
1280 void __iomem *port_base;
1281 int start_port, num_ports, p, start_hc, num_hcs, hc;
1282
1283 if (0 > port) {
1284 start_hc = start_port = 0;
1285 num_ports = 8; /* shld be benign for 4 port devs */
1286 num_hcs = 2;
1287 } else {
1288 start_hc = port >> MV_PORT_HC_SHIFT;
1289 start_port = port;
1290 num_ports = num_hcs = 1;
1291 }
1292 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1293 num_ports > 1 ? num_ports - 1 : start_port);
1294
1295 if (NULL != pdev) {
1296 DPRINTK("PCI config space regs:\n");
1297 mv_dump_pci_cfg(pdev, 0x68);
1298 }
1299 DPRINTK("PCI regs:\n");
1300 mv_dump_mem(mmio_base+0xc00, 0x3c);
1301 mv_dump_mem(mmio_base+0xd00, 0x34);
1302 mv_dump_mem(mmio_base+0xf00, 0x4);
1303 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1304 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1305 hc_base = mv_hc_base(mmio_base, hc);
1306 DPRINTK("HC regs (HC %i):\n", hc);
1307 mv_dump_mem(hc_base, 0x1c);
1308 }
1309 for (p = start_port; p < start_port + num_ports; p++) {
1310 port_base = mv_port_base(mmio_base, p);
1311 DPRINTK("EDMA regs (port %i):\n", p);
1312 mv_dump_mem(port_base, 0x54);
1313 DPRINTK("SATA regs (port %i):\n", p);
1314 mv_dump_mem(port_base+0x300, 0x60);
1315 }
1316 #endif
1317 }
1318
1319 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1320 {
1321 unsigned int ofs;
1322
1323 switch (sc_reg_in) {
1324 case SCR_STATUS:
1325 case SCR_CONTROL:
1326 case SCR_ERROR:
1327 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
1328 break;
1329 case SCR_ACTIVE:
1330 ofs = SATA_ACTIVE; /* active is not with the others */
1331 break;
1332 default:
1333 ofs = 0xffffffffU;
1334 break;
1335 }
1336 return ofs;
1337 }
1338
1339 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1340 {
1341 unsigned int ofs = mv_scr_offset(sc_reg_in);
1342
1343 if (ofs != 0xffffffffU) {
1344 *val = readl(mv_ap_base(link->ap) + ofs);
1345 return 0;
1346 } else
1347 return -EINVAL;
1348 }
1349
1350 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1351 {
1352 unsigned int ofs = mv_scr_offset(sc_reg_in);
1353
1354 if (ofs != 0xffffffffU) {
1355 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1356 if (sc_reg_in == SCR_CONTROL) {
1357 /*
1358 * Workaround for 88SX60x1 FEr SATA#26:
1359 *
1360 * COMRESETs have to take care not to accidently
1361 * put the drive to sleep when writing SCR_CONTROL.
1362 * Setting bits 12..15 prevents this problem.
1363 *
1364 * So if we see an outbound COMMRESET, set those bits.
1365 * Ditto for the followup write that clears the reset.
1366 *
1367 * The proprietary driver does this for
1368 * all chip versions, and so do we.
1369 */
1370 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1371 val |= 0xf000;
1372 }
1373 writelfl(val, addr);
1374 return 0;
1375 } else
1376 return -EINVAL;
1377 }
1378
1379 static void mv6_dev_config(struct ata_device *adev)
1380 {
1381 /*
1382 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1383 *
1384 * Gen-II does not support NCQ over a port multiplier
1385 * (no FIS-based switching).
1386 */
1387 if (adev->flags & ATA_DFLAG_NCQ) {
1388 if (sata_pmp_attached(adev->link->ap)) {
1389 adev->flags &= ~ATA_DFLAG_NCQ;
1390 ata_dev_printk(adev, KERN_INFO,
1391 "NCQ disabled for command-based switching\n");
1392 }
1393 }
1394 }
1395
1396 static int mv_qc_defer(struct ata_queued_cmd *qc)
1397 {
1398 struct ata_link *link = qc->dev->link;
1399 struct ata_port *ap = link->ap;
1400 struct mv_port_priv *pp = ap->private_data;
1401
1402 /*
1403 * Don't allow new commands if we're in a delayed EH state
1404 * for NCQ and/or FIS-based switching.
1405 */
1406 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1407 return ATA_DEFER_PORT;
1408
1409 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1410 * can run concurrently.
1411 * set excl_link when we want to send a PIO command in DMA mode
1412 * or a non-NCQ command in NCQ mode.
1413 * When we receive a command from that link, and there are no
1414 * outstanding commands, mark a flag to clear excl_link and let
1415 * the command go through.
1416 */
1417 if (unlikely(ap->excl_link)) {
1418 if (link == ap->excl_link) {
1419 if (ap->nr_active_links)
1420 return ATA_DEFER_PORT;
1421 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1422 return 0;
1423 } else
1424 return ATA_DEFER_PORT;
1425 }
1426
1427 /*
1428 * If the port is completely idle, then allow the new qc.
1429 */
1430 if (ap->nr_active_links == 0)
1431 return 0;
1432
1433 /*
1434 * The port is operating in host queuing mode (EDMA) with NCQ
1435 * enabled, allow multiple NCQ commands. EDMA also allows
1436 * queueing multiple DMA commands but libata core currently
1437 * doesn't allow it.
1438 */
1439 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1440 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1441 if (ata_is_ncq(qc->tf.protocol))
1442 return 0;
1443 else {
1444 ap->excl_link = link;
1445 return ATA_DEFER_PORT;
1446 }
1447 }
1448
1449 return ATA_DEFER_PORT;
1450 }
1451
1452 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1453 {
1454 struct mv_port_priv *pp = ap->private_data;
1455 void __iomem *port_mmio;
1456
1457 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1458 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1459 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1460
1461 ltmode = *old_ltmode & ~LTMODE_BIT8;
1462 haltcond = *old_haltcond | EDMA_ERR_DEV;
1463
1464 if (want_fbs) {
1465 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1466 ltmode = *old_ltmode | LTMODE_BIT8;
1467 if (want_ncq)
1468 haltcond &= ~EDMA_ERR_DEV;
1469 else
1470 fiscfg |= FISCFG_WAIT_DEV_ERR;
1471 } else {
1472 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1473 }
1474
1475 port_mmio = mv_ap_base(ap);
1476 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1477 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1478 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
1479 }
1480
1481 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1482 {
1483 struct mv_host_priv *hpriv = ap->host->private_data;
1484 u32 old, new;
1485
1486 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1487 old = readl(hpriv->base + GPIO_PORT_CTL);
1488 if (want_ncq)
1489 new = old | (1 << 22);
1490 else
1491 new = old & ~(1 << 22);
1492 if (new != old)
1493 writel(new, hpriv->base + GPIO_PORT_CTL);
1494 }
1495
1496 /**
1497 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1498 * @ap: Port being initialized
1499 *
1500 * There are two DMA modes on these chips: basic DMA, and EDMA.
1501 *
1502 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1503 * of basic DMA on the GEN_IIE versions of the chips.
1504 *
1505 * This bit survives EDMA resets, and must be set for basic DMA
1506 * to function, and should be cleared when EDMA is active.
1507 */
1508 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1509 {
1510 struct mv_port_priv *pp = ap->private_data;
1511 u32 new, *old = &pp->cached.unknown_rsvd;
1512
1513 if (enable_bmdma)
1514 new = *old | 1;
1515 else
1516 new = *old & ~1;
1517 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
1518 }
1519
1520 /*
1521 * SOC chips have an issue whereby the HDD LEDs don't always blink
1522 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1523 * of the SOC takes care of it, generating a steady blink rate when
1524 * any drive on the chip is active.
1525 *
1526 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1527 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1528 *
1529 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1530 * LED operation works then, and provides better (more accurate) feedback.
1531 *
1532 * Note that this code assumes that an SOC never has more than one HC onboard.
1533 */
1534 static void mv_soc_led_blink_enable(struct ata_port *ap)
1535 {
1536 struct ata_host *host = ap->host;
1537 struct mv_host_priv *hpriv = host->private_data;
1538 void __iomem *hc_mmio;
1539 u32 led_ctrl;
1540
1541 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1542 return;
1543 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1544 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1545 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1546 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1547 }
1548
1549 static void mv_soc_led_blink_disable(struct ata_port *ap)
1550 {
1551 struct ata_host *host = ap->host;
1552 struct mv_host_priv *hpriv = host->private_data;
1553 void __iomem *hc_mmio;
1554 u32 led_ctrl;
1555 unsigned int port;
1556
1557 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1558 return;
1559
1560 /* disable led-blink only if no ports are using NCQ */
1561 for (port = 0; port < hpriv->n_ports; port++) {
1562 struct ata_port *this_ap = host->ports[port];
1563 struct mv_port_priv *pp = this_ap->private_data;
1564
1565 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1566 return;
1567 }
1568
1569 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1570 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1571 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1572 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1573 }
1574
1575 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1576 {
1577 u32 cfg;
1578 struct mv_port_priv *pp = ap->private_data;
1579 struct mv_host_priv *hpriv = ap->host->private_data;
1580 void __iomem *port_mmio = mv_ap_base(ap);
1581
1582 /* set up non-NCQ EDMA configuration */
1583 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1584 pp->pp_flags &=
1585 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1586
1587 if (IS_GEN_I(hpriv))
1588 cfg |= (1 << 8); /* enab config burst size mask */
1589
1590 else if (IS_GEN_II(hpriv)) {
1591 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1592 mv_60x1_errata_sata25(ap, want_ncq);
1593
1594 } else if (IS_GEN_IIE(hpriv)) {
1595 int want_fbs = sata_pmp_attached(ap);
1596 /*
1597 * Possible future enhancement:
1598 *
1599 * The chip can use FBS with non-NCQ, if we allow it,
1600 * But first we need to have the error handling in place
1601 * for this mode (datasheet section 7.3.15.4.2.3).
1602 * So disallow non-NCQ FBS for now.
1603 */
1604 want_fbs &= want_ncq;
1605
1606 mv_config_fbs(ap, want_ncq, want_fbs);
1607
1608 if (want_fbs) {
1609 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1610 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1611 }
1612
1613 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1614 if (want_edma) {
1615 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1616 if (!IS_SOC(hpriv))
1617 cfg |= (1 << 18); /* enab early completion */
1618 }
1619 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1620 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1621 mv_bmdma_enable_iie(ap, !want_edma);
1622
1623 if (IS_SOC(hpriv)) {
1624 if (want_ncq)
1625 mv_soc_led_blink_enable(ap);
1626 else
1627 mv_soc_led_blink_disable(ap);
1628 }
1629 }
1630
1631 if (want_ncq) {
1632 cfg |= EDMA_CFG_NCQ;
1633 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1634 }
1635
1636 writelfl(cfg, port_mmio + EDMA_CFG);
1637 }
1638
1639 static void mv_port_free_dma_mem(struct ata_port *ap)
1640 {
1641 struct mv_host_priv *hpriv = ap->host->private_data;
1642 struct mv_port_priv *pp = ap->private_data;
1643 int tag;
1644
1645 if (pp->crqb) {
1646 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1647 pp->crqb = NULL;
1648 }
1649 if (pp->crpb) {
1650 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1651 pp->crpb = NULL;
1652 }
1653 /*
1654 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1655 * For later hardware, we have one unique sg_tbl per NCQ tag.
1656 */
1657 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1658 if (pp->sg_tbl[tag]) {
1659 if (tag == 0 || !IS_GEN_I(hpriv))
1660 dma_pool_free(hpriv->sg_tbl_pool,
1661 pp->sg_tbl[tag],
1662 pp->sg_tbl_dma[tag]);
1663 pp->sg_tbl[tag] = NULL;
1664 }
1665 }
1666 }
1667
1668 /**
1669 * mv_port_start - Port specific init/start routine.
1670 * @ap: ATA channel to manipulate
1671 *
1672 * Allocate and point to DMA memory, init port private memory,
1673 * zero indices.
1674 *
1675 * LOCKING:
1676 * Inherited from caller.
1677 */
1678 static int mv_port_start(struct ata_port *ap)
1679 {
1680 struct device *dev = ap->host->dev;
1681 struct mv_host_priv *hpriv = ap->host->private_data;
1682 struct mv_port_priv *pp;
1683 unsigned long flags;
1684 int tag;
1685
1686 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1687 if (!pp)
1688 return -ENOMEM;
1689 ap->private_data = pp;
1690
1691 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1692 if (!pp->crqb)
1693 return -ENOMEM;
1694 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1695
1696 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1697 if (!pp->crpb)
1698 goto out_port_free_dma_mem;
1699 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1700
1701 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1702 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1703 ap->flags |= ATA_FLAG_AN;
1704 /*
1705 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1706 * For later hardware, we need one unique sg_tbl per NCQ tag.
1707 */
1708 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1709 if (tag == 0 || !IS_GEN_I(hpriv)) {
1710 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1711 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1712 if (!pp->sg_tbl[tag])
1713 goto out_port_free_dma_mem;
1714 } else {
1715 pp->sg_tbl[tag] = pp->sg_tbl[0];
1716 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1717 }
1718 }
1719
1720 spin_lock_irqsave(ap->lock, flags);
1721 mv_save_cached_regs(ap);
1722 mv_edma_cfg(ap, 0, 0);
1723 spin_unlock_irqrestore(ap->lock, flags);
1724
1725 return 0;
1726
1727 out_port_free_dma_mem:
1728 mv_port_free_dma_mem(ap);
1729 return -ENOMEM;
1730 }
1731
1732 /**
1733 * mv_port_stop - Port specific cleanup/stop routine.
1734 * @ap: ATA channel to manipulate
1735 *
1736 * Stop DMA, cleanup port memory.
1737 *
1738 * LOCKING:
1739 * This routine uses the host lock to protect the DMA stop.
1740 */
1741 static void mv_port_stop(struct ata_port *ap)
1742 {
1743 unsigned long flags;
1744
1745 spin_lock_irqsave(ap->lock, flags);
1746 mv_stop_edma(ap);
1747 mv_enable_port_irqs(ap, 0);
1748 spin_unlock_irqrestore(ap->lock, flags);
1749 mv_port_free_dma_mem(ap);
1750 }
1751
1752 /**
1753 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1754 * @qc: queued command whose SG list to source from
1755 *
1756 * Populate the SG list and mark the last entry.
1757 *
1758 * LOCKING:
1759 * Inherited from caller.
1760 */
1761 static void mv_fill_sg(struct ata_queued_cmd *qc)
1762 {
1763 struct mv_port_priv *pp = qc->ap->private_data;
1764 struct scatterlist *sg;
1765 struct mv_sg *mv_sg, *last_sg = NULL;
1766 unsigned int si;
1767
1768 mv_sg = pp->sg_tbl[qc->tag];
1769 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1770 dma_addr_t addr = sg_dma_address(sg);
1771 u32 sg_len = sg_dma_len(sg);
1772
1773 while (sg_len) {
1774 u32 offset = addr & 0xffff;
1775 u32 len = sg_len;
1776
1777 if (offset + len > 0x10000)
1778 len = 0x10000 - offset;
1779
1780 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1781 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1782 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1783 mv_sg->reserved = 0;
1784
1785 sg_len -= len;
1786 addr += len;
1787
1788 last_sg = mv_sg;
1789 mv_sg++;
1790 }
1791 }
1792
1793 if (likely(last_sg))
1794 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1795 mb(); /* ensure data structure is visible to the chipset */
1796 }
1797
1798 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1799 {
1800 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1801 (last ? CRQB_CMD_LAST : 0);
1802 *cmdw = cpu_to_le16(tmp);
1803 }
1804
1805 /**
1806 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1807 * @ap: Port associated with this ATA transaction.
1808 *
1809 * We need this only for ATAPI bmdma transactions,
1810 * as otherwise we experience spurious interrupts
1811 * after libata-sff handles the bmdma interrupts.
1812 */
1813 static void mv_sff_irq_clear(struct ata_port *ap)
1814 {
1815 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1816 }
1817
1818 /**
1819 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1820 * @qc: queued command to check for chipset/DMA compatibility.
1821 *
1822 * The bmdma engines cannot handle speculative data sizes
1823 * (bytecount under/over flow). So only allow DMA for
1824 * data transfer commands with known data sizes.
1825 *
1826 * LOCKING:
1827 * Inherited from caller.
1828 */
1829 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1830 {
1831 struct scsi_cmnd *scmd = qc->scsicmd;
1832
1833 if (scmd) {
1834 switch (scmd->cmnd[0]) {
1835 case READ_6:
1836 case READ_10:
1837 case READ_12:
1838 case WRITE_6:
1839 case WRITE_10:
1840 case WRITE_12:
1841 case GPCMD_READ_CD:
1842 case GPCMD_SEND_DVD_STRUCTURE:
1843 case GPCMD_SEND_CUE_SHEET:
1844 return 0; /* DMA is safe */
1845 }
1846 }
1847 return -EOPNOTSUPP; /* use PIO instead */
1848 }
1849
1850 /**
1851 * mv_bmdma_setup - Set up BMDMA transaction
1852 * @qc: queued command to prepare DMA for.
1853 *
1854 * LOCKING:
1855 * Inherited from caller.
1856 */
1857 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1858 {
1859 struct ata_port *ap = qc->ap;
1860 void __iomem *port_mmio = mv_ap_base(ap);
1861 struct mv_port_priv *pp = ap->private_data;
1862
1863 mv_fill_sg(qc);
1864
1865 /* clear all DMA cmd bits */
1866 writel(0, port_mmio + BMDMA_CMD);
1867
1868 /* load PRD table addr. */
1869 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1870 port_mmio + BMDMA_PRD_HIGH);
1871 writelfl(pp->sg_tbl_dma[qc->tag],
1872 port_mmio + BMDMA_PRD_LOW);
1873
1874 /* issue r/w command */
1875 ap->ops->sff_exec_command(ap, &qc->tf);
1876 }
1877
1878 /**
1879 * mv_bmdma_start - Start a BMDMA transaction
1880 * @qc: queued command to start DMA on.
1881 *
1882 * LOCKING:
1883 * Inherited from caller.
1884 */
1885 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1886 {
1887 struct ata_port *ap = qc->ap;
1888 void __iomem *port_mmio = mv_ap_base(ap);
1889 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1890 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1891
1892 /* start host DMA transaction */
1893 writelfl(cmd, port_mmio + BMDMA_CMD);
1894 }
1895
1896 /**
1897 * mv_bmdma_stop - Stop BMDMA transfer
1898 * @qc: queued command to stop DMA on.
1899 *
1900 * Clears the ATA_DMA_START flag in the bmdma control register
1901 *
1902 * LOCKING:
1903 * Inherited from caller.
1904 */
1905 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1906 {
1907 struct ata_port *ap = qc->ap;
1908 void __iomem *port_mmio = mv_ap_base(ap);
1909 u32 cmd;
1910
1911 /* clear start/stop bit */
1912 cmd = readl(port_mmio + BMDMA_CMD);
1913 cmd &= ~ATA_DMA_START;
1914 writelfl(cmd, port_mmio + BMDMA_CMD);
1915
1916 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1917 ata_sff_dma_pause(ap);
1918 }
1919
1920 /**
1921 * mv_bmdma_status - Read BMDMA status
1922 * @ap: port for which to retrieve DMA status.
1923 *
1924 * Read and return equivalent of the sff BMDMA status register.
1925 *
1926 * LOCKING:
1927 * Inherited from caller.
1928 */
1929 static u8 mv_bmdma_status(struct ata_port *ap)
1930 {
1931 void __iomem *port_mmio = mv_ap_base(ap);
1932 u32 reg, status;
1933
1934 /*
1935 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1936 * and the ATA_DMA_INTR bit doesn't exist.
1937 */
1938 reg = readl(port_mmio + BMDMA_STATUS);
1939 if (reg & ATA_DMA_ACTIVE)
1940 status = ATA_DMA_ACTIVE;
1941 else
1942 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1943 return status;
1944 }
1945
1946 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1947 {
1948 struct ata_taskfile *tf = &qc->tf;
1949 /*
1950 * Workaround for 88SX60x1 FEr SATA#24.
1951 *
1952 * Chip may corrupt WRITEs if multi_count >= 4kB.
1953 * Note that READs are unaffected.
1954 *
1955 * It's not clear if this errata really means "4K bytes",
1956 * or if it always happens for multi_count > 7
1957 * regardless of device sector_size.
1958 *
1959 * So, for safety, any write with multi_count > 7
1960 * gets converted here into a regular PIO write instead:
1961 */
1962 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1963 if (qc->dev->multi_count > 7) {
1964 switch (tf->command) {
1965 case ATA_CMD_WRITE_MULTI:
1966 tf->command = ATA_CMD_PIO_WRITE;
1967 break;
1968 case ATA_CMD_WRITE_MULTI_FUA_EXT:
1969 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1970 /* fall through */
1971 case ATA_CMD_WRITE_MULTI_EXT:
1972 tf->command = ATA_CMD_PIO_WRITE_EXT;
1973 break;
1974 }
1975 }
1976 }
1977 }
1978
1979 /**
1980 * mv_qc_prep - Host specific command preparation.
1981 * @qc: queued command to prepare
1982 *
1983 * This routine simply redirects to the general purpose routine
1984 * if command is not DMA. Else, it handles prep of the CRQB
1985 * (command request block), does some sanity checking, and calls
1986 * the SG load routine.
1987 *
1988 * LOCKING:
1989 * Inherited from caller.
1990 */
1991 static void mv_qc_prep(struct ata_queued_cmd *qc)
1992 {
1993 struct ata_port *ap = qc->ap;
1994 struct mv_port_priv *pp = ap->private_data;
1995 __le16 *cw;
1996 struct ata_taskfile *tf = &qc->tf;
1997 u16 flags = 0;
1998 unsigned in_index;
1999
2000 switch (tf->protocol) {
2001 case ATA_PROT_DMA:
2002 case ATA_PROT_NCQ:
2003 break; /* continue below */
2004 case ATA_PROT_PIO:
2005 mv_rw_multi_errata_sata24(qc);
2006 return;
2007 default:
2008 return;
2009 }
2010
2011 /* Fill in command request block
2012 */
2013 if (!(tf->flags & ATA_TFLAG_WRITE))
2014 flags |= CRQB_FLAG_READ;
2015 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2016 flags |= qc->tag << CRQB_TAG_SHIFT;
2017 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2018
2019 /* get current queue index from software */
2020 in_index = pp->req_idx;
2021
2022 pp->crqb[in_index].sg_addr =
2023 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2024 pp->crqb[in_index].sg_addr_hi =
2025 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2026 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2027
2028 cw = &pp->crqb[in_index].ata_cmd[0];
2029
2030 /* Sadly, the CRQB cannot accomodate all registers--there are
2031 * only 11 bytes...so we must pick and choose required
2032 * registers based on the command. So, we drop feature and
2033 * hob_feature for [RW] DMA commands, but they are needed for
2034 * NCQ. NCQ will drop hob_nsect, which is not needed there
2035 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
2036 */
2037 switch (tf->command) {
2038 case ATA_CMD_READ:
2039 case ATA_CMD_READ_EXT:
2040 case ATA_CMD_WRITE:
2041 case ATA_CMD_WRITE_EXT:
2042 case ATA_CMD_WRITE_FUA_EXT:
2043 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2044 break;
2045 case ATA_CMD_FPDMA_READ:
2046 case ATA_CMD_FPDMA_WRITE:
2047 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
2048 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2049 break;
2050 default:
2051 /* The only other commands EDMA supports in non-queued and
2052 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2053 * of which are defined/used by Linux. If we get here, this
2054 * driver needs work.
2055 *
2056 * FIXME: modify libata to give qc_prep a return value and
2057 * return error here.
2058 */
2059 BUG_ON(tf->command);
2060 break;
2061 }
2062 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2063 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2064 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2065 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2066 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2067 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2068 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2069 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2070 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2071
2072 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2073 return;
2074 mv_fill_sg(qc);
2075 }
2076
2077 /**
2078 * mv_qc_prep_iie - Host specific command preparation.
2079 * @qc: queued command to prepare
2080 *
2081 * This routine simply redirects to the general purpose routine
2082 * if command is not DMA. Else, it handles prep of the CRQB
2083 * (command request block), does some sanity checking, and calls
2084 * the SG load routine.
2085 *
2086 * LOCKING:
2087 * Inherited from caller.
2088 */
2089 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2090 {
2091 struct ata_port *ap = qc->ap;
2092 struct mv_port_priv *pp = ap->private_data;
2093 struct mv_crqb_iie *crqb;
2094 struct ata_taskfile *tf = &qc->tf;
2095 unsigned in_index;
2096 u32 flags = 0;
2097
2098 if ((tf->protocol != ATA_PROT_DMA) &&
2099 (tf->protocol != ATA_PROT_NCQ))
2100 return;
2101
2102 /* Fill in Gen IIE command request block */
2103 if (!(tf->flags & ATA_TFLAG_WRITE))
2104 flags |= CRQB_FLAG_READ;
2105
2106 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2107 flags |= qc->tag << CRQB_TAG_SHIFT;
2108 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
2109 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2110
2111 /* get current queue index from software */
2112 in_index = pp->req_idx;
2113
2114 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2115 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2116 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2117 crqb->flags = cpu_to_le32(flags);
2118
2119 crqb->ata_cmd[0] = cpu_to_le32(
2120 (tf->command << 16) |
2121 (tf->feature << 24)
2122 );
2123 crqb->ata_cmd[1] = cpu_to_le32(
2124 (tf->lbal << 0) |
2125 (tf->lbam << 8) |
2126 (tf->lbah << 16) |
2127 (tf->device << 24)
2128 );
2129 crqb->ata_cmd[2] = cpu_to_le32(
2130 (tf->hob_lbal << 0) |
2131 (tf->hob_lbam << 8) |
2132 (tf->hob_lbah << 16) |
2133 (tf->hob_feature << 24)
2134 );
2135 crqb->ata_cmd[3] = cpu_to_le32(
2136 (tf->nsect << 0) |
2137 (tf->hob_nsect << 8)
2138 );
2139
2140 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2141 return;
2142 mv_fill_sg(qc);
2143 }
2144
2145 /**
2146 * mv_sff_check_status - fetch device status, if valid
2147 * @ap: ATA port to fetch status from
2148 *
2149 * When using command issue via mv_qc_issue_fis(),
2150 * the initial ATA_BUSY state does not show up in the
2151 * ATA status (shadow) register. This can confuse libata!
2152 *
2153 * So we have a hook here to fake ATA_BUSY for that situation,
2154 * until the first time a BUSY, DRQ, or ERR bit is seen.
2155 *
2156 * The rest of the time, it simply returns the ATA status register.
2157 */
2158 static u8 mv_sff_check_status(struct ata_port *ap)
2159 {
2160 u8 stat = ioread8(ap->ioaddr.status_addr);
2161 struct mv_port_priv *pp = ap->private_data;
2162
2163 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2164 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2165 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2166 else
2167 stat = ATA_BUSY;
2168 }
2169 return stat;
2170 }
2171
2172 /**
2173 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2174 * @fis: fis to be sent
2175 * @nwords: number of 32-bit words in the fis
2176 */
2177 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2178 {
2179 void __iomem *port_mmio = mv_ap_base(ap);
2180 u32 ifctl, old_ifctl, ifstat;
2181 int i, timeout = 200, final_word = nwords - 1;
2182
2183 /* Initiate FIS transmission mode */
2184 old_ifctl = readl(port_mmio + SATA_IFCTL);
2185 ifctl = 0x100 | (old_ifctl & 0xf);
2186 writelfl(ifctl, port_mmio + SATA_IFCTL);
2187
2188 /* Send all words of the FIS except for the final word */
2189 for (i = 0; i < final_word; ++i)
2190 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
2191
2192 /* Flag end-of-transmission, and then send the final word */
2193 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2194 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
2195
2196 /*
2197 * Wait for FIS transmission to complete.
2198 * This typically takes just a single iteration.
2199 */
2200 do {
2201 ifstat = readl(port_mmio + SATA_IFSTAT);
2202 } while (!(ifstat & 0x1000) && --timeout);
2203
2204 /* Restore original port configuration */
2205 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
2206
2207 /* See if it worked */
2208 if ((ifstat & 0x3000) != 0x1000) {
2209 ata_port_printk(ap, KERN_WARNING,
2210 "%s transmission error, ifstat=%08x\n",
2211 __func__, ifstat);
2212 return AC_ERR_OTHER;
2213 }
2214 return 0;
2215 }
2216
2217 /**
2218 * mv_qc_issue_fis - Issue a command directly as a FIS
2219 * @qc: queued command to start
2220 *
2221 * Note that the ATA shadow registers are not updated
2222 * after command issue, so the device will appear "READY"
2223 * if polled, even while it is BUSY processing the command.
2224 *
2225 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2226 *
2227 * Note: we don't get updated shadow regs on *completion*
2228 * of non-data commands. So avoid sending them via this function,
2229 * as they will appear to have completed immediately.
2230 *
2231 * GEN_IIE has special registers that we could get the result tf from,
2232 * but earlier chipsets do not. For now, we ignore those registers.
2233 */
2234 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2235 {
2236 struct ata_port *ap = qc->ap;
2237 struct mv_port_priv *pp = ap->private_data;
2238 struct ata_link *link = qc->dev->link;
2239 u32 fis[5];
2240 int err = 0;
2241
2242 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2243 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
2244 if (err)
2245 return err;
2246
2247 switch (qc->tf.protocol) {
2248 case ATAPI_PROT_PIO:
2249 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2250 /* fall through */
2251 case ATAPI_PROT_NODATA:
2252 ap->hsm_task_state = HSM_ST_FIRST;
2253 break;
2254 case ATA_PROT_PIO:
2255 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2256 if (qc->tf.flags & ATA_TFLAG_WRITE)
2257 ap->hsm_task_state = HSM_ST_FIRST;
2258 else
2259 ap->hsm_task_state = HSM_ST;
2260 break;
2261 default:
2262 ap->hsm_task_state = HSM_ST_LAST;
2263 break;
2264 }
2265
2266 if (qc->tf.flags & ATA_TFLAG_POLLING)
2267 ata_pio_queue_task(ap, qc, 0);
2268 return 0;
2269 }
2270
2271 /**
2272 * mv_qc_issue - Initiate a command to the host
2273 * @qc: queued command to start
2274 *
2275 * This routine simply redirects to the general purpose routine
2276 * if command is not DMA. Else, it sanity checks our local
2277 * caches of the request producer/consumer indices then enables
2278 * DMA and bumps the request producer index.
2279 *
2280 * LOCKING:
2281 * Inherited from caller.
2282 */
2283 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2284 {
2285 static int limit_warnings = 10;
2286 struct ata_port *ap = qc->ap;
2287 void __iomem *port_mmio = mv_ap_base(ap);
2288 struct mv_port_priv *pp = ap->private_data;
2289 u32 in_index;
2290 unsigned int port_irqs;
2291
2292 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2293
2294 switch (qc->tf.protocol) {
2295 case ATA_PROT_DMA:
2296 case ATA_PROT_NCQ:
2297 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2298 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2299 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2300
2301 /* Write the request in pointer to kick the EDMA to life */
2302 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2303 port_mmio + EDMA_REQ_Q_IN_PTR);
2304 return 0;
2305
2306 case ATA_PROT_PIO:
2307 /*
2308 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2309 *
2310 * Someday, we might implement special polling workarounds
2311 * for these, but it all seems rather unnecessary since we
2312 * normally use only DMA for commands which transfer more
2313 * than a single block of data.
2314 *
2315 * Much of the time, this could just work regardless.
2316 * So for now, just log the incident, and allow the attempt.
2317 */
2318 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2319 --limit_warnings;
2320 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2321 ": attempting PIO w/multiple DRQ: "
2322 "this may fail due to h/w errata\n");
2323 }
2324 /* drop through */
2325 case ATA_PROT_NODATA:
2326 case ATAPI_PROT_PIO:
2327 case ATAPI_PROT_NODATA:
2328 if (ap->flags & ATA_FLAG_PIO_POLLING)
2329 qc->tf.flags |= ATA_TFLAG_POLLING;
2330 break;
2331 }
2332
2333 if (qc->tf.flags & ATA_TFLAG_POLLING)
2334 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2335 else
2336 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2337
2338 /*
2339 * We're about to send a non-EDMA capable command to the
2340 * port. Turn off EDMA so there won't be problems accessing
2341 * shadow block, etc registers.
2342 */
2343 mv_stop_edma(ap);
2344 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2345 mv_pmp_select(ap, qc->dev->link->pmp);
2346
2347 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2348 struct mv_host_priv *hpriv = ap->host->private_data;
2349 /*
2350 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2351 *
2352 * After any NCQ error, the READ_LOG_EXT command
2353 * from libata-eh *must* use mv_qc_issue_fis().
2354 * Otherwise it might fail, due to chip errata.
2355 *
2356 * Rather than special-case it, we'll just *always*
2357 * use this method here for READ_LOG_EXT, making for
2358 * easier testing.
2359 */
2360 if (IS_GEN_II(hpriv))
2361 return mv_qc_issue_fis(qc);
2362 }
2363 return ata_sff_qc_issue(qc);
2364 }
2365
2366 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2367 {
2368 struct mv_port_priv *pp = ap->private_data;
2369 struct ata_queued_cmd *qc;
2370
2371 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2372 return NULL;
2373 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2374 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2375 return qc;
2376 return NULL;
2377 }
2378
2379 static void mv_pmp_error_handler(struct ata_port *ap)
2380 {
2381 unsigned int pmp, pmp_map;
2382 struct mv_port_priv *pp = ap->private_data;
2383
2384 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2385 /*
2386 * Perform NCQ error analysis on failed PMPs
2387 * before we freeze the port entirely.
2388 *
2389 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2390 */
2391 pmp_map = pp->delayed_eh_pmp_map;
2392 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2393 for (pmp = 0; pmp_map != 0; pmp++) {
2394 unsigned int this_pmp = (1 << pmp);
2395 if (pmp_map & this_pmp) {
2396 struct ata_link *link = &ap->pmp_link[pmp];
2397 pmp_map &= ~this_pmp;
2398 ata_eh_analyze_ncq_error(link);
2399 }
2400 }
2401 ata_port_freeze(ap);
2402 }
2403 sata_pmp_error_handler(ap);
2404 }
2405
2406 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2407 {
2408 void __iomem *port_mmio = mv_ap_base(ap);
2409
2410 return readl(port_mmio + SATA_TESTCTL) >> 16;
2411 }
2412
2413 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2414 {
2415 struct ata_eh_info *ehi;
2416 unsigned int pmp;
2417
2418 /*
2419 * Initialize EH info for PMPs which saw device errors
2420 */
2421 ehi = &ap->link.eh_info;
2422 for (pmp = 0; pmp_map != 0; pmp++) {
2423 unsigned int this_pmp = (1 << pmp);
2424 if (pmp_map & this_pmp) {
2425 struct ata_link *link = &ap->pmp_link[pmp];
2426
2427 pmp_map &= ~this_pmp;
2428 ehi = &link->eh_info;
2429 ata_ehi_clear_desc(ehi);
2430 ata_ehi_push_desc(ehi, "dev err");
2431 ehi->err_mask |= AC_ERR_DEV;
2432 ehi->action |= ATA_EH_RESET;
2433 ata_link_abort(link);
2434 }
2435 }
2436 }
2437
2438 static int mv_req_q_empty(struct ata_port *ap)
2439 {
2440 void __iomem *port_mmio = mv_ap_base(ap);
2441 u32 in_ptr, out_ptr;
2442
2443 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
2444 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2445 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
2446 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2447 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2448 }
2449
2450 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2451 {
2452 struct mv_port_priv *pp = ap->private_data;
2453 int failed_links;
2454 unsigned int old_map, new_map;
2455
2456 /*
2457 * Device error during FBS+NCQ operation:
2458 *
2459 * Set a port flag to prevent further I/O being enqueued.
2460 * Leave the EDMA running to drain outstanding commands from this port.
2461 * Perform the post-mortem/EH only when all responses are complete.
2462 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2463 */
2464 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2465 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2466 pp->delayed_eh_pmp_map = 0;
2467 }
2468 old_map = pp->delayed_eh_pmp_map;
2469 new_map = old_map | mv_get_err_pmp_map(ap);
2470
2471 if (old_map != new_map) {
2472 pp->delayed_eh_pmp_map = new_map;
2473 mv_pmp_eh_prep(ap, new_map & ~old_map);
2474 }
2475 failed_links = hweight16(new_map);
2476
2477 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2478 "failed_links=%d nr_active_links=%d\n",
2479 __func__, pp->delayed_eh_pmp_map,
2480 ap->qc_active, failed_links,
2481 ap->nr_active_links);
2482
2483 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2484 mv_process_crpb_entries(ap, pp);
2485 mv_stop_edma(ap);
2486 mv_eh_freeze(ap);
2487 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2488 return 1; /* handled */
2489 }
2490 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2491 return 1; /* handled */
2492 }
2493
2494 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2495 {
2496 /*
2497 * Possible future enhancement:
2498 *
2499 * FBS+non-NCQ operation is not yet implemented.
2500 * See related notes in mv_edma_cfg().
2501 *
2502 * Device error during FBS+non-NCQ operation:
2503 *
2504 * We need to snapshot the shadow registers for each failed command.
2505 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2506 */
2507 return 0; /* not handled */
2508 }
2509
2510 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2511 {
2512 struct mv_port_priv *pp = ap->private_data;
2513
2514 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2515 return 0; /* EDMA was not active: not handled */
2516 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2517 return 0; /* FBS was not active: not handled */
2518
2519 if (!(edma_err_cause & EDMA_ERR_DEV))
2520 return 0; /* non DEV error: not handled */
2521 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2522 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2523 return 0; /* other problems: not handled */
2524
2525 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2526 /*
2527 * EDMA should NOT have self-disabled for this case.
2528 * If it did, then something is wrong elsewhere,
2529 * and we cannot handle it here.
2530 */
2531 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2532 ata_port_printk(ap, KERN_WARNING,
2533 "%s: err_cause=0x%x pp_flags=0x%x\n",
2534 __func__, edma_err_cause, pp->pp_flags);
2535 return 0; /* not handled */
2536 }
2537 return mv_handle_fbs_ncq_dev_err(ap);
2538 } else {
2539 /*
2540 * EDMA should have self-disabled for this case.
2541 * If it did not, then something is wrong elsewhere,
2542 * and we cannot handle it here.
2543 */
2544 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2545 ata_port_printk(ap, KERN_WARNING,
2546 "%s: err_cause=0x%x pp_flags=0x%x\n",
2547 __func__, edma_err_cause, pp->pp_flags);
2548 return 0; /* not handled */
2549 }
2550 return mv_handle_fbs_non_ncq_dev_err(ap);
2551 }
2552 return 0; /* not handled */
2553 }
2554
2555 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2556 {
2557 struct ata_eh_info *ehi = &ap->link.eh_info;
2558 char *when = "idle";
2559
2560 ata_ehi_clear_desc(ehi);
2561 if (edma_was_enabled) {
2562 when = "EDMA enabled";
2563 } else {
2564 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2565 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2566 when = "polling";
2567 }
2568 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2569 ehi->err_mask |= AC_ERR_OTHER;
2570 ehi->action |= ATA_EH_RESET;
2571 ata_port_freeze(ap);
2572 }
2573
2574 /**
2575 * mv_err_intr - Handle error interrupts on the port
2576 * @ap: ATA channel to manipulate
2577 *
2578 * Most cases require a full reset of the chip's state machine,
2579 * which also performs a COMRESET.
2580 * Also, if the port disabled DMA, update our cached copy to match.
2581 *
2582 * LOCKING:
2583 * Inherited from caller.
2584 */
2585 static void mv_err_intr(struct ata_port *ap)
2586 {
2587 void __iomem *port_mmio = mv_ap_base(ap);
2588 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2589 u32 fis_cause = 0;
2590 struct mv_port_priv *pp = ap->private_data;
2591 struct mv_host_priv *hpriv = ap->host->private_data;
2592 unsigned int action = 0, err_mask = 0;
2593 struct ata_eh_info *ehi = &ap->link.eh_info;
2594 struct ata_queued_cmd *qc;
2595 int abort = 0;
2596
2597 /*
2598 * Read and clear the SError and err_cause bits.
2599 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2600 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2601 */
2602 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2603 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2604
2605 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
2606 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2607 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2608 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
2609 }
2610 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
2611
2612 if (edma_err_cause & EDMA_ERR_DEV) {
2613 /*
2614 * Device errors during FIS-based switching operation
2615 * require special handling.
2616 */
2617 if (mv_handle_dev_err(ap, edma_err_cause))
2618 return;
2619 }
2620
2621 qc = mv_get_active_qc(ap);
2622 ata_ehi_clear_desc(ehi);
2623 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2624 edma_err_cause, pp->pp_flags);
2625
2626 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2627 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2628 if (fis_cause & FIS_IRQ_CAUSE_AN) {
2629 u32 ec = edma_err_cause &
2630 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2631 sata_async_notification(ap);
2632 if (!ec)
2633 return; /* Just an AN; no need for the nukes */
2634 ata_ehi_push_desc(ehi, "SDB notify");
2635 }
2636 }
2637 /*
2638 * All generations share these EDMA error cause bits:
2639 */
2640 if (edma_err_cause & EDMA_ERR_DEV) {
2641 err_mask |= AC_ERR_DEV;
2642 action |= ATA_EH_RESET;
2643 ata_ehi_push_desc(ehi, "dev error");
2644 }
2645 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2646 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2647 EDMA_ERR_INTRL_PAR)) {
2648 err_mask |= AC_ERR_ATA_BUS;
2649 action |= ATA_EH_RESET;
2650 ata_ehi_push_desc(ehi, "parity error");
2651 }
2652 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2653 ata_ehi_hotplugged(ehi);
2654 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2655 "dev disconnect" : "dev connect");
2656 action |= ATA_EH_RESET;
2657 }
2658
2659 /*
2660 * Gen-I has a different SELF_DIS bit,
2661 * different FREEZE bits, and no SERR bit:
2662 */
2663 if (IS_GEN_I(hpriv)) {
2664 eh_freeze_mask = EDMA_EH_FREEZE_5;
2665 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2666 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2667 ata_ehi_push_desc(ehi, "EDMA self-disable");
2668 }
2669 } else {
2670 eh_freeze_mask = EDMA_EH_FREEZE;
2671 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2672 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2673 ata_ehi_push_desc(ehi, "EDMA self-disable");
2674 }
2675 if (edma_err_cause & EDMA_ERR_SERR) {
2676 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2677 err_mask |= AC_ERR_ATA_BUS;
2678 action |= ATA_EH_RESET;
2679 }
2680 }
2681
2682 if (!err_mask) {
2683 err_mask = AC_ERR_OTHER;
2684 action |= ATA_EH_RESET;
2685 }
2686
2687 ehi->serror |= serr;
2688 ehi->action |= action;
2689
2690 if (qc)
2691 qc->err_mask |= err_mask;
2692 else
2693 ehi->err_mask |= err_mask;
2694
2695 if (err_mask == AC_ERR_DEV) {
2696 /*
2697 * Cannot do ata_port_freeze() here,
2698 * because it would kill PIO access,
2699 * which is needed for further diagnosis.
2700 */
2701 mv_eh_freeze(ap);
2702 abort = 1;
2703 } else if (edma_err_cause & eh_freeze_mask) {
2704 /*
2705 * Note to self: ata_port_freeze() calls ata_port_abort()
2706 */
2707 ata_port_freeze(ap);
2708 } else {
2709 abort = 1;
2710 }
2711
2712 if (abort) {
2713 if (qc)
2714 ata_link_abort(qc->dev->link);
2715 else
2716 ata_port_abort(ap);
2717 }
2718 }
2719
2720 static void mv_process_crpb_response(struct ata_port *ap,
2721 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2722 {
2723 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2724
2725 if (qc) {
2726 u8 ata_status;
2727 u16 edma_status = le16_to_cpu(response->flags);
2728 /*
2729 * edma_status from a response queue entry:
2730 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2731 * MSB is saved ATA status from command completion.
2732 */
2733 if (!ncq_enabled) {
2734 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2735 if (err_cause) {
2736 /*
2737 * Error will be seen/handled by mv_err_intr().
2738 * So do nothing at all here.
2739 */
2740 return;
2741 }
2742 }
2743 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2744 if (!ac_err_mask(ata_status))
2745 ata_qc_complete(qc);
2746 /* else: leave it for mv_err_intr() */
2747 } else {
2748 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2749 __func__, tag);
2750 }
2751 }
2752
2753 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2754 {
2755 void __iomem *port_mmio = mv_ap_base(ap);
2756 struct mv_host_priv *hpriv = ap->host->private_data;
2757 u32 in_index;
2758 bool work_done = false;
2759 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2760
2761 /* Get the hardware queue position index */
2762 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
2763 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2764
2765 /* Process new responses from since the last time we looked */
2766 while (in_index != pp->resp_idx) {
2767 unsigned int tag;
2768 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2769
2770 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2771
2772 if (IS_GEN_I(hpriv)) {
2773 /* 50xx: no NCQ, only one command active at a time */
2774 tag = ap->link.active_tag;
2775 } else {
2776 /* Gen II/IIE: get command tag from CRPB entry */
2777 tag = le16_to_cpu(response->id) & 0x1f;
2778 }
2779 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2780 work_done = true;
2781 }
2782
2783 /* Update the software queue position index in hardware */
2784 if (work_done)
2785 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2786 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2787 port_mmio + EDMA_RSP_Q_OUT_PTR);
2788 }
2789
2790 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2791 {
2792 struct mv_port_priv *pp;
2793 int edma_was_enabled;
2794
2795 /*
2796 * Grab a snapshot of the EDMA_EN flag setting,
2797 * so that we have a consistent view for this port,
2798 * even if something we call of our routines changes it.
2799 */
2800 pp = ap->private_data;
2801 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2802 /*
2803 * Process completed CRPB response(s) before other events.
2804 */
2805 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2806 mv_process_crpb_entries(ap, pp);
2807 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2808 mv_handle_fbs_ncq_dev_err(ap);
2809 }
2810 /*
2811 * Handle chip-reported errors, or continue on to handle PIO.
2812 */
2813 if (unlikely(port_cause & ERR_IRQ)) {
2814 mv_err_intr(ap);
2815 } else if (!edma_was_enabled) {
2816 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2817 if (qc)
2818 ata_sff_host_intr(ap, qc);
2819 else
2820 mv_unexpected_intr(ap, edma_was_enabled);
2821 }
2822 }
2823
2824 /**
2825 * mv_host_intr - Handle all interrupts on the given host controller
2826 * @host: host specific structure
2827 * @main_irq_cause: Main interrupt cause register for the chip.
2828 *
2829 * LOCKING:
2830 * Inherited from caller.
2831 */
2832 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2833 {
2834 struct mv_host_priv *hpriv = host->private_data;
2835 void __iomem *mmio = hpriv->base, *hc_mmio;
2836 unsigned int handled = 0, port;
2837
2838 /* If asserted, clear the "all ports" IRQ coalescing bit */
2839 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2840 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2841
2842 for (port = 0; port < hpriv->n_ports; port++) {
2843 struct ata_port *ap = host->ports[port];
2844 unsigned int p, shift, hardport, port_cause;
2845
2846 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2847 /*
2848 * Each hc within the host has its own hc_irq_cause register,
2849 * where the interrupting ports bits get ack'd.
2850 */
2851 if (hardport == 0) { /* first port on this hc ? */
2852 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2853 u32 port_mask, ack_irqs;
2854 /*
2855 * Skip this entire hc if nothing pending for any ports
2856 */
2857 if (!hc_cause) {
2858 port += MV_PORTS_PER_HC - 1;
2859 continue;
2860 }
2861 /*
2862 * We don't need/want to read the hc_irq_cause register,
2863 * because doing so hurts performance, and
2864 * main_irq_cause already gives us everything we need.
2865 *
2866 * But we do have to *write* to the hc_irq_cause to ack
2867 * the ports that we are handling this time through.
2868 *
2869 * This requires that we create a bitmap for those
2870 * ports which interrupted us, and use that bitmap
2871 * to ack (only) those ports via hc_irq_cause.
2872 */
2873 ack_irqs = 0;
2874 if (hc_cause & PORTS_0_3_COAL_DONE)
2875 ack_irqs = HC_COAL_IRQ;
2876 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2877 if ((port + p) >= hpriv->n_ports)
2878 break;
2879 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2880 if (hc_cause & port_mask)
2881 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2882 }
2883 hc_mmio = mv_hc_base_from_port(mmio, port);
2884 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
2885 handled = 1;
2886 }
2887 /*
2888 * Handle interrupts signalled for this port:
2889 */
2890 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2891 if (port_cause)
2892 mv_port_intr(ap, port_cause);
2893 }
2894 return handled;
2895 }
2896
2897 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2898 {
2899 struct mv_host_priv *hpriv = host->private_data;
2900 struct ata_port *ap;
2901 struct ata_queued_cmd *qc;
2902 struct ata_eh_info *ehi;
2903 unsigned int i, err_mask, printed = 0;
2904 u32 err_cause;
2905
2906 err_cause = readl(mmio + hpriv->irq_cause_offset);
2907
2908 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2909 err_cause);
2910
2911 DPRINTK("All regs @ PCI error\n");
2912 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2913
2914 writelfl(0, mmio + hpriv->irq_cause_offset);
2915
2916 for (i = 0; i < host->n_ports; i++) {
2917 ap = host->ports[i];
2918 if (!ata_link_offline(&ap->link)) {
2919 ehi = &ap->link.eh_info;
2920 ata_ehi_clear_desc(ehi);
2921 if (!printed++)
2922 ata_ehi_push_desc(ehi,
2923 "PCI err cause 0x%08x", err_cause);
2924 err_mask = AC_ERR_HOST_BUS;
2925 ehi->action = ATA_EH_RESET;
2926 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2927 if (qc)
2928 qc->err_mask |= err_mask;
2929 else
2930 ehi->err_mask |= err_mask;
2931
2932 ata_port_freeze(ap);
2933 }
2934 }
2935 return 1; /* handled */
2936 }
2937
2938 /**
2939 * mv_interrupt - Main interrupt event handler
2940 * @irq: unused
2941 * @dev_instance: private data; in this case the host structure
2942 *
2943 * Read the read only register to determine if any host
2944 * controllers have pending interrupts. If so, call lower level
2945 * routine to handle. Also check for PCI errors which are only
2946 * reported here.
2947 *
2948 * LOCKING:
2949 * This routine holds the host lock while processing pending
2950 * interrupts.
2951 */
2952 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2953 {
2954 struct ata_host *host = dev_instance;
2955 struct mv_host_priv *hpriv = host->private_data;
2956 unsigned int handled = 0;
2957 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2958 u32 main_irq_cause, pending_irqs;
2959
2960 spin_lock(&host->lock);
2961
2962 /* for MSI: block new interrupts while in here */
2963 if (using_msi)
2964 mv_write_main_irq_mask(0, hpriv);
2965
2966 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2967 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2968 /*
2969 * Deal with cases where we either have nothing pending, or have read
2970 * a bogus register value which can indicate HW removal or PCI fault.
2971 */
2972 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2973 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2974 handled = mv_pci_error(host, hpriv->base);
2975 else
2976 handled = mv_host_intr(host, pending_irqs);
2977 }
2978
2979 /* for MSI: unmask; interrupt cause bits will retrigger now */
2980 if (using_msi)
2981 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
2982
2983 spin_unlock(&host->lock);
2984
2985 return IRQ_RETVAL(handled);
2986 }
2987
2988 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2989 {
2990 unsigned int ofs;
2991
2992 switch (sc_reg_in) {
2993 case SCR_STATUS:
2994 case SCR_ERROR:
2995 case SCR_CONTROL:
2996 ofs = sc_reg_in * sizeof(u32);
2997 break;
2998 default:
2999 ofs = 0xffffffffU;
3000 break;
3001 }
3002 return ofs;
3003 }
3004
3005 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
3006 {
3007 struct mv_host_priv *hpriv = link->ap->host->private_data;
3008 void __iomem *mmio = hpriv->base;
3009 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3010 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3011
3012 if (ofs != 0xffffffffU) {
3013 *val = readl(addr + ofs);
3014 return 0;
3015 } else
3016 return -EINVAL;
3017 }
3018
3019 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
3020 {
3021 struct mv_host_priv *hpriv = link->ap->host->private_data;
3022 void __iomem *mmio = hpriv->base;
3023 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3024 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3025
3026 if (ofs != 0xffffffffU) {
3027 writelfl(val, addr + ofs);
3028 return 0;
3029 } else
3030 return -EINVAL;
3031 }
3032
3033 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
3034 {
3035 struct pci_dev *pdev = to_pci_dev(host->dev);
3036 int early_5080;
3037
3038 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
3039
3040 if (!early_5080) {
3041 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3042 tmp |= (1 << 0);
3043 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3044 }
3045
3046 mv_reset_pci_bus(host, mmio);
3047 }
3048
3049 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3050 {
3051 writel(0x0fcfffff, mmio + FLASH_CTL);
3052 }
3053
3054 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
3055 void __iomem *mmio)
3056 {
3057 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3058 u32 tmp;
3059
3060 tmp = readl(phy_mmio + MV5_PHY_MODE);
3061
3062 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3063 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3064 }
3065
3066 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3067 {
3068 u32 tmp;
3069
3070 writel(0, mmio + GPIO_PORT_CTL);
3071
3072 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3073
3074 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3075 tmp |= ~(1 << 0);
3076 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3077 }
3078
3079 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3080 unsigned int port)
3081 {
3082 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3083 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3084 u32 tmp;
3085 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3086
3087 if (fix_apm_sq) {
3088 tmp = readl(phy_mmio + MV5_LTMODE);
3089 tmp |= (1 << 19);
3090 writel(tmp, phy_mmio + MV5_LTMODE);
3091
3092 tmp = readl(phy_mmio + MV5_PHY_CTL);
3093 tmp &= ~0x3;
3094 tmp |= 0x1;
3095 writel(tmp, phy_mmio + MV5_PHY_CTL);
3096 }
3097
3098 tmp = readl(phy_mmio + MV5_PHY_MODE);
3099 tmp &= ~mask;
3100 tmp |= hpriv->signal[port].pre;
3101 tmp |= hpriv->signal[port].amps;
3102 writel(tmp, phy_mmio + MV5_PHY_MODE);
3103 }
3104
3105
3106 #undef ZERO
3107 #define ZERO(reg) writel(0, port_mmio + (reg))
3108 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3109 unsigned int port)
3110 {
3111 void __iomem *port_mmio = mv_port_base(mmio, port);
3112
3113 mv_reset_channel(hpriv, mmio, port);
3114
3115 ZERO(0x028); /* command */
3116 writel(0x11f, port_mmio + EDMA_CFG);
3117 ZERO(0x004); /* timer */
3118 ZERO(0x008); /* irq err cause */
3119 ZERO(0x00c); /* irq err mask */
3120 ZERO(0x010); /* rq bah */
3121 ZERO(0x014); /* rq inp */
3122 ZERO(0x018); /* rq outp */
3123 ZERO(0x01c); /* respq bah */
3124 ZERO(0x024); /* respq outp */
3125 ZERO(0x020); /* respq inp */
3126 ZERO(0x02c); /* test control */
3127 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
3128 }
3129 #undef ZERO
3130
3131 #define ZERO(reg) writel(0, hc_mmio + (reg))
3132 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3133 unsigned int hc)
3134 {
3135 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3136 u32 tmp;
3137
3138 ZERO(0x00c);
3139 ZERO(0x010);
3140 ZERO(0x014);
3141 ZERO(0x018);
3142
3143 tmp = readl(hc_mmio + 0x20);
3144 tmp &= 0x1c1c1c1c;
3145 tmp |= 0x03030303;
3146 writel(tmp, hc_mmio + 0x20);
3147 }
3148 #undef ZERO
3149
3150 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3151 unsigned int n_hc)
3152 {
3153 unsigned int hc, port;
3154
3155 for (hc = 0; hc < n_hc; hc++) {
3156 for (port = 0; port < MV_PORTS_PER_HC; port++)
3157 mv5_reset_hc_port(hpriv, mmio,
3158 (hc * MV_PORTS_PER_HC) + port);
3159
3160 mv5_reset_one_hc(hpriv, mmio, hc);
3161 }
3162
3163 return 0;
3164 }
3165
3166 #undef ZERO
3167 #define ZERO(reg) writel(0, mmio + (reg))
3168 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3169 {
3170 struct mv_host_priv *hpriv = host->private_data;
3171 u32 tmp;
3172
3173 tmp = readl(mmio + MV_PCI_MODE);
3174 tmp &= 0xff00ffff;
3175 writel(tmp, mmio + MV_PCI_MODE);
3176
3177 ZERO(MV_PCI_DISC_TIMER);
3178 ZERO(MV_PCI_MSI_TRIGGER);
3179 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
3180 ZERO(MV_PCI_SERR_MASK);
3181 ZERO(hpriv->irq_cause_offset);
3182 ZERO(hpriv->irq_mask_offset);
3183 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3184 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3185 ZERO(MV_PCI_ERR_ATTRIBUTE);
3186 ZERO(MV_PCI_ERR_COMMAND);
3187 }
3188 #undef ZERO
3189
3190 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3191 {
3192 u32 tmp;
3193
3194 mv5_reset_flash(hpriv, mmio);
3195
3196 tmp = readl(mmio + GPIO_PORT_CTL);
3197 tmp &= 0x3;
3198 tmp |= (1 << 5) | (1 << 6);
3199 writel(tmp, mmio + GPIO_PORT_CTL);
3200 }
3201
3202 /**
3203 * mv6_reset_hc - Perform the 6xxx global soft reset
3204 * @mmio: base address of the HBA
3205 *
3206 * This routine only applies to 6xxx parts.
3207 *
3208 * LOCKING:
3209 * Inherited from caller.
3210 */
3211 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3212 unsigned int n_hc)
3213 {
3214 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
3215 int i, rc = 0;
3216 u32 t;
3217
3218 /* Following procedure defined in PCI "main command and status
3219 * register" table.
3220 */
3221 t = readl(reg);
3222 writel(t | STOP_PCI_MASTER, reg);
3223
3224 for (i = 0; i < 1000; i++) {
3225 udelay(1);
3226 t = readl(reg);
3227 if (PCI_MASTER_EMPTY & t)
3228 break;
3229 }
3230 if (!(PCI_MASTER_EMPTY & t)) {
3231 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3232 rc = 1;
3233 goto done;
3234 }
3235
3236 /* set reset */
3237 i = 5;
3238 do {
3239 writel(t | GLOB_SFT_RST, reg);
3240 t = readl(reg);
3241 udelay(1);
3242 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3243
3244 if (!(GLOB_SFT_RST & t)) {
3245 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3246 rc = 1;
3247 goto done;
3248 }
3249
3250 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3251 i = 5;
3252 do {
3253 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3254 t = readl(reg);
3255 udelay(1);
3256 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3257
3258 if (GLOB_SFT_RST & t) {
3259 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3260 rc = 1;
3261 }
3262 done:
3263 return rc;
3264 }
3265
3266 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3267 void __iomem *mmio)
3268 {
3269 void __iomem *port_mmio;
3270 u32 tmp;
3271
3272 tmp = readl(mmio + RESET_CFG);
3273 if ((tmp & (1 << 0)) == 0) {
3274 hpriv->signal[idx].amps = 0x7 << 8;
3275 hpriv->signal[idx].pre = 0x1 << 5;
3276 return;
3277 }
3278
3279 port_mmio = mv_port_base(mmio, idx);
3280 tmp = readl(port_mmio + PHY_MODE2);
3281
3282 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3283 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3284 }
3285
3286 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3287 {
3288 writel(0x00000060, mmio + GPIO_PORT_CTL);
3289 }
3290
3291 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3292 unsigned int port)
3293 {
3294 void __iomem *port_mmio = mv_port_base(mmio, port);
3295
3296 u32 hp_flags = hpriv->hp_flags;
3297 int fix_phy_mode2 =
3298 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3299 int fix_phy_mode4 =
3300 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3301 u32 m2, m3;
3302
3303 if (fix_phy_mode2) {
3304 m2 = readl(port_mmio + PHY_MODE2);
3305 m2 &= ~(1 << 16);
3306 m2 |= (1 << 31);
3307 writel(m2, port_mmio + PHY_MODE2);
3308
3309 udelay(200);
3310
3311 m2 = readl(port_mmio + PHY_MODE2);
3312 m2 &= ~((1 << 16) | (1 << 31));
3313 writel(m2, port_mmio + PHY_MODE2);
3314
3315 udelay(200);
3316 }
3317
3318 /*
3319 * Gen-II/IIe PHY_MODE3 errata RM#2:
3320 * Achieves better receiver noise performance than the h/w default:
3321 */
3322 m3 = readl(port_mmio + PHY_MODE3);
3323 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3324
3325 /* Guideline 88F5182 (GL# SATA-S11) */
3326 if (IS_SOC(hpriv))
3327 m3 &= ~0x1c;
3328
3329 if (fix_phy_mode4) {
3330 u32 m4 = readl(port_mmio + PHY_MODE4);
3331 /*
3332 * Enforce reserved-bit restrictions on GenIIe devices only.
3333 * For earlier chipsets, force only the internal config field
3334 * (workaround for errata FEr SATA#10 part 1).
3335 */
3336 if (IS_GEN_IIE(hpriv))
3337 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3338 else
3339 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3340 writel(m4, port_mmio + PHY_MODE4);
3341 }
3342 /*
3343 * Workaround for 60x1-B2 errata SATA#13:
3344 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3345 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3346 * Or ensure we use writelfl() when writing PHY_MODE4.
3347 */
3348 writel(m3, port_mmio + PHY_MODE3);
3349
3350 /* Revert values of pre-emphasis and signal amps to the saved ones */
3351 m2 = readl(port_mmio + PHY_MODE2);
3352
3353 m2 &= ~MV_M2_PREAMP_MASK;
3354 m2 |= hpriv->signal[port].amps;
3355 m2 |= hpriv->signal[port].pre;
3356 m2 &= ~(1 << 16);
3357
3358 /* according to mvSata 3.6.1, some IIE values are fixed */
3359 if (IS_GEN_IIE(hpriv)) {
3360 m2 &= ~0xC30FF01F;
3361 m2 |= 0x0000900F;
3362 }
3363
3364 writel(m2, port_mmio + PHY_MODE2);
3365 }
3366
3367 /* TODO: use the generic LED interface to configure the SATA Presence */
3368 /* & Acitivy LEDs on the board */
3369 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3370 void __iomem *mmio)
3371 {
3372 return;
3373 }
3374
3375 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3376 void __iomem *mmio)
3377 {
3378 void __iomem *port_mmio;
3379 u32 tmp;
3380
3381 port_mmio = mv_port_base(mmio, idx);
3382 tmp = readl(port_mmio + PHY_MODE2);
3383
3384 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3385 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3386 }
3387
3388 #undef ZERO
3389 #define ZERO(reg) writel(0, port_mmio + (reg))
3390 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3391 void __iomem *mmio, unsigned int port)
3392 {
3393 void __iomem *port_mmio = mv_port_base(mmio, port);
3394
3395 mv_reset_channel(hpriv, mmio, port);
3396
3397 ZERO(0x028); /* command */
3398 writel(0x101f, port_mmio + EDMA_CFG);
3399 ZERO(0x004); /* timer */
3400 ZERO(0x008); /* irq err cause */
3401 ZERO(0x00c); /* irq err mask */
3402 ZERO(0x010); /* rq bah */
3403 ZERO(0x014); /* rq inp */
3404 ZERO(0x018); /* rq outp */
3405 ZERO(0x01c); /* respq bah */
3406 ZERO(0x024); /* respq outp */
3407 ZERO(0x020); /* respq inp */
3408 ZERO(0x02c); /* test control */
3409 writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
3410 }
3411
3412 #undef ZERO
3413
3414 #define ZERO(reg) writel(0, hc_mmio + (reg))
3415 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3416 void __iomem *mmio)
3417 {
3418 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3419
3420 ZERO(0x00c);
3421 ZERO(0x010);
3422 ZERO(0x014);
3423
3424 }
3425
3426 #undef ZERO
3427
3428 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3429 void __iomem *mmio, unsigned int n_hc)
3430 {
3431 unsigned int port;
3432
3433 for (port = 0; port < hpriv->n_ports; port++)
3434 mv_soc_reset_hc_port(hpriv, mmio, port);
3435
3436 mv_soc_reset_one_hc(hpriv, mmio);
3437
3438 return 0;
3439 }
3440
3441 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3442 void __iomem *mmio)
3443 {
3444 return;
3445 }
3446
3447 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3448 {
3449 return;
3450 }
3451
3452 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3453 void __iomem *mmio, unsigned int port)
3454 {
3455 void __iomem *port_mmio = mv_port_base(mmio, port);
3456 u32 reg;
3457
3458 reg = readl(port_mmio + PHY_MODE3);
3459 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3460 reg |= (0x1 << 27);
3461 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3462 reg |= (0x1 << 29);
3463 writel(reg, port_mmio + PHY_MODE3);
3464
3465 reg = readl(port_mmio + PHY_MODE4);
3466 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3467 reg |= (0x1 << 16);
3468 writel(reg, port_mmio + PHY_MODE4);
3469
3470 reg = readl(port_mmio + PHY_MODE9_GEN2);
3471 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3472 reg |= 0x8;
3473 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3474 writel(reg, port_mmio + PHY_MODE9_GEN2);
3475
3476 reg = readl(port_mmio + PHY_MODE9_GEN1);
3477 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3478 reg |= 0x8;
3479 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3480 writel(reg, port_mmio + PHY_MODE9_GEN1);
3481 }
3482
3483 /**
3484 * soc_is_65 - check if the soc is 65 nano device
3485 *
3486 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3487 * register, this register should contain non-zero value and it exists only
3488 * in the 65 nano devices, when reading it from older devices we get 0.
3489 */
3490 static bool soc_is_65n(struct mv_host_priv *hpriv)
3491 {
3492 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3493
3494 if (readl(port0_mmio + PHYCFG_OFS))
3495 return true;
3496 return false;
3497 }
3498
3499 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3500 {
3501 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
3502
3503 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
3504 if (want_gen2i)
3505 ifcfg |= (1 << 7); /* enable gen2i speed */
3506 writelfl(ifcfg, port_mmio + SATA_IFCFG);
3507 }
3508
3509 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3510 unsigned int port_no)
3511 {
3512 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3513
3514 /*
3515 * The datasheet warns against setting EDMA_RESET when EDMA is active
3516 * (but doesn't say what the problem might be). So we first try
3517 * to disable the EDMA engine before doing the EDMA_RESET operation.
3518 */
3519 mv_stop_edma_engine(port_mmio);
3520 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3521
3522 if (!IS_GEN_I(hpriv)) {
3523 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3524 mv_setup_ifcfg(port_mmio, 1);
3525 }
3526 /*
3527 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3528 * link, and physical layers. It resets all SATA interface registers
3529 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
3530 */
3531 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3532 udelay(25); /* allow reset propagation */
3533 writelfl(0, port_mmio + EDMA_CMD);
3534
3535 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3536
3537 if (IS_GEN_I(hpriv))
3538 mdelay(1);
3539 }
3540
3541 static void mv_pmp_select(struct ata_port *ap, int pmp)
3542 {
3543 if (sata_pmp_supported(ap)) {
3544 void __iomem *port_mmio = mv_ap_base(ap);
3545 u32 reg = readl(port_mmio + SATA_IFCTL);
3546 int old = reg & 0xf;
3547
3548 if (old != pmp) {
3549 reg = (reg & ~0xf) | pmp;
3550 writelfl(reg, port_mmio + SATA_IFCTL);
3551 }
3552 }
3553 }
3554
3555 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3556 unsigned long deadline)
3557 {
3558 mv_pmp_select(link->ap, sata_srst_pmp(link));
3559 return sata_std_hardreset(link, class, deadline);
3560 }
3561
3562 static int mv_softreset(struct ata_link *link, unsigned int *class,
3563 unsigned long deadline)
3564 {
3565 mv_pmp_select(link->ap, sata_srst_pmp(link));
3566 return ata_sff_softreset(link, class, deadline);
3567 }
3568
3569 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3570 unsigned long deadline)
3571 {
3572 struct ata_port *ap = link->ap;
3573 struct mv_host_priv *hpriv = ap->host->private_data;
3574 struct mv_port_priv *pp = ap->private_data;
3575 void __iomem *mmio = hpriv->base;
3576 int rc, attempts = 0, extra = 0;
3577 u32 sstatus;
3578 bool online;
3579
3580 mv_reset_channel(hpriv, mmio, ap->port_no);
3581 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3582 pp->pp_flags &=
3583 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3584
3585 /* Workaround for errata FEr SATA#10 (part 2) */
3586 do {
3587 const unsigned long *timing =
3588 sata_ehc_deb_timing(&link->eh_context);
3589
3590 rc = sata_link_hardreset(link, timing, deadline + extra,
3591 &online, NULL);
3592 rc = online ? -EAGAIN : rc;
3593 if (rc)
3594 return rc;
3595 sata_scr_read(link, SCR_STATUS, &sstatus);
3596 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3597 /* Force 1.5gb/s link speed and try again */
3598 mv_setup_ifcfg(mv_ap_base(ap), 0);
3599 if (time_after(jiffies + HZ, deadline))
3600 extra = HZ; /* only extend it once, max */
3601 }
3602 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3603 mv_save_cached_regs(ap);
3604 mv_edma_cfg(ap, 0, 0);
3605
3606 return rc;
3607 }
3608
3609 static void mv_eh_freeze(struct ata_port *ap)
3610 {
3611 mv_stop_edma(ap);
3612 mv_enable_port_irqs(ap, 0);
3613 }
3614
3615 static void mv_eh_thaw(struct ata_port *ap)
3616 {
3617 struct mv_host_priv *hpriv = ap->host->private_data;
3618 unsigned int port = ap->port_no;
3619 unsigned int hardport = mv_hardport_from_port(port);
3620 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3621 void __iomem *port_mmio = mv_ap_base(ap);
3622 u32 hc_irq_cause;
3623
3624 /* clear EDMA errors on this port */
3625 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3626
3627 /* clear pending irq events */
3628 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3629 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
3630
3631 mv_enable_port_irqs(ap, ERR_IRQ);
3632 }
3633
3634 /**
3635 * mv_port_init - Perform some early initialization on a single port.
3636 * @port: libata data structure storing shadow register addresses
3637 * @port_mmio: base address of the port
3638 *
3639 * Initialize shadow register mmio addresses, clear outstanding
3640 * interrupts on the port, and unmask interrupts for the future
3641 * start of the port.
3642 *
3643 * LOCKING:
3644 * Inherited from caller.
3645 */
3646 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3647 {
3648 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
3649
3650 /* PIO related setup
3651 */
3652 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3653 port->error_addr =
3654 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3655 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3656 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3657 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3658 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3659 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3660 port->status_addr =
3661 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3662 /* special case: control/altstatus doesn't have ATA_REG_ address */
3663 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
3664
3665 /* Clear any currently outstanding port interrupt conditions */
3666 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3667 writelfl(readl(serr), serr);
3668 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3669
3670 /* unmask all non-transient EDMA error interrupts */
3671 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
3672
3673 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3674 readl(port_mmio + EDMA_CFG),
3675 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3676 readl(port_mmio + EDMA_ERR_IRQ_MASK));
3677 }
3678
3679 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3680 {
3681 struct mv_host_priv *hpriv = host->private_data;
3682 void __iomem *mmio = hpriv->base;
3683 u32 reg;
3684
3685 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3686 return 0; /* not PCI-X capable */
3687 reg = readl(mmio + MV_PCI_MODE);
3688 if ((reg & MV_PCI_MODE_MASK) == 0)
3689 return 0; /* conventional PCI mode */
3690 return 1; /* chip is in PCI-X mode */
3691 }
3692
3693 static int mv_pci_cut_through_okay(struct ata_host *host)
3694 {
3695 struct mv_host_priv *hpriv = host->private_data;
3696 void __iomem *mmio = hpriv->base;
3697 u32 reg;
3698
3699 if (!mv_in_pcix_mode(host)) {
3700 reg = readl(mmio + MV_PCI_COMMAND);
3701 if (reg & MV_PCI_COMMAND_MRDTRIG)
3702 return 0; /* not okay */
3703 }
3704 return 1; /* okay */
3705 }
3706
3707 static void mv_60x1b2_errata_pci7(struct ata_host *host)
3708 {
3709 struct mv_host_priv *hpriv = host->private_data;
3710 void __iomem *mmio = hpriv->base;
3711
3712 /* workaround for 60x1-B2 errata PCI#7 */
3713 if (mv_in_pcix_mode(host)) {
3714 u32 reg = readl(mmio + MV_PCI_COMMAND);
3715 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
3716 }
3717 }
3718
3719 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3720 {
3721 struct pci_dev *pdev = to_pci_dev(host->dev);
3722 struct mv_host_priv *hpriv = host->private_data;
3723 u32 hp_flags = hpriv->hp_flags;
3724
3725 switch (board_idx) {
3726 case chip_5080:
3727 hpriv->ops = &mv5xxx_ops;
3728 hp_flags |= MV_HP_GEN_I;
3729
3730 switch (pdev->revision) {
3731 case 0x1:
3732 hp_flags |= MV_HP_ERRATA_50XXB0;
3733 break;
3734 case 0x3:
3735 hp_flags |= MV_HP_ERRATA_50XXB2;
3736 break;
3737 default:
3738 dev_printk(KERN_WARNING, &pdev->dev,
3739 "Applying 50XXB2 workarounds to unknown rev\n");
3740 hp_flags |= MV_HP_ERRATA_50XXB2;
3741 break;
3742 }
3743 break;
3744
3745 case chip_504x:
3746 case chip_508x:
3747 hpriv->ops = &mv5xxx_ops;
3748 hp_flags |= MV_HP_GEN_I;
3749
3750 switch (pdev->revision) {
3751 case 0x0:
3752 hp_flags |= MV_HP_ERRATA_50XXB0;
3753 break;
3754 case 0x3:
3755 hp_flags |= MV_HP_ERRATA_50XXB2;
3756 break;
3757 default:
3758 dev_printk(KERN_WARNING, &pdev->dev,
3759 "Applying B2 workarounds to unknown rev\n");
3760 hp_flags |= MV_HP_ERRATA_50XXB2;
3761 break;
3762 }
3763 break;
3764
3765 case chip_604x:
3766 case chip_608x:
3767 hpriv->ops = &mv6xxx_ops;
3768 hp_flags |= MV_HP_GEN_II;
3769
3770 switch (pdev->revision) {
3771 case 0x7:
3772 mv_60x1b2_errata_pci7(host);
3773 hp_flags |= MV_HP_ERRATA_60X1B2;
3774 break;
3775 case 0x9:
3776 hp_flags |= MV_HP_ERRATA_60X1C0;
3777 break;
3778 default:
3779 dev_printk(KERN_WARNING, &pdev->dev,
3780 "Applying B2 workarounds to unknown rev\n");
3781 hp_flags |= MV_HP_ERRATA_60X1B2;
3782 break;
3783 }
3784 break;
3785
3786 case chip_7042:
3787 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3788 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3789 (pdev->device == 0x2300 || pdev->device == 0x2310))
3790 {
3791 /*
3792 * Highpoint RocketRAID PCIe 23xx series cards:
3793 *
3794 * Unconfigured drives are treated as "Legacy"
3795 * by the BIOS, and it overwrites sector 8 with
3796 * a "Lgcy" metadata block prior to Linux boot.
3797 *
3798 * Configured drives (RAID or JBOD) leave sector 8
3799 * alone, but instead overwrite a high numbered
3800 * sector for the RAID metadata. This sector can
3801 * be determined exactly, by truncating the physical
3802 * drive capacity to a nice even GB value.
3803 *
3804 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3805 *
3806 * Warn the user, lest they think we're just buggy.
3807 */
3808 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3809 " BIOS CORRUPTS DATA on all attached drives,"
3810 " regardless of if/how they are configured."
3811 " BEWARE!\n");
3812 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3813 " use sectors 8-9 on \"Legacy\" drives,"
3814 " and avoid the final two gigabytes on"
3815 " all RocketRAID BIOS initialized drives.\n");
3816 }
3817 /* drop through */
3818 case chip_6042:
3819 hpriv->ops = &mv6xxx_ops;
3820 hp_flags |= MV_HP_GEN_IIE;
3821 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3822 hp_flags |= MV_HP_CUT_THROUGH;
3823
3824 switch (pdev->revision) {
3825 case 0x2: /* Rev.B0: the first/only public release */
3826 hp_flags |= MV_HP_ERRATA_60X1C0;
3827 break;
3828 default:
3829 dev_printk(KERN_WARNING, &pdev->dev,
3830 "Applying 60X1C0 workarounds to unknown rev\n");
3831 hp_flags |= MV_HP_ERRATA_60X1C0;
3832 break;
3833 }
3834 break;
3835 case chip_soc:
3836 if (soc_is_65n(hpriv))
3837 hpriv->ops = &mv_soc_65n_ops;
3838 else
3839 hpriv->ops = &mv_soc_ops;
3840 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3841 MV_HP_ERRATA_60X1C0;
3842 break;
3843
3844 default:
3845 dev_printk(KERN_ERR, host->dev,
3846 "BUG: invalid board index %u\n", board_idx);
3847 return 1;
3848 }
3849
3850 hpriv->hp_flags = hp_flags;
3851 if (hp_flags & MV_HP_PCIE) {
3852 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3853 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
3854 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3855 } else {
3856 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3857 hpriv->irq_mask_offset = PCI_IRQ_MASK;
3858 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3859 }
3860
3861 return 0;
3862 }
3863
3864 /**
3865 * mv_init_host - Perform some early initialization of the host.
3866 * @host: ATA host to initialize
3867 *
3868 * If possible, do an early global reset of the host. Then do
3869 * our port init and clear/unmask all/relevant host interrupts.
3870 *
3871 * LOCKING:
3872 * Inherited from caller.
3873 */
3874 static int mv_init_host(struct ata_host *host)
3875 {
3876 int rc = 0, n_hc, port, hc;
3877 struct mv_host_priv *hpriv = host->private_data;
3878 void __iomem *mmio = hpriv->base;
3879
3880 rc = mv_chip_id(host, hpriv->board_idx);
3881 if (rc)
3882 goto done;
3883
3884 if (IS_SOC(hpriv)) {
3885 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3886 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
3887 } else {
3888 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3889 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
3890 }
3891
3892 /* initialize shadow irq mask with register's value */
3893 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3894
3895 /* global interrupt mask: 0 == mask everything */
3896 mv_set_main_irq_mask(host, ~0, 0);
3897
3898 n_hc = mv_get_hc_count(host->ports[0]->flags);
3899
3900 for (port = 0; port < host->n_ports; port++)
3901 if (hpriv->ops->read_preamp)
3902 hpriv->ops->read_preamp(hpriv, port, mmio);
3903
3904 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3905 if (rc)
3906 goto done;
3907
3908 hpriv->ops->reset_flash(hpriv, mmio);
3909 hpriv->ops->reset_bus(host, mmio);
3910 hpriv->ops->enable_leds(hpriv, mmio);
3911
3912 for (port = 0; port < host->n_ports; port++) {
3913 struct ata_port *ap = host->ports[port];
3914 void __iomem *port_mmio = mv_port_base(mmio, port);
3915
3916 mv_port_init(&ap->ioaddr, port_mmio);
3917 }
3918
3919 for (hc = 0; hc < n_hc; hc++) {
3920 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3921
3922 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3923 "(before clear)=0x%08x\n", hc,
3924 readl(hc_mmio + HC_CFG),
3925 readl(hc_mmio + HC_IRQ_CAUSE));
3926
3927 /* Clear any currently outstanding hc interrupt conditions */
3928 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
3929 }
3930
3931 if (!IS_SOC(hpriv)) {
3932 /* Clear any currently outstanding host interrupt conditions */
3933 writelfl(0, mmio + hpriv->irq_cause_offset);
3934
3935 /* and unmask interrupt generation for host regs */
3936 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
3937 }
3938
3939 /*
3940 * enable only global host interrupts for now.
3941 * The per-port interrupts get done later as ports are set up.
3942 */
3943 mv_set_main_irq_mask(host, 0, PCI_ERR);
3944 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3945 irq_coalescing_usecs);
3946 done:
3947 return rc;
3948 }
3949
3950 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3951 {
3952 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3953 MV_CRQB_Q_SZ, 0);
3954 if (!hpriv->crqb_pool)
3955 return -ENOMEM;
3956
3957 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3958 MV_CRPB_Q_SZ, 0);
3959 if (!hpriv->crpb_pool)
3960 return -ENOMEM;
3961
3962 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3963 MV_SG_TBL_SZ, 0);
3964 if (!hpriv->sg_tbl_pool)
3965 return -ENOMEM;
3966
3967 return 0;
3968 }
3969
3970 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3971 struct mbus_dram_target_info *dram)
3972 {
3973 int i;
3974
3975 for (i = 0; i < 4; i++) {
3976 writel(0, hpriv->base + WINDOW_CTRL(i));
3977 writel(0, hpriv->base + WINDOW_BASE(i));
3978 }
3979
3980 for (i = 0; i < dram->num_cs; i++) {
3981 struct mbus_dram_window *cs = dram->cs + i;
3982
3983 writel(((cs->size - 1) & 0xffff0000) |
3984 (cs->mbus_attr << 8) |
3985 (dram->mbus_dram_target_id << 4) | 1,
3986 hpriv->base + WINDOW_CTRL(i));
3987 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3988 }
3989 }
3990
3991 /**
3992 * mv_platform_probe - handle a positive probe of an soc Marvell
3993 * host
3994 * @pdev: platform device found
3995 *
3996 * LOCKING:
3997 * Inherited from caller.
3998 */
3999 static int mv_platform_probe(struct platform_device *pdev)
4000 {
4001 static int printed_version;
4002 const struct mv_sata_platform_data *mv_platform_data;
4003 const struct ata_port_info *ppi[] =
4004 { &mv_port_info[chip_soc], NULL };
4005 struct ata_host *host;
4006 struct mv_host_priv *hpriv;
4007 struct resource *res;
4008 int n_ports, rc;
4009
4010 if (!printed_version++)
4011 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4012
4013 /*
4014 * Simple resource validation ..
4015 */
4016 if (unlikely(pdev->num_resources != 2)) {
4017 dev_err(&pdev->dev, "invalid number of resources\n");
4018 return -EINVAL;
4019 }
4020
4021 /*
4022 * Get the register base first
4023 */
4024 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4025 if (res == NULL)
4026 return -EINVAL;
4027
4028 /* allocate host */
4029 mv_platform_data = pdev->dev.platform_data;
4030 n_ports = mv_platform_data->n_ports;
4031
4032 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4033 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4034
4035 if (!host || !hpriv)
4036 return -ENOMEM;
4037 host->private_data = hpriv;
4038 hpriv->n_ports = n_ports;
4039 hpriv->board_idx = chip_soc;
4040
4041 host->iomap = NULL;
4042 hpriv->base = devm_ioremap(&pdev->dev, res->start,
4043 resource_size(res));
4044 hpriv->base -= SATAHC0_REG_BASE;
4045
4046 #if defined(CONFIG_HAVE_CLK)
4047 hpriv->clk = clk_get(&pdev->dev, NULL);
4048 if (IS_ERR(hpriv->clk))
4049 dev_notice(&pdev->dev, "cannot get clkdev\n");
4050 else
4051 clk_enable(hpriv->clk);
4052 #endif
4053
4054 /*
4055 * (Re-)program MBUS remapping windows if we are asked to.
4056 */
4057 if (mv_platform_data->dram != NULL)
4058 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4059
4060 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4061 if (rc)
4062 goto err;
4063
4064 /* initialize adapter */
4065 rc = mv_init_host(host);
4066 if (rc)
4067 goto err;
4068
4069 dev_printk(KERN_INFO, &pdev->dev,
4070 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
4071 host->n_ports);
4072
4073 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
4074 IRQF_SHARED, &mv6_sht);
4075 err:
4076 #if defined(CONFIG_HAVE_CLK)
4077 if (!IS_ERR(hpriv->clk)) {
4078 clk_disable(hpriv->clk);
4079 clk_put(hpriv->clk);
4080 }
4081 #endif
4082
4083 return rc;
4084 }
4085
4086 /*
4087 *
4088 * mv_platform_remove - unplug a platform interface
4089 * @pdev: platform device
4090 *
4091 * A platform bus SATA device has been unplugged. Perform the needed
4092 * cleanup. Also called on module unload for any active devices.
4093 */
4094 static int __devexit mv_platform_remove(struct platform_device *pdev)
4095 {
4096 struct device *dev = &pdev->dev;
4097 struct ata_host *host = dev_get_drvdata(dev);
4098 #if defined(CONFIG_HAVE_CLK)
4099 struct mv_host_priv *hpriv = host->private_data;
4100 #endif
4101 ata_host_detach(host);
4102
4103 #if defined(CONFIG_HAVE_CLK)
4104 if (!IS_ERR(hpriv->clk)) {
4105 clk_disable(hpriv->clk);
4106 clk_put(hpriv->clk);
4107 }
4108 #endif
4109 return 0;
4110 }
4111
4112 #ifdef CONFIG_PM
4113 static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4114 {
4115 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4116 if (host)
4117 return ata_host_suspend(host, state);
4118 else
4119 return 0;
4120 }
4121
4122 static int mv_platform_resume(struct platform_device *pdev)
4123 {
4124 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4125 int ret;
4126
4127 if (host) {
4128 struct mv_host_priv *hpriv = host->private_data;
4129 const struct mv_sata_platform_data *mv_platform_data = \
4130 pdev->dev.platform_data;
4131 /*
4132 * (Re-)program MBUS remapping windows if we are asked to.
4133 */
4134 if (mv_platform_data->dram != NULL)
4135 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4136
4137 /* initialize adapter */
4138 ret = mv_init_host(host);
4139 if (ret) {
4140 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4141 return ret;
4142 }
4143 ata_host_resume(host);
4144 }
4145
4146 return 0;
4147 }
4148 #else
4149 #define mv_platform_suspend NULL
4150 #define mv_platform_resume NULL
4151 #endif
4152
4153 static struct platform_driver mv_platform_driver = {
4154 .probe = mv_platform_probe,
4155 .remove = __devexit_p(mv_platform_remove),
4156 .suspend = mv_platform_suspend,
4157 .resume = mv_platform_resume,
4158 .driver = {
4159 .name = DRV_NAME,
4160 .owner = THIS_MODULE,
4161 },
4162 };
4163
4164
4165 #ifdef CONFIG_PCI
4166 static int mv_pci_init_one(struct pci_dev *pdev,
4167 const struct pci_device_id *ent);
4168 #ifdef CONFIG_PM
4169 static int mv_pci_device_resume(struct pci_dev *pdev);
4170 #endif
4171
4172
4173 static struct pci_driver mv_pci_driver = {
4174 .name = DRV_NAME,
4175 .id_table = mv_pci_tbl,
4176 .probe = mv_pci_init_one,
4177 .remove = ata_pci_remove_one,
4178 #ifdef CONFIG_PM
4179 .suspend = ata_pci_device_suspend,
4180 .resume = mv_pci_device_resume,
4181 #endif
4182
4183 };
4184
4185 /* move to PCI layer or libata core? */
4186 static int pci_go_64(struct pci_dev *pdev)
4187 {
4188 int rc;
4189
4190 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4191 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4192 if (rc) {
4193 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4194 if (rc) {
4195 dev_printk(KERN_ERR, &pdev->dev,
4196 "64-bit DMA enable failed\n");
4197 return rc;
4198 }
4199 }
4200 } else {
4201 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4202 if (rc) {
4203 dev_printk(KERN_ERR, &pdev->dev,
4204 "32-bit DMA enable failed\n");
4205 return rc;
4206 }
4207 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4208 if (rc) {
4209 dev_printk(KERN_ERR, &pdev->dev,
4210 "32-bit consistent DMA enable failed\n");
4211 return rc;
4212 }
4213 }
4214
4215 return rc;
4216 }
4217
4218 /**
4219 * mv_print_info - Dump key info to kernel log for perusal.
4220 * @host: ATA host to print info about
4221 *
4222 * FIXME: complete this.
4223 *
4224 * LOCKING:
4225 * Inherited from caller.
4226 */
4227 static void mv_print_info(struct ata_host *host)
4228 {
4229 struct pci_dev *pdev = to_pci_dev(host->dev);
4230 struct mv_host_priv *hpriv = host->private_data;
4231 u8 scc;
4232 const char *scc_s, *gen;
4233
4234 /* Use this to determine the HW stepping of the chip so we know
4235 * what errata to workaround
4236 */
4237 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4238 if (scc == 0)
4239 scc_s = "SCSI";
4240 else if (scc == 0x01)
4241 scc_s = "RAID";
4242 else
4243 scc_s = "?";
4244
4245 if (IS_GEN_I(hpriv))
4246 gen = "I";
4247 else if (IS_GEN_II(hpriv))
4248 gen = "II";
4249 else if (IS_GEN_IIE(hpriv))
4250 gen = "IIE";
4251 else
4252 gen = "?";
4253
4254 dev_printk(KERN_INFO, &pdev->dev,
4255 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4256 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4257 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4258 }
4259
4260 /**
4261 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4262 * @pdev: PCI device found
4263 * @ent: PCI device ID entry for the matched host
4264 *
4265 * LOCKING:
4266 * Inherited from caller.
4267 */
4268 static int mv_pci_init_one(struct pci_dev *pdev,
4269 const struct pci_device_id *ent)
4270 {
4271 static int printed_version;
4272 unsigned int board_idx = (unsigned int)ent->driver_data;
4273 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4274 struct ata_host *host;
4275 struct mv_host_priv *hpriv;
4276 int n_ports, port, rc;
4277
4278 if (!printed_version++)
4279 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4280
4281 /* allocate host */
4282 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4283
4284 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4285 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4286 if (!host || !hpriv)
4287 return -ENOMEM;
4288 host->private_data = hpriv;
4289 hpriv->n_ports = n_ports;
4290 hpriv->board_idx = board_idx;
4291
4292 /* acquire resources */
4293 rc = pcim_enable_device(pdev);
4294 if (rc)
4295 return rc;
4296
4297 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4298 if (rc == -EBUSY)
4299 pcim_pin_device(pdev);
4300 if (rc)
4301 return rc;
4302 host->iomap = pcim_iomap_table(pdev);
4303 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4304
4305 rc = pci_go_64(pdev);
4306 if (rc)
4307 return rc;
4308
4309 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4310 if (rc)
4311 return rc;
4312
4313 for (port = 0; port < host->n_ports; port++) {
4314 struct ata_port *ap = host->ports[port];
4315 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4316 unsigned int offset = port_mmio - hpriv->base;
4317
4318 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4319 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4320 }
4321
4322 /* initialize adapter */
4323 rc = mv_init_host(host);
4324 if (rc)
4325 return rc;
4326
4327 /* Enable message-switched interrupts, if requested */
4328 if (msi && pci_enable_msi(pdev) == 0)
4329 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4330
4331 mv_dump_pci_cfg(pdev, 0x68);
4332 mv_print_info(host);
4333
4334 pci_set_master(pdev);
4335 pci_try_set_mwi(pdev);
4336 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4337 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4338 }
4339
4340 #ifdef CONFIG_PM
4341 static int mv_pci_device_resume(struct pci_dev *pdev)
4342 {
4343 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4344 int rc;
4345
4346 rc = ata_pci_device_do_resume(pdev);
4347 if (rc)
4348 return rc;
4349
4350 /* initialize adapter */
4351 rc = mv_init_host(host);
4352 if (rc)
4353 return rc;
4354
4355 ata_host_resume(host);
4356
4357 return 0;
4358 }
4359 #endif
4360 #endif
4361
4362 static int mv_platform_probe(struct platform_device *pdev);
4363 static int __devexit mv_platform_remove(struct platform_device *pdev);
4364
4365 static int __init mv_init(void)
4366 {
4367 int rc = -ENODEV;
4368 #ifdef CONFIG_PCI
4369 rc = pci_register_driver(&mv_pci_driver);
4370 if (rc < 0)
4371 return rc;
4372 #endif
4373 rc = platform_driver_register(&mv_platform_driver);
4374
4375 #ifdef CONFIG_PCI
4376 if (rc < 0)
4377 pci_unregister_driver(&mv_pci_driver);
4378 #endif
4379 return rc;
4380 }
4381
4382 static void __exit mv_exit(void)
4383 {
4384 #ifdef CONFIG_PCI
4385 pci_unregister_driver(&mv_pci_driver);
4386 #endif
4387 platform_driver_unregister(&mv_platform_driver);
4388 }
4389
4390 MODULE_AUTHOR("Brett Russ");
4391 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4392 MODULE_LICENSE("GPL");
4393 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4394 MODULE_VERSION(DRV_VERSION);
4395 MODULE_ALIAS("platform:" DRV_NAME);
4396
4397 module_init(mv_init);
4398 module_exit(mv_exit);
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